2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 mutex_lock(&dev
->struct_mutex
);
132 drm_gem_object_handle_unreference(obj
);
133 mutex_unlock(&dev
->struct_mutex
);
138 args
->handle
= handle
;
144 fast_shmem_read(struct page
**pages
,
145 loff_t page_base
, int page_offset
,
152 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
155 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
156 kunmap_atomic(vaddr
, KM_USER0
);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
166 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
167 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
169 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
170 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
174 slow_shmem_copy(struct page
*dst_page
,
176 struct page
*src_page
,
180 char *dst_vaddr
, *src_vaddr
;
182 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
183 if (dst_vaddr
== NULL
)
186 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
187 if (src_vaddr
== NULL
) {
188 kunmap_atomic(dst_vaddr
, KM_USER0
);
192 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
194 kunmap_atomic(src_vaddr
, KM_USER1
);
195 kunmap_atomic(dst_vaddr
, KM_USER0
);
201 slow_shmem_bit17_copy(struct page
*gpu_page
,
203 struct page
*cpu_page
,
208 char *gpu_vaddr
, *cpu_vaddr
;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page
, cpu_offset
,
214 gpu_page
, gpu_offset
, length
);
216 return slow_shmem_copy(gpu_page
, gpu_offset
,
217 cpu_page
, cpu_offset
, length
);
220 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
221 if (gpu_vaddr
== NULL
)
224 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
225 if (cpu_vaddr
== NULL
) {
226 kunmap_atomic(gpu_vaddr
, KM_USER0
);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
235 int this_length
= min(cacheline_end
- gpu_offset
, length
);
236 int swizzled_gpu_offset
= gpu_offset
^ 64;
239 memcpy(cpu_vaddr
+ cpu_offset
,
240 gpu_vaddr
+ swizzled_gpu_offset
,
243 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
244 cpu_vaddr
+ cpu_offset
,
247 cpu_offset
+= this_length
;
248 gpu_offset
+= this_length
;
249 length
-= this_length
;
252 kunmap_atomic(cpu_vaddr
, KM_USER1
);
253 kunmap_atomic(gpu_vaddr
, KM_USER0
);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
265 struct drm_i915_gem_pread
*args
,
266 struct drm_file
*file_priv
)
268 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
270 loff_t offset
, page_base
;
271 char __user
*user_data
;
272 int page_offset
, page_length
;
275 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
278 mutex_lock(&dev
->struct_mutex
);
280 ret
= i915_gem_object_get_pages(obj
);
284 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
289 obj_priv
= obj
->driver_private
;
290 offset
= args
->offset
;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base
= (offset
& ~(PAGE_SIZE
-1));
300 page_offset
= offset
& (PAGE_SIZE
-1);
301 page_length
= remain
;
302 if ((page_offset
+ remain
) > PAGE_SIZE
)
303 page_length
= PAGE_SIZE
- page_offset
;
305 ret
= fast_shmem_read(obj_priv
->pages
,
306 page_base
, page_offset
,
307 user_data
, page_length
);
311 remain
-= page_length
;
312 user_data
+= page_length
;
313 offset
+= page_length
;
317 i915_gem_object_put_pages(obj
);
319 mutex_unlock(&dev
->struct_mutex
);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object
*obj
)
327 return mapping_gfp_mask(obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object
*obj
, gfp_t gfp
)
333 mapping_set_gfp_mask(obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
, gfp
);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
341 ret
= i915_gem_object_get_pages(obj
);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret
== -ENOMEM
) {
347 struct drm_device
*dev
= obj
->dev
;
350 ret
= i915_gem_evict_something(dev
, obj
->size
);
354 gfp
= i915_gem_object_get_page_gfp_mask(obj
);
355 i915_gem_object_set_page_gfp_mask(obj
, gfp
& ~__GFP_NORETRY
);
356 ret
= i915_gem_object_get_pages(obj
);
357 i915_gem_object_set_page_gfp_mask (obj
, gfp
);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
371 struct drm_i915_gem_pread
*args
,
372 struct drm_file
*file_priv
)
374 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
375 struct mm_struct
*mm
= current
->mm
;
376 struct page
**user_pages
;
378 loff_t offset
, pinned_pages
, i
;
379 loff_t first_data_page
, last_data_page
, num_pages
;
380 int shmem_page_index
, shmem_page_offset
;
381 int data_page_index
, data_page_offset
;
384 uint64_t data_ptr
= args
->data_ptr
;
385 int do_bit17_swizzling
;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page
= data_ptr
/ PAGE_SIZE
;
394 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
395 num_pages
= last_data_page
- first_data_page
+ 1;
397 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
398 if (user_pages
== NULL
)
401 down_read(&mm
->mmap_sem
);
402 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
403 num_pages
, 1, 0, user_pages
, NULL
);
404 up_read(&mm
->mmap_sem
);
405 if (pinned_pages
< num_pages
) {
407 goto fail_put_user_pages
;
410 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
412 mutex_lock(&dev
->struct_mutex
);
414 ret
= i915_gem_object_get_pages_or_evict(obj
);
418 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
423 obj_priv
= obj
->driver_private
;
424 offset
= args
->offset
;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index
= offset
/ PAGE_SIZE
;
436 shmem_page_offset
= offset
& ~PAGE_MASK
;
437 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
438 data_page_offset
= data_ptr
& ~PAGE_MASK
;
440 page_length
= remain
;
441 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
442 page_length
= PAGE_SIZE
- shmem_page_offset
;
443 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
444 page_length
= PAGE_SIZE
- data_page_offset
;
446 if (do_bit17_swizzling
) {
447 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
449 user_pages
[data_page_index
],
454 ret
= slow_shmem_copy(user_pages
[data_page_index
],
456 obj_priv
->pages
[shmem_page_index
],
463 remain
-= page_length
;
464 data_ptr
+= page_length
;
465 offset
+= page_length
;
469 i915_gem_object_put_pages(obj
);
471 mutex_unlock(&dev
->struct_mutex
);
473 for (i
= 0; i
< pinned_pages
; i
++) {
474 SetPageDirty(user_pages
[i
]);
475 page_cache_release(user_pages
[i
]);
477 drm_free_large(user_pages
);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
489 struct drm_file
*file_priv
)
491 struct drm_i915_gem_pread
*args
= data
;
492 struct drm_gem_object
*obj
;
493 struct drm_i915_gem_object
*obj_priv
;
496 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
499 obj_priv
= obj
->driver_private
;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
506 args
->offset
+ args
->size
> obj
->size
) {
507 drm_gem_object_unreference(obj
);
511 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
512 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
514 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
516 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
520 drm_gem_object_unreference(obj
);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping
*mapping
,
531 loff_t page_base
, int page_offset
,
532 char __user
*user_data
,
536 unsigned long unwritten
;
538 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
539 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
541 io_mapping_unmap_atomic(vaddr_atomic
);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping
*mapping
,
553 loff_t gtt_base
, int gtt_offset
,
554 struct page
*user_page
, int user_offset
,
557 char *src_vaddr
, *dst_vaddr
;
558 unsigned long unwritten
;
560 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
561 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
562 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
563 src_vaddr
+ user_offset
,
565 kunmap_atomic(src_vaddr
, KM_USER1
);
566 io_mapping_unmap_atomic(dst_vaddr
);
573 fast_shmem_write(struct page
**pages
,
574 loff_t page_base
, int page_offset
,
579 unsigned long unwritten
;
581 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
584 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
585 kunmap_atomic(vaddr
, KM_USER0
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
598 struct drm_i915_gem_pwrite
*args
,
599 struct drm_file
*file_priv
)
601 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
;
609 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
611 if (!access_ok(VERIFY_READ
, user_data
, remain
))
615 mutex_lock(&dev
->struct_mutex
);
616 ret
= i915_gem_object_pin(obj
, 0);
618 mutex_unlock(&dev
->struct_mutex
);
621 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
625 obj_priv
= obj
->driver_private
;
626 offset
= obj_priv
->gtt_offset
+ args
->offset
;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base
= (offset
& ~(PAGE_SIZE
-1));
636 page_offset
= offset
& (PAGE_SIZE
-1);
637 page_length
= remain
;
638 if ((page_offset
+ remain
) > PAGE_SIZE
)
639 page_length
= PAGE_SIZE
- page_offset
;
641 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
642 page_offset
, user_data
, page_length
);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain
-= page_length
;
652 user_data
+= page_length
;
653 offset
+= page_length
;
657 i915_gem_object_unpin(obj
);
658 mutex_unlock(&dev
->struct_mutex
);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
672 struct drm_i915_gem_pwrite
*args
,
673 struct drm_file
*file_priv
)
675 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
678 loff_t gtt_page_base
, offset
;
679 loff_t first_data_page
, last_data_page
, num_pages
;
680 loff_t pinned_pages
, i
;
681 struct page
**user_pages
;
682 struct mm_struct
*mm
= current
->mm
;
683 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
685 uint64_t data_ptr
= args
->data_ptr
;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page
= data_ptr
/ PAGE_SIZE
;
694 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
695 num_pages
= last_data_page
- first_data_page
+ 1;
697 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
698 if (user_pages
== NULL
)
701 down_read(&mm
->mmap_sem
);
702 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
703 num_pages
, 0, 0, user_pages
, NULL
);
704 up_read(&mm
->mmap_sem
);
705 if (pinned_pages
< num_pages
) {
707 goto out_unpin_pages
;
710 mutex_lock(&dev
->struct_mutex
);
711 ret
= i915_gem_object_pin(obj
, 0);
715 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
717 goto out_unpin_object
;
719 obj_priv
= obj
->driver_private
;
720 offset
= obj_priv
->gtt_offset
+ args
->offset
;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base
= offset
& PAGE_MASK
;
732 gtt_page_offset
= offset
& ~PAGE_MASK
;
733 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
734 data_page_offset
= data_ptr
& ~PAGE_MASK
;
736 page_length
= remain
;
737 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
738 page_length
= PAGE_SIZE
- gtt_page_offset
;
739 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
740 page_length
= PAGE_SIZE
- data_page_offset
;
742 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
743 gtt_page_base
, gtt_page_offset
,
744 user_pages
[data_page_index
],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object
;
755 remain
-= page_length
;
756 offset
+= page_length
;
757 data_ptr
+= page_length
;
761 i915_gem_object_unpin(obj
);
763 mutex_unlock(&dev
->struct_mutex
);
765 for (i
= 0; i
< pinned_pages
; i
++)
766 page_cache_release(user_pages
[i
]);
767 drm_free_large(user_pages
);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
778 struct drm_i915_gem_pwrite
*args
,
779 struct drm_file
*file_priv
)
781 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
783 loff_t offset
, page_base
;
784 char __user
*user_data
;
785 int page_offset
, page_length
;
788 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
791 mutex_lock(&dev
->struct_mutex
);
793 ret
= i915_gem_object_get_pages(obj
);
797 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
801 obj_priv
= obj
->driver_private
;
802 offset
= args
->offset
;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base
= (offset
& ~(PAGE_SIZE
-1));
813 page_offset
= offset
& (PAGE_SIZE
-1);
814 page_length
= remain
;
815 if ((page_offset
+ remain
) > PAGE_SIZE
)
816 page_length
= PAGE_SIZE
- page_offset
;
818 ret
= fast_shmem_write(obj_priv
->pages
,
819 page_base
, page_offset
,
820 user_data
, page_length
);
824 remain
-= page_length
;
825 user_data
+= page_length
;
826 offset
+= page_length
;
830 i915_gem_object_put_pages(obj
);
832 mutex_unlock(&dev
->struct_mutex
);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
846 struct drm_i915_gem_pwrite
*args
,
847 struct drm_file
*file_priv
)
849 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
850 struct mm_struct
*mm
= current
->mm
;
851 struct page
**user_pages
;
853 loff_t offset
, pinned_pages
, i
;
854 loff_t first_data_page
, last_data_page
, num_pages
;
855 int shmem_page_index
, shmem_page_offset
;
856 int data_page_index
, data_page_offset
;
859 uint64_t data_ptr
= args
->data_ptr
;
860 int do_bit17_swizzling
;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page
= data_ptr
/ PAGE_SIZE
;
869 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
870 num_pages
= last_data_page
- first_data_page
+ 1;
872 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
873 if (user_pages
== NULL
)
876 down_read(&mm
->mmap_sem
);
877 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
878 num_pages
, 0, 0, user_pages
, NULL
);
879 up_read(&mm
->mmap_sem
);
880 if (pinned_pages
< num_pages
) {
882 goto fail_put_user_pages
;
885 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
887 mutex_lock(&dev
->struct_mutex
);
889 ret
= i915_gem_object_get_pages_or_evict(obj
);
893 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
897 obj_priv
= obj
->driver_private
;
898 offset
= args
->offset
;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index
= offset
/ PAGE_SIZE
;
911 shmem_page_offset
= offset
& ~PAGE_MASK
;
912 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
913 data_page_offset
= data_ptr
& ~PAGE_MASK
;
915 page_length
= remain
;
916 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
917 page_length
= PAGE_SIZE
- shmem_page_offset
;
918 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
919 page_length
= PAGE_SIZE
- data_page_offset
;
921 if (do_bit17_swizzling
) {
922 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
924 user_pages
[data_page_index
],
929 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
931 user_pages
[data_page_index
],
938 remain
-= page_length
;
939 data_ptr
+= page_length
;
940 offset
+= page_length
;
944 i915_gem_object_put_pages(obj
);
946 mutex_unlock(&dev
->struct_mutex
);
948 for (i
= 0; i
< pinned_pages
; i
++)
949 page_cache_release(user_pages
[i
]);
950 drm_free_large(user_pages
);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
962 struct drm_file
*file_priv
)
964 struct drm_i915_gem_pwrite
*args
= data
;
965 struct drm_gem_object
*obj
;
966 struct drm_i915_gem_object
*obj_priv
;
969 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
972 obj_priv
= obj
->driver_private
;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
979 args
->offset
+ args
->size
> obj
->size
) {
980 drm_gem_object_unreference(obj
);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv
->phys_obj
)
991 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
992 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
993 dev
->gtt_total
!= 0) {
994 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
995 if (ret
== -EFAULT
) {
996 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
1000 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
1002 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
1003 if (ret
== -EFAULT
) {
1004 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1011 DRM_INFO("pwrite failed %d\n", ret
);
1014 drm_gem_object_unreference(obj
);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1025 struct drm_file
*file_priv
)
1027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1028 struct drm_i915_gem_set_domain
*args
= data
;
1029 struct drm_gem_object
*obj
;
1030 struct drm_i915_gem_object
*obj_priv
;
1031 uint32_t read_domains
= args
->read_domains
;
1032 uint32_t write_domain
= args
->write_domain
;
1035 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1042 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain
!= 0 && read_domains
!= write_domain
)
1051 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1054 obj_priv
= obj
->driver_private
;
1056 mutex_lock(&dev
->struct_mutex
);
1058 intel_mark_busy(dev
, obj
);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj
, obj
->size
, read_domains
, write_domain
);
1064 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1065 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1071 list_move_tail(&obj_priv
->fence_list
,
1072 &dev_priv
->mm
.fence_list
);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1085 drm_gem_object_unreference(obj
);
1086 mutex_unlock(&dev
->struct_mutex
);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1095 struct drm_file
*file_priv
)
1097 struct drm_i915_gem_sw_finish
*args
= data
;
1098 struct drm_gem_object
*obj
;
1099 struct drm_i915_gem_object
*obj_priv
;
1102 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1105 mutex_lock(&dev
->struct_mutex
);
1106 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1108 mutex_unlock(&dev
->struct_mutex
);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__
, args
->handle
, obj
, obj
->size
);
1116 obj_priv
= obj
->driver_private
;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv
->pin_count
)
1120 i915_gem_object_flush_cpu_write_domain(obj
);
1122 drm_gem_object_unreference(obj
);
1123 mutex_unlock(&dev
->struct_mutex
);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1136 struct drm_file
*file_priv
)
1138 struct drm_i915_gem_mmap
*args
= data
;
1139 struct drm_gem_object
*obj
;
1143 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1146 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1150 offset
= args
->offset
;
1152 down_write(¤t
->mm
->mmap_sem
);
1153 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1154 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1156 up_write(¤t
->mm
->mmap_sem
);
1157 mutex_lock(&dev
->struct_mutex
);
1158 drm_gem_object_unreference(obj
);
1159 mutex_unlock(&dev
->struct_mutex
);
1160 if (IS_ERR((void *)addr
))
1163 args
->addr_ptr
= (uint64_t) addr
;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1186 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1187 struct drm_device
*dev
= obj
->dev
;
1188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1189 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1190 pgoff_t page_offset
;
1193 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev
->struct_mutex
);
1201 if (!obj_priv
->gtt_space
) {
1202 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1206 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1208 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1213 /* Need a new fence register? */
1214 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1215 ret
= i915_gem_object_get_fence_reg(obj
);
1220 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1223 /* Finally, remap it using the new GTT offset */
1224 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1226 mutex_unlock(&dev
->struct_mutex
);
1231 return VM_FAULT_NOPAGE
;
1234 return VM_FAULT_OOM
;
1236 return VM_FAULT_SIGBUS
;
1241 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242 * @obj: obj in question
1244 * GEM memory mapping works by handing back to userspace a fake mmap offset
1245 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1246 * up the object based on the offset and sets up the various memory mapping
1249 * This routine allocates and attaches a fake offset for @obj.
1252 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1254 struct drm_device
*dev
= obj
->dev
;
1255 struct drm_gem_mm
*mm
= dev
->mm_private
;
1256 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1257 struct drm_map_list
*list
;
1258 struct drm_local_map
*map
;
1261 /* Set the object up for mmap'ing */
1262 list
= &obj
->map_list
;
1263 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1268 map
->type
= _DRM_GEM
;
1269 map
->size
= obj
->size
;
1272 /* Get a DRM GEM mmap offset allocated... */
1273 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1274 obj
->size
/ PAGE_SIZE
, 0, 0);
1275 if (!list
->file_offset_node
) {
1276 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1281 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1282 obj
->size
/ PAGE_SIZE
, 0);
1283 if (!list
->file_offset_node
) {
1288 list
->hash
.key
= list
->file_offset_node
->start
;
1289 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1290 DRM_ERROR("failed to add to map hash\n");
1295 /* By now we should be all set, any drm_mmap request on the offset
1296 * below will get to our mmap & fault handler */
1297 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1302 drm_mm_put_block(list
->file_offset_node
);
1310 * i915_gem_release_mmap - remove physical page mappings
1311 * @obj: obj in question
1313 * Preserve the reservation of the mmaping with the DRM core code, but
1314 * relinquish ownership of the pages back to the system.
1316 * It is vital that we remove the page mapping if we have mapped a tiled
1317 * object through the GTT and then lose the fence register due to
1318 * resource pressure. Similarly if the object has been moved out of the
1319 * aperture, than pages mapped into userspace must be revoked. Removing the
1320 * mapping will then trigger a page fault on the next user access, allowing
1321 * fixup by i915_gem_fault().
1324 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1326 struct drm_device
*dev
= obj
->dev
;
1327 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1329 if (dev
->dev_mapping
)
1330 unmap_mapping_range(dev
->dev_mapping
,
1331 obj_priv
->mmap_offset
, obj
->size
, 1);
1335 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1337 struct drm_device
*dev
= obj
->dev
;
1338 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1339 struct drm_gem_mm
*mm
= dev
->mm_private
;
1340 struct drm_map_list
*list
;
1342 list
= &obj
->map_list
;
1343 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1345 if (list
->file_offset_node
) {
1346 drm_mm_put_block(list
->file_offset_node
);
1347 list
->file_offset_node
= NULL
;
1355 obj_priv
->mmap_offset
= 0;
1359 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1360 * @obj: object to check
1362 * Return the required GTT alignment for an object, taking into account
1363 * potential fence register mapping if needed.
1366 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1368 struct drm_device
*dev
= obj
->dev
;
1369 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1373 * Minimum alignment is 4k (GTT page size), but might be greater
1374 * if a fence register is needed for the object.
1376 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1380 * Previous chips need to be aligned to the size of the smallest
1381 * fence register that can contain the object.
1388 for (i
= start
; i
< obj
->size
; i
<<= 1)
1395 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1397 * @data: GTT mapping ioctl data
1398 * @file_priv: GEM object info
1400 * Simply returns the fake offset to userspace so it can mmap it.
1401 * The mmap call will end up in drm_gem_mmap(), which will set things
1402 * up so we can get faults in the handler above.
1404 * The fault handler will take care of binding the object into the GTT
1405 * (since it may have been evicted to make room for something), allocating
1406 * a fence register, and mapping the appropriate aperture address into
1410 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1411 struct drm_file
*file_priv
)
1413 struct drm_i915_gem_mmap_gtt
*args
= data
;
1414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1415 struct drm_gem_object
*obj
;
1416 struct drm_i915_gem_object
*obj_priv
;
1419 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1422 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1426 mutex_lock(&dev
->struct_mutex
);
1428 obj_priv
= obj
->driver_private
;
1430 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1431 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1432 drm_gem_object_unreference(obj
);
1433 mutex_unlock(&dev
->struct_mutex
);
1438 if (!obj_priv
->mmap_offset
) {
1439 ret
= i915_gem_create_mmap_offset(obj
);
1441 drm_gem_object_unreference(obj
);
1442 mutex_unlock(&dev
->struct_mutex
);
1447 args
->offset
= obj_priv
->mmap_offset
;
1450 * Pull it into the GTT so that we have a page list (makes the
1451 * initial fault faster and any subsequent flushing possible).
1453 if (!obj_priv
->agp_mem
) {
1454 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1456 drm_gem_object_unreference(obj
);
1457 mutex_unlock(&dev
->struct_mutex
);
1460 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1463 drm_gem_object_unreference(obj
);
1464 mutex_unlock(&dev
->struct_mutex
);
1470 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1472 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1473 int page_count
= obj
->size
/ PAGE_SIZE
;
1476 BUG_ON(obj_priv
->pages_refcount
== 0);
1477 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1479 if (--obj_priv
->pages_refcount
!= 0)
1482 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1483 i915_gem_object_save_bit_17_swizzle(obj
);
1485 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1486 obj_priv
->dirty
= 0;
1488 for (i
= 0; i
< page_count
; i
++) {
1489 if (obj_priv
->pages
[i
] == NULL
)
1492 if (obj_priv
->dirty
)
1493 set_page_dirty(obj_priv
->pages
[i
]);
1495 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1496 mark_page_accessed(obj_priv
->pages
[i
]);
1498 page_cache_release(obj_priv
->pages
[i
]);
1500 obj_priv
->dirty
= 0;
1502 drm_free_large(obj_priv
->pages
);
1503 obj_priv
->pages
= NULL
;
1507 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1513 /* Add a reference if we're newly entering the active list. */
1514 if (!obj_priv
->active
) {
1515 drm_gem_object_reference(obj
);
1516 obj_priv
->active
= 1;
1518 /* Move from whatever list we were on to the tail of execution. */
1519 spin_lock(&dev_priv
->mm
.active_list_lock
);
1520 list_move_tail(&obj_priv
->list
,
1521 &dev_priv
->mm
.active_list
);
1522 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1523 obj_priv
->last_rendering_seqno
= seqno
;
1527 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1529 struct drm_device
*dev
= obj
->dev
;
1530 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1531 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1533 BUG_ON(!obj_priv
->active
);
1534 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1535 obj_priv
->last_rendering_seqno
= 0;
1538 /* Immediately discard the backing storage */
1540 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1542 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1543 struct inode
*inode
;
1545 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1546 if (inode
->i_op
->truncate
)
1547 inode
->i_op
->truncate (inode
);
1549 obj_priv
->madv
= __I915_MADV_PURGED
;
1553 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1555 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1559 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1561 struct drm_device
*dev
= obj
->dev
;
1562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1563 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1565 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1566 if (obj_priv
->pin_count
!= 0)
1567 list_del_init(&obj_priv
->list
);
1569 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1571 obj_priv
->last_rendering_seqno
= 0;
1572 if (obj_priv
->active
) {
1573 obj_priv
->active
= 0;
1574 drm_gem_object_unreference(obj
);
1576 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1580 * Creates a new sequence number, emitting a write of it to the status page
1581 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1583 * Must be called with struct_lock held.
1585 * Returned sequence numbers are nonzero on success.
1588 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1589 uint32_t flush_domains
)
1591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1592 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1593 struct drm_i915_gem_request
*request
;
1598 if (file_priv
!= NULL
)
1599 i915_file_priv
= file_priv
->driver_priv
;
1601 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1602 if (request
== NULL
)
1605 /* Grab the seqno we're going to make this request be, and bump the
1606 * next (skipping 0 so it can be the reserved no-seqno value).
1608 seqno
= dev_priv
->mm
.next_gem_seqno
;
1609 dev_priv
->mm
.next_gem_seqno
++;
1610 if (dev_priv
->mm
.next_gem_seqno
== 0)
1611 dev_priv
->mm
.next_gem_seqno
++;
1614 OUT_RING(MI_STORE_DWORD_INDEX
);
1615 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1618 OUT_RING(MI_USER_INTERRUPT
);
1621 DRM_DEBUG_DRIVER("%d\n", seqno
);
1623 request
->seqno
= seqno
;
1624 request
->emitted_jiffies
= jiffies
;
1625 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1626 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1627 if (i915_file_priv
) {
1628 list_add_tail(&request
->client_list
,
1629 &i915_file_priv
->mm
.request_list
);
1631 INIT_LIST_HEAD(&request
->client_list
);
1634 /* Associate any objects on the flushing list matching the write
1635 * domain we're flushing with our flush.
1637 if (flush_domains
!= 0) {
1638 struct drm_i915_gem_object
*obj_priv
, *next
;
1640 list_for_each_entry_safe(obj_priv
, next
,
1641 &dev_priv
->mm
.flushing_list
, list
) {
1642 struct drm_gem_object
*obj
= obj_priv
->obj
;
1644 if ((obj
->write_domain
& flush_domains
) ==
1645 obj
->write_domain
) {
1646 uint32_t old_write_domain
= obj
->write_domain
;
1648 obj
->write_domain
= 0;
1649 i915_gem_object_move_to_active(obj
, seqno
);
1651 trace_i915_gem_object_change_domain(obj
,
1659 if (!dev_priv
->mm
.suspended
) {
1660 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1662 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1668 * Command execution barrier
1670 * Ensures that all commands in the ring are finished
1671 * before signalling the CPU
1674 i915_retire_commands(struct drm_device
*dev
)
1676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1677 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1678 uint32_t flush_domains
= 0;
1681 /* The sampler always gets flushed on i965 (sigh) */
1683 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1686 OUT_RING(0); /* noop */
1688 return flush_domains
;
1692 * Moves buffers associated only with the given active seqno from the active
1693 * to inactive list, potentially freeing them.
1696 i915_gem_retire_request(struct drm_device
*dev
,
1697 struct drm_i915_gem_request
*request
)
1699 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1701 trace_i915_gem_request_retire(dev
, request
->seqno
);
1703 /* Move any buffers on the active list that are no longer referenced
1704 * by the ringbuffer to the flushing/inactive lists as appropriate.
1706 spin_lock(&dev_priv
->mm
.active_list_lock
);
1707 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1708 struct drm_gem_object
*obj
;
1709 struct drm_i915_gem_object
*obj_priv
;
1711 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1712 struct drm_i915_gem_object
,
1714 obj
= obj_priv
->obj
;
1716 /* If the seqno being retired doesn't match the oldest in the
1717 * list, then the oldest in the list must still be newer than
1720 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1724 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1725 __func__
, request
->seqno
, obj
);
1728 if (obj
->write_domain
!= 0)
1729 i915_gem_object_move_to_flushing(obj
);
1731 /* Take a reference on the object so it won't be
1732 * freed while the spinlock is held. The list
1733 * protection for this spinlock is safe when breaking
1734 * the lock like this since the next thing we do
1735 * is just get the head of the list again.
1737 drm_gem_object_reference(obj
);
1738 i915_gem_object_move_to_inactive(obj
);
1739 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1740 drm_gem_object_unreference(obj
);
1741 spin_lock(&dev_priv
->mm
.active_list_lock
);
1745 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1749 * Returns true if seq1 is later than seq2.
1752 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1754 return (int32_t)(seq1
- seq2
) >= 0;
1758 i915_get_gem_seqno(struct drm_device
*dev
)
1760 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1762 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1766 * This function clears the request list as sequence numbers are passed.
1769 i915_gem_retire_requests(struct drm_device
*dev
)
1771 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1774 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1777 seqno
= i915_get_gem_seqno(dev
);
1779 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1780 struct drm_i915_gem_request
*request
;
1781 uint32_t retiring_seqno
;
1783 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1784 struct drm_i915_gem_request
,
1786 retiring_seqno
= request
->seqno
;
1788 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1789 atomic_read(&dev_priv
->mm
.wedged
)) {
1790 i915_gem_retire_request(dev
, request
);
1792 list_del(&request
->list
);
1793 list_del(&request
->client_list
);
1799 if (unlikely (dev_priv
->trace_irq_seqno
&&
1800 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1801 i915_user_irq_put(dev
);
1802 dev_priv
->trace_irq_seqno
= 0;
1807 i915_gem_retire_work_handler(struct work_struct
*work
)
1809 drm_i915_private_t
*dev_priv
;
1810 struct drm_device
*dev
;
1812 dev_priv
= container_of(work
, drm_i915_private_t
,
1813 mm
.retire_work
.work
);
1814 dev
= dev_priv
->dev
;
1816 mutex_lock(&dev
->struct_mutex
);
1817 i915_gem_retire_requests(dev
);
1818 if (!dev_priv
->mm
.suspended
&&
1819 !list_empty(&dev_priv
->mm
.request_list
))
1820 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1821 mutex_unlock(&dev
->struct_mutex
);
1825 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1827 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1833 if (atomic_read(&dev_priv
->mm
.wedged
))
1836 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1837 if (IS_IRONLAKE(dev
))
1838 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1840 ier
= I915_READ(IER
);
1842 DRM_ERROR("something (likely vbetool) disabled "
1843 "interrupts, re-enabling\n");
1844 i915_driver_irq_preinstall(dev
);
1845 i915_driver_irq_postinstall(dev
);
1848 trace_i915_gem_request_wait_begin(dev
, seqno
);
1850 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1851 i915_user_irq_get(dev
);
1853 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1854 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1855 atomic_read(&dev_priv
->mm
.wedged
));
1857 wait_event(dev_priv
->irq_queue
,
1858 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1859 atomic_read(&dev_priv
->mm
.wedged
));
1861 i915_user_irq_put(dev
);
1862 dev_priv
->mm
.waiting_gem_seqno
= 0;
1864 trace_i915_gem_request_wait_end(dev
, seqno
);
1866 if (atomic_read(&dev_priv
->mm
.wedged
))
1869 if (ret
&& ret
!= -ERESTARTSYS
)
1870 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1871 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1873 /* Directly dispatch request retiring. While we have the work queue
1874 * to handle this, the waiter on a request often wants an associated
1875 * buffer to have made it to the inactive list, and we would need
1876 * a separate wait queue to handle that.
1879 i915_gem_retire_requests(dev
);
1885 * Waits for a sequence number to be signaled, and cleans up the
1886 * request and object lists appropriately for that event.
1889 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1891 return i915_do_wait_request(dev
, seqno
, 1);
1895 i915_gem_flush(struct drm_device
*dev
,
1896 uint32_t invalidate_domains
,
1897 uint32_t flush_domains
)
1899 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1904 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1905 invalidate_domains
, flush_domains
);
1907 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1908 invalidate_domains
, flush_domains
);
1910 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1911 drm_agp_chipset_flush(dev
);
1913 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1915 * read/write caches:
1917 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1918 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1919 * also flushed at 2d versus 3d pipeline switches.
1923 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1924 * MI_READ_FLUSH is set, and is always flushed on 965.
1926 * I915_GEM_DOMAIN_COMMAND may not exist?
1928 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1929 * invalidated when MI_EXE_FLUSH is set.
1931 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1932 * invalidated with every MI_FLUSH.
1936 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1937 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1938 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1939 * are flushed at any MI_FLUSH.
1942 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1943 if ((invalidate_domains
|flush_domains
) &
1944 I915_GEM_DOMAIN_RENDER
)
1945 cmd
&= ~MI_NO_WRITE_FLUSH
;
1946 if (!IS_I965G(dev
)) {
1948 * On the 965, the sampler cache always gets flushed
1949 * and this bit is reserved.
1951 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1952 cmd
|= MI_READ_FLUSH
;
1954 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1955 cmd
|= MI_EXE_FLUSH
;
1958 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1968 * Ensures that all rendering to the object has completed and the object is
1969 * safe to unbind from the GTT or access from the CPU.
1972 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1974 struct drm_device
*dev
= obj
->dev
;
1975 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1978 /* This function only exists to support waiting for existing rendering,
1979 * not for emitting required flushes.
1981 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1983 /* If there is rendering queued on the buffer being evicted, wait for
1986 if (obj_priv
->active
) {
1988 DRM_INFO("%s: object %p wait for seqno %08x\n",
1989 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1991 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
2000 * Unbinds an object from the GTT aperture.
2003 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2005 struct drm_device
*dev
= obj
->dev
;
2006 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2010 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
2011 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
2013 if (obj_priv
->gtt_space
== NULL
)
2016 if (obj_priv
->pin_count
!= 0) {
2017 DRM_ERROR("Attempting to unbind pinned buffer\n");
2021 /* blow away mappings if mapped through GTT */
2022 i915_gem_release_mmap(obj
);
2024 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2025 i915_gem_clear_fence_reg(obj
);
2027 /* Move the object to the CPU domain to ensure that
2028 * any possible CPU writes while it's not in the GTT
2029 * are flushed when we go to remap it. This will
2030 * also ensure that all pending GPU writes are finished
2033 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2035 if (ret
!= -ERESTARTSYS
)
2036 DRM_ERROR("set_domain failed: %d\n", ret
);
2040 BUG_ON(obj_priv
->active
);
2042 if (obj_priv
->agp_mem
!= NULL
) {
2043 drm_unbind_agp(obj_priv
->agp_mem
);
2044 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2045 obj_priv
->agp_mem
= NULL
;
2048 i915_gem_object_put_pages(obj
);
2049 BUG_ON(obj_priv
->pages_refcount
);
2051 if (obj_priv
->gtt_space
) {
2052 atomic_dec(&dev
->gtt_count
);
2053 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2055 drm_mm_put_block(obj_priv
->gtt_space
);
2056 obj_priv
->gtt_space
= NULL
;
2059 /* Remove ourselves from the LRU list if present. */
2060 if (!list_empty(&obj_priv
->list
))
2061 list_del_init(&obj_priv
->list
);
2063 if (i915_gem_object_is_purgeable(obj_priv
))
2064 i915_gem_object_truncate(obj
);
2066 trace_i915_gem_object_unbind(obj
);
2071 static struct drm_gem_object
*
2072 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2074 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2075 struct drm_i915_gem_object
*obj_priv
;
2076 struct drm_gem_object
*best
= NULL
;
2077 struct drm_gem_object
*first
= NULL
;
2079 /* Try to find the smallest clean object */
2080 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2081 struct drm_gem_object
*obj
= obj_priv
->obj
;
2082 if (obj
->size
>= min_size
) {
2083 if ((!obj_priv
->dirty
||
2084 i915_gem_object_is_purgeable(obj_priv
)) &&
2085 (!best
|| obj
->size
< best
->size
)) {
2087 if (best
->size
== min_size
)
2095 return best
? best
: first
;
2099 i915_gem_evict_everything(struct drm_device
*dev
)
2101 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2106 spin_lock(&dev_priv
->mm
.active_list_lock
);
2107 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2108 list_empty(&dev_priv
->mm
.flushing_list
) &&
2109 list_empty(&dev_priv
->mm
.active_list
));
2110 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2115 /* Flush everything (on to the inactive lists) and evict */
2116 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2117 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2121 ret
= i915_wait_request(dev
, seqno
);
2125 ret
= i915_gem_evict_from_inactive_list(dev
);
2129 spin_lock(&dev_priv
->mm
.active_list_lock
);
2130 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2131 list_empty(&dev_priv
->mm
.flushing_list
) &&
2132 list_empty(&dev_priv
->mm
.active_list
));
2133 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2134 BUG_ON(!lists_empty
);
2140 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2142 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2143 struct drm_gem_object
*obj
;
2147 i915_gem_retire_requests(dev
);
2149 /* If there's an inactive buffer available now, grab it
2152 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2154 struct drm_i915_gem_object
*obj_priv
;
2157 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2159 obj_priv
= obj
->driver_private
;
2160 BUG_ON(obj_priv
->pin_count
!= 0);
2161 BUG_ON(obj_priv
->active
);
2163 /* Wait on the rendering and unbind the buffer. */
2164 return i915_gem_object_unbind(obj
);
2167 /* If we didn't get anything, but the ring is still processing
2168 * things, wait for the next to finish and hopefully leave us
2169 * a buffer to evict.
2171 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2172 struct drm_i915_gem_request
*request
;
2174 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2175 struct drm_i915_gem_request
,
2178 ret
= i915_wait_request(dev
, request
->seqno
);
2185 /* If we didn't have anything on the request list but there
2186 * are buffers awaiting a flush, emit one and try again.
2187 * When we wait on it, those buffers waiting for that flush
2188 * will get moved to inactive.
2190 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2191 struct drm_i915_gem_object
*obj_priv
;
2193 /* Find an object that we can immediately reuse */
2194 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2195 obj
= obj_priv
->obj
;
2196 if (obj
->size
>= min_size
)
2208 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2212 ret
= i915_wait_request(dev
, seqno
);
2220 /* If we didn't do any of the above, there's no single buffer
2221 * large enough to swap out for the new one, so just evict
2222 * everything and start again. (This should be rare.)
2224 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2225 return i915_gem_evict_from_inactive_list(dev
);
2227 return i915_gem_evict_everything(dev
);
2232 i915_gem_object_get_pages(struct drm_gem_object
*obj
)
2234 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2236 struct address_space
*mapping
;
2237 struct inode
*inode
;
2241 if (obj_priv
->pages_refcount
++ != 0)
2244 /* Get the list of pages out of our struct file. They'll be pinned
2245 * at this point until we release them.
2247 page_count
= obj
->size
/ PAGE_SIZE
;
2248 BUG_ON(obj_priv
->pages
!= NULL
);
2249 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2250 if (obj_priv
->pages
== NULL
) {
2251 obj_priv
->pages_refcount
--;
2255 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2256 mapping
= inode
->i_mapping
;
2257 for (i
= 0; i
< page_count
; i
++) {
2258 page
= read_mapping_page(mapping
, i
, NULL
);
2260 ret
= PTR_ERR(page
);
2261 i915_gem_object_put_pages(obj
);
2264 obj_priv
->pages
[i
] = page
;
2267 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2268 i915_gem_object_do_bit_17_swizzle(obj
);
2273 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2275 struct drm_gem_object
*obj
= reg
->obj
;
2276 struct drm_device
*dev
= obj
->dev
;
2277 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2278 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2279 int regnum
= obj_priv
->fence_reg
;
2282 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2284 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2285 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2286 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2287 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2288 val
|= I965_FENCE_REG_VALID
;
2290 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2293 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2295 struct drm_gem_object
*obj
= reg
->obj
;
2296 struct drm_device
*dev
= obj
->dev
;
2297 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2298 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2299 int regnum
= obj_priv
->fence_reg
;
2301 uint32_t fence_reg
, val
;
2304 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2305 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2306 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2307 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2311 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2312 HAS_128_BYTE_Y_TILING(dev
))
2317 /* Note: pitch better be a power of two tile widths */
2318 pitch_val
= obj_priv
->stride
/ tile_width
;
2319 pitch_val
= ffs(pitch_val
) - 1;
2321 val
= obj_priv
->gtt_offset
;
2322 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2323 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2324 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2325 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2326 val
|= I830_FENCE_REG_VALID
;
2329 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2331 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2332 I915_WRITE(fence_reg
, val
);
2335 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2337 struct drm_gem_object
*obj
= reg
->obj
;
2338 struct drm_device
*dev
= obj
->dev
;
2339 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2340 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2341 int regnum
= obj_priv
->fence_reg
;
2344 uint32_t fence_size_bits
;
2346 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2347 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2348 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2349 __func__
, obj_priv
->gtt_offset
);
2353 pitch_val
= obj_priv
->stride
/ 128;
2354 pitch_val
= ffs(pitch_val
) - 1;
2355 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2357 val
= obj_priv
->gtt_offset
;
2358 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2359 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2360 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2361 WARN_ON(fence_size_bits
& ~0x00000f00);
2362 val
|= fence_size_bits
;
2363 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2364 val
|= I830_FENCE_REG_VALID
;
2366 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2370 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2371 * @obj: object to map through a fence reg
2373 * When mapping objects through the GTT, userspace wants to be able to write
2374 * to them without having to worry about swizzling if the object is tiled.
2376 * This function walks the fence regs looking for a free one for @obj,
2377 * stealing one if it can't find any.
2379 * It then sets up the reg based on the object's properties: address, pitch
2380 * and tiling format.
2383 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2385 struct drm_device
*dev
= obj
->dev
;
2386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2387 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2388 struct drm_i915_fence_reg
*reg
= NULL
;
2389 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2392 /* Just update our place in the LRU if our fence is getting used. */
2393 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2394 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2398 switch (obj_priv
->tiling_mode
) {
2399 case I915_TILING_NONE
:
2400 WARN(1, "allocating a fence for non-tiled object?\n");
2403 if (!obj_priv
->stride
)
2405 WARN((obj_priv
->stride
& (512 - 1)),
2406 "object 0x%08x is X tiled but has non-512B pitch\n",
2407 obj_priv
->gtt_offset
);
2410 if (!obj_priv
->stride
)
2412 WARN((obj_priv
->stride
& (128 - 1)),
2413 "object 0x%08x is Y tiled but has non-128B pitch\n",
2414 obj_priv
->gtt_offset
);
2418 /* First try to find a free reg */
2420 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2421 reg
= &dev_priv
->fence_regs
[i
];
2425 old_obj_priv
= reg
->obj
->driver_private
;
2426 if (!old_obj_priv
->pin_count
)
2430 /* None available, try to steal one or wait for a user to finish */
2431 if (i
== dev_priv
->num_fence_regs
) {
2432 struct drm_gem_object
*old_obj
= NULL
;
2437 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2439 old_obj
= old_obj_priv
->obj
;
2441 if (old_obj_priv
->pin_count
)
2444 /* Take a reference, as otherwise the wait_rendering
2445 * below may cause the object to get freed out from
2448 drm_gem_object_reference(old_obj
);
2450 /* i915 uses fences for GPU access to tiled buffers */
2451 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2454 /* This brings the object to the head of the LRU if it
2455 * had been written to. The only way this should
2456 * result in us waiting longer than the expected
2457 * optimal amount of time is if there was a
2458 * fence-using buffer later that was read-only.
2460 i915_gem_object_flush_gpu_write_domain(old_obj
);
2461 ret
= i915_gem_object_wait_rendering(old_obj
);
2463 drm_gem_object_unreference(old_obj
);
2471 * Zap this virtual mapping so we can set up a fence again
2472 * for this object next time we need it.
2474 i915_gem_release_mmap(old_obj
);
2476 i
= old_obj_priv
->fence_reg
;
2477 reg
= &dev_priv
->fence_regs
[i
];
2479 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2480 list_del_init(&old_obj_priv
->fence_list
);
2482 drm_gem_object_unreference(old_obj
);
2485 obj_priv
->fence_reg
= i
;
2486 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2491 i965_write_fence_reg(reg
);
2492 else if (IS_I9XX(dev
))
2493 i915_write_fence_reg(reg
);
2495 i830_write_fence_reg(reg
);
2497 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2503 * i915_gem_clear_fence_reg - clear out fence register info
2504 * @obj: object to clear
2506 * Zeroes out the fence register itself and clears out the associated
2507 * data structures in dev_priv and obj_priv.
2510 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2512 struct drm_device
*dev
= obj
->dev
;
2513 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2514 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2517 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2521 if (obj_priv
->fence_reg
< 8)
2522 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2524 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2527 I915_WRITE(fence_reg
, 0);
2530 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2531 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2532 list_del_init(&obj_priv
->fence_list
);
2536 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2537 * to the buffer to finish, and then resets the fence register.
2538 * @obj: tiled object holding a fence register.
2540 * Zeroes out the fence register itself and clears out the associated
2541 * data structures in dev_priv and obj_priv.
2544 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2546 struct drm_device
*dev
= obj
->dev
;
2547 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2549 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2552 /* On the i915, GPU access to tiled buffers is via a fence,
2553 * therefore we must wait for any outstanding access to complete
2554 * before clearing the fence.
2556 if (!IS_I965G(dev
)) {
2559 i915_gem_object_flush_gpu_write_domain(obj
);
2560 i915_gem_object_flush_gtt_write_domain(obj
);
2561 ret
= i915_gem_object_wait_rendering(obj
);
2566 i915_gem_clear_fence_reg (obj
);
2572 * Finds free space in the GTT aperture and binds the object there.
2575 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2577 struct drm_device
*dev
= obj
->dev
;
2578 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2579 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2580 struct drm_mm_node
*free_space
;
2581 bool retry_alloc
= false;
2584 if (dev_priv
->mm
.suspended
)
2587 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2588 DRM_ERROR("Attempting to bind a purgeable object\n");
2593 alignment
= i915_gem_get_gtt_alignment(obj
);
2594 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2595 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2600 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2601 obj
->size
, alignment
, 0);
2602 if (free_space
!= NULL
) {
2603 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2605 if (obj_priv
->gtt_space
!= NULL
) {
2606 obj_priv
->gtt_space
->private = obj
;
2607 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2610 if (obj_priv
->gtt_space
== NULL
) {
2611 /* If the gtt is empty and we're still having trouble
2612 * fitting our object in, we're out of memory.
2615 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2617 ret
= i915_gem_evict_something(dev
, obj
->size
);
2625 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2626 obj
->size
, obj_priv
->gtt_offset
);
2629 i915_gem_object_set_page_gfp_mask (obj
,
2630 i915_gem_object_get_page_gfp_mask (obj
) & ~__GFP_NORETRY
);
2632 ret
= i915_gem_object_get_pages(obj
);
2634 i915_gem_object_set_page_gfp_mask (obj
,
2635 i915_gem_object_get_page_gfp_mask (obj
) | __GFP_NORETRY
);
2638 drm_mm_put_block(obj_priv
->gtt_space
);
2639 obj_priv
->gtt_space
= NULL
;
2641 if (ret
== -ENOMEM
) {
2642 /* first try to clear up some space from the GTT */
2643 ret
= i915_gem_evict_something(dev
, obj
->size
);
2645 /* now try to shrink everyone else */
2646 if (! retry_alloc
) {
2660 /* Create an AGP memory structure pointing at our pages, and bind it
2663 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2665 obj
->size
>> PAGE_SHIFT
,
2666 obj_priv
->gtt_offset
,
2667 obj_priv
->agp_type
);
2668 if (obj_priv
->agp_mem
== NULL
) {
2669 i915_gem_object_put_pages(obj
);
2670 drm_mm_put_block(obj_priv
->gtt_space
);
2671 obj_priv
->gtt_space
= NULL
;
2673 ret
= i915_gem_evict_something(dev
, obj
->size
);
2679 atomic_inc(&dev
->gtt_count
);
2680 atomic_add(obj
->size
, &dev
->gtt_memory
);
2682 /* Assert that the object is not currently in any GPU domain. As it
2683 * wasn't in the GTT, there shouldn't be any way it could have been in
2686 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2687 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2689 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2695 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2697 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2699 /* If we don't have a page list set up, then we're not pinned
2700 * to GPU, and we can ignore the cache flush because it'll happen
2701 * again at bind time.
2703 if (obj_priv
->pages
== NULL
)
2706 trace_i915_gem_object_clflush(obj
);
2708 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2711 /** Flushes any GPU write domain for the object if it's dirty. */
2713 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2715 struct drm_device
*dev
= obj
->dev
;
2717 uint32_t old_write_domain
;
2719 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2722 /* Queue the GPU write cache flushing we need. */
2723 old_write_domain
= obj
->write_domain
;
2724 i915_gem_flush(dev
, 0, obj
->write_domain
);
2725 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2726 obj
->write_domain
= 0;
2727 i915_gem_object_move_to_active(obj
, seqno
);
2729 trace_i915_gem_object_change_domain(obj
,
2734 /** Flushes the GTT write domain for the object if it's dirty. */
2736 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2738 uint32_t old_write_domain
;
2740 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2743 /* No actual flushing is required for the GTT write domain. Writes
2744 * to it immediately go to main memory as far as we know, so there's
2745 * no chipset flush. It also doesn't land in render cache.
2747 old_write_domain
= obj
->write_domain
;
2748 obj
->write_domain
= 0;
2750 trace_i915_gem_object_change_domain(obj
,
2755 /** Flushes the CPU write domain for the object if it's dirty. */
2757 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2759 struct drm_device
*dev
= obj
->dev
;
2760 uint32_t old_write_domain
;
2762 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2765 i915_gem_clflush_object(obj
);
2766 drm_agp_chipset_flush(dev
);
2767 old_write_domain
= obj
->write_domain
;
2768 obj
->write_domain
= 0;
2770 trace_i915_gem_object_change_domain(obj
,
2776 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2778 switch (obj
->write_domain
) {
2779 case I915_GEM_DOMAIN_GTT
:
2780 i915_gem_object_flush_gtt_write_domain(obj
);
2782 case I915_GEM_DOMAIN_CPU
:
2783 i915_gem_object_flush_cpu_write_domain(obj
);
2786 i915_gem_object_flush_gpu_write_domain(obj
);
2792 * Moves a single object to the GTT read, and possibly write domain.
2794 * This function returns when the move is complete, including waiting on
2798 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2800 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2801 uint32_t old_write_domain
, old_read_domains
;
2804 /* Not valid to be called on unbound objects. */
2805 if (obj_priv
->gtt_space
== NULL
)
2808 i915_gem_object_flush_gpu_write_domain(obj
);
2809 /* Wait on any GPU rendering and flushing to occur. */
2810 ret
= i915_gem_object_wait_rendering(obj
);
2814 old_write_domain
= obj
->write_domain
;
2815 old_read_domains
= obj
->read_domains
;
2817 /* If we're writing through the GTT domain, then CPU and GPU caches
2818 * will need to be invalidated at next use.
2821 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2823 i915_gem_object_flush_cpu_write_domain(obj
);
2825 /* It should now be out of any other write domains, and we can update
2826 * the domain values for our changes.
2828 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2829 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2831 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2832 obj_priv
->dirty
= 1;
2835 trace_i915_gem_object_change_domain(obj
,
2843 * Moves a single object to the CPU read, and possibly write domain.
2845 * This function returns when the move is complete, including waiting on
2849 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2851 uint32_t old_write_domain
, old_read_domains
;
2854 i915_gem_object_flush_gpu_write_domain(obj
);
2855 /* Wait on any GPU rendering and flushing to occur. */
2856 ret
= i915_gem_object_wait_rendering(obj
);
2860 i915_gem_object_flush_gtt_write_domain(obj
);
2862 /* If we have a partially-valid cache of the object in the CPU,
2863 * finish invalidating it and free the per-page flags.
2865 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2867 old_write_domain
= obj
->write_domain
;
2868 old_read_domains
= obj
->read_domains
;
2870 /* Flush the CPU cache if it's still invalid. */
2871 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2872 i915_gem_clflush_object(obj
);
2874 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2877 /* It should now be out of any other write domains, and we can update
2878 * the domain values for our changes.
2880 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2882 /* If we're writing through the CPU, then the GPU read domains will
2883 * need to be invalidated at next use.
2886 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2887 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2890 trace_i915_gem_object_change_domain(obj
,
2898 * Set the next domain for the specified object. This
2899 * may not actually perform the necessary flushing/invaliding though,
2900 * as that may want to be batched with other set_domain operations
2902 * This is (we hope) the only really tricky part of gem. The goal
2903 * is fairly simple -- track which caches hold bits of the object
2904 * and make sure they remain coherent. A few concrete examples may
2905 * help to explain how it works. For shorthand, we use the notation
2906 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2907 * a pair of read and write domain masks.
2909 * Case 1: the batch buffer
2915 * 5. Unmapped from GTT
2918 * Let's take these a step at a time
2921 * Pages allocated from the kernel may still have
2922 * cache contents, so we set them to (CPU, CPU) always.
2923 * 2. Written by CPU (using pwrite)
2924 * The pwrite function calls set_domain (CPU, CPU) and
2925 * this function does nothing (as nothing changes)
2927 * This function asserts that the object is not
2928 * currently in any GPU-based read or write domains
2930 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2931 * As write_domain is zero, this function adds in the
2932 * current read domains (CPU+COMMAND, 0).
2933 * flush_domains is set to CPU.
2934 * invalidate_domains is set to COMMAND
2935 * clflush is run to get data out of the CPU caches
2936 * then i915_dev_set_domain calls i915_gem_flush to
2937 * emit an MI_FLUSH and drm_agp_chipset_flush
2938 * 5. Unmapped from GTT
2939 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2940 * flush_domains and invalidate_domains end up both zero
2941 * so no flushing/invalidating happens
2945 * Case 2: The shared render buffer
2949 * 3. Read/written by GPU
2950 * 4. set_domain to (CPU,CPU)
2951 * 5. Read/written by CPU
2952 * 6. Read/written by GPU
2955 * Same as last example, (CPU, CPU)
2957 * Nothing changes (assertions find that it is not in the GPU)
2958 * 3. Read/written by GPU
2959 * execbuffer calls set_domain (RENDER, RENDER)
2960 * flush_domains gets CPU
2961 * invalidate_domains gets GPU
2963 * MI_FLUSH and drm_agp_chipset_flush
2964 * 4. set_domain (CPU, CPU)
2965 * flush_domains gets GPU
2966 * invalidate_domains gets CPU
2967 * wait_rendering (obj) to make sure all drawing is complete.
2968 * This will include an MI_FLUSH to get the data from GPU
2970 * clflush (obj) to invalidate the CPU cache
2971 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2972 * 5. Read/written by CPU
2973 * cache lines are loaded and dirtied
2974 * 6. Read written by GPU
2975 * Same as last GPU access
2977 * Case 3: The constant buffer
2982 * 4. Updated (written) by CPU again
2991 * flush_domains = CPU
2992 * invalidate_domains = RENDER
2995 * drm_agp_chipset_flush
2996 * 4. Updated (written) by CPU again
2998 * flush_domains = 0 (no previous write domain)
2999 * invalidate_domains = 0 (no new read domains)
3002 * flush_domains = CPU
3003 * invalidate_domains = RENDER
3006 * drm_agp_chipset_flush
3009 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3011 struct drm_device
*dev
= obj
->dev
;
3012 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3013 uint32_t invalidate_domains
= 0;
3014 uint32_t flush_domains
= 0;
3015 uint32_t old_read_domains
;
3017 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3018 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3020 intel_mark_busy(dev
, obj
);
3023 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3025 obj
->read_domains
, obj
->pending_read_domains
,
3026 obj
->write_domain
, obj
->pending_write_domain
);
3029 * If the object isn't moving to a new write domain,
3030 * let the object stay in multiple read domains
3032 if (obj
->pending_write_domain
== 0)
3033 obj
->pending_read_domains
|= obj
->read_domains
;
3035 obj_priv
->dirty
= 1;
3038 * Flush the current write domain if
3039 * the new read domains don't match. Invalidate
3040 * any read domains which differ from the old
3043 if (obj
->write_domain
&&
3044 obj
->write_domain
!= obj
->pending_read_domains
) {
3045 flush_domains
|= obj
->write_domain
;
3046 invalidate_domains
|=
3047 obj
->pending_read_domains
& ~obj
->write_domain
;
3050 * Invalidate any read caches which may have
3051 * stale data. That is, any new read domains.
3053 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3054 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3056 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3057 __func__
, flush_domains
, invalidate_domains
);
3059 i915_gem_clflush_object(obj
);
3062 old_read_domains
= obj
->read_domains
;
3064 /* The actual obj->write_domain will be updated with
3065 * pending_write_domain after we emit the accumulated flush for all
3066 * of our domain changes in execbuffers (which clears objects'
3067 * write_domains). So if we have a current write domain that we
3068 * aren't changing, set pending_write_domain to that.
3070 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3071 obj
->pending_write_domain
= obj
->write_domain
;
3072 obj
->read_domains
= obj
->pending_read_domains
;
3074 dev
->invalidate_domains
|= invalidate_domains
;
3075 dev
->flush_domains
|= flush_domains
;
3077 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3079 obj
->read_domains
, obj
->write_domain
,
3080 dev
->invalidate_domains
, dev
->flush_domains
);
3083 trace_i915_gem_object_change_domain(obj
,
3089 * Moves the object from a partially CPU read to a full one.
3091 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3092 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3095 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3097 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3099 if (!obj_priv
->page_cpu_valid
)
3102 /* If we're partially in the CPU read domain, finish moving it in.
3104 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3107 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3108 if (obj_priv
->page_cpu_valid
[i
])
3110 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3114 /* Free the page_cpu_valid mappings which are now stale, whether
3115 * or not we've got I915_GEM_DOMAIN_CPU.
3117 kfree(obj_priv
->page_cpu_valid
);
3118 obj_priv
->page_cpu_valid
= NULL
;
3122 * Set the CPU read domain on a range of the object.
3124 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3125 * not entirely valid. The page_cpu_valid member of the object flags which
3126 * pages have been flushed, and will be respected by
3127 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3128 * of the whole object.
3130 * This function returns when the move is complete, including waiting on
3134 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3135 uint64_t offset
, uint64_t size
)
3137 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3138 uint32_t old_read_domains
;
3141 if (offset
== 0 && size
== obj
->size
)
3142 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3144 i915_gem_object_flush_gpu_write_domain(obj
);
3145 /* Wait on any GPU rendering and flushing to occur. */
3146 ret
= i915_gem_object_wait_rendering(obj
);
3149 i915_gem_object_flush_gtt_write_domain(obj
);
3151 /* If we're already fully in the CPU read domain, we're done. */
3152 if (obj_priv
->page_cpu_valid
== NULL
&&
3153 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3156 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3157 * newly adding I915_GEM_DOMAIN_CPU
3159 if (obj_priv
->page_cpu_valid
== NULL
) {
3160 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3162 if (obj_priv
->page_cpu_valid
== NULL
)
3164 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3165 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3167 /* Flush the cache on any pages that are still invalid from the CPU's
3170 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3172 if (obj_priv
->page_cpu_valid
[i
])
3175 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3177 obj_priv
->page_cpu_valid
[i
] = 1;
3180 /* It should now be out of any other write domains, and we can update
3181 * the domain values for our changes.
3183 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3185 old_read_domains
= obj
->read_domains
;
3186 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3188 trace_i915_gem_object_change_domain(obj
,
3196 * Pin an object to the GTT and evaluate the relocations landing in it.
3199 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3200 struct drm_file
*file_priv
,
3201 struct drm_i915_gem_exec_object
*entry
,
3202 struct drm_i915_gem_relocation_entry
*relocs
)
3204 struct drm_device
*dev
= obj
->dev
;
3205 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3206 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3208 void __iomem
*reloc_page
;
3210 /* Choose the GTT offset for our buffer and put it there. */
3211 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3215 entry
->offset
= obj_priv
->gtt_offset
;
3217 /* Apply the relocations, using the GTT aperture to avoid cache
3218 * flushing requirements.
3220 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3221 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3222 struct drm_gem_object
*target_obj
;
3223 struct drm_i915_gem_object
*target_obj_priv
;
3224 uint32_t reloc_val
, reloc_offset
;
3225 uint32_t __iomem
*reloc_entry
;
3227 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3228 reloc
->target_handle
);
3229 if (target_obj
== NULL
) {
3230 i915_gem_object_unpin(obj
);
3233 target_obj_priv
= target_obj
->driver_private
;
3236 DRM_INFO("%s: obj %p offset %08x target %d "
3237 "read %08x write %08x gtt %08x "
3238 "presumed %08x delta %08x\n",
3241 (int) reloc
->offset
,
3242 (int) reloc
->target_handle
,
3243 (int) reloc
->read_domains
,
3244 (int) reloc
->write_domain
,
3245 (int) target_obj_priv
->gtt_offset
,
3246 (int) reloc
->presumed_offset
,
3250 /* The target buffer should have appeared before us in the
3251 * exec_object list, so it should have a GTT space bound by now.
3253 if (target_obj_priv
->gtt_space
== NULL
) {
3254 DRM_ERROR("No GTT space found for object %d\n",
3255 reloc
->target_handle
);
3256 drm_gem_object_unreference(target_obj
);
3257 i915_gem_object_unpin(obj
);
3261 /* Validate that the target is in a valid r/w GPU domain */
3262 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3263 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3264 DRM_ERROR("reloc with read/write CPU domains: "
3265 "obj %p target %d offset %d "
3266 "read %08x write %08x",
3267 obj
, reloc
->target_handle
,
3268 (int) reloc
->offset
,
3269 reloc
->read_domains
,
3270 reloc
->write_domain
);
3271 drm_gem_object_unreference(target_obj
);
3272 i915_gem_object_unpin(obj
);
3275 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3276 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3277 DRM_ERROR("Write domain conflict: "
3278 "obj %p target %d offset %d "
3279 "new %08x old %08x\n",
3280 obj
, reloc
->target_handle
,
3281 (int) reloc
->offset
,
3282 reloc
->write_domain
,
3283 target_obj
->pending_write_domain
);
3284 drm_gem_object_unreference(target_obj
);
3285 i915_gem_object_unpin(obj
);
3289 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3290 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3292 /* If the relocation already has the right value in it, no
3293 * more work needs to be done.
3295 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3296 drm_gem_object_unreference(target_obj
);
3300 /* Check that the relocation address is valid... */
3301 if (reloc
->offset
> obj
->size
- 4) {
3302 DRM_ERROR("Relocation beyond object bounds: "
3303 "obj %p target %d offset %d size %d.\n",
3304 obj
, reloc
->target_handle
,
3305 (int) reloc
->offset
, (int) obj
->size
);
3306 drm_gem_object_unreference(target_obj
);
3307 i915_gem_object_unpin(obj
);
3310 if (reloc
->offset
& 3) {
3311 DRM_ERROR("Relocation not 4-byte aligned: "
3312 "obj %p target %d offset %d.\n",
3313 obj
, reloc
->target_handle
,
3314 (int) reloc
->offset
);
3315 drm_gem_object_unreference(target_obj
);
3316 i915_gem_object_unpin(obj
);
3320 /* and points to somewhere within the target object. */
3321 if (reloc
->delta
>= target_obj
->size
) {
3322 DRM_ERROR("Relocation beyond target object bounds: "
3323 "obj %p target %d delta %d size %d.\n",
3324 obj
, reloc
->target_handle
,
3325 (int) reloc
->delta
, (int) target_obj
->size
);
3326 drm_gem_object_unreference(target_obj
);
3327 i915_gem_object_unpin(obj
);
3331 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3333 drm_gem_object_unreference(target_obj
);
3334 i915_gem_object_unpin(obj
);
3338 /* Map the page containing the relocation we're going to
3341 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3342 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3345 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3346 (reloc_offset
& (PAGE_SIZE
- 1)));
3347 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3350 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3351 obj
, (unsigned int) reloc
->offset
,
3352 readl(reloc_entry
), reloc_val
);
3354 writel(reloc_val
, reloc_entry
);
3355 io_mapping_unmap_atomic(reloc_page
);
3357 /* The updated presumed offset for this entry will be
3358 * copied back out to the user.
3360 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3362 drm_gem_object_unreference(target_obj
);
3367 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3372 /** Dispatch a batchbuffer to the ring
3375 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3376 struct drm_i915_gem_execbuffer
*exec
,
3377 struct drm_clip_rect
*cliprects
,
3378 uint64_t exec_offset
)
3380 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3381 int nbox
= exec
->num_cliprects
;
3383 uint32_t exec_start
, exec_len
;
3386 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3387 exec_len
= (uint32_t) exec
->batch_len
;
3389 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3391 count
= nbox
? nbox
: 1;
3393 for (i
= 0; i
< count
; i
++) {
3395 int ret
= i915_emit_box(dev
, cliprects
, i
,
3396 exec
->DR1
, exec
->DR4
);
3401 if (IS_I830(dev
) || IS_845G(dev
)) {
3403 OUT_RING(MI_BATCH_BUFFER
);
3404 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3405 OUT_RING(exec_start
+ exec_len
- 4);
3410 if (IS_I965G(dev
)) {
3411 OUT_RING(MI_BATCH_BUFFER_START
|
3413 MI_BATCH_NON_SECURE_I965
);
3414 OUT_RING(exec_start
);
3416 OUT_RING(MI_BATCH_BUFFER_START
|
3418 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3424 /* XXX breadcrumb */
3428 /* Throttle our rendering by waiting until the ring has completed our requests
3429 * emitted over 20 msec ago.
3431 * Note that if we were to use the current jiffies each time around the loop,
3432 * we wouldn't escape the function with any frames outstanding if the time to
3433 * render a frame was over 20ms.
3435 * This should get us reasonable parallelism between CPU and GPU but also
3436 * relatively low latency when blocking on a particular request to finish.
3439 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3441 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3443 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3445 mutex_lock(&dev
->struct_mutex
);
3446 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3447 struct drm_i915_gem_request
*request
;
3449 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3450 struct drm_i915_gem_request
,
3453 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3456 ret
= i915_wait_request(dev
, request
->seqno
);
3460 mutex_unlock(&dev
->struct_mutex
);
3466 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object
*exec_list
,
3467 uint32_t buffer_count
,
3468 struct drm_i915_gem_relocation_entry
**relocs
)
3470 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3474 for (i
= 0; i
< buffer_count
; i
++) {
3475 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3477 reloc_count
+= exec_list
[i
].relocation_count
;
3480 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3481 if (*relocs
== NULL
)
3484 for (i
= 0; i
< buffer_count
; i
++) {
3485 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3487 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3489 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3491 exec_list
[i
].relocation_count
*
3494 drm_free_large(*relocs
);
3499 reloc_index
+= exec_list
[i
].relocation_count
;
3506 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object
*exec_list
,
3507 uint32_t buffer_count
,
3508 struct drm_i915_gem_relocation_entry
*relocs
)
3510 uint32_t reloc_count
= 0, i
;
3513 for (i
= 0; i
< buffer_count
; i
++) {
3514 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3517 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3519 unwritten
= copy_to_user(user_relocs
,
3520 &relocs
[reloc_count
],
3521 exec_list
[i
].relocation_count
*
3529 reloc_count
+= exec_list
[i
].relocation_count
;
3533 drm_free_large(relocs
);
3539 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer
*exec
,
3540 uint64_t exec_offset
)
3542 uint32_t exec_start
, exec_len
;
3544 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3545 exec_len
= (uint32_t) exec
->batch_len
;
3547 if ((exec_start
| exec_len
) & 0x7)
3557 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3558 struct drm_gem_object
**object_list
,
3561 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3562 struct drm_i915_gem_object
*obj_priv
;
3567 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3568 &wait
, TASK_INTERRUPTIBLE
);
3569 for (i
= 0; i
< count
; i
++) {
3570 obj_priv
= object_list
[i
]->driver_private
;
3571 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3577 if (!signal_pending(current
)) {
3578 mutex_unlock(&dev
->struct_mutex
);
3580 mutex_lock(&dev
->struct_mutex
);
3586 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3592 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3593 struct drm_file
*file_priv
)
3595 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3596 struct drm_i915_gem_execbuffer
*args
= data
;
3597 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3598 struct drm_gem_object
**object_list
= NULL
;
3599 struct drm_gem_object
*batch_obj
;
3600 struct drm_i915_gem_object
*obj_priv
;
3601 struct drm_clip_rect
*cliprects
= NULL
;
3602 struct drm_i915_gem_relocation_entry
*relocs
;
3603 int ret
, ret2
, i
, pinned
= 0;
3604 uint64_t exec_offset
;
3605 uint32_t seqno
, flush_domains
, reloc_index
;
3606 int pin_tries
, flips
;
3609 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3610 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3613 if (args
->buffer_count
< 1) {
3614 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3617 /* Copy in the exec list from userland */
3618 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3619 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3620 if (exec_list
== NULL
|| object_list
== NULL
) {
3621 DRM_ERROR("Failed to allocate exec or object list "
3623 args
->buffer_count
);
3627 ret
= copy_from_user(exec_list
,
3628 (struct drm_i915_relocation_entry __user
*)
3629 (uintptr_t) args
->buffers_ptr
,
3630 sizeof(*exec_list
) * args
->buffer_count
);
3632 DRM_ERROR("copy %d exec entries failed %d\n",
3633 args
->buffer_count
, ret
);
3637 if (args
->num_cliprects
!= 0) {
3638 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3640 if (cliprects
== NULL
)
3643 ret
= copy_from_user(cliprects
,
3644 (struct drm_clip_rect __user
*)
3645 (uintptr_t) args
->cliprects_ptr
,
3646 sizeof(*cliprects
) * args
->num_cliprects
);
3648 DRM_ERROR("copy %d cliprects failed: %d\n",
3649 args
->num_cliprects
, ret
);
3654 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3659 mutex_lock(&dev
->struct_mutex
);
3661 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3663 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3664 mutex_unlock(&dev
->struct_mutex
);
3669 if (dev_priv
->mm
.suspended
) {
3670 mutex_unlock(&dev
->struct_mutex
);
3675 /* Look up object handles */
3677 for (i
= 0; i
< args
->buffer_count
; i
++) {
3678 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3679 exec_list
[i
].handle
);
3680 if (object_list
[i
] == NULL
) {
3681 DRM_ERROR("Invalid object handle %d at index %d\n",
3682 exec_list
[i
].handle
, i
);
3687 obj_priv
= object_list
[i
]->driver_private
;
3688 if (obj_priv
->in_execbuffer
) {
3689 DRM_ERROR("Object %p appears more than once in object list\n",
3694 obj_priv
->in_execbuffer
= true;
3695 flips
+= atomic_read(&obj_priv
->pending_flip
);
3699 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3700 args
->buffer_count
);
3705 /* Pin and relocate */
3706 for (pin_tries
= 0; ; pin_tries
++) {
3710 for (i
= 0; i
< args
->buffer_count
; i
++) {
3711 object_list
[i
]->pending_read_domains
= 0;
3712 object_list
[i
]->pending_write_domain
= 0;
3713 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3716 &relocs
[reloc_index
]);
3720 reloc_index
+= exec_list
[i
].relocation_count
;
3726 /* error other than GTT full, or we've already tried again */
3727 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3728 if (ret
!= -ERESTARTSYS
) {
3729 unsigned long long total_size
= 0;
3730 for (i
= 0; i
< args
->buffer_count
; i
++)
3731 total_size
+= object_list
[i
]->size
;
3732 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3733 pinned
+1, args
->buffer_count
,
3735 DRM_ERROR("%d objects [%d pinned], "
3736 "%d object bytes [%d pinned], "
3737 "%d/%d gtt bytes\n",
3738 atomic_read(&dev
->object_count
),
3739 atomic_read(&dev
->pin_count
),
3740 atomic_read(&dev
->object_memory
),
3741 atomic_read(&dev
->pin_memory
),
3742 atomic_read(&dev
->gtt_memory
),
3748 /* unpin all of our buffers */
3749 for (i
= 0; i
< pinned
; i
++)
3750 i915_gem_object_unpin(object_list
[i
]);
3753 /* evict everyone we can from the aperture */
3754 ret
= i915_gem_evict_everything(dev
);
3755 if (ret
&& ret
!= -ENOSPC
)
3759 /* Set the pending read domains for the batch buffer to COMMAND */
3760 batch_obj
= object_list
[args
->buffer_count
-1];
3761 if (batch_obj
->pending_write_domain
) {
3762 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3766 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3768 /* Sanity check the batch buffer, prior to moving objects */
3769 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3770 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3772 DRM_ERROR("execbuf with invalid offset/length\n");
3776 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3778 /* Zero the global flush/invalidate flags. These
3779 * will be modified as new domains are computed
3782 dev
->invalidate_domains
= 0;
3783 dev
->flush_domains
= 0;
3785 for (i
= 0; i
< args
->buffer_count
; i
++) {
3786 struct drm_gem_object
*obj
= object_list
[i
];
3788 /* Compute new gpu domains and update invalidate/flush */
3789 i915_gem_object_set_to_gpu_domain(obj
);
3792 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3794 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3796 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3798 dev
->invalidate_domains
,
3799 dev
->flush_domains
);
3802 dev
->invalidate_domains
,
3803 dev
->flush_domains
);
3804 if (dev
->flush_domains
)
3805 (void)i915_add_request(dev
, file_priv
,
3806 dev
->flush_domains
);
3809 for (i
= 0; i
< args
->buffer_count
; i
++) {
3810 struct drm_gem_object
*obj
= object_list
[i
];
3811 uint32_t old_write_domain
= obj
->write_domain
;
3813 obj
->write_domain
= obj
->pending_write_domain
;
3814 trace_i915_gem_object_change_domain(obj
,
3819 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3822 for (i
= 0; i
< args
->buffer_count
; i
++) {
3823 i915_gem_object_check_coherency(object_list
[i
],
3824 exec_list
[i
].handle
);
3829 i915_gem_dump_object(batch_obj
,
3835 /* Exec the batchbuffer */
3836 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3838 DRM_ERROR("dispatch failed %d\n", ret
);
3843 * Ensure that the commands in the batch buffer are
3844 * finished before the interrupt fires
3846 flush_domains
= i915_retire_commands(dev
);
3848 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3851 * Get a seqno representing the execution of the current buffer,
3852 * which we can wait on. We would like to mitigate these interrupts,
3853 * likely by only creating seqnos occasionally (so that we have
3854 * *some* interrupts representing completion of buffers that we can
3855 * wait on when trying to clear up gtt space).
3857 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3859 for (i
= 0; i
< args
->buffer_count
; i
++) {
3860 struct drm_gem_object
*obj
= object_list
[i
];
3862 i915_gem_object_move_to_active(obj
, seqno
);
3864 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3868 i915_dump_lru(dev
, __func__
);
3871 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3874 for (i
= 0; i
< pinned
; i
++)
3875 i915_gem_object_unpin(object_list
[i
]);
3877 for (i
= 0; i
< args
->buffer_count
; i
++) {
3878 if (object_list
[i
]) {
3879 obj_priv
= object_list
[i
]->driver_private
;
3880 obj_priv
->in_execbuffer
= false;
3882 drm_gem_object_unreference(object_list
[i
]);
3885 mutex_unlock(&dev
->struct_mutex
);
3888 /* Copy the new buffer offsets back to the user's exec list. */
3889 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3890 (uintptr_t) args
->buffers_ptr
,
3892 sizeof(*exec_list
) * args
->buffer_count
);
3895 DRM_ERROR("failed to copy %d exec entries "
3896 "back to user (%d)\n",
3897 args
->buffer_count
, ret
);
3901 /* Copy the updated relocations out regardless of current error
3902 * state. Failure to update the relocs would mean that the next
3903 * time userland calls execbuf, it would do so with presumed offset
3904 * state that didn't match the actual object state.
3906 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3909 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3916 drm_free_large(object_list
);
3917 drm_free_large(exec_list
);
3924 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3926 struct drm_device
*dev
= obj
->dev
;
3927 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3930 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3931 if (obj_priv
->gtt_space
== NULL
) {
3932 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
3937 * Pre-965 chips need a fence register set up in order to
3938 * properly handle tiled surfaces.
3940 if (!IS_I965G(dev
) && obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
3941 ret
= i915_gem_object_get_fence_reg(obj
);
3943 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3944 DRM_ERROR("Failure to install fence: %d\n",
3949 obj_priv
->pin_count
++;
3951 /* If the object is not active and not pending a flush,
3952 * remove it from the inactive list
3954 if (obj_priv
->pin_count
== 1) {
3955 atomic_inc(&dev
->pin_count
);
3956 atomic_add(obj
->size
, &dev
->pin_memory
);
3957 if (!obj_priv
->active
&&
3958 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
3959 !list_empty(&obj_priv
->list
))
3960 list_del_init(&obj_priv
->list
);
3962 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3968 i915_gem_object_unpin(struct drm_gem_object
*obj
)
3970 struct drm_device
*dev
= obj
->dev
;
3971 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3972 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3974 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3975 obj_priv
->pin_count
--;
3976 BUG_ON(obj_priv
->pin_count
< 0);
3977 BUG_ON(obj_priv
->gtt_space
== NULL
);
3979 /* If the object is no longer pinned, and is
3980 * neither active nor being flushed, then stick it on
3983 if (obj_priv
->pin_count
== 0) {
3984 if (!obj_priv
->active
&&
3985 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
3986 list_move_tail(&obj_priv
->list
,
3987 &dev_priv
->mm
.inactive_list
);
3988 atomic_dec(&dev
->pin_count
);
3989 atomic_sub(obj
->size
, &dev
->pin_memory
);
3991 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3995 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3996 struct drm_file
*file_priv
)
3998 struct drm_i915_gem_pin
*args
= data
;
3999 struct drm_gem_object
*obj
;
4000 struct drm_i915_gem_object
*obj_priv
;
4003 mutex_lock(&dev
->struct_mutex
);
4005 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4007 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4009 mutex_unlock(&dev
->struct_mutex
);
4012 obj_priv
= obj
->driver_private
;
4014 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4015 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4016 drm_gem_object_unreference(obj
);
4017 mutex_unlock(&dev
->struct_mutex
);
4021 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4022 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4024 drm_gem_object_unreference(obj
);
4025 mutex_unlock(&dev
->struct_mutex
);
4029 obj_priv
->user_pin_count
++;
4030 obj_priv
->pin_filp
= file_priv
;
4031 if (obj_priv
->user_pin_count
== 1) {
4032 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4034 drm_gem_object_unreference(obj
);
4035 mutex_unlock(&dev
->struct_mutex
);
4040 /* XXX - flush the CPU caches for pinned objects
4041 * as the X server doesn't manage domains yet
4043 i915_gem_object_flush_cpu_write_domain(obj
);
4044 args
->offset
= obj_priv
->gtt_offset
;
4045 drm_gem_object_unreference(obj
);
4046 mutex_unlock(&dev
->struct_mutex
);
4052 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4053 struct drm_file
*file_priv
)
4055 struct drm_i915_gem_pin
*args
= data
;
4056 struct drm_gem_object
*obj
;
4057 struct drm_i915_gem_object
*obj_priv
;
4059 mutex_lock(&dev
->struct_mutex
);
4061 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4063 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4065 mutex_unlock(&dev
->struct_mutex
);
4069 obj_priv
= obj
->driver_private
;
4070 if (obj_priv
->pin_filp
!= file_priv
) {
4071 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4073 drm_gem_object_unreference(obj
);
4074 mutex_unlock(&dev
->struct_mutex
);
4077 obj_priv
->user_pin_count
--;
4078 if (obj_priv
->user_pin_count
== 0) {
4079 obj_priv
->pin_filp
= NULL
;
4080 i915_gem_object_unpin(obj
);
4083 drm_gem_object_unreference(obj
);
4084 mutex_unlock(&dev
->struct_mutex
);
4089 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4090 struct drm_file
*file_priv
)
4092 struct drm_i915_gem_busy
*args
= data
;
4093 struct drm_gem_object
*obj
;
4094 struct drm_i915_gem_object
*obj_priv
;
4096 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4098 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4103 mutex_lock(&dev
->struct_mutex
);
4104 /* Update the active list for the hardware's current position.
4105 * Otherwise this only updates on a delayed timer or when irqs are
4106 * actually unmasked, and our working set ends up being larger than
4109 i915_gem_retire_requests(dev
);
4111 obj_priv
= obj
->driver_private
;
4112 /* Don't count being on the flushing list against the object being
4113 * done. Otherwise, a buffer left on the flushing list but not getting
4114 * flushed (because nobody's flushing that domain) won't ever return
4115 * unbusy and get reused by libdrm's bo cache. The other expected
4116 * consumer of this interface, OpenGL's occlusion queries, also specs
4117 * that the objects get unbusy "eventually" without any interference.
4119 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4121 drm_gem_object_unreference(obj
);
4122 mutex_unlock(&dev
->struct_mutex
);
4127 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4128 struct drm_file
*file_priv
)
4130 return i915_gem_ring_throttle(dev
, file_priv
);
4134 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4135 struct drm_file
*file_priv
)
4137 struct drm_i915_gem_madvise
*args
= data
;
4138 struct drm_gem_object
*obj
;
4139 struct drm_i915_gem_object
*obj_priv
;
4141 switch (args
->madv
) {
4142 case I915_MADV_DONTNEED
:
4143 case I915_MADV_WILLNEED
:
4149 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4151 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4156 mutex_lock(&dev
->struct_mutex
);
4157 obj_priv
= obj
->driver_private
;
4159 if (obj_priv
->pin_count
) {
4160 drm_gem_object_unreference(obj
);
4161 mutex_unlock(&dev
->struct_mutex
);
4163 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4167 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4168 obj_priv
->madv
= args
->madv
;
4170 /* if the object is no longer bound, discard its backing storage */
4171 if (i915_gem_object_is_purgeable(obj_priv
) &&
4172 obj_priv
->gtt_space
== NULL
)
4173 i915_gem_object_truncate(obj
);
4175 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4177 drm_gem_object_unreference(obj
);
4178 mutex_unlock(&dev
->struct_mutex
);
4183 int i915_gem_init_object(struct drm_gem_object
*obj
)
4185 struct drm_i915_gem_object
*obj_priv
;
4187 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4188 if (obj_priv
== NULL
)
4192 * We've just allocated pages from the kernel,
4193 * so they've just been written by the CPU with
4194 * zeros. They'll need to be clflushed before we
4195 * use them with the GPU.
4197 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4198 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4200 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4202 obj
->driver_private
= obj_priv
;
4203 obj_priv
->obj
= obj
;
4204 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4205 INIT_LIST_HEAD(&obj_priv
->list
);
4206 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4207 obj_priv
->madv
= I915_MADV_WILLNEED
;
4209 trace_i915_gem_object_create(obj
);
4214 void i915_gem_free_object(struct drm_gem_object
*obj
)
4216 struct drm_device
*dev
= obj
->dev
;
4217 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4219 trace_i915_gem_object_destroy(obj
);
4221 while (obj_priv
->pin_count
> 0)
4222 i915_gem_object_unpin(obj
);
4224 if (obj_priv
->phys_obj
)
4225 i915_gem_detach_phys_object(dev
, obj
);
4227 i915_gem_object_unbind(obj
);
4229 if (obj_priv
->mmap_offset
)
4230 i915_gem_free_mmap_offset(obj
);
4232 kfree(obj_priv
->page_cpu_valid
);
4233 kfree(obj_priv
->bit_17
);
4234 kfree(obj
->driver_private
);
4237 /** Unbinds all inactive objects. */
4239 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4241 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4243 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4244 struct drm_gem_object
*obj
;
4247 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4248 struct drm_i915_gem_object
,
4251 ret
= i915_gem_object_unbind(obj
);
4253 DRM_ERROR("Error unbinding object: %d\n", ret
);
4262 i915_gem_idle(struct drm_device
*dev
)
4264 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4265 uint32_t seqno
, cur_seqno
, last_seqno
;
4268 mutex_lock(&dev
->struct_mutex
);
4270 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4271 mutex_unlock(&dev
->struct_mutex
);
4275 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4276 * We need to replace this with a semaphore, or something.
4278 dev_priv
->mm
.suspended
= 1;
4279 del_timer(&dev_priv
->hangcheck_timer
);
4281 /* Cancel the retire work handler, wait for it to finish if running
4283 mutex_unlock(&dev
->struct_mutex
);
4284 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4285 mutex_lock(&dev
->struct_mutex
);
4287 i915_kernel_lost_context(dev
);
4289 /* Flush the GPU along with all non-CPU write domains
4291 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4292 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4295 mutex_unlock(&dev
->struct_mutex
);
4299 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4303 cur_seqno
= i915_get_gem_seqno(dev
);
4304 if (i915_seqno_passed(cur_seqno
, seqno
))
4306 if (last_seqno
== cur_seqno
) {
4307 if (stuck
++ > 100) {
4308 DRM_ERROR("hardware wedged\n");
4309 atomic_set(&dev_priv
->mm
.wedged
, 1);
4310 DRM_WAKEUP(&dev_priv
->irq_queue
);
4315 last_seqno
= cur_seqno
;
4317 dev_priv
->mm
.waiting_gem_seqno
= 0;
4319 i915_gem_retire_requests(dev
);
4321 spin_lock(&dev_priv
->mm
.active_list_lock
);
4322 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4323 /* Active and flushing should now be empty as we've
4324 * waited for a sequence higher than any pending execbuffer
4326 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4327 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4328 /* Request should now be empty as we've also waited
4329 * for the last request in the list
4331 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4334 /* Empty the active and flushing lists to inactive. If there's
4335 * anything left at this point, it means that we're wedged and
4336 * nothing good's going to happen by leaving them there. So strip
4337 * the GPU domains and just stuff them onto inactive.
4339 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4340 struct drm_gem_object
*obj
;
4341 uint32_t old_write_domain
;
4343 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4344 struct drm_i915_gem_object
,
4346 old_write_domain
= obj
->write_domain
;
4347 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4348 i915_gem_object_move_to_inactive(obj
);
4350 trace_i915_gem_object_change_domain(obj
,
4354 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4356 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4357 struct drm_gem_object
*obj
;
4358 uint32_t old_write_domain
;
4360 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4361 struct drm_i915_gem_object
,
4363 old_write_domain
= obj
->write_domain
;
4364 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4365 i915_gem_object_move_to_inactive(obj
);
4367 trace_i915_gem_object_change_domain(obj
,
4373 /* Move all inactive buffers out of the GTT. */
4374 ret
= i915_gem_evict_from_inactive_list(dev
);
4375 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4377 mutex_unlock(&dev
->struct_mutex
);
4381 i915_gem_cleanup_ringbuffer(dev
);
4382 mutex_unlock(&dev
->struct_mutex
);
4388 i915_gem_init_hws(struct drm_device
*dev
)
4390 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4391 struct drm_gem_object
*obj
;
4392 struct drm_i915_gem_object
*obj_priv
;
4395 /* If we need a physical address for the status page, it's already
4396 * initialized at driver load time.
4398 if (!I915_NEED_GFX_HWS(dev
))
4401 obj
= drm_gem_object_alloc(dev
, 4096);
4403 DRM_ERROR("Failed to allocate status page\n");
4406 obj_priv
= obj
->driver_private
;
4407 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4409 ret
= i915_gem_object_pin(obj
, 4096);
4411 drm_gem_object_unreference(obj
);
4415 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4417 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4418 if (dev_priv
->hw_status_page
== NULL
) {
4419 DRM_ERROR("Failed to map status page.\n");
4420 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4421 i915_gem_object_unpin(obj
);
4422 drm_gem_object_unreference(obj
);
4425 dev_priv
->hws_obj
= obj
;
4426 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4427 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4428 I915_READ(HWS_PGA
); /* posting read */
4429 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4435 i915_gem_cleanup_hws(struct drm_device
*dev
)
4437 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4438 struct drm_gem_object
*obj
;
4439 struct drm_i915_gem_object
*obj_priv
;
4441 if (dev_priv
->hws_obj
== NULL
)
4444 obj
= dev_priv
->hws_obj
;
4445 obj_priv
= obj
->driver_private
;
4447 kunmap(obj_priv
->pages
[0]);
4448 i915_gem_object_unpin(obj
);
4449 drm_gem_object_unreference(obj
);
4450 dev_priv
->hws_obj
= NULL
;
4452 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4453 dev_priv
->hw_status_page
= NULL
;
4455 /* Write high address into HWS_PGA when disabling. */
4456 I915_WRITE(HWS_PGA
, 0x1ffff000);
4460 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4462 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4463 struct drm_gem_object
*obj
;
4464 struct drm_i915_gem_object
*obj_priv
;
4465 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4469 ret
= i915_gem_init_hws(dev
);
4473 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4475 DRM_ERROR("Failed to allocate ringbuffer\n");
4476 i915_gem_cleanup_hws(dev
);
4479 obj_priv
= obj
->driver_private
;
4481 ret
= i915_gem_object_pin(obj
, 4096);
4483 drm_gem_object_unreference(obj
);
4484 i915_gem_cleanup_hws(dev
);
4488 /* Set up the kernel mapping for the ring. */
4489 ring
->Size
= obj
->size
;
4491 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4492 ring
->map
.size
= obj
->size
;
4494 ring
->map
.flags
= 0;
4497 drm_core_ioremap_wc(&ring
->map
, dev
);
4498 if (ring
->map
.handle
== NULL
) {
4499 DRM_ERROR("Failed to map ringbuffer.\n");
4500 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4501 i915_gem_object_unpin(obj
);
4502 drm_gem_object_unreference(obj
);
4503 i915_gem_cleanup_hws(dev
);
4506 ring
->ring_obj
= obj
;
4507 ring
->virtual_start
= ring
->map
.handle
;
4509 /* Stop the ring if it's running. */
4510 I915_WRITE(PRB0_CTL
, 0);
4511 I915_WRITE(PRB0_TAIL
, 0);
4512 I915_WRITE(PRB0_HEAD
, 0);
4514 /* Initialize the ring. */
4515 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4516 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4518 /* G45 ring initialization fails to reset head to zero */
4520 DRM_ERROR("Ring head not reset to zero "
4521 "ctl %08x head %08x tail %08x start %08x\n",
4522 I915_READ(PRB0_CTL
),
4523 I915_READ(PRB0_HEAD
),
4524 I915_READ(PRB0_TAIL
),
4525 I915_READ(PRB0_START
));
4526 I915_WRITE(PRB0_HEAD
, 0);
4528 DRM_ERROR("Ring head forced to zero "
4529 "ctl %08x head %08x tail %08x start %08x\n",
4530 I915_READ(PRB0_CTL
),
4531 I915_READ(PRB0_HEAD
),
4532 I915_READ(PRB0_TAIL
),
4533 I915_READ(PRB0_START
));
4536 I915_WRITE(PRB0_CTL
,
4537 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4541 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4543 /* If the head is still not zero, the ring is dead */
4545 DRM_ERROR("Ring initialization failed "
4546 "ctl %08x head %08x tail %08x start %08x\n",
4547 I915_READ(PRB0_CTL
),
4548 I915_READ(PRB0_HEAD
),
4549 I915_READ(PRB0_TAIL
),
4550 I915_READ(PRB0_START
));
4554 /* Update our cache of the ring state */
4555 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4556 i915_kernel_lost_context(dev
);
4558 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4559 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4560 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4561 if (ring
->space
< 0)
4562 ring
->space
+= ring
->Size
;
4569 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4571 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4573 if (dev_priv
->ring
.ring_obj
== NULL
)
4576 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4578 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4579 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4580 dev_priv
->ring
.ring_obj
= NULL
;
4581 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4583 i915_gem_cleanup_hws(dev
);
4587 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4588 struct drm_file
*file_priv
)
4590 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4593 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4596 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4597 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4598 atomic_set(&dev_priv
->mm
.wedged
, 0);
4601 mutex_lock(&dev
->struct_mutex
);
4602 dev_priv
->mm
.suspended
= 0;
4604 ret
= i915_gem_init_ringbuffer(dev
);
4606 mutex_unlock(&dev
->struct_mutex
);
4610 spin_lock(&dev_priv
->mm
.active_list_lock
);
4611 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4612 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4614 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4615 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4616 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4617 mutex_unlock(&dev
->struct_mutex
);
4619 drm_irq_install(dev
);
4625 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4626 struct drm_file
*file_priv
)
4628 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4631 drm_irq_uninstall(dev
);
4632 return i915_gem_idle(dev
);
4636 i915_gem_lastclose(struct drm_device
*dev
)
4640 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4643 ret
= i915_gem_idle(dev
);
4645 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4649 i915_gem_load(struct drm_device
*dev
)
4652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4654 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4655 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4656 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4657 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4658 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4659 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4660 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4661 i915_gem_retire_work_handler
);
4662 dev_priv
->mm
.next_gem_seqno
= 1;
4664 spin_lock(&shrink_list_lock
);
4665 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4666 spin_unlock(&shrink_list_lock
);
4668 /* Old X drivers will take 0-2 for front, back, depth buffers */
4669 dev_priv
->fence_reg_start
= 3;
4671 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4672 dev_priv
->num_fence_regs
= 16;
4674 dev_priv
->num_fence_regs
= 8;
4676 /* Initialize fence registers to zero */
4677 if (IS_I965G(dev
)) {
4678 for (i
= 0; i
< 16; i
++)
4679 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4681 for (i
= 0; i
< 8; i
++)
4682 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4683 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4684 for (i
= 0; i
< 8; i
++)
4685 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4687 i915_gem_detect_bit_6_swizzle(dev
);
4688 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4692 * Create a physically contiguous memory object for this object
4693 * e.g. for cursor + overlay regs
4695 int i915_gem_init_phys_object(struct drm_device
*dev
,
4698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4699 struct drm_i915_gem_phys_object
*phys_obj
;
4702 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4705 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4711 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4712 if (!phys_obj
->handle
) {
4717 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4720 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4728 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4730 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4731 struct drm_i915_gem_phys_object
*phys_obj
;
4733 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4736 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4737 if (phys_obj
->cur_obj
) {
4738 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4742 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4744 drm_pci_free(dev
, phys_obj
->handle
);
4746 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4749 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4753 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4754 i915_gem_free_phys_object(dev
, i
);
4757 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4758 struct drm_gem_object
*obj
)
4760 struct drm_i915_gem_object
*obj_priv
;
4765 obj_priv
= obj
->driver_private
;
4766 if (!obj_priv
->phys_obj
)
4769 ret
= i915_gem_object_get_pages(obj
);
4773 page_count
= obj
->size
/ PAGE_SIZE
;
4775 for (i
= 0; i
< page_count
; i
++) {
4776 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4777 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4779 memcpy(dst
, src
, PAGE_SIZE
);
4780 kunmap_atomic(dst
, KM_USER0
);
4782 drm_clflush_pages(obj_priv
->pages
, page_count
);
4783 drm_agp_chipset_flush(dev
);
4785 i915_gem_object_put_pages(obj
);
4787 obj_priv
->phys_obj
->cur_obj
= NULL
;
4788 obj_priv
->phys_obj
= NULL
;
4792 i915_gem_attach_phys_object(struct drm_device
*dev
,
4793 struct drm_gem_object
*obj
, int id
)
4795 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4796 struct drm_i915_gem_object
*obj_priv
;
4801 if (id
> I915_MAX_PHYS_OBJECT
)
4804 obj_priv
= obj
->driver_private
;
4806 if (obj_priv
->phys_obj
) {
4807 if (obj_priv
->phys_obj
->id
== id
)
4809 i915_gem_detach_phys_object(dev
, obj
);
4813 /* create a new object */
4814 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4815 ret
= i915_gem_init_phys_object(dev
, id
,
4818 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4823 /* bind to the object */
4824 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4825 obj_priv
->phys_obj
->cur_obj
= obj
;
4827 ret
= i915_gem_object_get_pages(obj
);
4829 DRM_ERROR("failed to get page list\n");
4833 page_count
= obj
->size
/ PAGE_SIZE
;
4835 for (i
= 0; i
< page_count
; i
++) {
4836 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4837 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4839 memcpy(dst
, src
, PAGE_SIZE
);
4840 kunmap_atomic(src
, KM_USER0
);
4843 i915_gem_object_put_pages(obj
);
4851 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4852 struct drm_i915_gem_pwrite
*args
,
4853 struct drm_file
*file_priv
)
4855 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4858 char __user
*user_data
;
4860 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4861 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4863 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4864 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4868 drm_agp_chipset_flush(dev
);
4872 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4874 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4876 /* Clean up our request list when the client is going away, so that
4877 * later retire_requests won't dereference our soon-to-be-gone
4880 mutex_lock(&dev
->struct_mutex
);
4881 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4882 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4883 mutex_unlock(&dev
->struct_mutex
);
4887 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
4889 drm_i915_private_t
*dev_priv
, *next_dev
;
4890 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4892 int would_deadlock
= 1;
4894 /* "fast-path" to count number of available objects */
4895 if (nr_to_scan
== 0) {
4896 spin_lock(&shrink_list_lock
);
4897 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4898 struct drm_device
*dev
= dev_priv
->dev
;
4900 if (mutex_trylock(&dev
->struct_mutex
)) {
4901 list_for_each_entry(obj_priv
,
4902 &dev_priv
->mm
.inactive_list
,
4905 mutex_unlock(&dev
->struct_mutex
);
4908 spin_unlock(&shrink_list_lock
);
4910 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4913 spin_lock(&shrink_list_lock
);
4915 /* first scan for clean buffers */
4916 list_for_each_entry_safe(dev_priv
, next_dev
,
4917 &shrink_list
, mm
.shrink_list
) {
4918 struct drm_device
*dev
= dev_priv
->dev
;
4920 if (! mutex_trylock(&dev
->struct_mutex
))
4923 spin_unlock(&shrink_list_lock
);
4925 i915_gem_retire_requests(dev
);
4927 list_for_each_entry_safe(obj_priv
, next_obj
,
4928 &dev_priv
->mm
.inactive_list
,
4930 if (i915_gem_object_is_purgeable(obj_priv
)) {
4931 i915_gem_object_unbind(obj_priv
->obj
);
4932 if (--nr_to_scan
<= 0)
4937 spin_lock(&shrink_list_lock
);
4938 mutex_unlock(&dev
->struct_mutex
);
4942 if (nr_to_scan
<= 0)
4946 /* second pass, evict/count anything still on the inactive list */
4947 list_for_each_entry_safe(dev_priv
, next_dev
,
4948 &shrink_list
, mm
.shrink_list
) {
4949 struct drm_device
*dev
= dev_priv
->dev
;
4951 if (! mutex_trylock(&dev
->struct_mutex
))
4954 spin_unlock(&shrink_list_lock
);
4956 list_for_each_entry_safe(obj_priv
, next_obj
,
4957 &dev_priv
->mm
.inactive_list
,
4959 if (nr_to_scan
> 0) {
4960 i915_gem_object_unbind(obj_priv
->obj
);
4966 spin_lock(&shrink_list_lock
);
4967 mutex_unlock(&dev
->struct_mutex
);
4972 spin_unlock(&shrink_list_lock
);
4977 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4982 static struct shrinker shrinker
= {
4983 .shrink
= i915_gem_shrink
,
4984 .seeks
= DEFAULT_SEEKS
,
4988 i915_gem_shrinker_init(void)
4990 register_shrinker(&shrinker
);
4994 i915_gem_shrinker_exit(void)
4996 unregister_shrinker(&shrinker
);