2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 drm_gem_object_handle_unreference_unlocked(obj
);
136 args
->handle
= handle
;
142 fast_shmem_read(struct page
**pages
,
143 loff_t page_base
, int page_offset
,
150 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
153 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
154 kunmap_atomic(vaddr
, KM_USER0
);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
164 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
165 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
167 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
168 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
172 slow_shmem_copy(struct page
*dst_page
,
174 struct page
*src_page
,
178 char *dst_vaddr
, *src_vaddr
;
180 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
181 if (dst_vaddr
== NULL
)
184 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
185 if (src_vaddr
== NULL
) {
186 kunmap_atomic(dst_vaddr
, KM_USER0
);
190 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
192 kunmap_atomic(src_vaddr
, KM_USER1
);
193 kunmap_atomic(dst_vaddr
, KM_USER0
);
199 slow_shmem_bit17_copy(struct page
*gpu_page
,
201 struct page
*cpu_page
,
206 char *gpu_vaddr
, *cpu_vaddr
;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page
, cpu_offset
,
212 gpu_page
, gpu_offset
, length
);
214 return slow_shmem_copy(gpu_page
, gpu_offset
,
215 cpu_page
, cpu_offset
, length
);
218 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
219 if (gpu_vaddr
== NULL
)
222 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
223 if (cpu_vaddr
== NULL
) {
224 kunmap_atomic(gpu_vaddr
, KM_USER0
);
228 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
229 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
233 int this_length
= min(cacheline_end
- gpu_offset
, length
);
234 int swizzled_gpu_offset
= gpu_offset
^ 64;
237 memcpy(cpu_vaddr
+ cpu_offset
,
238 gpu_vaddr
+ swizzled_gpu_offset
,
241 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
242 cpu_vaddr
+ cpu_offset
,
245 cpu_offset
+= this_length
;
246 gpu_offset
+= this_length
;
247 length
-= this_length
;
250 kunmap_atomic(cpu_vaddr
, KM_USER1
);
251 kunmap_atomic(gpu_vaddr
, KM_USER0
);
257 * This is the fast shmem pread path, which attempts to copy_from_user directly
258 * from the backing pages of the object to the user's address space. On a
259 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
263 struct drm_i915_gem_pread
*args
,
264 struct drm_file
*file_priv
)
266 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
268 loff_t offset
, page_base
;
269 char __user
*user_data
;
270 int page_offset
, page_length
;
273 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
276 mutex_lock(&dev
->struct_mutex
);
278 ret
= i915_gem_object_get_pages(obj
, 0);
282 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
287 obj_priv
= obj
->driver_private
;
288 offset
= args
->offset
;
291 /* Operation in this page
293 * page_base = page offset within aperture
294 * page_offset = offset within page
295 * page_length = bytes to copy for this page
297 page_base
= (offset
& ~(PAGE_SIZE
-1));
298 page_offset
= offset
& (PAGE_SIZE
-1);
299 page_length
= remain
;
300 if ((page_offset
+ remain
) > PAGE_SIZE
)
301 page_length
= PAGE_SIZE
- page_offset
;
303 ret
= fast_shmem_read(obj_priv
->pages
,
304 page_base
, page_offset
,
305 user_data
, page_length
);
309 remain
-= page_length
;
310 user_data
+= page_length
;
311 offset
+= page_length
;
315 i915_gem_object_put_pages(obj
);
317 mutex_unlock(&dev
->struct_mutex
);
323 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
327 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
329 /* If we've insufficient memory to map in the pages, attempt
330 * to make some space by throwing out some old buffers.
332 if (ret
== -ENOMEM
) {
333 struct drm_device
*dev
= obj
->dev
;
335 ret
= i915_gem_evict_something(dev
, obj
->size
);
339 ret
= i915_gem_object_get_pages(obj
, 0);
346 * This is the fallback shmem pread path, which allocates temporary storage
347 * in kernel space to copy_to_user into outside of the struct_mutex, so we
348 * can copy out of the object's backing pages while holding the struct mutex
349 * and not take page faults.
352 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
353 struct drm_i915_gem_pread
*args
,
354 struct drm_file
*file_priv
)
356 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
357 struct mm_struct
*mm
= current
->mm
;
358 struct page
**user_pages
;
360 loff_t offset
, pinned_pages
, i
;
361 loff_t first_data_page
, last_data_page
, num_pages
;
362 int shmem_page_index
, shmem_page_offset
;
363 int data_page_index
, data_page_offset
;
366 uint64_t data_ptr
= args
->data_ptr
;
367 int do_bit17_swizzling
;
371 /* Pin the user pages containing the data. We can't fault while
372 * holding the struct mutex, yet we want to hold it while
373 * dereferencing the user data.
375 first_data_page
= data_ptr
/ PAGE_SIZE
;
376 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
377 num_pages
= last_data_page
- first_data_page
+ 1;
379 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
380 if (user_pages
== NULL
)
383 down_read(&mm
->mmap_sem
);
384 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
385 num_pages
, 1, 0, user_pages
, NULL
);
386 up_read(&mm
->mmap_sem
);
387 if (pinned_pages
< num_pages
) {
389 goto fail_put_user_pages
;
392 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
394 mutex_lock(&dev
->struct_mutex
);
396 ret
= i915_gem_object_get_pages_or_evict(obj
);
400 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
405 obj_priv
= obj
->driver_private
;
406 offset
= args
->offset
;
409 /* Operation in this page
411 * shmem_page_index = page number within shmem file
412 * shmem_page_offset = offset within page in shmem file
413 * data_page_index = page number in get_user_pages return
414 * data_page_offset = offset with data_page_index page.
415 * page_length = bytes to copy for this page
417 shmem_page_index
= offset
/ PAGE_SIZE
;
418 shmem_page_offset
= offset
& ~PAGE_MASK
;
419 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
420 data_page_offset
= data_ptr
& ~PAGE_MASK
;
422 page_length
= remain
;
423 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
424 page_length
= PAGE_SIZE
- shmem_page_offset
;
425 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
426 page_length
= PAGE_SIZE
- data_page_offset
;
428 if (do_bit17_swizzling
) {
429 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
431 user_pages
[data_page_index
],
436 ret
= slow_shmem_copy(user_pages
[data_page_index
],
438 obj_priv
->pages
[shmem_page_index
],
445 remain
-= page_length
;
446 data_ptr
+= page_length
;
447 offset
+= page_length
;
451 i915_gem_object_put_pages(obj
);
453 mutex_unlock(&dev
->struct_mutex
);
455 for (i
= 0; i
< pinned_pages
; i
++) {
456 SetPageDirty(user_pages
[i
]);
457 page_cache_release(user_pages
[i
]);
459 drm_free_large(user_pages
);
465 * Reads data from the object referenced by handle.
467 * On error, the contents of *data are undefined.
470 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
471 struct drm_file
*file_priv
)
473 struct drm_i915_gem_pread
*args
= data
;
474 struct drm_gem_object
*obj
;
475 struct drm_i915_gem_object
*obj_priv
;
478 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
481 obj_priv
= obj
->driver_private
;
483 /* Bounds check source.
485 * XXX: This could use review for overflow issues...
487 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
488 args
->offset
+ args
->size
> obj
->size
) {
489 drm_gem_object_unreference_unlocked(obj
);
493 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
494 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
496 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
498 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
502 drm_gem_object_unreference_unlocked(obj
);
507 /* This is the fast write path which cannot handle
508 * page faults in the source data
512 fast_user_write(struct io_mapping
*mapping
,
513 loff_t page_base
, int page_offset
,
514 char __user
*user_data
,
518 unsigned long unwritten
;
520 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
521 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
523 io_mapping_unmap_atomic(vaddr_atomic
);
529 /* Here's the write path which can sleep for
534 slow_kernel_write(struct io_mapping
*mapping
,
535 loff_t gtt_base
, int gtt_offset
,
536 struct page
*user_page
, int user_offset
,
539 char *src_vaddr
, *dst_vaddr
;
540 unsigned long unwritten
;
542 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
543 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
544 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
545 src_vaddr
+ user_offset
,
547 kunmap_atomic(src_vaddr
, KM_USER1
);
548 io_mapping_unmap_atomic(dst_vaddr
);
555 fast_shmem_write(struct page
**pages
,
556 loff_t page_base
, int page_offset
,
561 unsigned long unwritten
;
563 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
566 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
567 kunmap_atomic(vaddr
, KM_USER0
);
575 * This is the fast pwrite path, where we copy the data directly from the
576 * user into the GTT, uncached.
579 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
580 struct drm_i915_gem_pwrite
*args
,
581 struct drm_file
*file_priv
)
583 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
584 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
586 loff_t offset
, page_base
;
587 char __user
*user_data
;
588 int page_offset
, page_length
;
591 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
593 if (!access_ok(VERIFY_READ
, user_data
, remain
))
597 mutex_lock(&dev
->struct_mutex
);
598 ret
= i915_gem_object_pin(obj
, 0);
600 mutex_unlock(&dev
->struct_mutex
);
603 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
607 obj_priv
= obj
->driver_private
;
608 offset
= obj_priv
->gtt_offset
+ args
->offset
;
611 /* Operation in this page
613 * page_base = page offset within aperture
614 * page_offset = offset within page
615 * page_length = bytes to copy for this page
617 page_base
= (offset
& ~(PAGE_SIZE
-1));
618 page_offset
= offset
& (PAGE_SIZE
-1);
619 page_length
= remain
;
620 if ((page_offset
+ remain
) > PAGE_SIZE
)
621 page_length
= PAGE_SIZE
- page_offset
;
623 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
624 page_offset
, user_data
, page_length
);
626 /* If we get a fault while copying data, then (presumably) our
627 * source page isn't available. Return the error and we'll
628 * retry in the slow path.
633 remain
-= page_length
;
634 user_data
+= page_length
;
635 offset
+= page_length
;
639 i915_gem_object_unpin(obj
);
640 mutex_unlock(&dev
->struct_mutex
);
646 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
647 * the memory and maps it using kmap_atomic for copying.
649 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
650 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
654 struct drm_i915_gem_pwrite
*args
,
655 struct drm_file
*file_priv
)
657 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
658 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
660 loff_t gtt_page_base
, offset
;
661 loff_t first_data_page
, last_data_page
, num_pages
;
662 loff_t pinned_pages
, i
;
663 struct page
**user_pages
;
664 struct mm_struct
*mm
= current
->mm
;
665 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
667 uint64_t data_ptr
= args
->data_ptr
;
671 /* Pin the user pages containing the data. We can't fault while
672 * holding the struct mutex, and all of the pwrite implementations
673 * want to hold it while dereferencing the user data.
675 first_data_page
= data_ptr
/ PAGE_SIZE
;
676 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
677 num_pages
= last_data_page
- first_data_page
+ 1;
679 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
680 if (user_pages
== NULL
)
683 down_read(&mm
->mmap_sem
);
684 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
685 num_pages
, 0, 0, user_pages
, NULL
);
686 up_read(&mm
->mmap_sem
);
687 if (pinned_pages
< num_pages
) {
689 goto out_unpin_pages
;
692 mutex_lock(&dev
->struct_mutex
);
693 ret
= i915_gem_object_pin(obj
, 0);
697 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
699 goto out_unpin_object
;
701 obj_priv
= obj
->driver_private
;
702 offset
= obj_priv
->gtt_offset
+ args
->offset
;
705 /* Operation in this page
707 * gtt_page_base = page offset within aperture
708 * gtt_page_offset = offset within page in aperture
709 * data_page_index = page number in get_user_pages return
710 * data_page_offset = offset with data_page_index page.
711 * page_length = bytes to copy for this page
713 gtt_page_base
= offset
& PAGE_MASK
;
714 gtt_page_offset
= offset
& ~PAGE_MASK
;
715 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
716 data_page_offset
= data_ptr
& ~PAGE_MASK
;
718 page_length
= remain
;
719 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
720 page_length
= PAGE_SIZE
- gtt_page_offset
;
721 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
722 page_length
= PAGE_SIZE
- data_page_offset
;
724 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
725 gtt_page_base
, gtt_page_offset
,
726 user_pages
[data_page_index
],
730 /* If we get a fault while copying data, then (presumably) our
731 * source page isn't available. Return the error and we'll
732 * retry in the slow path.
735 goto out_unpin_object
;
737 remain
-= page_length
;
738 offset
+= page_length
;
739 data_ptr
+= page_length
;
743 i915_gem_object_unpin(obj
);
745 mutex_unlock(&dev
->struct_mutex
);
747 for (i
= 0; i
< pinned_pages
; i
++)
748 page_cache_release(user_pages
[i
]);
749 drm_free_large(user_pages
);
755 * This is the fast shmem pwrite path, which attempts to directly
756 * copy_from_user into the kmapped pages backing the object.
759 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
760 struct drm_i915_gem_pwrite
*args
,
761 struct drm_file
*file_priv
)
763 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
765 loff_t offset
, page_base
;
766 char __user
*user_data
;
767 int page_offset
, page_length
;
770 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
773 mutex_lock(&dev
->struct_mutex
);
775 ret
= i915_gem_object_get_pages(obj
, 0);
779 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
783 obj_priv
= obj
->driver_private
;
784 offset
= args
->offset
;
788 /* Operation in this page
790 * page_base = page offset within aperture
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
794 page_base
= (offset
& ~(PAGE_SIZE
-1));
795 page_offset
= offset
& (PAGE_SIZE
-1);
796 page_length
= remain
;
797 if ((page_offset
+ remain
) > PAGE_SIZE
)
798 page_length
= PAGE_SIZE
- page_offset
;
800 ret
= fast_shmem_write(obj_priv
->pages
,
801 page_base
, page_offset
,
802 user_data
, page_length
);
806 remain
-= page_length
;
807 user_data
+= page_length
;
808 offset
+= page_length
;
812 i915_gem_object_put_pages(obj
);
814 mutex_unlock(&dev
->struct_mutex
);
820 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
821 * the memory and maps it using kmap_atomic for copying.
823 * This avoids taking mmap_sem for faulting on the user's address while the
824 * struct_mutex is held.
827 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
828 struct drm_i915_gem_pwrite
*args
,
829 struct drm_file
*file_priv
)
831 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
832 struct mm_struct
*mm
= current
->mm
;
833 struct page
**user_pages
;
835 loff_t offset
, pinned_pages
, i
;
836 loff_t first_data_page
, last_data_page
, num_pages
;
837 int shmem_page_index
, shmem_page_offset
;
838 int data_page_index
, data_page_offset
;
841 uint64_t data_ptr
= args
->data_ptr
;
842 int do_bit17_swizzling
;
846 /* Pin the user pages containing the data. We can't fault while
847 * holding the struct mutex, and all of the pwrite implementations
848 * want to hold it while dereferencing the user data.
850 first_data_page
= data_ptr
/ PAGE_SIZE
;
851 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
852 num_pages
= last_data_page
- first_data_page
+ 1;
854 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
855 if (user_pages
== NULL
)
858 down_read(&mm
->mmap_sem
);
859 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
860 num_pages
, 0, 0, user_pages
, NULL
);
861 up_read(&mm
->mmap_sem
);
862 if (pinned_pages
< num_pages
) {
864 goto fail_put_user_pages
;
867 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
869 mutex_lock(&dev
->struct_mutex
);
871 ret
= i915_gem_object_get_pages_or_evict(obj
);
875 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
879 obj_priv
= obj
->driver_private
;
880 offset
= args
->offset
;
884 /* Operation in this page
886 * shmem_page_index = page number within shmem file
887 * shmem_page_offset = offset within page in shmem file
888 * data_page_index = page number in get_user_pages return
889 * data_page_offset = offset with data_page_index page.
890 * page_length = bytes to copy for this page
892 shmem_page_index
= offset
/ PAGE_SIZE
;
893 shmem_page_offset
= offset
& ~PAGE_MASK
;
894 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
895 data_page_offset
= data_ptr
& ~PAGE_MASK
;
897 page_length
= remain
;
898 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
899 page_length
= PAGE_SIZE
- shmem_page_offset
;
900 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
901 page_length
= PAGE_SIZE
- data_page_offset
;
903 if (do_bit17_swizzling
) {
904 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
906 user_pages
[data_page_index
],
911 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
913 user_pages
[data_page_index
],
920 remain
-= page_length
;
921 data_ptr
+= page_length
;
922 offset
+= page_length
;
926 i915_gem_object_put_pages(obj
);
928 mutex_unlock(&dev
->struct_mutex
);
930 for (i
= 0; i
< pinned_pages
; i
++)
931 page_cache_release(user_pages
[i
]);
932 drm_free_large(user_pages
);
938 * Writes data to the object referenced by handle.
940 * On error, the contents of the buffer that were to be modified are undefined.
943 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
944 struct drm_file
*file_priv
)
946 struct drm_i915_gem_pwrite
*args
= data
;
947 struct drm_gem_object
*obj
;
948 struct drm_i915_gem_object
*obj_priv
;
951 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
954 obj_priv
= obj
->driver_private
;
956 /* Bounds check destination.
958 * XXX: This could use review for overflow issues...
960 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
961 args
->offset
+ args
->size
> obj
->size
) {
962 drm_gem_object_unreference_unlocked(obj
);
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
972 if (obj_priv
->phys_obj
)
973 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
974 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
975 dev
->gtt_total
!= 0) {
976 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
977 if (ret
== -EFAULT
) {
978 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
981 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
982 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
984 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
985 if (ret
== -EFAULT
) {
986 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
993 DRM_INFO("pwrite failed %d\n", ret
);
996 drm_gem_object_unreference_unlocked(obj
);
1002 * Called when user space prepares to use an object with the CPU, either
1003 * through the mmap ioctl's mapping or a GTT mapping.
1006 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1007 struct drm_file
*file_priv
)
1009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1010 struct drm_i915_gem_set_domain
*args
= data
;
1011 struct drm_gem_object
*obj
;
1012 struct drm_i915_gem_object
*obj_priv
;
1013 uint32_t read_domains
= args
->read_domains
;
1014 uint32_t write_domain
= args
->write_domain
;
1017 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1020 /* Only handle setting domains to types used by the CPU. */
1021 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1024 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1027 /* Having something in the write domain implies it's in the read
1028 * domain, and only that read domain. Enforce that in the request.
1030 if (write_domain
!= 0 && read_domains
!= write_domain
)
1033 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1036 obj_priv
= obj
->driver_private
;
1038 mutex_lock(&dev
->struct_mutex
);
1040 intel_mark_busy(dev
, obj
);
1043 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044 obj
, obj
->size
, read_domains
, write_domain
);
1046 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1047 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1049 /* Update the LRU on the fence for the CPU access that's
1052 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1053 list_move_tail(&obj_priv
->fence_list
,
1054 &dev_priv
->mm
.fence_list
);
1057 /* Silently promote "you're not bound, there was nothing to do"
1058 * to success, since the client was just asking us to
1059 * make sure everything was done.
1064 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1067 drm_gem_object_unreference(obj
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file_priv
)
1079 struct drm_i915_gem_sw_finish
*args
= data
;
1080 struct drm_gem_object
*obj
;
1081 struct drm_i915_gem_object
*obj_priv
;
1084 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1087 mutex_lock(&dev
->struct_mutex
);
1088 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1090 mutex_unlock(&dev
->struct_mutex
);
1095 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1096 __func__
, args
->handle
, obj
, obj
->size
);
1098 obj_priv
= obj
->driver_private
;
1100 /* Pinned buffers may be scanout, so flush the cache */
1101 if (obj_priv
->pin_count
)
1102 i915_gem_object_flush_cpu_write_domain(obj
);
1104 drm_gem_object_unreference(obj
);
1105 mutex_unlock(&dev
->struct_mutex
);
1110 * Maps the contents of an object, returning the address it is mapped
1113 * While the mapping holds a reference on the contents of the object, it doesn't
1114 * imply a ref on the object itself.
1117 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
)
1120 struct drm_i915_gem_mmap
*args
= data
;
1121 struct drm_gem_object
*obj
;
1125 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1128 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1132 offset
= args
->offset
;
1134 down_write(¤t
->mm
->mmap_sem
);
1135 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1136 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1138 up_write(¤t
->mm
->mmap_sem
);
1139 drm_gem_object_unreference_unlocked(obj
);
1140 if (IS_ERR((void *)addr
))
1143 args
->addr_ptr
= (uint64_t) addr
;
1149 * i915_gem_fault - fault a page into the GTT
1150 * vma: VMA in question
1153 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154 * from userspace. The fault handler takes care of binding the object to
1155 * the GTT (if needed), allocating and programming a fence register (again,
1156 * only if needed based on whether the old reg is still valid or the object
1157 * is tiled) and inserting a new PTE into the faulting process.
1159 * Note that the faulting process may involve evicting existing objects
1160 * from the GTT and/or fence registers to make room. So performance may
1161 * suffer if the GTT working set is large or there are few fence registers
1164 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1166 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1167 struct drm_device
*dev
= obj
->dev
;
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1170 pgoff_t page_offset
;
1173 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1175 /* We don't use vmf->pgoff since that has the fake offset */
1176 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1179 /* Now bind it into the GTT if needed */
1180 mutex_lock(&dev
->struct_mutex
);
1181 if (!obj_priv
->gtt_space
) {
1182 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1186 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1188 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1193 /* Need a new fence register? */
1194 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1195 ret
= i915_gem_object_get_fence_reg(obj
);
1200 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1203 /* Finally, remap it using the new GTT offset */
1204 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1206 mutex_unlock(&dev
->struct_mutex
);
1211 return VM_FAULT_NOPAGE
;
1214 return VM_FAULT_OOM
;
1216 return VM_FAULT_SIGBUS
;
1221 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1222 * @obj: obj in question
1224 * GEM memory mapping works by handing back to userspace a fake mmap offset
1225 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1226 * up the object based on the offset and sets up the various memory mapping
1229 * This routine allocates and attaches a fake offset for @obj.
1232 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1234 struct drm_device
*dev
= obj
->dev
;
1235 struct drm_gem_mm
*mm
= dev
->mm_private
;
1236 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1237 struct drm_map_list
*list
;
1238 struct drm_local_map
*map
;
1241 /* Set the object up for mmap'ing */
1242 list
= &obj
->map_list
;
1243 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1248 map
->type
= _DRM_GEM
;
1249 map
->size
= obj
->size
;
1252 /* Get a DRM GEM mmap offset allocated... */
1253 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1254 obj
->size
/ PAGE_SIZE
, 0, 0);
1255 if (!list
->file_offset_node
) {
1256 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1261 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1262 obj
->size
/ PAGE_SIZE
, 0);
1263 if (!list
->file_offset_node
) {
1268 list
->hash
.key
= list
->file_offset_node
->start
;
1269 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1270 DRM_ERROR("failed to add to map hash\n");
1275 /* By now we should be all set, any drm_mmap request on the offset
1276 * below will get to our mmap & fault handler */
1277 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1282 drm_mm_put_block(list
->file_offset_node
);
1290 * i915_gem_release_mmap - remove physical page mappings
1291 * @obj: obj in question
1293 * Preserve the reservation of the mmapping with the DRM core code, but
1294 * relinquish ownership of the pages back to the system.
1296 * It is vital that we remove the page mapping if we have mapped a tiled
1297 * object through the GTT and then lose the fence register due to
1298 * resource pressure. Similarly if the object has been moved out of the
1299 * aperture, than pages mapped into userspace must be revoked. Removing the
1300 * mapping will then trigger a page fault on the next user access, allowing
1301 * fixup by i915_gem_fault().
1304 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1306 struct drm_device
*dev
= obj
->dev
;
1307 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1309 if (dev
->dev_mapping
)
1310 unmap_mapping_range(dev
->dev_mapping
,
1311 obj_priv
->mmap_offset
, obj
->size
, 1);
1315 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1317 struct drm_device
*dev
= obj
->dev
;
1318 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1319 struct drm_gem_mm
*mm
= dev
->mm_private
;
1320 struct drm_map_list
*list
;
1322 list
= &obj
->map_list
;
1323 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1325 if (list
->file_offset_node
) {
1326 drm_mm_put_block(list
->file_offset_node
);
1327 list
->file_offset_node
= NULL
;
1335 obj_priv
->mmap_offset
= 0;
1339 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1340 * @obj: object to check
1342 * Return the required GTT alignment for an object, taking into account
1343 * potential fence register mapping if needed.
1346 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1348 struct drm_device
*dev
= obj
->dev
;
1349 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1353 * Minimum alignment is 4k (GTT page size), but might be greater
1354 * if a fence register is needed for the object.
1356 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1360 * Previous chips need to be aligned to the size of the smallest
1361 * fence register that can contain the object.
1368 for (i
= start
; i
< obj
->size
; i
<<= 1)
1375 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @data: GTT mapping ioctl data
1378 * @file_priv: GEM object info
1380 * Simply returns the fake offset to userspace so it can mmap it.
1381 * The mmap call will end up in drm_gem_mmap(), which will set things
1382 * up so we can get faults in the handler above.
1384 * The fault handler will take care of binding the object into the GTT
1385 * (since it may have been evicted to make room for something), allocating
1386 * a fence register, and mapping the appropriate aperture address into
1390 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1391 struct drm_file
*file_priv
)
1393 struct drm_i915_gem_mmap_gtt
*args
= data
;
1394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1395 struct drm_gem_object
*obj
;
1396 struct drm_i915_gem_object
*obj_priv
;
1399 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1402 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1406 mutex_lock(&dev
->struct_mutex
);
1408 obj_priv
= obj
->driver_private
;
1410 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1411 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1412 drm_gem_object_unreference(obj
);
1413 mutex_unlock(&dev
->struct_mutex
);
1418 if (!obj_priv
->mmap_offset
) {
1419 ret
= i915_gem_create_mmap_offset(obj
);
1421 drm_gem_object_unreference(obj
);
1422 mutex_unlock(&dev
->struct_mutex
);
1427 args
->offset
= obj_priv
->mmap_offset
;
1430 * Pull it into the GTT so that we have a page list (makes the
1431 * initial fault faster and any subsequent flushing possible).
1433 if (!obj_priv
->agp_mem
) {
1434 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1436 drm_gem_object_unreference(obj
);
1437 mutex_unlock(&dev
->struct_mutex
);
1440 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1443 drm_gem_object_unreference(obj
);
1444 mutex_unlock(&dev
->struct_mutex
);
1450 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1452 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1453 int page_count
= obj
->size
/ PAGE_SIZE
;
1456 BUG_ON(obj_priv
->pages_refcount
== 0);
1457 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1459 if (--obj_priv
->pages_refcount
!= 0)
1462 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1463 i915_gem_object_save_bit_17_swizzle(obj
);
1465 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1466 obj_priv
->dirty
= 0;
1468 for (i
= 0; i
< page_count
; i
++) {
1469 if (obj_priv
->pages
[i
] == NULL
)
1472 if (obj_priv
->dirty
)
1473 set_page_dirty(obj_priv
->pages
[i
]);
1475 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1476 mark_page_accessed(obj_priv
->pages
[i
]);
1478 page_cache_release(obj_priv
->pages
[i
]);
1480 obj_priv
->dirty
= 0;
1482 drm_free_large(obj_priv
->pages
);
1483 obj_priv
->pages
= NULL
;
1487 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1489 struct drm_device
*dev
= obj
->dev
;
1490 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1491 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv
->active
) {
1495 drm_gem_object_reference(obj
);
1496 obj_priv
->active
= 1;
1498 /* Move from whatever list we were on to the tail of execution. */
1499 spin_lock(&dev_priv
->mm
.active_list_lock
);
1500 list_move_tail(&obj_priv
->list
,
1501 &dev_priv
->mm
.active_list
);
1502 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1503 obj_priv
->last_rendering_seqno
= seqno
;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1513 BUG_ON(!obj_priv
->active
);
1514 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1515 obj_priv
->last_rendering_seqno
= 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1523 struct inode
*inode
;
1525 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1526 if (inode
->i_op
->truncate
)
1527 inode
->i_op
->truncate (inode
);
1529 obj_priv
->madv
= __I915_MADV_PURGED
;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1535 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1541 struct drm_device
*dev
= obj
->dev
;
1542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1543 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1545 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1546 if (obj_priv
->pin_count
!= 0)
1547 list_del_init(&obj_priv
->list
);
1549 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1551 obj_priv
->last_rendering_seqno
= 0;
1552 if (obj_priv
->active
) {
1553 obj_priv
->active
= 0;
1554 drm_gem_object_unreference(obj
);
1556 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1560 * Creates a new sequence number, emitting a write of it to the status page
1561 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1563 * Must be called with struct_lock held.
1565 * Returned sequence numbers are nonzero on success.
1568 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1569 uint32_t flush_domains
)
1571 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1572 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1573 struct drm_i915_gem_request
*request
;
1578 if (file_priv
!= NULL
)
1579 i915_file_priv
= file_priv
->driver_priv
;
1581 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1582 if (request
== NULL
)
1585 /* Grab the seqno we're going to make this request be, and bump the
1586 * next (skipping 0 so it can be the reserved no-seqno value).
1588 seqno
= dev_priv
->mm
.next_gem_seqno
;
1589 dev_priv
->mm
.next_gem_seqno
++;
1590 if (dev_priv
->mm
.next_gem_seqno
== 0)
1591 dev_priv
->mm
.next_gem_seqno
++;
1594 OUT_RING(MI_STORE_DWORD_INDEX
);
1595 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1598 OUT_RING(MI_USER_INTERRUPT
);
1601 DRM_DEBUG_DRIVER("%d\n", seqno
);
1603 request
->seqno
= seqno
;
1604 request
->emitted_jiffies
= jiffies
;
1605 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1606 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1607 if (i915_file_priv
) {
1608 list_add_tail(&request
->client_list
,
1609 &i915_file_priv
->mm
.request_list
);
1611 INIT_LIST_HEAD(&request
->client_list
);
1614 /* Associate any objects on the flushing list matching the write
1615 * domain we're flushing with our flush.
1617 if (flush_domains
!= 0) {
1618 struct drm_i915_gem_object
*obj_priv
, *next
;
1620 list_for_each_entry_safe(obj_priv
, next
,
1621 &dev_priv
->mm
.flushing_list
, list
) {
1622 struct drm_gem_object
*obj
= obj_priv
->obj
;
1624 if ((obj
->write_domain
& flush_domains
) ==
1625 obj
->write_domain
) {
1626 uint32_t old_write_domain
= obj
->write_domain
;
1628 obj
->write_domain
= 0;
1629 i915_gem_object_move_to_active(obj
, seqno
);
1631 trace_i915_gem_object_change_domain(obj
,
1639 if (!dev_priv
->mm
.suspended
) {
1640 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1642 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1648 * Command execution barrier
1650 * Ensures that all commands in the ring are finished
1651 * before signalling the CPU
1654 i915_retire_commands(struct drm_device
*dev
)
1656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1657 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1658 uint32_t flush_domains
= 0;
1661 /* The sampler always gets flushed on i965 (sigh) */
1663 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1666 OUT_RING(0); /* noop */
1668 return flush_domains
;
1672 * Moves buffers associated only with the given active seqno from the active
1673 * to inactive list, potentially freeing them.
1676 i915_gem_retire_request(struct drm_device
*dev
,
1677 struct drm_i915_gem_request
*request
)
1679 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1681 trace_i915_gem_request_retire(dev
, request
->seqno
);
1683 /* Move any buffers on the active list that are no longer referenced
1684 * by the ringbuffer to the flushing/inactive lists as appropriate.
1686 spin_lock(&dev_priv
->mm
.active_list_lock
);
1687 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1688 struct drm_gem_object
*obj
;
1689 struct drm_i915_gem_object
*obj_priv
;
1691 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1692 struct drm_i915_gem_object
,
1694 obj
= obj_priv
->obj
;
1696 /* If the seqno being retired doesn't match the oldest in the
1697 * list, then the oldest in the list must still be newer than
1700 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1704 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1705 __func__
, request
->seqno
, obj
);
1708 if (obj
->write_domain
!= 0)
1709 i915_gem_object_move_to_flushing(obj
);
1711 /* Take a reference on the object so it won't be
1712 * freed while the spinlock is held. The list
1713 * protection for this spinlock is safe when breaking
1714 * the lock like this since the next thing we do
1715 * is just get the head of the list again.
1717 drm_gem_object_reference(obj
);
1718 i915_gem_object_move_to_inactive(obj
);
1719 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1720 drm_gem_object_unreference(obj
);
1721 spin_lock(&dev_priv
->mm
.active_list_lock
);
1725 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1729 * Returns true if seq1 is later than seq2.
1732 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1734 return (int32_t)(seq1
- seq2
) >= 0;
1738 i915_get_gem_seqno(struct drm_device
*dev
)
1740 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1742 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1746 * This function clears the request list as sequence numbers are passed.
1749 i915_gem_retire_requests(struct drm_device
*dev
)
1751 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1754 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1757 seqno
= i915_get_gem_seqno(dev
);
1759 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1760 struct drm_i915_gem_request
*request
;
1761 uint32_t retiring_seqno
;
1763 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1764 struct drm_i915_gem_request
,
1766 retiring_seqno
= request
->seqno
;
1768 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1769 atomic_read(&dev_priv
->mm
.wedged
)) {
1770 i915_gem_retire_request(dev
, request
);
1772 list_del(&request
->list
);
1773 list_del(&request
->client_list
);
1779 if (unlikely (dev_priv
->trace_irq_seqno
&&
1780 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1781 i915_user_irq_put(dev
);
1782 dev_priv
->trace_irq_seqno
= 0;
1787 i915_gem_retire_work_handler(struct work_struct
*work
)
1789 drm_i915_private_t
*dev_priv
;
1790 struct drm_device
*dev
;
1792 dev_priv
= container_of(work
, drm_i915_private_t
,
1793 mm
.retire_work
.work
);
1794 dev
= dev_priv
->dev
;
1796 mutex_lock(&dev
->struct_mutex
);
1797 i915_gem_retire_requests(dev
);
1798 if (!dev_priv
->mm
.suspended
&&
1799 !list_empty(&dev_priv
->mm
.request_list
))
1800 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1801 mutex_unlock(&dev
->struct_mutex
);
1805 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1807 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1813 if (atomic_read(&dev_priv
->mm
.wedged
))
1816 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1817 if (IS_IRONLAKE(dev
))
1818 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1820 ier
= I915_READ(IER
);
1822 DRM_ERROR("something (likely vbetool) disabled "
1823 "interrupts, re-enabling\n");
1824 i915_driver_irq_preinstall(dev
);
1825 i915_driver_irq_postinstall(dev
);
1828 trace_i915_gem_request_wait_begin(dev
, seqno
);
1830 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1831 i915_user_irq_get(dev
);
1833 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1834 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1835 atomic_read(&dev_priv
->mm
.wedged
));
1837 wait_event(dev_priv
->irq_queue
,
1838 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1839 atomic_read(&dev_priv
->mm
.wedged
));
1841 i915_user_irq_put(dev
);
1842 dev_priv
->mm
.waiting_gem_seqno
= 0;
1844 trace_i915_gem_request_wait_end(dev
, seqno
);
1846 if (atomic_read(&dev_priv
->mm
.wedged
))
1849 if (ret
&& ret
!= -ERESTARTSYS
)
1850 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1851 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1853 /* Directly dispatch request retiring. While we have the work queue
1854 * to handle this, the waiter on a request often wants an associated
1855 * buffer to have made it to the inactive list, and we would need
1856 * a separate wait queue to handle that.
1859 i915_gem_retire_requests(dev
);
1865 * Waits for a sequence number to be signaled, and cleans up the
1866 * request and object lists appropriately for that event.
1869 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1871 return i915_do_wait_request(dev
, seqno
, 1);
1875 i915_gem_flush(struct drm_device
*dev
,
1876 uint32_t invalidate_domains
,
1877 uint32_t flush_domains
)
1879 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1884 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1885 invalidate_domains
, flush_domains
);
1887 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1888 invalidate_domains
, flush_domains
);
1890 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1891 drm_agp_chipset_flush(dev
);
1893 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1895 * read/write caches:
1897 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1898 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1899 * also flushed at 2d versus 3d pipeline switches.
1903 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1904 * MI_READ_FLUSH is set, and is always flushed on 965.
1906 * I915_GEM_DOMAIN_COMMAND may not exist?
1908 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1909 * invalidated when MI_EXE_FLUSH is set.
1911 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1912 * invalidated with every MI_FLUSH.
1916 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1917 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1918 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1919 * are flushed at any MI_FLUSH.
1922 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1923 if ((invalidate_domains
|flush_domains
) &
1924 I915_GEM_DOMAIN_RENDER
)
1925 cmd
&= ~MI_NO_WRITE_FLUSH
;
1926 if (!IS_I965G(dev
)) {
1928 * On the 965, the sampler cache always gets flushed
1929 * and this bit is reserved.
1931 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1932 cmd
|= MI_READ_FLUSH
;
1934 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1935 cmd
|= MI_EXE_FLUSH
;
1938 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1948 * Ensures that all rendering to the object has completed and the object is
1949 * safe to unbind from the GTT or access from the CPU.
1952 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1954 struct drm_device
*dev
= obj
->dev
;
1955 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1958 /* This function only exists to support waiting for existing rendering,
1959 * not for emitting required flushes.
1961 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1963 /* If there is rendering queued on the buffer being evicted, wait for
1966 if (obj_priv
->active
) {
1968 DRM_INFO("%s: object %p wait for seqno %08x\n",
1969 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1971 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1980 * Unbinds an object from the GTT aperture.
1983 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1985 struct drm_device
*dev
= obj
->dev
;
1986 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1990 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1991 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1993 if (obj_priv
->gtt_space
== NULL
)
1996 if (obj_priv
->pin_count
!= 0) {
1997 DRM_ERROR("Attempting to unbind pinned buffer\n");
2001 /* blow away mappings if mapped through GTT */
2002 i915_gem_release_mmap(obj
);
2004 /* Move the object to the CPU domain to ensure that
2005 * any possible CPU writes while it's not in the GTT
2006 * are flushed when we go to remap it. This will
2007 * also ensure that all pending GPU writes are finished
2010 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2012 if (ret
!= -ERESTARTSYS
)
2013 DRM_ERROR("set_domain failed: %d\n", ret
);
2017 BUG_ON(obj_priv
->active
);
2019 /* release the fence reg _after_ flushing */
2020 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2021 i915_gem_clear_fence_reg(obj
);
2023 if (obj_priv
->agp_mem
!= NULL
) {
2024 drm_unbind_agp(obj_priv
->agp_mem
);
2025 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2026 obj_priv
->agp_mem
= NULL
;
2029 i915_gem_object_put_pages(obj
);
2030 BUG_ON(obj_priv
->pages_refcount
);
2032 if (obj_priv
->gtt_space
) {
2033 atomic_dec(&dev
->gtt_count
);
2034 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2036 drm_mm_put_block(obj_priv
->gtt_space
);
2037 obj_priv
->gtt_space
= NULL
;
2040 /* Remove ourselves from the LRU list if present. */
2041 if (!list_empty(&obj_priv
->list
))
2042 list_del_init(&obj_priv
->list
);
2044 if (i915_gem_object_is_purgeable(obj_priv
))
2045 i915_gem_object_truncate(obj
);
2047 trace_i915_gem_object_unbind(obj
);
2052 static struct drm_gem_object
*
2053 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2055 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2056 struct drm_i915_gem_object
*obj_priv
;
2057 struct drm_gem_object
*best
= NULL
;
2058 struct drm_gem_object
*first
= NULL
;
2060 /* Try to find the smallest clean object */
2061 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2062 struct drm_gem_object
*obj
= obj_priv
->obj
;
2063 if (obj
->size
>= min_size
) {
2064 if ((!obj_priv
->dirty
||
2065 i915_gem_object_is_purgeable(obj_priv
)) &&
2066 (!best
|| obj
->size
< best
->size
)) {
2068 if (best
->size
== min_size
)
2076 return best
? best
: first
;
2080 i915_gem_evict_everything(struct drm_device
*dev
)
2082 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2087 spin_lock(&dev_priv
->mm
.active_list_lock
);
2088 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2089 list_empty(&dev_priv
->mm
.flushing_list
) &&
2090 list_empty(&dev_priv
->mm
.active_list
));
2091 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2096 /* Flush everything (on to the inactive lists) and evict */
2097 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2098 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2102 ret
= i915_wait_request(dev
, seqno
);
2106 ret
= i915_gem_evict_from_inactive_list(dev
);
2110 spin_lock(&dev_priv
->mm
.active_list_lock
);
2111 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2112 list_empty(&dev_priv
->mm
.flushing_list
) &&
2113 list_empty(&dev_priv
->mm
.active_list
));
2114 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2115 BUG_ON(!lists_empty
);
2121 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2123 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2124 struct drm_gem_object
*obj
;
2128 i915_gem_retire_requests(dev
);
2130 /* If there's an inactive buffer available now, grab it
2133 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2135 struct drm_i915_gem_object
*obj_priv
;
2138 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2140 obj_priv
= obj
->driver_private
;
2141 BUG_ON(obj_priv
->pin_count
!= 0);
2142 BUG_ON(obj_priv
->active
);
2144 /* Wait on the rendering and unbind the buffer. */
2145 return i915_gem_object_unbind(obj
);
2148 /* If we didn't get anything, but the ring is still processing
2149 * things, wait for the next to finish and hopefully leave us
2150 * a buffer to evict.
2152 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2153 struct drm_i915_gem_request
*request
;
2155 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2156 struct drm_i915_gem_request
,
2159 ret
= i915_wait_request(dev
, request
->seqno
);
2166 /* If we didn't have anything on the request list but there
2167 * are buffers awaiting a flush, emit one and try again.
2168 * When we wait on it, those buffers waiting for that flush
2169 * will get moved to inactive.
2171 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2172 struct drm_i915_gem_object
*obj_priv
;
2174 /* Find an object that we can immediately reuse */
2175 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2176 obj
= obj_priv
->obj
;
2177 if (obj
->size
>= min_size
)
2189 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2193 ret
= i915_wait_request(dev
, seqno
);
2201 /* If we didn't do any of the above, there's no single buffer
2202 * large enough to swap out for the new one, so just evict
2203 * everything and start again. (This should be rare.)
2205 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2206 return i915_gem_evict_from_inactive_list(dev
);
2208 return i915_gem_evict_everything(dev
);
2213 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2216 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2218 struct address_space
*mapping
;
2219 struct inode
*inode
;
2223 if (obj_priv
->pages_refcount
++ != 0)
2226 /* Get the list of pages out of our struct file. They'll be pinned
2227 * at this point until we release them.
2229 page_count
= obj
->size
/ PAGE_SIZE
;
2230 BUG_ON(obj_priv
->pages
!= NULL
);
2231 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2232 if (obj_priv
->pages
== NULL
) {
2233 obj_priv
->pages_refcount
--;
2237 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2238 mapping
= inode
->i_mapping
;
2239 for (i
= 0; i
< page_count
; i
++) {
2240 page
= read_cache_page_gfp(mapping
, i
,
2241 mapping_gfp_mask (mapping
) |
2245 ret
= PTR_ERR(page
);
2246 i915_gem_object_put_pages(obj
);
2249 obj_priv
->pages
[i
] = page
;
2252 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2253 i915_gem_object_do_bit_17_swizzle(obj
);
2258 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2260 struct drm_gem_object
*obj
= reg
->obj
;
2261 struct drm_device
*dev
= obj
->dev
;
2262 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2263 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2264 int regnum
= obj_priv
->fence_reg
;
2267 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2269 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2270 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2271 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2272 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2273 val
|= I965_FENCE_REG_VALID
;
2275 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2278 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2280 struct drm_gem_object
*obj
= reg
->obj
;
2281 struct drm_device
*dev
= obj
->dev
;
2282 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2283 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2284 int regnum
= obj_priv
->fence_reg
;
2286 uint32_t fence_reg
, val
;
2289 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2290 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2291 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2292 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2296 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2297 HAS_128_BYTE_Y_TILING(dev
))
2302 /* Note: pitch better be a power of two tile widths */
2303 pitch_val
= obj_priv
->stride
/ tile_width
;
2304 pitch_val
= ffs(pitch_val
) - 1;
2306 val
= obj_priv
->gtt_offset
;
2307 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2308 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2309 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2310 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2311 val
|= I830_FENCE_REG_VALID
;
2314 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2316 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2317 I915_WRITE(fence_reg
, val
);
2320 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2322 struct drm_gem_object
*obj
= reg
->obj
;
2323 struct drm_device
*dev
= obj
->dev
;
2324 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2325 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2326 int regnum
= obj_priv
->fence_reg
;
2329 uint32_t fence_size_bits
;
2331 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2332 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2333 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2334 __func__
, obj_priv
->gtt_offset
);
2338 pitch_val
= obj_priv
->stride
/ 128;
2339 pitch_val
= ffs(pitch_val
) - 1;
2340 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2342 val
= obj_priv
->gtt_offset
;
2343 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2344 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2345 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2346 WARN_ON(fence_size_bits
& ~0x00000f00);
2347 val
|= fence_size_bits
;
2348 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2349 val
|= I830_FENCE_REG_VALID
;
2351 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2355 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2356 * @obj: object to map through a fence reg
2358 * When mapping objects through the GTT, userspace wants to be able to write
2359 * to them without having to worry about swizzling if the object is tiled.
2361 * This function walks the fence regs looking for a free one for @obj,
2362 * stealing one if it can't find any.
2364 * It then sets up the reg based on the object's properties: address, pitch
2365 * and tiling format.
2368 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2370 struct drm_device
*dev
= obj
->dev
;
2371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2372 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2373 struct drm_i915_fence_reg
*reg
= NULL
;
2374 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2377 /* Just update our place in the LRU if our fence is getting used. */
2378 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2379 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2383 switch (obj_priv
->tiling_mode
) {
2384 case I915_TILING_NONE
:
2385 WARN(1, "allocating a fence for non-tiled object?\n");
2388 if (!obj_priv
->stride
)
2390 WARN((obj_priv
->stride
& (512 - 1)),
2391 "object 0x%08x is X tiled but has non-512B pitch\n",
2392 obj_priv
->gtt_offset
);
2395 if (!obj_priv
->stride
)
2397 WARN((obj_priv
->stride
& (128 - 1)),
2398 "object 0x%08x is Y tiled but has non-128B pitch\n",
2399 obj_priv
->gtt_offset
);
2403 /* First try to find a free reg */
2405 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2406 reg
= &dev_priv
->fence_regs
[i
];
2410 old_obj_priv
= reg
->obj
->driver_private
;
2411 if (!old_obj_priv
->pin_count
)
2415 /* None available, try to steal one or wait for a user to finish */
2416 if (i
== dev_priv
->num_fence_regs
) {
2417 struct drm_gem_object
*old_obj
= NULL
;
2422 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2424 old_obj
= old_obj_priv
->obj
;
2426 if (old_obj_priv
->pin_count
)
2429 /* Take a reference, as otherwise the wait_rendering
2430 * below may cause the object to get freed out from
2433 drm_gem_object_reference(old_obj
);
2435 /* i915 uses fences for GPU access to tiled buffers */
2436 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2439 /* This brings the object to the head of the LRU if it
2440 * had been written to. The only way this should
2441 * result in us waiting longer than the expected
2442 * optimal amount of time is if there was a
2443 * fence-using buffer later that was read-only.
2445 i915_gem_object_flush_gpu_write_domain(old_obj
);
2446 ret
= i915_gem_object_wait_rendering(old_obj
);
2448 drm_gem_object_unreference(old_obj
);
2456 * Zap this virtual mapping so we can set up a fence again
2457 * for this object next time we need it.
2459 i915_gem_release_mmap(old_obj
);
2461 i
= old_obj_priv
->fence_reg
;
2462 reg
= &dev_priv
->fence_regs
[i
];
2464 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2465 list_del_init(&old_obj_priv
->fence_list
);
2467 drm_gem_object_unreference(old_obj
);
2470 obj_priv
->fence_reg
= i
;
2471 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2476 i965_write_fence_reg(reg
);
2477 else if (IS_I9XX(dev
))
2478 i915_write_fence_reg(reg
);
2480 i830_write_fence_reg(reg
);
2482 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2488 * i915_gem_clear_fence_reg - clear out fence register info
2489 * @obj: object to clear
2491 * Zeroes out the fence register itself and clears out the associated
2492 * data structures in dev_priv and obj_priv.
2495 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2497 struct drm_device
*dev
= obj
->dev
;
2498 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2499 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2502 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2506 if (obj_priv
->fence_reg
< 8)
2507 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2509 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2512 I915_WRITE(fence_reg
, 0);
2515 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2516 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2517 list_del_init(&obj_priv
->fence_list
);
2521 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2522 * to the buffer to finish, and then resets the fence register.
2523 * @obj: tiled object holding a fence register.
2525 * Zeroes out the fence register itself and clears out the associated
2526 * data structures in dev_priv and obj_priv.
2529 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2531 struct drm_device
*dev
= obj
->dev
;
2532 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2534 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2537 /* On the i915, GPU access to tiled buffers is via a fence,
2538 * therefore we must wait for any outstanding access to complete
2539 * before clearing the fence.
2541 if (!IS_I965G(dev
)) {
2544 i915_gem_object_flush_gpu_write_domain(obj
);
2545 i915_gem_object_flush_gtt_write_domain(obj
);
2546 ret
= i915_gem_object_wait_rendering(obj
);
2551 i915_gem_clear_fence_reg (obj
);
2557 * Finds free space in the GTT aperture and binds the object there.
2560 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2562 struct drm_device
*dev
= obj
->dev
;
2563 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2564 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2565 struct drm_mm_node
*free_space
;
2566 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2569 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2570 DRM_ERROR("Attempting to bind a purgeable object\n");
2575 alignment
= i915_gem_get_gtt_alignment(obj
);
2576 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2577 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2582 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2583 obj
->size
, alignment
, 0);
2584 if (free_space
!= NULL
) {
2585 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2587 if (obj_priv
->gtt_space
!= NULL
) {
2588 obj_priv
->gtt_space
->private = obj
;
2589 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2592 if (obj_priv
->gtt_space
== NULL
) {
2593 /* If the gtt is empty and we're still having trouble
2594 * fitting our object in, we're out of memory.
2597 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2599 ret
= i915_gem_evict_something(dev
, obj
->size
);
2607 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2608 obj
->size
, obj_priv
->gtt_offset
);
2610 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2612 drm_mm_put_block(obj_priv
->gtt_space
);
2613 obj_priv
->gtt_space
= NULL
;
2615 if (ret
== -ENOMEM
) {
2616 /* first try to clear up some space from the GTT */
2617 ret
= i915_gem_evict_something(dev
, obj
->size
);
2619 /* now try to shrink everyone else */
2634 /* Create an AGP memory structure pointing at our pages, and bind it
2637 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2639 obj
->size
>> PAGE_SHIFT
,
2640 obj_priv
->gtt_offset
,
2641 obj_priv
->agp_type
);
2642 if (obj_priv
->agp_mem
== NULL
) {
2643 i915_gem_object_put_pages(obj
);
2644 drm_mm_put_block(obj_priv
->gtt_space
);
2645 obj_priv
->gtt_space
= NULL
;
2647 ret
= i915_gem_evict_something(dev
, obj
->size
);
2653 atomic_inc(&dev
->gtt_count
);
2654 atomic_add(obj
->size
, &dev
->gtt_memory
);
2656 /* Assert that the object is not currently in any GPU domain. As it
2657 * wasn't in the GTT, there shouldn't be any way it could have been in
2660 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2661 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2663 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2669 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2671 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2673 /* If we don't have a page list set up, then we're not pinned
2674 * to GPU, and we can ignore the cache flush because it'll happen
2675 * again at bind time.
2677 if (obj_priv
->pages
== NULL
)
2680 trace_i915_gem_object_clflush(obj
);
2682 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2685 /** Flushes any GPU write domain for the object if it's dirty. */
2687 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2689 struct drm_device
*dev
= obj
->dev
;
2691 uint32_t old_write_domain
;
2693 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2696 /* Queue the GPU write cache flushing we need. */
2697 old_write_domain
= obj
->write_domain
;
2698 i915_gem_flush(dev
, 0, obj
->write_domain
);
2699 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2700 obj
->write_domain
= 0;
2701 i915_gem_object_move_to_active(obj
, seqno
);
2703 trace_i915_gem_object_change_domain(obj
,
2708 /** Flushes the GTT write domain for the object if it's dirty. */
2710 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2712 uint32_t old_write_domain
;
2714 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2717 /* No actual flushing is required for the GTT write domain. Writes
2718 * to it immediately go to main memory as far as we know, so there's
2719 * no chipset flush. It also doesn't land in render cache.
2721 old_write_domain
= obj
->write_domain
;
2722 obj
->write_domain
= 0;
2724 trace_i915_gem_object_change_domain(obj
,
2729 /** Flushes the CPU write domain for the object if it's dirty. */
2731 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2733 struct drm_device
*dev
= obj
->dev
;
2734 uint32_t old_write_domain
;
2736 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2739 i915_gem_clflush_object(obj
);
2740 drm_agp_chipset_flush(dev
);
2741 old_write_domain
= obj
->write_domain
;
2742 obj
->write_domain
= 0;
2744 trace_i915_gem_object_change_domain(obj
,
2750 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2752 switch (obj
->write_domain
) {
2753 case I915_GEM_DOMAIN_GTT
:
2754 i915_gem_object_flush_gtt_write_domain(obj
);
2756 case I915_GEM_DOMAIN_CPU
:
2757 i915_gem_object_flush_cpu_write_domain(obj
);
2760 i915_gem_object_flush_gpu_write_domain(obj
);
2766 * Moves a single object to the GTT read, and possibly write domain.
2768 * This function returns when the move is complete, including waiting on
2772 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2774 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2775 uint32_t old_write_domain
, old_read_domains
;
2778 /* Not valid to be called on unbound objects. */
2779 if (obj_priv
->gtt_space
== NULL
)
2782 i915_gem_object_flush_gpu_write_domain(obj
);
2783 /* Wait on any GPU rendering and flushing to occur. */
2784 ret
= i915_gem_object_wait_rendering(obj
);
2788 old_write_domain
= obj
->write_domain
;
2789 old_read_domains
= obj
->read_domains
;
2791 /* If we're writing through the GTT domain, then CPU and GPU caches
2792 * will need to be invalidated at next use.
2795 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2797 i915_gem_object_flush_cpu_write_domain(obj
);
2799 /* It should now be out of any other write domains, and we can update
2800 * the domain values for our changes.
2802 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2803 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2805 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2806 obj_priv
->dirty
= 1;
2809 trace_i915_gem_object_change_domain(obj
,
2817 * Prepare buffer for display plane. Use uninterruptible for possible flush
2818 * wait, as in modesetting process we're not supposed to be interrupted.
2821 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2823 struct drm_device
*dev
= obj
->dev
;
2824 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2825 uint32_t old_write_domain
, old_read_domains
;
2828 /* Not valid to be called on unbound objects. */
2829 if (obj_priv
->gtt_space
== NULL
)
2832 i915_gem_object_flush_gpu_write_domain(obj
);
2834 /* Wait on any GPU rendering and flushing to occur. */
2835 if (obj_priv
->active
) {
2837 DRM_INFO("%s: object %p wait for seqno %08x\n",
2838 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2840 ret
= i915_do_wait_request(dev
, obj_priv
->last_rendering_seqno
, 0);
2845 old_write_domain
= obj
->write_domain
;
2846 old_read_domains
= obj
->read_domains
;
2848 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2850 i915_gem_object_flush_cpu_write_domain(obj
);
2852 /* It should now be out of any other write domains, and we can update
2853 * the domain values for our changes.
2855 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2856 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2857 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2858 obj_priv
->dirty
= 1;
2860 trace_i915_gem_object_change_domain(obj
,
2868 * Moves a single object to the CPU read, and possibly write domain.
2870 * This function returns when the move is complete, including waiting on
2874 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2876 uint32_t old_write_domain
, old_read_domains
;
2879 i915_gem_object_flush_gpu_write_domain(obj
);
2880 /* Wait on any GPU rendering and flushing to occur. */
2881 ret
= i915_gem_object_wait_rendering(obj
);
2885 i915_gem_object_flush_gtt_write_domain(obj
);
2887 /* If we have a partially-valid cache of the object in the CPU,
2888 * finish invalidating it and free the per-page flags.
2890 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2892 old_write_domain
= obj
->write_domain
;
2893 old_read_domains
= obj
->read_domains
;
2895 /* Flush the CPU cache if it's still invalid. */
2896 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2897 i915_gem_clflush_object(obj
);
2899 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2902 /* It should now be out of any other write domains, and we can update
2903 * the domain values for our changes.
2905 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2907 /* If we're writing through the CPU, then the GPU read domains will
2908 * need to be invalidated at next use.
2911 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2912 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2915 trace_i915_gem_object_change_domain(obj
,
2923 * Set the next domain for the specified object. This
2924 * may not actually perform the necessary flushing/invaliding though,
2925 * as that may want to be batched with other set_domain operations
2927 * This is (we hope) the only really tricky part of gem. The goal
2928 * is fairly simple -- track which caches hold bits of the object
2929 * and make sure they remain coherent. A few concrete examples may
2930 * help to explain how it works. For shorthand, we use the notation
2931 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2932 * a pair of read and write domain masks.
2934 * Case 1: the batch buffer
2940 * 5. Unmapped from GTT
2943 * Let's take these a step at a time
2946 * Pages allocated from the kernel may still have
2947 * cache contents, so we set them to (CPU, CPU) always.
2948 * 2. Written by CPU (using pwrite)
2949 * The pwrite function calls set_domain (CPU, CPU) and
2950 * this function does nothing (as nothing changes)
2952 * This function asserts that the object is not
2953 * currently in any GPU-based read or write domains
2955 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2956 * As write_domain is zero, this function adds in the
2957 * current read domains (CPU+COMMAND, 0).
2958 * flush_domains is set to CPU.
2959 * invalidate_domains is set to COMMAND
2960 * clflush is run to get data out of the CPU caches
2961 * then i915_dev_set_domain calls i915_gem_flush to
2962 * emit an MI_FLUSH and drm_agp_chipset_flush
2963 * 5. Unmapped from GTT
2964 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2965 * flush_domains and invalidate_domains end up both zero
2966 * so no flushing/invalidating happens
2970 * Case 2: The shared render buffer
2974 * 3. Read/written by GPU
2975 * 4. set_domain to (CPU,CPU)
2976 * 5. Read/written by CPU
2977 * 6. Read/written by GPU
2980 * Same as last example, (CPU, CPU)
2982 * Nothing changes (assertions find that it is not in the GPU)
2983 * 3. Read/written by GPU
2984 * execbuffer calls set_domain (RENDER, RENDER)
2985 * flush_domains gets CPU
2986 * invalidate_domains gets GPU
2988 * MI_FLUSH and drm_agp_chipset_flush
2989 * 4. set_domain (CPU, CPU)
2990 * flush_domains gets GPU
2991 * invalidate_domains gets CPU
2992 * wait_rendering (obj) to make sure all drawing is complete.
2993 * This will include an MI_FLUSH to get the data from GPU
2995 * clflush (obj) to invalidate the CPU cache
2996 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2997 * 5. Read/written by CPU
2998 * cache lines are loaded and dirtied
2999 * 6. Read written by GPU
3000 * Same as last GPU access
3002 * Case 3: The constant buffer
3007 * 4. Updated (written) by CPU again
3016 * flush_domains = CPU
3017 * invalidate_domains = RENDER
3020 * drm_agp_chipset_flush
3021 * 4. Updated (written) by CPU again
3023 * flush_domains = 0 (no previous write domain)
3024 * invalidate_domains = 0 (no new read domains)
3027 * flush_domains = CPU
3028 * invalidate_domains = RENDER
3031 * drm_agp_chipset_flush
3034 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3036 struct drm_device
*dev
= obj
->dev
;
3037 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3038 uint32_t invalidate_domains
= 0;
3039 uint32_t flush_domains
= 0;
3040 uint32_t old_read_domains
;
3042 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3043 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3045 intel_mark_busy(dev
, obj
);
3048 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3050 obj
->read_domains
, obj
->pending_read_domains
,
3051 obj
->write_domain
, obj
->pending_write_domain
);
3054 * If the object isn't moving to a new write domain,
3055 * let the object stay in multiple read domains
3057 if (obj
->pending_write_domain
== 0)
3058 obj
->pending_read_domains
|= obj
->read_domains
;
3060 obj_priv
->dirty
= 1;
3063 * Flush the current write domain if
3064 * the new read domains don't match. Invalidate
3065 * any read domains which differ from the old
3068 if (obj
->write_domain
&&
3069 obj
->write_domain
!= obj
->pending_read_domains
) {
3070 flush_domains
|= obj
->write_domain
;
3071 invalidate_domains
|=
3072 obj
->pending_read_domains
& ~obj
->write_domain
;
3075 * Invalidate any read caches which may have
3076 * stale data. That is, any new read domains.
3078 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3079 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3081 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3082 __func__
, flush_domains
, invalidate_domains
);
3084 i915_gem_clflush_object(obj
);
3087 old_read_domains
= obj
->read_domains
;
3089 /* The actual obj->write_domain will be updated with
3090 * pending_write_domain after we emit the accumulated flush for all
3091 * of our domain changes in execbuffers (which clears objects'
3092 * write_domains). So if we have a current write domain that we
3093 * aren't changing, set pending_write_domain to that.
3095 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3096 obj
->pending_write_domain
= obj
->write_domain
;
3097 obj
->read_domains
= obj
->pending_read_domains
;
3099 dev
->invalidate_domains
|= invalidate_domains
;
3100 dev
->flush_domains
|= flush_domains
;
3102 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3104 obj
->read_domains
, obj
->write_domain
,
3105 dev
->invalidate_domains
, dev
->flush_domains
);
3108 trace_i915_gem_object_change_domain(obj
,
3114 * Moves the object from a partially CPU read to a full one.
3116 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3117 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3120 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3122 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3124 if (!obj_priv
->page_cpu_valid
)
3127 /* If we're partially in the CPU read domain, finish moving it in.
3129 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3132 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3133 if (obj_priv
->page_cpu_valid
[i
])
3135 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3139 /* Free the page_cpu_valid mappings which are now stale, whether
3140 * or not we've got I915_GEM_DOMAIN_CPU.
3142 kfree(obj_priv
->page_cpu_valid
);
3143 obj_priv
->page_cpu_valid
= NULL
;
3147 * Set the CPU read domain on a range of the object.
3149 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3150 * not entirely valid. The page_cpu_valid member of the object flags which
3151 * pages have been flushed, and will be respected by
3152 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3153 * of the whole object.
3155 * This function returns when the move is complete, including waiting on
3159 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3160 uint64_t offset
, uint64_t size
)
3162 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3163 uint32_t old_read_domains
;
3166 if (offset
== 0 && size
== obj
->size
)
3167 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3169 i915_gem_object_flush_gpu_write_domain(obj
);
3170 /* Wait on any GPU rendering and flushing to occur. */
3171 ret
= i915_gem_object_wait_rendering(obj
);
3174 i915_gem_object_flush_gtt_write_domain(obj
);
3176 /* If we're already fully in the CPU read domain, we're done. */
3177 if (obj_priv
->page_cpu_valid
== NULL
&&
3178 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3181 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3182 * newly adding I915_GEM_DOMAIN_CPU
3184 if (obj_priv
->page_cpu_valid
== NULL
) {
3185 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3187 if (obj_priv
->page_cpu_valid
== NULL
)
3189 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3190 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3192 /* Flush the cache on any pages that are still invalid from the CPU's
3195 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3197 if (obj_priv
->page_cpu_valid
[i
])
3200 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3202 obj_priv
->page_cpu_valid
[i
] = 1;
3205 /* It should now be out of any other write domains, and we can update
3206 * the domain values for our changes.
3208 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3210 old_read_domains
= obj
->read_domains
;
3211 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3213 trace_i915_gem_object_change_domain(obj
,
3221 * Pin an object to the GTT and evaluate the relocations landing in it.
3224 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3225 struct drm_file
*file_priv
,
3226 struct drm_i915_gem_exec_object2
*entry
,
3227 struct drm_i915_gem_relocation_entry
*relocs
)
3229 struct drm_device
*dev
= obj
->dev
;
3230 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3231 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3233 void __iomem
*reloc_page
;
3236 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3237 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3239 /* Check fence reg constraints and rebind if necessary */
3240 if (need_fence
&& !i915_obj_fenceable(dev
, obj
))
3241 i915_gem_object_unbind(obj
);
3243 /* Choose the GTT offset for our buffer and put it there. */
3244 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3249 * Pre-965 chips need a fence register set up in order to
3250 * properly handle blits to/from tiled surfaces.
3253 ret
= i915_gem_object_get_fence_reg(obj
);
3255 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3256 DRM_ERROR("Failure to install fence: %d\n",
3258 i915_gem_object_unpin(obj
);
3263 entry
->offset
= obj_priv
->gtt_offset
;
3265 /* Apply the relocations, using the GTT aperture to avoid cache
3266 * flushing requirements.
3268 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3269 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3270 struct drm_gem_object
*target_obj
;
3271 struct drm_i915_gem_object
*target_obj_priv
;
3272 uint32_t reloc_val
, reloc_offset
;
3273 uint32_t __iomem
*reloc_entry
;
3275 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3276 reloc
->target_handle
);
3277 if (target_obj
== NULL
) {
3278 i915_gem_object_unpin(obj
);
3281 target_obj_priv
= target_obj
->driver_private
;
3284 DRM_INFO("%s: obj %p offset %08x target %d "
3285 "read %08x write %08x gtt %08x "
3286 "presumed %08x delta %08x\n",
3289 (int) reloc
->offset
,
3290 (int) reloc
->target_handle
,
3291 (int) reloc
->read_domains
,
3292 (int) reloc
->write_domain
,
3293 (int) target_obj_priv
->gtt_offset
,
3294 (int) reloc
->presumed_offset
,
3298 /* The target buffer should have appeared before us in the
3299 * exec_object list, so it should have a GTT space bound by now.
3301 if (target_obj_priv
->gtt_space
== NULL
) {
3302 DRM_ERROR("No GTT space found for object %d\n",
3303 reloc
->target_handle
);
3304 drm_gem_object_unreference(target_obj
);
3305 i915_gem_object_unpin(obj
);
3309 /* Validate that the target is in a valid r/w GPU domain */
3310 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3311 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3312 DRM_ERROR("reloc with read/write CPU domains: "
3313 "obj %p target %d offset %d "
3314 "read %08x write %08x",
3315 obj
, reloc
->target_handle
,
3316 (int) reloc
->offset
,
3317 reloc
->read_domains
,
3318 reloc
->write_domain
);
3319 drm_gem_object_unreference(target_obj
);
3320 i915_gem_object_unpin(obj
);
3323 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3324 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3325 DRM_ERROR("Write domain conflict: "
3326 "obj %p target %d offset %d "
3327 "new %08x old %08x\n",
3328 obj
, reloc
->target_handle
,
3329 (int) reloc
->offset
,
3330 reloc
->write_domain
,
3331 target_obj
->pending_write_domain
);
3332 drm_gem_object_unreference(target_obj
);
3333 i915_gem_object_unpin(obj
);
3337 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3338 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3340 /* If the relocation already has the right value in it, no
3341 * more work needs to be done.
3343 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3344 drm_gem_object_unreference(target_obj
);
3348 /* Check that the relocation address is valid... */
3349 if (reloc
->offset
> obj
->size
- 4) {
3350 DRM_ERROR("Relocation beyond object bounds: "
3351 "obj %p target %d offset %d size %d.\n",
3352 obj
, reloc
->target_handle
,
3353 (int) reloc
->offset
, (int) obj
->size
);
3354 drm_gem_object_unreference(target_obj
);
3355 i915_gem_object_unpin(obj
);
3358 if (reloc
->offset
& 3) {
3359 DRM_ERROR("Relocation not 4-byte aligned: "
3360 "obj %p target %d offset %d.\n",
3361 obj
, reloc
->target_handle
,
3362 (int) reloc
->offset
);
3363 drm_gem_object_unreference(target_obj
);
3364 i915_gem_object_unpin(obj
);
3368 /* and points to somewhere within the target object. */
3369 if (reloc
->delta
>= target_obj
->size
) {
3370 DRM_ERROR("Relocation beyond target object bounds: "
3371 "obj %p target %d delta %d size %d.\n",
3372 obj
, reloc
->target_handle
,
3373 (int) reloc
->delta
, (int) target_obj
->size
);
3374 drm_gem_object_unreference(target_obj
);
3375 i915_gem_object_unpin(obj
);
3379 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3381 drm_gem_object_unreference(target_obj
);
3382 i915_gem_object_unpin(obj
);
3386 /* Map the page containing the relocation we're going to
3389 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3390 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3393 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3394 (reloc_offset
& (PAGE_SIZE
- 1)));
3395 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3398 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3399 obj
, (unsigned int) reloc
->offset
,
3400 readl(reloc_entry
), reloc_val
);
3402 writel(reloc_val
, reloc_entry
);
3403 io_mapping_unmap_atomic(reloc_page
);
3405 /* The updated presumed offset for this entry will be
3406 * copied back out to the user.
3408 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3410 drm_gem_object_unreference(target_obj
);
3415 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3420 /** Dispatch a batchbuffer to the ring
3423 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3424 struct drm_i915_gem_execbuffer2
*exec
,
3425 struct drm_clip_rect
*cliprects
,
3426 uint64_t exec_offset
)
3428 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3429 int nbox
= exec
->num_cliprects
;
3431 uint32_t exec_start
, exec_len
;
3434 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3435 exec_len
= (uint32_t) exec
->batch_len
;
3437 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3439 count
= nbox
? nbox
: 1;
3441 for (i
= 0; i
< count
; i
++) {
3443 int ret
= i915_emit_box(dev
, cliprects
, i
,
3444 exec
->DR1
, exec
->DR4
);
3449 if (IS_I830(dev
) || IS_845G(dev
)) {
3451 OUT_RING(MI_BATCH_BUFFER
);
3452 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3453 OUT_RING(exec_start
+ exec_len
- 4);
3458 if (IS_I965G(dev
)) {
3459 OUT_RING(MI_BATCH_BUFFER_START
|
3461 MI_BATCH_NON_SECURE_I965
);
3462 OUT_RING(exec_start
);
3464 OUT_RING(MI_BATCH_BUFFER_START
|
3466 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3472 /* XXX breadcrumb */
3476 /* Throttle our rendering by waiting until the ring has completed our requests
3477 * emitted over 20 msec ago.
3479 * Note that if we were to use the current jiffies each time around the loop,
3480 * we wouldn't escape the function with any frames outstanding if the time to
3481 * render a frame was over 20ms.
3483 * This should get us reasonable parallelism between CPU and GPU but also
3484 * relatively low latency when blocking on a particular request to finish.
3487 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3489 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3491 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3493 mutex_lock(&dev
->struct_mutex
);
3494 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3495 struct drm_i915_gem_request
*request
;
3497 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3498 struct drm_i915_gem_request
,
3501 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3504 ret
= i915_wait_request(dev
, request
->seqno
);
3508 mutex_unlock(&dev
->struct_mutex
);
3514 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3515 uint32_t buffer_count
,
3516 struct drm_i915_gem_relocation_entry
**relocs
)
3518 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3522 for (i
= 0; i
< buffer_count
; i
++) {
3523 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3525 reloc_count
+= exec_list
[i
].relocation_count
;
3528 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3529 if (*relocs
== NULL
) {
3530 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3534 for (i
= 0; i
< buffer_count
; i
++) {
3535 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3537 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3539 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3541 exec_list
[i
].relocation_count
*
3544 drm_free_large(*relocs
);
3549 reloc_index
+= exec_list
[i
].relocation_count
;
3556 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3557 uint32_t buffer_count
,
3558 struct drm_i915_gem_relocation_entry
*relocs
)
3560 uint32_t reloc_count
= 0, i
;
3566 for (i
= 0; i
< buffer_count
; i
++) {
3567 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3570 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3572 unwritten
= copy_to_user(user_relocs
,
3573 &relocs
[reloc_count
],
3574 exec_list
[i
].relocation_count
*
3582 reloc_count
+= exec_list
[i
].relocation_count
;
3586 drm_free_large(relocs
);
3592 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3593 uint64_t exec_offset
)
3595 uint32_t exec_start
, exec_len
;
3597 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3598 exec_len
= (uint32_t) exec
->batch_len
;
3600 if ((exec_start
| exec_len
) & 0x7)
3610 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3611 struct drm_gem_object
**object_list
,
3614 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3615 struct drm_i915_gem_object
*obj_priv
;
3620 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3621 &wait
, TASK_INTERRUPTIBLE
);
3622 for (i
= 0; i
< count
; i
++) {
3623 obj_priv
= object_list
[i
]->driver_private
;
3624 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3630 if (!signal_pending(current
)) {
3631 mutex_unlock(&dev
->struct_mutex
);
3633 mutex_lock(&dev
->struct_mutex
);
3639 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3645 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3646 struct drm_file
*file_priv
,
3647 struct drm_i915_gem_execbuffer2
*args
,
3648 struct drm_i915_gem_exec_object2
*exec_list
)
3650 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3651 struct drm_gem_object
**object_list
= NULL
;
3652 struct drm_gem_object
*batch_obj
;
3653 struct drm_i915_gem_object
*obj_priv
;
3654 struct drm_clip_rect
*cliprects
= NULL
;
3655 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3656 int ret
= 0, ret2
, i
, pinned
= 0;
3657 uint64_t exec_offset
;
3658 uint32_t seqno
, flush_domains
, reloc_index
;
3659 int pin_tries
, flips
;
3662 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3663 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3666 if (args
->buffer_count
< 1) {
3667 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3670 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3671 if (object_list
== NULL
) {
3672 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3673 args
->buffer_count
);
3678 if (args
->num_cliprects
!= 0) {
3679 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3681 if (cliprects
== NULL
)
3684 ret
= copy_from_user(cliprects
,
3685 (struct drm_clip_rect __user
*)
3686 (uintptr_t) args
->cliprects_ptr
,
3687 sizeof(*cliprects
) * args
->num_cliprects
);
3689 DRM_ERROR("copy %d cliprects failed: %d\n",
3690 args
->num_cliprects
, ret
);
3695 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3700 mutex_lock(&dev
->struct_mutex
);
3702 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3704 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3705 mutex_unlock(&dev
->struct_mutex
);
3710 if (dev_priv
->mm
.suspended
) {
3711 mutex_unlock(&dev
->struct_mutex
);
3716 /* Look up object handles */
3718 for (i
= 0; i
< args
->buffer_count
; i
++) {
3719 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3720 exec_list
[i
].handle
);
3721 if (object_list
[i
] == NULL
) {
3722 DRM_ERROR("Invalid object handle %d at index %d\n",
3723 exec_list
[i
].handle
, i
);
3724 /* prevent error path from reading uninitialized data */
3725 args
->buffer_count
= i
+ 1;
3730 obj_priv
= object_list
[i
]->driver_private
;
3731 if (obj_priv
->in_execbuffer
) {
3732 DRM_ERROR("Object %p appears more than once in object list\n",
3734 /* prevent error path from reading uninitialized data */
3735 args
->buffer_count
= i
+ 1;
3739 obj_priv
->in_execbuffer
= true;
3740 flips
+= atomic_read(&obj_priv
->pending_flip
);
3744 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3745 args
->buffer_count
);
3750 /* Pin and relocate */
3751 for (pin_tries
= 0; ; pin_tries
++) {
3755 for (i
= 0; i
< args
->buffer_count
; i
++) {
3756 object_list
[i
]->pending_read_domains
= 0;
3757 object_list
[i
]->pending_write_domain
= 0;
3758 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3761 &relocs
[reloc_index
]);
3765 reloc_index
+= exec_list
[i
].relocation_count
;
3771 /* error other than GTT full, or we've already tried again */
3772 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3773 if (ret
!= -ERESTARTSYS
) {
3774 unsigned long long total_size
= 0;
3775 for (i
= 0; i
< args
->buffer_count
; i
++)
3776 total_size
+= object_list
[i
]->size
;
3777 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3778 pinned
+1, args
->buffer_count
,
3780 DRM_ERROR("%d objects [%d pinned], "
3781 "%d object bytes [%d pinned], "
3782 "%d/%d gtt bytes\n",
3783 atomic_read(&dev
->object_count
),
3784 atomic_read(&dev
->pin_count
),
3785 atomic_read(&dev
->object_memory
),
3786 atomic_read(&dev
->pin_memory
),
3787 atomic_read(&dev
->gtt_memory
),
3793 /* unpin all of our buffers */
3794 for (i
= 0; i
< pinned
; i
++)
3795 i915_gem_object_unpin(object_list
[i
]);
3798 /* evict everyone we can from the aperture */
3799 ret
= i915_gem_evict_everything(dev
);
3800 if (ret
&& ret
!= -ENOSPC
)
3804 /* Set the pending read domains for the batch buffer to COMMAND */
3805 batch_obj
= object_list
[args
->buffer_count
-1];
3806 if (batch_obj
->pending_write_domain
) {
3807 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3811 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3813 /* Sanity check the batch buffer, prior to moving objects */
3814 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3815 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3817 DRM_ERROR("execbuf with invalid offset/length\n");
3821 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3823 /* Zero the global flush/invalidate flags. These
3824 * will be modified as new domains are computed
3827 dev
->invalidate_domains
= 0;
3828 dev
->flush_domains
= 0;
3830 for (i
= 0; i
< args
->buffer_count
; i
++) {
3831 struct drm_gem_object
*obj
= object_list
[i
];
3833 /* Compute new gpu domains and update invalidate/flush */
3834 i915_gem_object_set_to_gpu_domain(obj
);
3837 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3839 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3841 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3843 dev
->invalidate_domains
,
3844 dev
->flush_domains
);
3847 dev
->invalidate_domains
,
3848 dev
->flush_domains
);
3849 if (dev
->flush_domains
)
3850 (void)i915_add_request(dev
, file_priv
,
3851 dev
->flush_domains
);
3854 for (i
= 0; i
< args
->buffer_count
; i
++) {
3855 struct drm_gem_object
*obj
= object_list
[i
];
3856 uint32_t old_write_domain
= obj
->write_domain
;
3858 obj
->write_domain
= obj
->pending_write_domain
;
3859 trace_i915_gem_object_change_domain(obj
,
3864 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3867 for (i
= 0; i
< args
->buffer_count
; i
++) {
3868 i915_gem_object_check_coherency(object_list
[i
],
3869 exec_list
[i
].handle
);
3874 i915_gem_dump_object(batch_obj
,
3880 /* Exec the batchbuffer */
3881 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3883 DRM_ERROR("dispatch failed %d\n", ret
);
3888 * Ensure that the commands in the batch buffer are
3889 * finished before the interrupt fires
3891 flush_domains
= i915_retire_commands(dev
);
3893 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3896 * Get a seqno representing the execution of the current buffer,
3897 * which we can wait on. We would like to mitigate these interrupts,
3898 * likely by only creating seqnos occasionally (so that we have
3899 * *some* interrupts representing completion of buffers that we can
3900 * wait on when trying to clear up gtt space).
3902 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3904 for (i
= 0; i
< args
->buffer_count
; i
++) {
3905 struct drm_gem_object
*obj
= object_list
[i
];
3907 i915_gem_object_move_to_active(obj
, seqno
);
3909 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3913 i915_dump_lru(dev
, __func__
);
3916 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3919 for (i
= 0; i
< pinned
; i
++)
3920 i915_gem_object_unpin(object_list
[i
]);
3922 for (i
= 0; i
< args
->buffer_count
; i
++) {
3923 if (object_list
[i
]) {
3924 obj_priv
= object_list
[i
]->driver_private
;
3925 obj_priv
->in_execbuffer
= false;
3927 drm_gem_object_unreference(object_list
[i
]);
3930 mutex_unlock(&dev
->struct_mutex
);
3933 /* Copy the updated relocations out regardless of current error
3934 * state. Failure to update the relocs would mean that the next
3935 * time userland calls execbuf, it would do so with presumed offset
3936 * state that didn't match the actual object state.
3938 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3941 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3947 drm_free_large(object_list
);
3954 * Legacy execbuffer just creates an exec2 list from the original exec object
3955 * list array and passes it to the real function.
3958 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3959 struct drm_file
*file_priv
)
3961 struct drm_i915_gem_execbuffer
*args
= data
;
3962 struct drm_i915_gem_execbuffer2 exec2
;
3963 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3964 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3968 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3969 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3972 if (args
->buffer_count
< 1) {
3973 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3977 /* Copy in the exec list from userland */
3978 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3979 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3980 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3981 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3982 args
->buffer_count
);
3983 drm_free_large(exec_list
);
3984 drm_free_large(exec2_list
);
3987 ret
= copy_from_user(exec_list
,
3988 (struct drm_i915_relocation_entry __user
*)
3989 (uintptr_t) args
->buffers_ptr
,
3990 sizeof(*exec_list
) * args
->buffer_count
);
3992 DRM_ERROR("copy %d exec entries failed %d\n",
3993 args
->buffer_count
, ret
);
3994 drm_free_large(exec_list
);
3995 drm_free_large(exec2_list
);
3999 for (i
= 0; i
< args
->buffer_count
; i
++) {
4000 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4001 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4002 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4003 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4004 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4006 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4008 exec2_list
[i
].flags
= 0;
4011 exec2
.buffers_ptr
= args
->buffers_ptr
;
4012 exec2
.buffer_count
= args
->buffer_count
;
4013 exec2
.batch_start_offset
= args
->batch_start_offset
;
4014 exec2
.batch_len
= args
->batch_len
;
4015 exec2
.DR1
= args
->DR1
;
4016 exec2
.DR4
= args
->DR4
;
4017 exec2
.num_cliprects
= args
->num_cliprects
;
4018 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4021 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4023 /* Copy the new buffer offsets back to the user's exec list. */
4024 for (i
= 0; i
< args
->buffer_count
; i
++)
4025 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4026 /* ... and back out to userspace */
4027 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4028 (uintptr_t) args
->buffers_ptr
,
4030 sizeof(*exec_list
) * args
->buffer_count
);
4033 DRM_ERROR("failed to copy %d exec entries "
4034 "back to user (%d)\n",
4035 args
->buffer_count
, ret
);
4039 drm_free_large(exec_list
);
4040 drm_free_large(exec2_list
);
4045 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4046 struct drm_file
*file_priv
)
4048 struct drm_i915_gem_execbuffer2
*args
= data
;
4049 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4053 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4054 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4057 if (args
->buffer_count
< 1) {
4058 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4062 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4063 if (exec2_list
== NULL
) {
4064 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4065 args
->buffer_count
);
4068 ret
= copy_from_user(exec2_list
,
4069 (struct drm_i915_relocation_entry __user
*)
4070 (uintptr_t) args
->buffers_ptr
,
4071 sizeof(*exec2_list
) * args
->buffer_count
);
4073 DRM_ERROR("copy %d exec entries failed %d\n",
4074 args
->buffer_count
, ret
);
4075 drm_free_large(exec2_list
);
4079 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4081 /* Copy the new buffer offsets back to the user's exec list. */
4082 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4083 (uintptr_t) args
->buffers_ptr
,
4085 sizeof(*exec2_list
) * args
->buffer_count
);
4088 DRM_ERROR("failed to copy %d exec entries "
4089 "back to user (%d)\n",
4090 args
->buffer_count
, ret
);
4094 drm_free_large(exec2_list
);
4099 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4101 struct drm_device
*dev
= obj
->dev
;
4102 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4105 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4106 if (obj_priv
->gtt_space
== NULL
) {
4107 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4112 obj_priv
->pin_count
++;
4114 /* If the object is not active and not pending a flush,
4115 * remove it from the inactive list
4117 if (obj_priv
->pin_count
== 1) {
4118 atomic_inc(&dev
->pin_count
);
4119 atomic_add(obj
->size
, &dev
->pin_memory
);
4120 if (!obj_priv
->active
&&
4121 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4122 !list_empty(&obj_priv
->list
))
4123 list_del_init(&obj_priv
->list
);
4125 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4131 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4133 struct drm_device
*dev
= obj
->dev
;
4134 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4135 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4137 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4138 obj_priv
->pin_count
--;
4139 BUG_ON(obj_priv
->pin_count
< 0);
4140 BUG_ON(obj_priv
->gtt_space
== NULL
);
4142 /* If the object is no longer pinned, and is
4143 * neither active nor being flushed, then stick it on
4146 if (obj_priv
->pin_count
== 0) {
4147 if (!obj_priv
->active
&&
4148 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4149 list_move_tail(&obj_priv
->list
,
4150 &dev_priv
->mm
.inactive_list
);
4151 atomic_dec(&dev
->pin_count
);
4152 atomic_sub(obj
->size
, &dev
->pin_memory
);
4154 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4158 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4159 struct drm_file
*file_priv
)
4161 struct drm_i915_gem_pin
*args
= data
;
4162 struct drm_gem_object
*obj
;
4163 struct drm_i915_gem_object
*obj_priv
;
4166 mutex_lock(&dev
->struct_mutex
);
4168 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4170 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4172 mutex_unlock(&dev
->struct_mutex
);
4175 obj_priv
= obj
->driver_private
;
4177 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4178 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4179 drm_gem_object_unreference(obj
);
4180 mutex_unlock(&dev
->struct_mutex
);
4184 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4185 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4187 drm_gem_object_unreference(obj
);
4188 mutex_unlock(&dev
->struct_mutex
);
4192 obj_priv
->user_pin_count
++;
4193 obj_priv
->pin_filp
= file_priv
;
4194 if (obj_priv
->user_pin_count
== 1) {
4195 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4197 drm_gem_object_unreference(obj
);
4198 mutex_unlock(&dev
->struct_mutex
);
4203 /* XXX - flush the CPU caches for pinned objects
4204 * as the X server doesn't manage domains yet
4206 i915_gem_object_flush_cpu_write_domain(obj
);
4207 args
->offset
= obj_priv
->gtt_offset
;
4208 drm_gem_object_unreference(obj
);
4209 mutex_unlock(&dev
->struct_mutex
);
4215 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4216 struct drm_file
*file_priv
)
4218 struct drm_i915_gem_pin
*args
= data
;
4219 struct drm_gem_object
*obj
;
4220 struct drm_i915_gem_object
*obj_priv
;
4222 mutex_lock(&dev
->struct_mutex
);
4224 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4226 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4228 mutex_unlock(&dev
->struct_mutex
);
4232 obj_priv
= obj
->driver_private
;
4233 if (obj_priv
->pin_filp
!= file_priv
) {
4234 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4236 drm_gem_object_unreference(obj
);
4237 mutex_unlock(&dev
->struct_mutex
);
4240 obj_priv
->user_pin_count
--;
4241 if (obj_priv
->user_pin_count
== 0) {
4242 obj_priv
->pin_filp
= NULL
;
4243 i915_gem_object_unpin(obj
);
4246 drm_gem_object_unreference(obj
);
4247 mutex_unlock(&dev
->struct_mutex
);
4252 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4253 struct drm_file
*file_priv
)
4255 struct drm_i915_gem_busy
*args
= data
;
4256 struct drm_gem_object
*obj
;
4257 struct drm_i915_gem_object
*obj_priv
;
4259 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4261 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4266 mutex_lock(&dev
->struct_mutex
);
4267 /* Update the active list for the hardware's current position.
4268 * Otherwise this only updates on a delayed timer or when irqs are
4269 * actually unmasked, and our working set ends up being larger than
4272 i915_gem_retire_requests(dev
);
4274 obj_priv
= obj
->driver_private
;
4275 /* Don't count being on the flushing list against the object being
4276 * done. Otherwise, a buffer left on the flushing list but not getting
4277 * flushed (because nobody's flushing that domain) won't ever return
4278 * unbusy and get reused by libdrm's bo cache. The other expected
4279 * consumer of this interface, OpenGL's occlusion queries, also specs
4280 * that the objects get unbusy "eventually" without any interference.
4282 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4284 drm_gem_object_unreference(obj
);
4285 mutex_unlock(&dev
->struct_mutex
);
4290 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4291 struct drm_file
*file_priv
)
4293 return i915_gem_ring_throttle(dev
, file_priv
);
4297 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4298 struct drm_file
*file_priv
)
4300 struct drm_i915_gem_madvise
*args
= data
;
4301 struct drm_gem_object
*obj
;
4302 struct drm_i915_gem_object
*obj_priv
;
4304 switch (args
->madv
) {
4305 case I915_MADV_DONTNEED
:
4306 case I915_MADV_WILLNEED
:
4312 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4314 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4319 mutex_lock(&dev
->struct_mutex
);
4320 obj_priv
= obj
->driver_private
;
4322 if (obj_priv
->pin_count
) {
4323 drm_gem_object_unreference(obj
);
4324 mutex_unlock(&dev
->struct_mutex
);
4326 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4330 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4331 obj_priv
->madv
= args
->madv
;
4333 /* if the object is no longer bound, discard its backing storage */
4334 if (i915_gem_object_is_purgeable(obj_priv
) &&
4335 obj_priv
->gtt_space
== NULL
)
4336 i915_gem_object_truncate(obj
);
4338 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4340 drm_gem_object_unreference(obj
);
4341 mutex_unlock(&dev
->struct_mutex
);
4346 int i915_gem_init_object(struct drm_gem_object
*obj
)
4348 struct drm_i915_gem_object
*obj_priv
;
4350 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4351 if (obj_priv
== NULL
)
4355 * We've just allocated pages from the kernel,
4356 * so they've just been written by the CPU with
4357 * zeros. They'll need to be clflushed before we
4358 * use them with the GPU.
4360 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4361 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4363 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4365 obj
->driver_private
= obj_priv
;
4366 obj_priv
->obj
= obj
;
4367 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4368 INIT_LIST_HEAD(&obj_priv
->list
);
4369 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4370 obj_priv
->madv
= I915_MADV_WILLNEED
;
4372 trace_i915_gem_object_create(obj
);
4377 void i915_gem_free_object(struct drm_gem_object
*obj
)
4379 struct drm_device
*dev
= obj
->dev
;
4380 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4382 trace_i915_gem_object_destroy(obj
);
4384 while (obj_priv
->pin_count
> 0)
4385 i915_gem_object_unpin(obj
);
4387 if (obj_priv
->phys_obj
)
4388 i915_gem_detach_phys_object(dev
, obj
);
4390 i915_gem_object_unbind(obj
);
4392 if (obj_priv
->mmap_offset
)
4393 i915_gem_free_mmap_offset(obj
);
4395 kfree(obj_priv
->page_cpu_valid
);
4396 kfree(obj_priv
->bit_17
);
4397 kfree(obj
->driver_private
);
4400 /** Unbinds all inactive objects. */
4402 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4404 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4406 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4407 struct drm_gem_object
*obj
;
4410 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4411 struct drm_i915_gem_object
,
4414 ret
= i915_gem_object_unbind(obj
);
4416 DRM_ERROR("Error unbinding object: %d\n", ret
);
4425 i915_gem_idle(struct drm_device
*dev
)
4427 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4428 uint32_t seqno
, cur_seqno
, last_seqno
;
4431 mutex_lock(&dev
->struct_mutex
);
4433 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4434 mutex_unlock(&dev
->struct_mutex
);
4438 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4439 * We need to replace this with a semaphore, or something.
4441 dev_priv
->mm
.suspended
= 1;
4442 del_timer(&dev_priv
->hangcheck_timer
);
4444 /* Cancel the retire work handler, wait for it to finish if running
4446 mutex_unlock(&dev
->struct_mutex
);
4447 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4448 mutex_lock(&dev
->struct_mutex
);
4450 i915_kernel_lost_context(dev
);
4452 /* Flush the GPU along with all non-CPU write domains
4454 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4455 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4458 mutex_unlock(&dev
->struct_mutex
);
4462 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4466 cur_seqno
= i915_get_gem_seqno(dev
);
4467 if (i915_seqno_passed(cur_seqno
, seqno
))
4469 if (last_seqno
== cur_seqno
) {
4470 if (stuck
++ > 100) {
4471 DRM_ERROR("hardware wedged\n");
4472 atomic_set(&dev_priv
->mm
.wedged
, 1);
4473 DRM_WAKEUP(&dev_priv
->irq_queue
);
4478 last_seqno
= cur_seqno
;
4480 dev_priv
->mm
.waiting_gem_seqno
= 0;
4482 i915_gem_retire_requests(dev
);
4484 spin_lock(&dev_priv
->mm
.active_list_lock
);
4485 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4486 /* Active and flushing should now be empty as we've
4487 * waited for a sequence higher than any pending execbuffer
4489 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4490 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4491 /* Request should now be empty as we've also waited
4492 * for the last request in the list
4494 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4497 /* Empty the active and flushing lists to inactive. If there's
4498 * anything left at this point, it means that we're wedged and
4499 * nothing good's going to happen by leaving them there. So strip
4500 * the GPU domains and just stuff them onto inactive.
4502 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4503 struct drm_gem_object
*obj
;
4504 uint32_t old_write_domain
;
4506 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4507 struct drm_i915_gem_object
,
4509 old_write_domain
= obj
->write_domain
;
4510 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4511 i915_gem_object_move_to_inactive(obj
);
4513 trace_i915_gem_object_change_domain(obj
,
4517 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4519 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4520 struct drm_gem_object
*obj
;
4521 uint32_t old_write_domain
;
4523 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4524 struct drm_i915_gem_object
,
4526 old_write_domain
= obj
->write_domain
;
4527 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4528 i915_gem_object_move_to_inactive(obj
);
4530 trace_i915_gem_object_change_domain(obj
,
4536 /* Move all inactive buffers out of the GTT. */
4537 ret
= i915_gem_evict_from_inactive_list(dev
);
4538 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4540 mutex_unlock(&dev
->struct_mutex
);
4544 i915_gem_cleanup_ringbuffer(dev
);
4545 mutex_unlock(&dev
->struct_mutex
);
4551 i915_gem_init_hws(struct drm_device
*dev
)
4553 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4554 struct drm_gem_object
*obj
;
4555 struct drm_i915_gem_object
*obj_priv
;
4558 /* If we need a physical address for the status page, it's already
4559 * initialized at driver load time.
4561 if (!I915_NEED_GFX_HWS(dev
))
4564 obj
= drm_gem_object_alloc(dev
, 4096);
4566 DRM_ERROR("Failed to allocate status page\n");
4569 obj_priv
= obj
->driver_private
;
4570 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4572 ret
= i915_gem_object_pin(obj
, 4096);
4574 drm_gem_object_unreference(obj
);
4578 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4580 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4581 if (dev_priv
->hw_status_page
== NULL
) {
4582 DRM_ERROR("Failed to map status page.\n");
4583 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4584 i915_gem_object_unpin(obj
);
4585 drm_gem_object_unreference(obj
);
4588 dev_priv
->hws_obj
= obj
;
4589 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4590 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4591 I915_READ(HWS_PGA
); /* posting read */
4592 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4598 i915_gem_cleanup_hws(struct drm_device
*dev
)
4600 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4601 struct drm_gem_object
*obj
;
4602 struct drm_i915_gem_object
*obj_priv
;
4604 if (dev_priv
->hws_obj
== NULL
)
4607 obj
= dev_priv
->hws_obj
;
4608 obj_priv
= obj
->driver_private
;
4610 kunmap(obj_priv
->pages
[0]);
4611 i915_gem_object_unpin(obj
);
4612 drm_gem_object_unreference(obj
);
4613 dev_priv
->hws_obj
= NULL
;
4615 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4616 dev_priv
->hw_status_page
= NULL
;
4618 /* Write high address into HWS_PGA when disabling. */
4619 I915_WRITE(HWS_PGA
, 0x1ffff000);
4623 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4625 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4626 struct drm_gem_object
*obj
;
4627 struct drm_i915_gem_object
*obj_priv
;
4628 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4632 ret
= i915_gem_init_hws(dev
);
4636 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4638 DRM_ERROR("Failed to allocate ringbuffer\n");
4639 i915_gem_cleanup_hws(dev
);
4642 obj_priv
= obj
->driver_private
;
4644 ret
= i915_gem_object_pin(obj
, 4096);
4646 drm_gem_object_unreference(obj
);
4647 i915_gem_cleanup_hws(dev
);
4651 /* Set up the kernel mapping for the ring. */
4652 ring
->Size
= obj
->size
;
4654 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4655 ring
->map
.size
= obj
->size
;
4657 ring
->map
.flags
= 0;
4660 drm_core_ioremap_wc(&ring
->map
, dev
);
4661 if (ring
->map
.handle
== NULL
) {
4662 DRM_ERROR("Failed to map ringbuffer.\n");
4663 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4664 i915_gem_object_unpin(obj
);
4665 drm_gem_object_unreference(obj
);
4666 i915_gem_cleanup_hws(dev
);
4669 ring
->ring_obj
= obj
;
4670 ring
->virtual_start
= ring
->map
.handle
;
4672 /* Stop the ring if it's running. */
4673 I915_WRITE(PRB0_CTL
, 0);
4674 I915_WRITE(PRB0_TAIL
, 0);
4675 I915_WRITE(PRB0_HEAD
, 0);
4677 /* Initialize the ring. */
4678 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4679 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4681 /* G45 ring initialization fails to reset head to zero */
4683 DRM_ERROR("Ring head not reset to zero "
4684 "ctl %08x head %08x tail %08x start %08x\n",
4685 I915_READ(PRB0_CTL
),
4686 I915_READ(PRB0_HEAD
),
4687 I915_READ(PRB0_TAIL
),
4688 I915_READ(PRB0_START
));
4689 I915_WRITE(PRB0_HEAD
, 0);
4691 DRM_ERROR("Ring head forced to zero "
4692 "ctl %08x head %08x tail %08x start %08x\n",
4693 I915_READ(PRB0_CTL
),
4694 I915_READ(PRB0_HEAD
),
4695 I915_READ(PRB0_TAIL
),
4696 I915_READ(PRB0_START
));
4699 I915_WRITE(PRB0_CTL
,
4700 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4704 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4706 /* If the head is still not zero, the ring is dead */
4708 DRM_ERROR("Ring initialization failed "
4709 "ctl %08x head %08x tail %08x start %08x\n",
4710 I915_READ(PRB0_CTL
),
4711 I915_READ(PRB0_HEAD
),
4712 I915_READ(PRB0_TAIL
),
4713 I915_READ(PRB0_START
));
4717 /* Update our cache of the ring state */
4718 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4719 i915_kernel_lost_context(dev
);
4721 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4722 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4723 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4724 if (ring
->space
< 0)
4725 ring
->space
+= ring
->Size
;
4732 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4734 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4736 if (dev_priv
->ring
.ring_obj
== NULL
)
4739 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4741 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4742 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4743 dev_priv
->ring
.ring_obj
= NULL
;
4744 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4746 i915_gem_cleanup_hws(dev
);
4750 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4751 struct drm_file
*file_priv
)
4753 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4756 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4759 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4760 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4761 atomic_set(&dev_priv
->mm
.wedged
, 0);
4764 mutex_lock(&dev
->struct_mutex
);
4765 dev_priv
->mm
.suspended
= 0;
4767 ret
= i915_gem_init_ringbuffer(dev
);
4769 mutex_unlock(&dev
->struct_mutex
);
4773 spin_lock(&dev_priv
->mm
.active_list_lock
);
4774 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4775 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4777 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4778 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4779 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4780 mutex_unlock(&dev
->struct_mutex
);
4782 drm_irq_install(dev
);
4788 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4789 struct drm_file
*file_priv
)
4791 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4794 drm_irq_uninstall(dev
);
4795 return i915_gem_idle(dev
);
4799 i915_gem_lastclose(struct drm_device
*dev
)
4803 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4806 ret
= i915_gem_idle(dev
);
4808 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4812 i915_gem_load(struct drm_device
*dev
)
4815 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4817 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4818 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4819 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4820 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4821 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4822 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4823 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4824 i915_gem_retire_work_handler
);
4825 dev_priv
->mm
.next_gem_seqno
= 1;
4827 spin_lock(&shrink_list_lock
);
4828 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4829 spin_unlock(&shrink_list_lock
);
4831 /* Old X drivers will take 0-2 for front, back, depth buffers */
4832 dev_priv
->fence_reg_start
= 3;
4834 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4835 dev_priv
->num_fence_regs
= 16;
4837 dev_priv
->num_fence_regs
= 8;
4839 /* Initialize fence registers to zero */
4840 if (IS_I965G(dev
)) {
4841 for (i
= 0; i
< 16; i
++)
4842 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4844 for (i
= 0; i
< 8; i
++)
4845 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4846 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4847 for (i
= 0; i
< 8; i
++)
4848 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4850 i915_gem_detect_bit_6_swizzle(dev
);
4851 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4855 * Create a physically contiguous memory object for this object
4856 * e.g. for cursor + overlay regs
4858 int i915_gem_init_phys_object(struct drm_device
*dev
,
4861 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4862 struct drm_i915_gem_phys_object
*phys_obj
;
4865 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4868 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4874 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4875 if (!phys_obj
->handle
) {
4880 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4883 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4891 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4893 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4894 struct drm_i915_gem_phys_object
*phys_obj
;
4896 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4899 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4900 if (phys_obj
->cur_obj
) {
4901 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4905 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4907 drm_pci_free(dev
, phys_obj
->handle
);
4909 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4912 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4916 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4917 i915_gem_free_phys_object(dev
, i
);
4920 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4921 struct drm_gem_object
*obj
)
4923 struct drm_i915_gem_object
*obj_priv
;
4928 obj_priv
= obj
->driver_private
;
4929 if (!obj_priv
->phys_obj
)
4932 ret
= i915_gem_object_get_pages(obj
, 0);
4936 page_count
= obj
->size
/ PAGE_SIZE
;
4938 for (i
= 0; i
< page_count
; i
++) {
4939 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4940 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4942 memcpy(dst
, src
, PAGE_SIZE
);
4943 kunmap_atomic(dst
, KM_USER0
);
4945 drm_clflush_pages(obj_priv
->pages
, page_count
);
4946 drm_agp_chipset_flush(dev
);
4948 i915_gem_object_put_pages(obj
);
4950 obj_priv
->phys_obj
->cur_obj
= NULL
;
4951 obj_priv
->phys_obj
= NULL
;
4955 i915_gem_attach_phys_object(struct drm_device
*dev
,
4956 struct drm_gem_object
*obj
, int id
)
4958 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4959 struct drm_i915_gem_object
*obj_priv
;
4964 if (id
> I915_MAX_PHYS_OBJECT
)
4967 obj_priv
= obj
->driver_private
;
4969 if (obj_priv
->phys_obj
) {
4970 if (obj_priv
->phys_obj
->id
== id
)
4972 i915_gem_detach_phys_object(dev
, obj
);
4976 /* create a new object */
4977 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4978 ret
= i915_gem_init_phys_object(dev
, id
,
4981 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4986 /* bind to the object */
4987 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4988 obj_priv
->phys_obj
->cur_obj
= obj
;
4990 ret
= i915_gem_object_get_pages(obj
, 0);
4992 DRM_ERROR("failed to get page list\n");
4996 page_count
= obj
->size
/ PAGE_SIZE
;
4998 for (i
= 0; i
< page_count
; i
++) {
4999 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
5000 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
5002 memcpy(dst
, src
, PAGE_SIZE
);
5003 kunmap_atomic(src
, KM_USER0
);
5006 i915_gem_object_put_pages(obj
);
5014 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5015 struct drm_i915_gem_pwrite
*args
,
5016 struct drm_file
*file_priv
)
5018 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
5021 char __user
*user_data
;
5023 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5024 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5026 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
5027 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
5031 drm_agp_chipset_flush(dev
);
5035 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
5037 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
5039 /* Clean up our request list when the client is going away, so that
5040 * later retire_requests won't dereference our soon-to-be-gone
5043 mutex_lock(&dev
->struct_mutex
);
5044 while (!list_empty(&i915_file_priv
->mm
.request_list
))
5045 list_del_init(i915_file_priv
->mm
.request_list
.next
);
5046 mutex_unlock(&dev
->struct_mutex
);
5050 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
5052 drm_i915_private_t
*dev_priv
, *next_dev
;
5053 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
5055 int would_deadlock
= 1;
5057 /* "fast-path" to count number of available objects */
5058 if (nr_to_scan
== 0) {
5059 spin_lock(&shrink_list_lock
);
5060 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5061 struct drm_device
*dev
= dev_priv
->dev
;
5063 if (mutex_trylock(&dev
->struct_mutex
)) {
5064 list_for_each_entry(obj_priv
,
5065 &dev_priv
->mm
.inactive_list
,
5068 mutex_unlock(&dev
->struct_mutex
);
5071 spin_unlock(&shrink_list_lock
);
5073 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5076 spin_lock(&shrink_list_lock
);
5078 /* first scan for clean buffers */
5079 list_for_each_entry_safe(dev_priv
, next_dev
,
5080 &shrink_list
, mm
.shrink_list
) {
5081 struct drm_device
*dev
= dev_priv
->dev
;
5083 if (! mutex_trylock(&dev
->struct_mutex
))
5086 spin_unlock(&shrink_list_lock
);
5088 i915_gem_retire_requests(dev
);
5090 list_for_each_entry_safe(obj_priv
, next_obj
,
5091 &dev_priv
->mm
.inactive_list
,
5093 if (i915_gem_object_is_purgeable(obj_priv
)) {
5094 i915_gem_object_unbind(obj_priv
->obj
);
5095 if (--nr_to_scan
<= 0)
5100 spin_lock(&shrink_list_lock
);
5101 mutex_unlock(&dev
->struct_mutex
);
5105 if (nr_to_scan
<= 0)
5109 /* second pass, evict/count anything still on the inactive list */
5110 list_for_each_entry_safe(dev_priv
, next_dev
,
5111 &shrink_list
, mm
.shrink_list
) {
5112 struct drm_device
*dev
= dev_priv
->dev
;
5114 if (! mutex_trylock(&dev
->struct_mutex
))
5117 spin_unlock(&shrink_list_lock
);
5119 list_for_each_entry_safe(obj_priv
, next_obj
,
5120 &dev_priv
->mm
.inactive_list
,
5122 if (nr_to_scan
> 0) {
5123 i915_gem_object_unbind(obj_priv
->obj
);
5129 spin_lock(&shrink_list_lock
);
5130 mutex_unlock(&dev
->struct_mutex
);
5135 spin_unlock(&shrink_list_lock
);
5140 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5145 static struct shrinker shrinker
= {
5146 .shrink
= i915_gem_shrink
,
5147 .seeks
= DEFAULT_SEEKS
,
5151 i915_gem_shrinker_init(void)
5153 register_shrinker(&shrinker
);
5157 i915_gem_shrinker_exit(void)
5159 unregister_shrinker(&shrinker
);