2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 struct change_domains
{
40 uint32_t invalidate_domains
;
41 uint32_t flush_domains
;
45 static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
);
46 static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
);
48 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
50 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
51 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
52 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
54 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
57 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
58 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
60 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
62 bool map_and_fenceable
);
63 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
64 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
65 struct drm_i915_gem_pwrite
*args
,
66 struct drm_file
*file_priv
);
67 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
69 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
89 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
90 struct drm_i915_gem_object
*obj
)
92 dev_priv
->mm
.gtt_count
++;
93 dev_priv
->mm
.gtt_memory
+= obj
->gtt_space
->size
;
94 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
95 dev_priv
->mm
.mappable_gtt_used
+=
96 min_t(size_t, obj
->gtt_space
->size
,
97 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
101 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
102 struct drm_i915_gem_object
*obj
)
104 dev_priv
->mm
.gtt_count
--;
105 dev_priv
->mm
.gtt_memory
-= obj
->gtt_space
->size
;
106 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
107 dev_priv
->mm
.mappable_gtt_used
-=
108 min_t(size_t, obj
->gtt_space
->size
,
109 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
114 * Update the mappable working set counters. Call _only_ when there is a change
115 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
116 * @mappable: new state the changed mappable flag (either pin_ or fault_).
119 i915_gem_info_update_mappable(struct drm_i915_private
*dev_priv
,
120 struct drm_i915_gem_object
*obj
,
124 if (obj
->pin_mappable
&& obj
->fault_mappable
)
125 /* Combined state was already mappable. */
127 dev_priv
->mm
.gtt_mappable_count
++;
128 dev_priv
->mm
.gtt_mappable_memory
+= obj
->gtt_space
->size
;
130 if (obj
->pin_mappable
|| obj
->fault_mappable
)
131 /* Combined state still mappable. */
133 dev_priv
->mm
.gtt_mappable_count
--;
134 dev_priv
->mm
.gtt_mappable_memory
-= obj
->gtt_space
->size
;
138 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
139 struct drm_i915_gem_object
*obj
,
142 dev_priv
->mm
.pin_count
++;
143 dev_priv
->mm
.pin_memory
+= obj
->gtt_space
->size
;
145 obj
->pin_mappable
= true;
146 i915_gem_info_update_mappable(dev_priv
, obj
, true);
150 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
151 struct drm_i915_gem_object
*obj
)
153 dev_priv
->mm
.pin_count
--;
154 dev_priv
->mm
.pin_memory
-= obj
->gtt_space
->size
;
155 if (obj
->pin_mappable
) {
156 obj
->pin_mappable
= false;
157 i915_gem_info_update_mappable(dev_priv
, obj
, false);
162 i915_gem_check_is_wedged(struct drm_device
*dev
)
164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
165 struct completion
*x
= &dev_priv
->error_completion
;
169 if (!atomic_read(&dev_priv
->mm
.wedged
))
172 ret
= wait_for_completion_interruptible(x
);
176 /* Success, we reset the GPU! */
177 if (!atomic_read(&dev_priv
->mm
.wedged
))
180 /* GPU is hung, bump the completion count to account for
181 * the token we just consumed so that we never hit zero and
182 * end up waiting upon a subsequent completion event that
185 spin_lock_irqsave(&x
->wait
.lock
, flags
);
187 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
191 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 ret
= i915_gem_check_is_wedged(dev
);
200 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
204 if (atomic_read(&dev_priv
->mm
.wedged
)) {
205 mutex_unlock(&dev
->struct_mutex
);
209 WARN_ON(i915_verify_lists(dev
));
214 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
216 return obj_priv
->gtt_space
&&
218 obj_priv
->pin_count
== 0;
221 int i915_gem_do_init(struct drm_device
*dev
,
223 unsigned long mappable_end
,
226 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
229 (start
& (PAGE_SIZE
- 1)) != 0 ||
230 (end
& (PAGE_SIZE
- 1)) != 0) {
234 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
237 dev_priv
->mm
.gtt_total
= end
- start
;
238 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
239 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
245 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
246 struct drm_file
*file_priv
)
248 struct drm_i915_gem_init
*args
= data
;
251 mutex_lock(&dev
->struct_mutex
);
252 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
253 mutex_unlock(&dev
->struct_mutex
);
259 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
260 struct drm_file
*file_priv
)
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
263 struct drm_i915_gem_get_aperture
*args
= data
;
265 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
268 mutex_lock(&dev
->struct_mutex
);
269 args
->aper_size
= dev_priv
->mm
.gtt_total
;
270 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
271 mutex_unlock(&dev
->struct_mutex
);
278 * Creates a new mm object and returns a handle to it.
281 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
282 struct drm_file
*file_priv
)
284 struct drm_i915_gem_create
*args
= data
;
285 struct drm_gem_object
*obj
;
289 args
->size
= roundup(args
->size
, PAGE_SIZE
);
291 /* Allocate the new object */
292 obj
= i915_gem_alloc_object(dev
, args
->size
);
296 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
298 drm_gem_object_release(obj
);
299 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
304 /* drop reference from allocate - handle holds it now */
305 drm_gem_object_unreference(obj
);
306 trace_i915_gem_object_create(obj
);
308 args
->handle
= handle
;
312 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
314 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
315 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
317 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
318 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
322 slow_shmem_copy(struct page
*dst_page
,
324 struct page
*src_page
,
328 char *dst_vaddr
, *src_vaddr
;
330 dst_vaddr
= kmap(dst_page
);
331 src_vaddr
= kmap(src_page
);
333 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
340 slow_shmem_bit17_copy(struct page
*gpu_page
,
342 struct page
*cpu_page
,
347 char *gpu_vaddr
, *cpu_vaddr
;
349 /* Use the unswizzled path if this page isn't affected. */
350 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
352 return slow_shmem_copy(cpu_page
, cpu_offset
,
353 gpu_page
, gpu_offset
, length
);
355 return slow_shmem_copy(gpu_page
, gpu_offset
,
356 cpu_page
, cpu_offset
, length
);
359 gpu_vaddr
= kmap(gpu_page
);
360 cpu_vaddr
= kmap(cpu_page
);
362 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
363 * XORing with the other bits (A9 for Y, A9 and A10 for X)
366 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
367 int this_length
= min(cacheline_end
- gpu_offset
, length
);
368 int swizzled_gpu_offset
= gpu_offset
^ 64;
371 memcpy(cpu_vaddr
+ cpu_offset
,
372 gpu_vaddr
+ swizzled_gpu_offset
,
375 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
376 cpu_vaddr
+ cpu_offset
,
379 cpu_offset
+= this_length
;
380 gpu_offset
+= this_length
;
381 length
-= this_length
;
389 * This is the fast shmem pread path, which attempts to copy_from_user directly
390 * from the backing pages of the object to the user's address space. On a
391 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
394 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
395 struct drm_i915_gem_pread
*args
,
396 struct drm_file
*file_priv
)
398 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
399 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
402 char __user
*user_data
;
403 int page_offset
, page_length
;
405 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
408 obj_priv
= to_intel_bo(obj
);
409 offset
= args
->offset
;
416 /* Operation in this page
418 * page_offset = offset within page
419 * page_length = bytes to copy for this page
421 page_offset
= offset
& (PAGE_SIZE
-1);
422 page_length
= remain
;
423 if ((page_offset
+ remain
) > PAGE_SIZE
)
424 page_length
= PAGE_SIZE
- page_offset
;
426 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
427 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
429 return PTR_ERR(page
);
431 vaddr
= kmap_atomic(page
);
432 ret
= __copy_to_user_inatomic(user_data
,
435 kunmap_atomic(vaddr
);
437 mark_page_accessed(page
);
438 page_cache_release(page
);
442 remain
-= page_length
;
443 user_data
+= page_length
;
444 offset
+= page_length
;
451 * This is the fallback shmem pread path, which allocates temporary storage
452 * in kernel space to copy_to_user into outside of the struct_mutex, so we
453 * can copy out of the object's backing pages while holding the struct mutex
454 * and not take page faults.
457 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
458 struct drm_i915_gem_pread
*args
,
459 struct drm_file
*file_priv
)
461 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
462 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
463 struct mm_struct
*mm
= current
->mm
;
464 struct page
**user_pages
;
466 loff_t offset
, pinned_pages
, i
;
467 loff_t first_data_page
, last_data_page
, num_pages
;
468 int shmem_page_offset
;
469 int data_page_index
, data_page_offset
;
472 uint64_t data_ptr
= args
->data_ptr
;
473 int do_bit17_swizzling
;
477 /* Pin the user pages containing the data. We can't fault while
478 * holding the struct mutex, yet we want to hold it while
479 * dereferencing the user data.
481 first_data_page
= data_ptr
/ PAGE_SIZE
;
482 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
483 num_pages
= last_data_page
- first_data_page
+ 1;
485 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
486 if (user_pages
== NULL
)
489 mutex_unlock(&dev
->struct_mutex
);
490 down_read(&mm
->mmap_sem
);
491 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
492 num_pages
, 1, 0, user_pages
, NULL
);
493 up_read(&mm
->mmap_sem
);
494 mutex_lock(&dev
->struct_mutex
);
495 if (pinned_pages
< num_pages
) {
500 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
506 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
508 obj_priv
= to_intel_bo(obj
);
509 offset
= args
->offset
;
514 /* Operation in this page
516 * shmem_page_offset = offset within page in shmem file
517 * data_page_index = page number in get_user_pages return
518 * data_page_offset = offset with data_page_index page.
519 * page_length = bytes to copy for this page
521 shmem_page_offset
= offset
& ~PAGE_MASK
;
522 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
523 data_page_offset
= data_ptr
& ~PAGE_MASK
;
525 page_length
= remain
;
526 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
527 page_length
= PAGE_SIZE
- shmem_page_offset
;
528 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
529 page_length
= PAGE_SIZE
- data_page_offset
;
531 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
532 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
534 return PTR_ERR(page
);
536 if (do_bit17_swizzling
) {
537 slow_shmem_bit17_copy(page
,
539 user_pages
[data_page_index
],
544 slow_shmem_copy(user_pages
[data_page_index
],
551 mark_page_accessed(page
);
552 page_cache_release(page
);
554 remain
-= page_length
;
555 data_ptr
+= page_length
;
556 offset
+= page_length
;
560 for (i
= 0; i
< pinned_pages
; i
++) {
561 SetPageDirty(user_pages
[i
]);
562 mark_page_accessed(user_pages
[i
]);
563 page_cache_release(user_pages
[i
]);
565 drm_free_large(user_pages
);
571 * Reads data from the object referenced by handle.
573 * On error, the contents of *data are undefined.
576 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
577 struct drm_file
*file_priv
)
579 struct drm_i915_gem_pread
*args
= data
;
580 struct drm_gem_object
*obj
;
581 struct drm_i915_gem_object
*obj_priv
;
587 if (!access_ok(VERIFY_WRITE
,
588 (char __user
*)(uintptr_t)args
->data_ptr
,
592 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
597 ret
= i915_mutex_lock_interruptible(dev
);
601 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
606 obj_priv
= to_intel_bo(obj
);
608 /* Bounds check source. */
609 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
614 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
621 if (!i915_gem_object_needs_bit17_swizzle(obj
))
622 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
624 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
627 drm_gem_object_unreference(obj
);
629 mutex_unlock(&dev
->struct_mutex
);
633 /* This is the fast write path which cannot handle
634 * page faults in the source data
638 fast_user_write(struct io_mapping
*mapping
,
639 loff_t page_base
, int page_offset
,
640 char __user
*user_data
,
644 unsigned long unwritten
;
646 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
647 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
649 io_mapping_unmap_atomic(vaddr_atomic
);
653 /* Here's the write path which can sleep for
658 slow_kernel_write(struct io_mapping
*mapping
,
659 loff_t gtt_base
, int gtt_offset
,
660 struct page
*user_page
, int user_offset
,
663 char __iomem
*dst_vaddr
;
666 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
667 src_vaddr
= kmap(user_page
);
669 memcpy_toio(dst_vaddr
+ gtt_offset
,
670 src_vaddr
+ user_offset
,
674 io_mapping_unmap(dst_vaddr
);
678 * This is the fast pwrite path, where we copy the data directly from the
679 * user into the GTT, uncached.
682 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
683 struct drm_i915_gem_pwrite
*args
,
684 struct drm_file
*file_priv
)
686 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
687 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
689 loff_t offset
, page_base
;
690 char __user
*user_data
;
691 int page_offset
, page_length
;
693 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
696 obj_priv
= to_intel_bo(obj
);
697 offset
= obj_priv
->gtt_offset
+ args
->offset
;
700 /* Operation in this page
702 * page_base = page offset within aperture
703 * page_offset = offset within page
704 * page_length = bytes to copy for this page
706 page_base
= (offset
& ~(PAGE_SIZE
-1));
707 page_offset
= offset
& (PAGE_SIZE
-1);
708 page_length
= remain
;
709 if ((page_offset
+ remain
) > PAGE_SIZE
)
710 page_length
= PAGE_SIZE
- page_offset
;
712 /* If we get a fault while copying data, then (presumably) our
713 * source page isn't available. Return the error and we'll
714 * retry in the slow path.
716 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
717 page_offset
, user_data
, page_length
))
721 remain
-= page_length
;
722 user_data
+= page_length
;
723 offset
+= page_length
;
730 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
731 * the memory and maps it using kmap_atomic for copying.
733 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
734 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
737 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
738 struct drm_i915_gem_pwrite
*args
,
739 struct drm_file
*file_priv
)
741 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
742 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
744 loff_t gtt_page_base
, offset
;
745 loff_t first_data_page
, last_data_page
, num_pages
;
746 loff_t pinned_pages
, i
;
747 struct page
**user_pages
;
748 struct mm_struct
*mm
= current
->mm
;
749 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
751 uint64_t data_ptr
= args
->data_ptr
;
755 /* Pin the user pages containing the data. We can't fault while
756 * holding the struct mutex, and all of the pwrite implementations
757 * want to hold it while dereferencing the user data.
759 first_data_page
= data_ptr
/ PAGE_SIZE
;
760 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
761 num_pages
= last_data_page
- first_data_page
+ 1;
763 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
764 if (user_pages
== NULL
)
767 mutex_unlock(&dev
->struct_mutex
);
768 down_read(&mm
->mmap_sem
);
769 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
770 num_pages
, 0, 0, user_pages
, NULL
);
771 up_read(&mm
->mmap_sem
);
772 mutex_lock(&dev
->struct_mutex
);
773 if (pinned_pages
< num_pages
) {
775 goto out_unpin_pages
;
778 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
780 goto out_unpin_pages
;
782 obj_priv
= to_intel_bo(obj
);
783 offset
= obj_priv
->gtt_offset
+ args
->offset
;
786 /* Operation in this page
788 * gtt_page_base = page offset within aperture
789 * gtt_page_offset = offset within page in aperture
790 * data_page_index = page number in get_user_pages return
791 * data_page_offset = offset with data_page_index page.
792 * page_length = bytes to copy for this page
794 gtt_page_base
= offset
& PAGE_MASK
;
795 gtt_page_offset
= offset
& ~PAGE_MASK
;
796 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
797 data_page_offset
= data_ptr
& ~PAGE_MASK
;
799 page_length
= remain
;
800 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
801 page_length
= PAGE_SIZE
- gtt_page_offset
;
802 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
803 page_length
= PAGE_SIZE
- data_page_offset
;
805 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
806 gtt_page_base
, gtt_page_offset
,
807 user_pages
[data_page_index
],
811 remain
-= page_length
;
812 offset
+= page_length
;
813 data_ptr
+= page_length
;
817 for (i
= 0; i
< pinned_pages
; i
++)
818 page_cache_release(user_pages
[i
]);
819 drm_free_large(user_pages
);
825 * This is the fast shmem pwrite path, which attempts to directly
826 * copy_from_user into the kmapped pages backing the object.
829 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
830 struct drm_i915_gem_pwrite
*args
,
831 struct drm_file
*file_priv
)
833 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
834 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
837 char __user
*user_data
;
838 int page_offset
, page_length
;
840 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
843 obj_priv
= to_intel_bo(obj
);
844 offset
= args
->offset
;
852 /* Operation in this page
854 * page_offset = offset within page
855 * page_length = bytes to copy for this page
857 page_offset
= offset
& (PAGE_SIZE
-1);
858 page_length
= remain
;
859 if ((page_offset
+ remain
) > PAGE_SIZE
)
860 page_length
= PAGE_SIZE
- page_offset
;
862 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
863 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
865 return PTR_ERR(page
);
867 vaddr
= kmap_atomic(page
, KM_USER0
);
868 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
871 kunmap_atomic(vaddr
, KM_USER0
);
873 set_page_dirty(page
);
874 mark_page_accessed(page
);
875 page_cache_release(page
);
877 /* If we get a fault while copying data, then (presumably) our
878 * source page isn't available. Return the error and we'll
879 * retry in the slow path.
884 remain
-= page_length
;
885 user_data
+= page_length
;
886 offset
+= page_length
;
893 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
894 * the memory and maps it using kmap_atomic for copying.
896 * This avoids taking mmap_sem for faulting on the user's address while the
897 * struct_mutex is held.
900 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
901 struct drm_i915_gem_pwrite
*args
,
902 struct drm_file
*file_priv
)
904 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
905 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
906 struct mm_struct
*mm
= current
->mm
;
907 struct page
**user_pages
;
909 loff_t offset
, pinned_pages
, i
;
910 loff_t first_data_page
, last_data_page
, num_pages
;
911 int shmem_page_offset
;
912 int data_page_index
, data_page_offset
;
915 uint64_t data_ptr
= args
->data_ptr
;
916 int do_bit17_swizzling
;
920 /* Pin the user pages containing the data. We can't fault while
921 * holding the struct mutex, and all of the pwrite implementations
922 * want to hold it while dereferencing the user data.
924 first_data_page
= data_ptr
/ PAGE_SIZE
;
925 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
926 num_pages
= last_data_page
- first_data_page
+ 1;
928 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
929 if (user_pages
== NULL
)
932 mutex_unlock(&dev
->struct_mutex
);
933 down_read(&mm
->mmap_sem
);
934 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
935 num_pages
, 0, 0, user_pages
, NULL
);
936 up_read(&mm
->mmap_sem
);
937 mutex_lock(&dev
->struct_mutex
);
938 if (pinned_pages
< num_pages
) {
943 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
947 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
949 obj_priv
= to_intel_bo(obj
);
950 offset
= args
->offset
;
956 /* Operation in this page
958 * shmem_page_offset = offset within page in shmem file
959 * data_page_index = page number in get_user_pages return
960 * data_page_offset = offset with data_page_index page.
961 * page_length = bytes to copy for this page
963 shmem_page_offset
= offset
& ~PAGE_MASK
;
964 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
965 data_page_offset
= data_ptr
& ~PAGE_MASK
;
967 page_length
= remain
;
968 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
969 page_length
= PAGE_SIZE
- shmem_page_offset
;
970 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
971 page_length
= PAGE_SIZE
- data_page_offset
;
973 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
974 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
980 if (do_bit17_swizzling
) {
981 slow_shmem_bit17_copy(page
,
983 user_pages
[data_page_index
],
988 slow_shmem_copy(page
,
990 user_pages
[data_page_index
],
995 set_page_dirty(page
);
996 mark_page_accessed(page
);
997 page_cache_release(page
);
999 remain
-= page_length
;
1000 data_ptr
+= page_length
;
1001 offset
+= page_length
;
1005 for (i
= 0; i
< pinned_pages
; i
++)
1006 page_cache_release(user_pages
[i
]);
1007 drm_free_large(user_pages
);
1013 * Writes data to the object referenced by handle.
1015 * On error, the contents of the buffer that were to be modified are undefined.
1018 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1019 struct drm_file
*file
)
1021 struct drm_i915_gem_pwrite
*args
= data
;
1022 struct drm_gem_object
*obj
;
1023 struct drm_i915_gem_object
*obj_priv
;
1026 if (args
->size
== 0)
1029 if (!access_ok(VERIFY_READ
,
1030 (char __user
*)(uintptr_t)args
->data_ptr
,
1034 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1039 ret
= i915_mutex_lock_interruptible(dev
);
1043 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1048 obj_priv
= to_intel_bo(obj
);
1050 /* Bounds check destination. */
1051 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1056 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1057 * it would end up going through the fenced access, and we'll get
1058 * different detiling behavior between reading and writing.
1059 * pread/pwrite currently are reading and writing from the CPU
1060 * perspective, requiring manual detiling by the client.
1062 if (obj_priv
->phys_obj
)
1063 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1064 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1065 obj_priv
->gtt_space
&&
1066 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1067 ret
= i915_gem_object_pin(obj
, 0, true);
1071 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1075 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1077 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1080 i915_gem_object_unpin(obj
);
1082 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1087 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1088 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1090 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1094 drm_gem_object_unreference(obj
);
1096 mutex_unlock(&dev
->struct_mutex
);
1101 * Called when user space prepares to use an object with the CPU, either
1102 * through the mmap ioctl's mapping or a GTT mapping.
1105 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1106 struct drm_file
*file_priv
)
1108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1109 struct drm_i915_gem_set_domain
*args
= data
;
1110 struct drm_gem_object
*obj
;
1111 struct drm_i915_gem_object
*obj_priv
;
1112 uint32_t read_domains
= args
->read_domains
;
1113 uint32_t write_domain
= args
->write_domain
;
1116 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1119 /* Only handle setting domains to types used by the CPU. */
1120 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1123 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1126 /* Having something in the write domain implies it's in the read
1127 * domain, and only that read domain. Enforce that in the request.
1129 if (write_domain
!= 0 && read_domains
!= write_domain
)
1132 ret
= i915_mutex_lock_interruptible(dev
);
1136 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1141 obj_priv
= to_intel_bo(obj
);
1143 intel_mark_busy(dev
, obj
);
1145 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1146 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1148 /* Update the LRU on the fence for the CPU access that's
1151 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1152 struct drm_i915_fence_reg
*reg
=
1153 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1154 list_move_tail(®
->lru_list
,
1155 &dev_priv
->mm
.fence_list
);
1158 /* Silently promote "you're not bound, there was nothing to do"
1159 * to success, since the client was just asking us to
1160 * make sure everything was done.
1165 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1168 /* Maintain LRU order of "inactive" objects */
1169 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1170 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1172 drm_gem_object_unreference(obj
);
1174 mutex_unlock(&dev
->struct_mutex
);
1179 * Called when user space has done writes to this buffer
1182 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1183 struct drm_file
*file_priv
)
1185 struct drm_i915_gem_sw_finish
*args
= data
;
1186 struct drm_gem_object
*obj
;
1189 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1192 ret
= i915_mutex_lock_interruptible(dev
);
1196 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1202 /* Pinned buffers may be scanout, so flush the cache */
1203 if (to_intel_bo(obj
)->pin_count
)
1204 i915_gem_object_flush_cpu_write_domain(obj
);
1206 drm_gem_object_unreference(obj
);
1208 mutex_unlock(&dev
->struct_mutex
);
1213 * Maps the contents of an object, returning the address it is mapped
1216 * While the mapping holds a reference on the contents of the object, it doesn't
1217 * imply a ref on the object itself.
1220 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1221 struct drm_file
*file_priv
)
1223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1224 struct drm_i915_gem_mmap
*args
= data
;
1225 struct drm_gem_object
*obj
;
1229 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1232 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1236 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1237 drm_gem_object_unreference_unlocked(obj
);
1241 offset
= args
->offset
;
1243 down_write(¤t
->mm
->mmap_sem
);
1244 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1245 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1247 up_write(¤t
->mm
->mmap_sem
);
1248 drm_gem_object_unreference_unlocked(obj
);
1249 if (IS_ERR((void *)addr
))
1252 args
->addr_ptr
= (uint64_t) addr
;
1258 * i915_gem_fault - fault a page into the GTT
1259 * vma: VMA in question
1262 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1263 * from userspace. The fault handler takes care of binding the object to
1264 * the GTT (if needed), allocating and programming a fence register (again,
1265 * only if needed based on whether the old reg is still valid or the object
1266 * is tiled) and inserting a new PTE into the faulting process.
1268 * Note that the faulting process may involve evicting existing objects
1269 * from the GTT and/or fence registers to make room. So performance may
1270 * suffer if the GTT working set is large or there are few fence registers
1273 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1275 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1276 struct drm_device
*dev
= obj
->dev
;
1277 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1278 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1279 pgoff_t page_offset
;
1282 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1284 /* We don't use vmf->pgoff since that has the fake offset */
1285 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1288 /* Now bind it into the GTT if needed */
1289 mutex_lock(&dev
->struct_mutex
);
1290 BUG_ON(obj_priv
->pin_count
&& !obj_priv
->pin_mappable
);
1292 if (obj_priv
->gtt_space
) {
1293 if (!obj_priv
->map_and_fenceable
) {
1294 ret
= i915_gem_object_unbind(obj
);
1300 if (!obj_priv
->gtt_space
) {
1301 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1306 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1310 if (!obj_priv
->fault_mappable
) {
1311 obj_priv
->fault_mappable
= true;
1312 i915_gem_info_update_mappable(dev_priv
, obj_priv
, true);
1315 /* Need a new fence register? */
1316 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1317 ret
= i915_gem_object_get_fence_reg(obj
, true);
1322 if (i915_gem_object_is_inactive(obj_priv
))
1323 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1325 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1328 /* Finally, remap it using the new GTT offset */
1329 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1331 mutex_unlock(&dev
->struct_mutex
);
1338 return VM_FAULT_NOPAGE
;
1340 return VM_FAULT_OOM
;
1342 return VM_FAULT_SIGBUS
;
1347 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1348 * @obj: obj in question
1350 * GEM memory mapping works by handing back to userspace a fake mmap offset
1351 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1352 * up the object based on the offset and sets up the various memory mapping
1355 * This routine allocates and attaches a fake offset for @obj.
1358 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1360 struct drm_device
*dev
= obj
->dev
;
1361 struct drm_gem_mm
*mm
= dev
->mm_private
;
1362 struct drm_map_list
*list
;
1363 struct drm_local_map
*map
;
1366 /* Set the object up for mmap'ing */
1367 list
= &obj
->map_list
;
1368 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1373 map
->type
= _DRM_GEM
;
1374 map
->size
= obj
->size
;
1377 /* Get a DRM GEM mmap offset allocated... */
1378 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1379 obj
->size
/ PAGE_SIZE
, 0, 0);
1380 if (!list
->file_offset_node
) {
1381 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1386 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1387 obj
->size
/ PAGE_SIZE
, 0);
1388 if (!list
->file_offset_node
) {
1393 list
->hash
.key
= list
->file_offset_node
->start
;
1394 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1396 DRM_ERROR("failed to add to map hash\n");
1403 drm_mm_put_block(list
->file_offset_node
);
1412 * i915_gem_release_mmap - remove physical page mappings
1413 * @obj: obj in question
1415 * Preserve the reservation of the mmapping with the DRM core code, but
1416 * relinquish ownership of the pages back to the system.
1418 * It is vital that we remove the page mapping if we have mapped a tiled
1419 * object through the GTT and then lose the fence register due to
1420 * resource pressure. Similarly if the object has been moved out of the
1421 * aperture, than pages mapped into userspace must be revoked. Removing the
1422 * mapping will then trigger a page fault on the next user access, allowing
1423 * fixup by i915_gem_fault().
1426 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1428 struct drm_device
*dev
= obj
->dev
;
1429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1430 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1432 if (unlikely(obj
->map_list
.map
&& dev
->dev_mapping
))
1433 unmap_mapping_range(dev
->dev_mapping
,
1434 (loff_t
)obj
->map_list
.hash
.key
<<PAGE_SHIFT
,
1437 if (obj_priv
->fault_mappable
) {
1438 obj_priv
->fault_mappable
= false;
1439 i915_gem_info_update_mappable(dev_priv
, obj_priv
, false);
1444 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1446 struct drm_device
*dev
= obj
->dev
;
1447 struct drm_gem_mm
*mm
= dev
->mm_private
;
1448 struct drm_map_list
*list
= &obj
->map_list
;
1450 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1451 drm_mm_put_block(list
->file_offset_node
);
1457 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1458 * @obj: object to check
1460 * Return the required GTT alignment for an object, taking into account
1461 * potential fence register mapping.
1464 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1466 struct drm_device
*dev
= obj_priv
->base
.dev
;
1469 * Minimum alignment is 4k (GTT page size), but might be greater
1470 * if a fence register is needed for the object.
1472 if (INTEL_INFO(dev
)->gen
>= 4 ||
1473 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1477 * Previous chips need to be aligned to the size of the smallest
1478 * fence register that can contain the object.
1480 return i915_gem_get_gtt_size(obj_priv
);
1484 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1486 * @obj: object to check
1488 * Return the required GTT alignment for an object, only taking into account
1489 * unfenced tiled surface requirements.
1492 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1494 struct drm_device
*dev
= obj_priv
->base
.dev
;
1498 * Minimum alignment is 4k (GTT page size) for sane hw.
1500 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1501 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1505 * Older chips need unfenced tiled buffers to be aligned to the left
1506 * edge of an even tile row (where tile rows are counted as if the bo is
1507 * placed in a fenced gtt region).
1510 (obj_priv
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1515 return tile_height
* obj_priv
->stride
* 2;
1519 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
)
1521 struct drm_device
*dev
= obj_priv
->base
.dev
;
1525 * Minimum alignment is 4k (GTT page size), but might be greater
1526 * if a fence register is needed for the object.
1528 if (INTEL_INFO(dev
)->gen
>= 4)
1529 return obj_priv
->base
.size
;
1532 * Previous chips need to be aligned to the size of the smallest
1533 * fence register that can contain the object.
1535 if (INTEL_INFO(dev
)->gen
== 3)
1540 while (size
< obj_priv
->base
.size
)
1547 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1549 * @data: GTT mapping ioctl data
1550 * @file_priv: GEM object info
1552 * Simply returns the fake offset to userspace so it can mmap it.
1553 * The mmap call will end up in drm_gem_mmap(), which will set things
1554 * up so we can get faults in the handler above.
1556 * The fault handler will take care of binding the object into the GTT
1557 * (since it may have been evicted to make room for something), allocating
1558 * a fence register, and mapping the appropriate aperture address into
1562 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1563 struct drm_file
*file_priv
)
1565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1566 struct drm_i915_gem_mmap_gtt
*args
= data
;
1567 struct drm_gem_object
*obj
;
1568 struct drm_i915_gem_object
*obj_priv
;
1571 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1574 ret
= i915_mutex_lock_interruptible(dev
);
1578 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1583 obj_priv
= to_intel_bo(obj
);
1585 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1590 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1591 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1596 if (!obj
->map_list
.map
) {
1597 ret
= i915_gem_create_mmap_offset(obj
);
1602 args
->offset
= (u64
)obj
->map_list
.hash
.key
<< PAGE_SHIFT
;
1605 drm_gem_object_unreference(obj
);
1607 mutex_unlock(&dev
->struct_mutex
);
1612 i915_gem_object_get_pages_gtt(struct drm_gem_object
*obj
,
1615 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1617 struct address_space
*mapping
;
1618 struct inode
*inode
;
1621 /* Get the list of pages out of our struct file. They'll be pinned
1622 * at this point until we release them.
1624 page_count
= obj
->size
/ PAGE_SIZE
;
1625 BUG_ON(obj_priv
->pages
!= NULL
);
1626 obj_priv
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1627 if (obj_priv
->pages
== NULL
)
1630 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1631 mapping
= inode
->i_mapping
;
1632 for (i
= 0; i
< page_count
; i
++) {
1633 page
= read_cache_page_gfp(mapping
, i
,
1641 obj_priv
->pages
[i
] = page
;
1644 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1645 i915_gem_object_do_bit_17_swizzle(obj
);
1651 page_cache_release(obj_priv
->pages
[i
]);
1653 drm_free_large(obj_priv
->pages
);
1654 obj_priv
->pages
= NULL
;
1655 return PTR_ERR(page
);
1659 i915_gem_object_put_pages_gtt(struct drm_gem_object
*obj
)
1661 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1662 int page_count
= obj
->size
/ PAGE_SIZE
;
1665 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1667 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1668 i915_gem_object_save_bit_17_swizzle(obj
);
1670 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1671 obj_priv
->dirty
= 0;
1673 for (i
= 0; i
< page_count
; i
++) {
1674 if (obj_priv
->dirty
)
1675 set_page_dirty(obj_priv
->pages
[i
]);
1677 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1678 mark_page_accessed(obj_priv
->pages
[i
]);
1680 page_cache_release(obj_priv
->pages
[i
]);
1682 obj_priv
->dirty
= 0;
1684 drm_free_large(obj_priv
->pages
);
1685 obj_priv
->pages
= NULL
;
1689 i915_gem_next_request_seqno(struct drm_device
*dev
,
1690 struct intel_ring_buffer
*ring
)
1692 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1693 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1697 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1698 struct intel_ring_buffer
*ring
)
1700 struct drm_device
*dev
= obj
->dev
;
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1702 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1703 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1705 BUG_ON(ring
== NULL
);
1706 obj_priv
->ring
= ring
;
1708 /* Add a reference if we're newly entering the active list. */
1709 if (!obj_priv
->active
) {
1710 drm_gem_object_reference(obj
);
1711 obj_priv
->active
= 1;
1714 /* Move from whatever list we were on to the tail of execution. */
1715 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1716 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1717 obj_priv
->last_rendering_seqno
= seqno
;
1721 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1723 struct drm_device
*dev
= obj
->dev
;
1724 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1725 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1727 BUG_ON(!obj_priv
->active
);
1728 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1729 list_del_init(&obj_priv
->ring_list
);
1730 obj_priv
->last_rendering_seqno
= 0;
1733 /* Immediately discard the backing storage */
1735 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1737 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1738 struct inode
*inode
;
1740 /* Our goal here is to return as much of the memory as
1741 * is possible back to the system as we are called from OOM.
1742 * To do this we must instruct the shmfs to drop all of its
1743 * backing pages, *now*. Here we mirror the actions taken
1744 * when by shmem_delete_inode() to release the backing store.
1746 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1747 truncate_inode_pages(inode
->i_mapping
, 0);
1748 if (inode
->i_op
->truncate_range
)
1749 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1751 obj_priv
->madv
= __I915_MADV_PURGED
;
1755 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1757 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1761 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1763 struct drm_device
*dev
= obj
->dev
;
1764 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1765 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1767 if (obj_priv
->pin_count
!= 0)
1768 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1770 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1771 list_del_init(&obj_priv
->ring_list
);
1773 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1775 obj_priv
->last_rendering_seqno
= 0;
1776 obj_priv
->ring
= NULL
;
1777 if (obj_priv
->active
) {
1778 obj_priv
->active
= 0;
1779 drm_gem_object_unreference(obj
);
1781 WARN_ON(i915_verify_lists(dev
));
1785 i915_gem_process_flushing_list(struct drm_device
*dev
,
1786 uint32_t flush_domains
,
1787 struct intel_ring_buffer
*ring
)
1789 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1790 struct drm_i915_gem_object
*obj_priv
, *next
;
1792 list_for_each_entry_safe(obj_priv
, next
,
1793 &ring
->gpu_write_list
,
1795 struct drm_gem_object
*obj
= &obj_priv
->base
;
1797 if (obj
->write_domain
& flush_domains
) {
1798 uint32_t old_write_domain
= obj
->write_domain
;
1800 obj
->write_domain
= 0;
1801 list_del_init(&obj_priv
->gpu_write_list
);
1802 i915_gem_object_move_to_active(obj
, ring
);
1804 /* update the fence lru list */
1805 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1806 struct drm_i915_fence_reg
*reg
=
1807 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1808 list_move_tail(®
->lru_list
,
1809 &dev_priv
->mm
.fence_list
);
1812 trace_i915_gem_object_change_domain(obj
,
1820 i915_add_request(struct drm_device
*dev
,
1821 struct drm_file
*file
,
1822 struct drm_i915_gem_request
*request
,
1823 struct intel_ring_buffer
*ring
)
1825 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1826 struct drm_i915_file_private
*file_priv
= NULL
;
1831 BUG_ON(request
== NULL
);
1834 file_priv
= file
->driver_priv
;
1836 ret
= ring
->add_request(ring
, &seqno
);
1840 ring
->outstanding_lazy_request
= false;
1842 request
->seqno
= seqno
;
1843 request
->ring
= ring
;
1844 request
->emitted_jiffies
= jiffies
;
1845 was_empty
= list_empty(&ring
->request_list
);
1846 list_add_tail(&request
->list
, &ring
->request_list
);
1849 spin_lock(&file_priv
->mm
.lock
);
1850 request
->file_priv
= file_priv
;
1851 list_add_tail(&request
->client_list
,
1852 &file_priv
->mm
.request_list
);
1853 spin_unlock(&file_priv
->mm
.lock
);
1856 if (!dev_priv
->mm
.suspended
) {
1857 mod_timer(&dev_priv
->hangcheck_timer
,
1858 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1860 queue_delayed_work(dev_priv
->wq
,
1861 &dev_priv
->mm
.retire_work
, HZ
);
1867 * Command execution barrier
1869 * Ensures that all commands in the ring are finished
1870 * before signalling the CPU
1873 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1875 uint32_t flush_domains
= 0;
1877 /* The sampler always gets flushed on i965 (sigh) */
1878 if (INTEL_INFO(dev
)->gen
>= 4)
1879 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1881 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1885 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1887 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1892 spin_lock(&file_priv
->mm
.lock
);
1893 list_del(&request
->client_list
);
1894 request
->file_priv
= NULL
;
1895 spin_unlock(&file_priv
->mm
.lock
);
1898 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1899 struct intel_ring_buffer
*ring
)
1901 while (!list_empty(&ring
->request_list
)) {
1902 struct drm_i915_gem_request
*request
;
1904 request
= list_first_entry(&ring
->request_list
,
1905 struct drm_i915_gem_request
,
1908 list_del(&request
->list
);
1909 i915_gem_request_remove_from_client(request
);
1913 while (!list_empty(&ring
->active_list
)) {
1914 struct drm_i915_gem_object
*obj_priv
;
1916 obj_priv
= list_first_entry(&ring
->active_list
,
1917 struct drm_i915_gem_object
,
1920 obj_priv
->base
.write_domain
= 0;
1921 list_del_init(&obj_priv
->gpu_write_list
);
1922 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1926 void i915_gem_reset(struct drm_device
*dev
)
1928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1929 struct drm_i915_gem_object
*obj_priv
;
1932 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1933 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1934 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1936 /* Remove anything from the flushing lists. The GPU cache is likely
1937 * to be lost on reset along with the data, so simply move the
1938 * lost bo to the inactive list.
1940 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1941 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1942 struct drm_i915_gem_object
,
1945 obj_priv
->base
.write_domain
= 0;
1946 list_del_init(&obj_priv
->gpu_write_list
);
1947 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1950 /* Move everything out of the GPU domains to ensure we do any
1951 * necessary invalidation upon reuse.
1953 list_for_each_entry(obj_priv
,
1954 &dev_priv
->mm
.inactive_list
,
1957 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1960 /* The fence registers are invalidated so clear them out */
1961 for (i
= 0; i
< 16; i
++) {
1962 struct drm_i915_fence_reg
*reg
;
1964 reg
= &dev_priv
->fence_regs
[i
];
1968 i915_gem_clear_fence_reg(reg
->obj
);
1973 * This function clears the request list as sequence numbers are passed.
1976 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1977 struct intel_ring_buffer
*ring
)
1979 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1982 if (!ring
->status_page
.page_addr
||
1983 list_empty(&ring
->request_list
))
1986 WARN_ON(i915_verify_lists(dev
));
1988 seqno
= ring
->get_seqno(ring
);
1989 while (!list_empty(&ring
->request_list
)) {
1990 struct drm_i915_gem_request
*request
;
1992 request
= list_first_entry(&ring
->request_list
,
1993 struct drm_i915_gem_request
,
1996 if (!i915_seqno_passed(seqno
, request
->seqno
))
1999 trace_i915_gem_request_retire(dev
, request
->seqno
);
2001 list_del(&request
->list
);
2002 i915_gem_request_remove_from_client(request
);
2006 /* Move any buffers on the active list that are no longer referenced
2007 * by the ringbuffer to the flushing/inactive lists as appropriate.
2009 while (!list_empty(&ring
->active_list
)) {
2010 struct drm_gem_object
*obj
;
2011 struct drm_i915_gem_object
*obj_priv
;
2013 obj_priv
= list_first_entry(&ring
->active_list
,
2014 struct drm_i915_gem_object
,
2017 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
2020 obj
= &obj_priv
->base
;
2021 if (obj
->write_domain
!= 0)
2022 i915_gem_object_move_to_flushing(obj
);
2024 i915_gem_object_move_to_inactive(obj
);
2027 if (unlikely (dev_priv
->trace_irq_seqno
&&
2028 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
2029 ring
->user_irq_put(ring
);
2030 dev_priv
->trace_irq_seqno
= 0;
2033 WARN_ON(i915_verify_lists(dev
));
2037 i915_gem_retire_requests(struct drm_device
*dev
)
2039 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2041 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
2042 struct drm_i915_gem_object
*obj_priv
, *tmp
;
2044 /* We must be careful that during unbind() we do not
2045 * accidentally infinitely recurse into retire requests.
2047 * retire -> free -> unbind -> wait -> retire_ring
2049 list_for_each_entry_safe(obj_priv
, tmp
,
2050 &dev_priv
->mm
.deferred_free_list
,
2052 i915_gem_free_object_tail(&obj_priv
->base
);
2055 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
2056 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
2057 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
2061 i915_gem_retire_work_handler(struct work_struct
*work
)
2063 drm_i915_private_t
*dev_priv
;
2064 struct drm_device
*dev
;
2066 dev_priv
= container_of(work
, drm_i915_private_t
,
2067 mm
.retire_work
.work
);
2068 dev
= dev_priv
->dev
;
2070 /* Come back later if the device is busy... */
2071 if (!mutex_trylock(&dev
->struct_mutex
)) {
2072 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2076 i915_gem_retire_requests(dev
);
2078 if (!dev_priv
->mm
.suspended
&&
2079 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
2080 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
2081 !list_empty(&dev_priv
->blt_ring
.request_list
)))
2082 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2083 mutex_unlock(&dev
->struct_mutex
);
2087 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2088 bool interruptible
, struct intel_ring_buffer
*ring
)
2090 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2096 if (atomic_read(&dev_priv
->mm
.wedged
))
2099 if (seqno
== ring
->outstanding_lazy_request
) {
2100 struct drm_i915_gem_request
*request
;
2102 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2103 if (request
== NULL
)
2106 ret
= i915_add_request(dev
, NULL
, request
, ring
);
2112 seqno
= request
->seqno
;
2115 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2116 if (HAS_PCH_SPLIT(dev
))
2117 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2119 ier
= I915_READ(IER
);
2121 DRM_ERROR("something (likely vbetool) disabled "
2122 "interrupts, re-enabling\n");
2123 i915_driver_irq_preinstall(dev
);
2124 i915_driver_irq_postinstall(dev
);
2127 trace_i915_gem_request_wait_begin(dev
, seqno
);
2129 ring
->waiting_seqno
= seqno
;
2130 ring
->user_irq_get(ring
);
2132 ret
= wait_event_interruptible(ring
->irq_queue
,
2133 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2134 || atomic_read(&dev_priv
->mm
.wedged
));
2136 wait_event(ring
->irq_queue
,
2137 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2138 || atomic_read(&dev_priv
->mm
.wedged
));
2140 ring
->user_irq_put(ring
);
2141 ring
->waiting_seqno
= 0;
2143 trace_i915_gem_request_wait_end(dev
, seqno
);
2145 if (atomic_read(&dev_priv
->mm
.wedged
))
2148 if (ret
&& ret
!= -ERESTARTSYS
)
2149 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2150 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2151 dev_priv
->next_seqno
);
2153 /* Directly dispatch request retiring. While we have the work queue
2154 * to handle this, the waiter on a request often wants an associated
2155 * buffer to have made it to the inactive list, and we would need
2156 * a separate wait queue to handle that.
2159 i915_gem_retire_requests_ring(dev
, ring
);
2165 * Waits for a sequence number to be signaled, and cleans up the
2166 * request and object lists appropriately for that event.
2169 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2170 struct intel_ring_buffer
*ring
)
2172 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2176 i915_gem_flush_ring(struct drm_device
*dev
,
2177 struct drm_file
*file_priv
,
2178 struct intel_ring_buffer
*ring
,
2179 uint32_t invalidate_domains
,
2180 uint32_t flush_domains
)
2182 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2183 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2187 i915_gem_flush(struct drm_device
*dev
,
2188 struct drm_file
*file_priv
,
2189 uint32_t invalidate_domains
,
2190 uint32_t flush_domains
,
2191 uint32_t flush_rings
)
2193 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2195 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2196 drm_agp_chipset_flush(dev
);
2198 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2199 if (flush_rings
& RING_RENDER
)
2200 i915_gem_flush_ring(dev
, file_priv
,
2201 &dev_priv
->render_ring
,
2202 invalidate_domains
, flush_domains
);
2203 if (flush_rings
& RING_BSD
)
2204 i915_gem_flush_ring(dev
, file_priv
,
2205 &dev_priv
->bsd_ring
,
2206 invalidate_domains
, flush_domains
);
2207 if (flush_rings
& RING_BLT
)
2208 i915_gem_flush_ring(dev
, file_priv
,
2209 &dev_priv
->blt_ring
,
2210 invalidate_domains
, flush_domains
);
2215 * Ensures that all rendering to the object has completed and the object is
2216 * safe to unbind from the GTT or access from the CPU.
2219 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2222 struct drm_device
*dev
= obj
->dev
;
2223 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2226 /* This function only exists to support waiting for existing rendering,
2227 * not for emitting required flushes.
2229 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2231 /* If there is rendering queued on the buffer being evicted, wait for
2234 if (obj_priv
->active
) {
2235 ret
= i915_do_wait_request(dev
,
2236 obj_priv
->last_rendering_seqno
,
2247 * Unbinds an object from the GTT aperture.
2250 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2252 struct drm_device
*dev
= obj
->dev
;
2253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2254 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2257 if (obj_priv
->gtt_space
== NULL
)
2260 if (obj_priv
->pin_count
!= 0) {
2261 DRM_ERROR("Attempting to unbind pinned buffer\n");
2265 /* blow away mappings if mapped through GTT */
2266 i915_gem_release_mmap(obj
);
2268 /* Move the object to the CPU domain to ensure that
2269 * any possible CPU writes while it's not in the GTT
2270 * are flushed when we go to remap it. This will
2271 * also ensure that all pending GPU writes are finished
2274 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2275 if (ret
== -ERESTARTSYS
)
2277 /* Continue on if we fail due to EIO, the GPU is hung so we
2278 * should be safe and we need to cleanup or else we might
2279 * cause memory corruption through use-after-free.
2282 i915_gem_clflush_object(obj
);
2283 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2286 /* release the fence reg _after_ flushing */
2287 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2288 i915_gem_clear_fence_reg(obj
);
2290 drm_unbind_agp(obj_priv
->agp_mem
);
2291 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2293 i915_gem_object_put_pages_gtt(obj
);
2295 i915_gem_info_remove_gtt(dev_priv
, obj_priv
);
2296 list_del_init(&obj_priv
->mm_list
);
2297 /* Avoid an unnecessary call to unbind on rebind. */
2298 obj_priv
->map_and_fenceable
= true;
2300 drm_mm_put_block(obj_priv
->gtt_space
);
2301 obj_priv
->gtt_space
= NULL
;
2302 obj_priv
->gtt_offset
= 0;
2304 if (i915_gem_object_is_purgeable(obj_priv
))
2305 i915_gem_object_truncate(obj
);
2307 trace_i915_gem_object_unbind(obj
);
2312 static int i915_ring_idle(struct drm_device
*dev
,
2313 struct intel_ring_buffer
*ring
)
2315 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2318 i915_gem_flush_ring(dev
, NULL
, ring
,
2319 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2320 return i915_wait_request(dev
,
2321 i915_gem_next_request_seqno(dev
, ring
),
2326 i915_gpu_idle(struct drm_device
*dev
)
2328 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2332 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2333 list_empty(&dev_priv
->mm
.active_list
));
2337 /* Flush everything onto the inactive list. */
2338 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2342 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2346 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2353 static void sandybridge_write_fence_reg(struct drm_gem_object
*obj
)
2355 struct drm_device
*dev
= obj
->dev
;
2356 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2357 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2358 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2359 int regnum
= obj_priv
->fence_reg
;
2362 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2364 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2365 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2366 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2368 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2369 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2370 val
|= I965_FENCE_REG_VALID
;
2372 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2375 static void i965_write_fence_reg(struct drm_gem_object
*obj
)
2377 struct drm_device
*dev
= obj
->dev
;
2378 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2379 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2380 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2381 int regnum
= obj_priv
->fence_reg
;
2384 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2386 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2387 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2388 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2389 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2390 val
|= I965_FENCE_REG_VALID
;
2392 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2395 static void i915_write_fence_reg(struct drm_gem_object
*obj
)
2397 struct drm_device
*dev
= obj
->dev
;
2398 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2399 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2400 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2401 uint32_t fence_reg
, val
, pitch_val
;
2404 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2405 (obj_priv
->gtt_offset
& (size
- 1))) {
2406 WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
2407 __func__
, obj_priv
->gtt_offset
, obj_priv
->map_and_fenceable
, size
,
2408 obj_priv
->gtt_space
->start
, obj_priv
->gtt_space
->size
);
2412 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2413 HAS_128_BYTE_Y_TILING(dev
))
2418 /* Note: pitch better be a power of two tile widths */
2419 pitch_val
= obj_priv
->stride
/ tile_width
;
2420 pitch_val
= ffs(pitch_val
) - 1;
2422 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2423 HAS_128_BYTE_Y_TILING(dev
))
2424 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2426 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2428 val
= obj_priv
->gtt_offset
;
2429 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2430 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2431 val
|= I915_FENCE_SIZE_BITS(size
);
2432 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2433 val
|= I830_FENCE_REG_VALID
;
2435 fence_reg
= obj_priv
->fence_reg
;
2437 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2439 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2440 I915_WRITE(fence_reg
, val
);
2443 static void i830_write_fence_reg(struct drm_gem_object
*obj
)
2445 struct drm_device
*dev
= obj
->dev
;
2446 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2447 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2448 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2449 int regnum
= obj_priv
->fence_reg
;
2452 uint32_t fence_size_bits
;
2454 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2455 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2456 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2457 __func__
, obj_priv
->gtt_offset
);
2461 pitch_val
= obj_priv
->stride
/ 128;
2462 pitch_val
= ffs(pitch_val
) - 1;
2463 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2465 val
= obj_priv
->gtt_offset
;
2466 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2467 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2468 fence_size_bits
= I830_FENCE_SIZE_BITS(size
);
2469 WARN_ON(fence_size_bits
& ~0x00000f00);
2470 val
|= fence_size_bits
;
2471 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2472 val
|= I830_FENCE_REG_VALID
;
2474 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2477 static int i915_find_fence_reg(struct drm_device
*dev
,
2480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2481 struct drm_i915_fence_reg
*reg
;
2482 struct drm_i915_gem_object
*obj_priv
= NULL
;
2485 /* First try to find a free reg */
2487 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2488 reg
= &dev_priv
->fence_regs
[i
];
2492 obj_priv
= to_intel_bo(reg
->obj
);
2493 if (!obj_priv
->pin_count
)
2500 /* None available, try to steal one or wait for a user to finish */
2501 avail
= I915_FENCE_REG_NONE
;
2502 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2504 obj_priv
= to_intel_bo(reg
->obj
);
2505 if (obj_priv
->pin_count
)
2509 avail
= obj_priv
->fence_reg
;
2513 BUG_ON(avail
== I915_FENCE_REG_NONE
);
2515 /* We only have a reference on obj from the active list. put_fence_reg
2516 * might drop that one, causing a use-after-free in it. So hold a
2517 * private reference to obj like the other callers of put_fence_reg
2518 * (set_tiling ioctl) do. */
2519 drm_gem_object_reference(&obj_priv
->base
);
2520 ret
= i915_gem_object_put_fence_reg(&obj_priv
->base
, interruptible
);
2521 drm_gem_object_unreference(&obj_priv
->base
);
2529 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2530 * @obj: object to map through a fence reg
2532 * When mapping objects through the GTT, userspace wants to be able to write
2533 * to them without having to worry about swizzling if the object is tiled.
2535 * This function walks the fence regs looking for a free one for @obj,
2536 * stealing one if it can't find any.
2538 * It then sets up the reg based on the object's properties: address, pitch
2539 * and tiling format.
2542 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2545 struct drm_device
*dev
= obj
->dev
;
2546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2548 struct drm_i915_fence_reg
*reg
= NULL
;
2551 /* Just update our place in the LRU if our fence is getting used. */
2552 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2553 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2554 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2558 switch (obj_priv
->tiling_mode
) {
2559 case I915_TILING_NONE
:
2560 WARN(1, "allocating a fence for non-tiled object?\n");
2563 if (!obj_priv
->stride
)
2565 WARN((obj_priv
->stride
& (512 - 1)),
2566 "object 0x%08x is X tiled but has non-512B pitch\n",
2567 obj_priv
->gtt_offset
);
2570 if (!obj_priv
->stride
)
2572 WARN((obj_priv
->stride
& (128 - 1)),
2573 "object 0x%08x is Y tiled but has non-128B pitch\n",
2574 obj_priv
->gtt_offset
);
2578 ret
= i915_find_fence_reg(dev
, interruptible
);
2582 obj_priv
->fence_reg
= ret
;
2583 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2584 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2588 switch (INTEL_INFO(dev
)->gen
) {
2590 sandybridge_write_fence_reg(obj
);
2594 i965_write_fence_reg(obj
);
2597 i915_write_fence_reg(obj
);
2600 i830_write_fence_reg(obj
);
2604 trace_i915_gem_object_get_fence(obj
,
2605 obj_priv
->fence_reg
,
2606 obj_priv
->tiling_mode
);
2612 * i915_gem_clear_fence_reg - clear out fence register info
2613 * @obj: object to clear
2615 * Zeroes out the fence register itself and clears out the associated
2616 * data structures in dev_priv and obj_priv.
2619 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2621 struct drm_device
*dev
= obj
->dev
;
2622 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2623 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2624 struct drm_i915_fence_reg
*reg
=
2625 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2628 switch (INTEL_INFO(dev
)->gen
) {
2630 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2631 (obj_priv
->fence_reg
* 8), 0);
2635 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2638 if (obj_priv
->fence_reg
>= 8)
2639 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2642 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2644 I915_WRITE(fence_reg
, 0);
2649 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2650 list_del_init(®
->lru_list
);
2654 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2655 * to the buffer to finish, and then resets the fence register.
2656 * @obj: tiled object holding a fence register.
2657 * @bool: whether the wait upon the fence is interruptible
2659 * Zeroes out the fence register itself and clears out the associated
2660 * data structures in dev_priv and obj_priv.
2663 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2666 struct drm_device
*dev
= obj
->dev
;
2667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2668 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2669 struct drm_i915_fence_reg
*reg
;
2671 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2674 /* If we've changed tiling, GTT-mappings of the object
2675 * need to re-fault to ensure that the correct fence register
2676 * setup is in place.
2678 i915_gem_release_mmap(obj
);
2680 /* On the i915, GPU access to tiled buffers is via a fence,
2681 * therefore we must wait for any outstanding access to complete
2682 * before clearing the fence.
2684 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2688 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2692 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2699 i915_gem_object_flush_gtt_write_domain(obj
);
2700 i915_gem_clear_fence_reg(obj
);
2706 * Finds free space in the GTT aperture and binds the object there.
2709 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
2711 bool map_and_fenceable
)
2713 struct drm_device
*dev
= obj
->dev
;
2714 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2715 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2716 struct drm_mm_node
*free_space
;
2717 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2718 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2719 bool mappable
, fenceable
;
2722 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2723 DRM_ERROR("Attempting to bind a purgeable object\n");
2727 fence_size
= i915_gem_get_gtt_size(obj_priv
);
2728 fence_alignment
= i915_gem_get_gtt_alignment(obj_priv
);
2729 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj_priv
);
2732 alignment
= map_and_fenceable
? fence_alignment
:
2734 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2735 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2739 size
= map_and_fenceable
? fence_size
: obj
->size
;
2741 /* If the object is bigger than the entire aperture, reject it early
2742 * before evicting everything in a vain attempt to find space.
2745 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2746 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2751 if (map_and_fenceable
)
2753 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2755 dev_priv
->mm
.gtt_mappable_end
,
2758 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2759 size
, alignment
, 0);
2761 if (free_space
!= NULL
) {
2762 if (map_and_fenceable
)
2763 obj_priv
->gtt_space
=
2764 drm_mm_get_block_range_generic(free_space
,
2766 dev_priv
->mm
.gtt_mappable_end
,
2769 obj_priv
->gtt_space
=
2770 drm_mm_get_block(free_space
, size
, alignment
);
2772 if (obj_priv
->gtt_space
== NULL
) {
2773 /* If the gtt is empty and we're still having trouble
2774 * fitting our object in, we're out of memory.
2776 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2784 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2786 drm_mm_put_block(obj_priv
->gtt_space
);
2787 obj_priv
->gtt_space
= NULL
;
2789 if (ret
== -ENOMEM
) {
2790 /* first try to clear up some space from the GTT */
2791 ret
= i915_gem_evict_something(dev
, size
,
2795 /* now try to shrink everyone else */
2810 /* Create an AGP memory structure pointing at our pages, and bind it
2813 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2815 obj
->size
>> PAGE_SHIFT
,
2816 obj_priv
->gtt_space
->start
,
2817 obj_priv
->agp_type
);
2818 if (obj_priv
->agp_mem
== NULL
) {
2819 i915_gem_object_put_pages_gtt(obj
);
2820 drm_mm_put_block(obj_priv
->gtt_space
);
2821 obj_priv
->gtt_space
= NULL
;
2823 ret
= i915_gem_evict_something(dev
, size
,
2824 alignment
, map_and_fenceable
);
2831 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2833 /* keep track of bounds object by adding it to the inactive list */
2834 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2835 i915_gem_info_add_gtt(dev_priv
, obj_priv
);
2837 /* Assert that the object is not currently in any GPU domain. As it
2838 * wasn't in the GTT, there shouldn't be any way it could have been in
2841 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2842 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2844 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
, map_and_fenceable
);
2847 obj_priv
->gtt_space
->size
== fence_size
&&
2848 (obj_priv
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2851 obj_priv
->gtt_offset
+ obj
->size
<= dev_priv
->mm
.gtt_mappable_end
;
2853 obj_priv
->map_and_fenceable
= mappable
&& fenceable
;
2859 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2861 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2863 /* If we don't have a page list set up, then we're not pinned
2864 * to GPU, and we can ignore the cache flush because it'll happen
2865 * again at bind time.
2867 if (obj_priv
->pages
== NULL
)
2870 trace_i915_gem_object_clflush(obj
);
2872 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2875 /** Flushes any GPU write domain for the object if it's dirty. */
2877 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2880 struct drm_device
*dev
= obj
->dev
;
2882 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2885 /* Queue the GPU write cache flushing we need. */
2886 i915_gem_flush_ring(dev
, NULL
,
2887 to_intel_bo(obj
)->ring
,
2888 0, obj
->write_domain
);
2889 BUG_ON(obj
->write_domain
);
2894 return i915_gem_object_wait_rendering(obj
, true);
2897 /** Flushes the GTT write domain for the object if it's dirty. */
2899 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2901 uint32_t old_write_domain
;
2903 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2906 /* No actual flushing is required for the GTT write domain. Writes
2907 * to it immediately go to main memory as far as we know, so there's
2908 * no chipset flush. It also doesn't land in render cache.
2910 i915_gem_release_mmap(obj
);
2912 old_write_domain
= obj
->write_domain
;
2913 obj
->write_domain
= 0;
2915 trace_i915_gem_object_change_domain(obj
,
2920 /** Flushes the CPU write domain for the object if it's dirty. */
2922 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2924 struct drm_device
*dev
= obj
->dev
;
2925 uint32_t old_write_domain
;
2927 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2930 i915_gem_clflush_object(obj
);
2931 drm_agp_chipset_flush(dev
);
2932 old_write_domain
= obj
->write_domain
;
2933 obj
->write_domain
= 0;
2935 trace_i915_gem_object_change_domain(obj
,
2941 * Moves a single object to the GTT read, and possibly write domain.
2943 * This function returns when the move is complete, including waiting on
2947 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2949 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2950 uint32_t old_write_domain
, old_read_domains
;
2953 /* Not valid to be called on unbound objects. */
2954 if (obj_priv
->gtt_space
== NULL
)
2957 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2961 i915_gem_object_flush_cpu_write_domain(obj
);
2964 ret
= i915_gem_object_wait_rendering(obj
, true);
2969 old_write_domain
= obj
->write_domain
;
2970 old_read_domains
= obj
->read_domains
;
2972 /* It should now be out of any other write domains, and we can update
2973 * the domain values for our changes.
2975 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2976 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2978 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2979 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2980 obj_priv
->dirty
= 1;
2983 trace_i915_gem_object_change_domain(obj
,
2991 * Prepare buffer for display plane. Use uninterruptible for possible flush
2992 * wait, as in modesetting process we're not supposed to be interrupted.
2995 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2998 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2999 uint32_t old_read_domains
;
3002 /* Not valid to be called on unbound objects. */
3003 if (obj_priv
->gtt_space
== NULL
)
3006 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
3010 /* Currently, we are always called from an non-interruptible context. */
3012 ret
= i915_gem_object_wait_rendering(obj
, false);
3017 i915_gem_object_flush_cpu_write_domain(obj
);
3019 old_read_domains
= obj
->read_domains
;
3020 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
3022 trace_i915_gem_object_change_domain(obj
,
3030 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
3036 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
)
3037 i915_gem_flush_ring(obj
->base
.dev
, NULL
, obj
->ring
,
3038 0, obj
->base
.write_domain
);
3040 return i915_gem_object_wait_rendering(&obj
->base
, interruptible
);
3044 * Moves a single object to the CPU read, and possibly write domain.
3046 * This function returns when the move is complete, including waiting on
3050 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
3052 uint32_t old_write_domain
, old_read_domains
;
3055 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3059 i915_gem_object_flush_gtt_write_domain(obj
);
3061 /* If we have a partially-valid cache of the object in the CPU,
3062 * finish invalidating it and free the per-page flags.
3064 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3067 ret
= i915_gem_object_wait_rendering(obj
, true);
3072 old_write_domain
= obj
->write_domain
;
3073 old_read_domains
= obj
->read_domains
;
3075 /* Flush the CPU cache if it's still invalid. */
3076 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3077 i915_gem_clflush_object(obj
);
3079 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3082 /* It should now be out of any other write domains, and we can update
3083 * the domain values for our changes.
3085 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3087 /* If we're writing through the CPU, then the GPU read domains will
3088 * need to be invalidated at next use.
3091 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3092 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3095 trace_i915_gem_object_change_domain(obj
,
3103 * Set the next domain for the specified object. This
3104 * may not actually perform the necessary flushing/invaliding though,
3105 * as that may want to be batched with other set_domain operations
3107 * This is (we hope) the only really tricky part of gem. The goal
3108 * is fairly simple -- track which caches hold bits of the object
3109 * and make sure they remain coherent. A few concrete examples may
3110 * help to explain how it works. For shorthand, we use the notation
3111 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3112 * a pair of read and write domain masks.
3114 * Case 1: the batch buffer
3120 * 5. Unmapped from GTT
3123 * Let's take these a step at a time
3126 * Pages allocated from the kernel may still have
3127 * cache contents, so we set them to (CPU, CPU) always.
3128 * 2. Written by CPU (using pwrite)
3129 * The pwrite function calls set_domain (CPU, CPU) and
3130 * this function does nothing (as nothing changes)
3132 * This function asserts that the object is not
3133 * currently in any GPU-based read or write domains
3135 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3136 * As write_domain is zero, this function adds in the
3137 * current read domains (CPU+COMMAND, 0).
3138 * flush_domains is set to CPU.
3139 * invalidate_domains is set to COMMAND
3140 * clflush is run to get data out of the CPU caches
3141 * then i915_dev_set_domain calls i915_gem_flush to
3142 * emit an MI_FLUSH and drm_agp_chipset_flush
3143 * 5. Unmapped from GTT
3144 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3145 * flush_domains and invalidate_domains end up both zero
3146 * so no flushing/invalidating happens
3150 * Case 2: The shared render buffer
3154 * 3. Read/written by GPU
3155 * 4. set_domain to (CPU,CPU)
3156 * 5. Read/written by CPU
3157 * 6. Read/written by GPU
3160 * Same as last example, (CPU, CPU)
3162 * Nothing changes (assertions find that it is not in the GPU)
3163 * 3. Read/written by GPU
3164 * execbuffer calls set_domain (RENDER, RENDER)
3165 * flush_domains gets CPU
3166 * invalidate_domains gets GPU
3168 * MI_FLUSH and drm_agp_chipset_flush
3169 * 4. set_domain (CPU, CPU)
3170 * flush_domains gets GPU
3171 * invalidate_domains gets CPU
3172 * wait_rendering (obj) to make sure all drawing is complete.
3173 * This will include an MI_FLUSH to get the data from GPU
3175 * clflush (obj) to invalidate the CPU cache
3176 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3177 * 5. Read/written by CPU
3178 * cache lines are loaded and dirtied
3179 * 6. Read written by GPU
3180 * Same as last GPU access
3182 * Case 3: The constant buffer
3187 * 4. Updated (written) by CPU again
3196 * flush_domains = CPU
3197 * invalidate_domains = RENDER
3200 * drm_agp_chipset_flush
3201 * 4. Updated (written) by CPU again
3203 * flush_domains = 0 (no previous write domain)
3204 * invalidate_domains = 0 (no new read domains)
3207 * flush_domains = CPU
3208 * invalidate_domains = RENDER
3211 * drm_agp_chipset_flush
3214 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3215 struct intel_ring_buffer
*ring
,
3216 struct change_domains
*cd
)
3218 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3219 uint32_t invalidate_domains
= 0;
3220 uint32_t flush_domains
= 0;
3223 * If the object isn't moving to a new write domain,
3224 * let the object stay in multiple read domains
3226 if (obj
->pending_write_domain
== 0)
3227 obj
->pending_read_domains
|= obj
->read_domains
;
3230 * Flush the current write domain if
3231 * the new read domains don't match. Invalidate
3232 * any read domains which differ from the old
3235 if (obj
->write_domain
&&
3236 (obj
->write_domain
!= obj
->pending_read_domains
||
3237 obj_priv
->ring
!= ring
)) {
3238 flush_domains
|= obj
->write_domain
;
3239 invalidate_domains
|=
3240 obj
->pending_read_domains
& ~obj
->write_domain
;
3243 * Invalidate any read caches which may have
3244 * stale data. That is, any new read domains.
3246 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3247 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3248 i915_gem_clflush_object(obj
);
3250 /* blow away mappings if mapped through GTT */
3251 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
3252 i915_gem_release_mmap(obj
);
3254 /* The actual obj->write_domain will be updated with
3255 * pending_write_domain after we emit the accumulated flush for all
3256 * of our domain changes in execbuffers (which clears objects'
3257 * write_domains). So if we have a current write domain that we
3258 * aren't changing, set pending_write_domain to that.
3260 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3261 obj
->pending_write_domain
= obj
->write_domain
;
3263 cd
->invalidate_domains
|= invalidate_domains
;
3264 cd
->flush_domains
|= flush_domains
;
3265 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3266 cd
->flush_rings
|= obj_priv
->ring
->id
;
3267 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3268 cd
->flush_rings
|= ring
->id
;
3272 * Moves the object from a partially CPU read to a full one.
3274 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3275 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3278 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3280 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3282 if (!obj_priv
->page_cpu_valid
)
3285 /* If we're partially in the CPU read domain, finish moving it in.
3287 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3290 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3291 if (obj_priv
->page_cpu_valid
[i
])
3293 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3297 /* Free the page_cpu_valid mappings which are now stale, whether
3298 * or not we've got I915_GEM_DOMAIN_CPU.
3300 kfree(obj_priv
->page_cpu_valid
);
3301 obj_priv
->page_cpu_valid
= NULL
;
3305 * Set the CPU read domain on a range of the object.
3307 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3308 * not entirely valid. The page_cpu_valid member of the object flags which
3309 * pages have been flushed, and will be respected by
3310 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3311 * of the whole object.
3313 * This function returns when the move is complete, including waiting on
3317 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3318 uint64_t offset
, uint64_t size
)
3320 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3321 uint32_t old_read_domains
;
3324 if (offset
== 0 && size
== obj
->size
)
3325 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3327 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3330 i915_gem_object_flush_gtt_write_domain(obj
);
3332 /* If we're already fully in the CPU read domain, we're done. */
3333 if (obj_priv
->page_cpu_valid
== NULL
&&
3334 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3337 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3338 * newly adding I915_GEM_DOMAIN_CPU
3340 if (obj_priv
->page_cpu_valid
== NULL
) {
3341 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3343 if (obj_priv
->page_cpu_valid
== NULL
)
3345 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3346 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3348 /* Flush the cache on any pages that are still invalid from the CPU's
3351 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3353 if (obj_priv
->page_cpu_valid
[i
])
3356 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3358 obj_priv
->page_cpu_valid
[i
] = 1;
3361 /* It should now be out of any other write domains, and we can update
3362 * the domain values for our changes.
3364 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3366 old_read_domains
= obj
->read_domains
;
3367 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3369 trace_i915_gem_object_change_domain(obj
,
3377 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
3378 struct drm_file
*file_priv
,
3379 struct drm_i915_gem_exec_object2
*entry
,
3380 struct drm_i915_gem_relocation_entry
*reloc
)
3382 struct drm_device
*dev
= obj
->base
.dev
;
3383 struct drm_gem_object
*target_obj
;
3384 uint32_t target_offset
;
3387 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3388 reloc
->target_handle
);
3389 if (target_obj
== NULL
)
3392 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3395 DRM_INFO("%s: obj %p offset %08x target %d "
3396 "read %08x write %08x gtt %08x "
3397 "presumed %08x delta %08x\n",
3400 (int) reloc
->offset
,
3401 (int) reloc
->target_handle
,
3402 (int) reloc
->read_domains
,
3403 (int) reloc
->write_domain
,
3404 (int) target_offset
,
3405 (int) reloc
->presumed_offset
,
3409 /* The target buffer should have appeared before us in the
3410 * exec_object list, so it should have a GTT space bound by now.
3412 if (target_offset
== 0) {
3413 DRM_ERROR("No GTT space found for object %d\n",
3414 reloc
->target_handle
);
3418 /* Validate that the target is in a valid r/w GPU domain */
3419 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3420 DRM_ERROR("reloc with multiple write domains: "
3421 "obj %p target %d offset %d "
3422 "read %08x write %08x",
3423 obj
, reloc
->target_handle
,
3424 (int) reloc
->offset
,
3425 reloc
->read_domains
,
3426 reloc
->write_domain
);
3429 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3430 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3431 DRM_ERROR("reloc with read/write CPU domains: "
3432 "obj %p target %d offset %d "
3433 "read %08x write %08x",
3434 obj
, reloc
->target_handle
,
3435 (int) reloc
->offset
,
3436 reloc
->read_domains
,
3437 reloc
->write_domain
);
3440 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3441 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3442 DRM_ERROR("Write domain conflict: "
3443 "obj %p target %d offset %d "
3444 "new %08x old %08x\n",
3445 obj
, reloc
->target_handle
,
3446 (int) reloc
->offset
,
3447 reloc
->write_domain
,
3448 target_obj
->pending_write_domain
);
3452 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3453 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3455 /* If the relocation already has the right value in it, no
3456 * more work needs to be done.
3458 if (target_offset
== reloc
->presumed_offset
)
3461 /* Check that the relocation address is valid... */
3462 if (reloc
->offset
> obj
->base
.size
- 4) {
3463 DRM_ERROR("Relocation beyond object bounds: "
3464 "obj %p target %d offset %d size %d.\n",
3465 obj
, reloc
->target_handle
,
3466 (int) reloc
->offset
,
3467 (int) obj
->base
.size
);
3470 if (reloc
->offset
& 3) {
3471 DRM_ERROR("Relocation not 4-byte aligned: "
3472 "obj %p target %d offset %d.\n",
3473 obj
, reloc
->target_handle
,
3474 (int) reloc
->offset
);
3478 /* and points to somewhere within the target object. */
3479 if (reloc
->delta
>= target_obj
->size
) {
3480 DRM_ERROR("Relocation beyond target object bounds: "
3481 "obj %p target %d delta %d size %d.\n",
3482 obj
, reloc
->target_handle
,
3484 (int) target_obj
->size
);
3488 reloc
->delta
+= target_offset
;
3489 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3490 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
3493 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
3494 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
3495 kunmap_atomic(vaddr
);
3497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3498 uint32_t __iomem
*reloc_entry
;
3499 void __iomem
*reloc_page
;
3501 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3505 /* Map the page containing the relocation we're going to perform. */
3506 reloc
->offset
+= obj
->gtt_offset
;
3507 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3508 reloc
->offset
& PAGE_MASK
);
3509 reloc_entry
= (uint32_t __iomem
*)
3510 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
3511 iowrite32(reloc
->delta
, reloc_entry
);
3512 io_mapping_unmap_atomic(reloc_page
);
3515 /* and update the user's relocation entry */
3516 reloc
->presumed_offset
= target_offset
;
3521 drm_gem_object_unreference(target_obj
);
3526 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
3527 struct drm_file
*file_priv
,
3528 struct drm_i915_gem_exec_object2
*entry
)
3530 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3533 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3534 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3535 struct drm_i915_gem_relocation_entry reloc
;
3537 if (__copy_from_user_inatomic(&reloc
,
3542 ret
= i915_gem_execbuffer_relocate_entry(obj
, file_priv
, entry
, &reloc
);
3546 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3547 &reloc
.presumed_offset
,
3548 sizeof(reloc
.presumed_offset
)))
3556 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
3557 struct drm_file
*file_priv
,
3558 struct drm_i915_gem_exec_object2
*entry
,
3559 struct drm_i915_gem_relocation_entry
*relocs
)
3563 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3564 ret
= i915_gem_execbuffer_relocate_entry(obj
, file_priv
, entry
, &relocs
[i
]);
3573 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
3574 struct drm_file
*file
,
3575 struct drm_gem_object
**object_list
,
3576 struct drm_i915_gem_exec_object2
*exec_list
,
3581 for (i
= 0; i
< count
; i
++) {
3582 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3583 obj
->base
.pending_read_domains
= 0;
3584 obj
->base
.pending_write_domain
= 0;
3585 ret
= i915_gem_execbuffer_relocate_object(obj
, file
,
3595 i915_gem_execbuffer_reserve(struct drm_device
*dev
,
3596 struct drm_file
*file
,
3597 struct drm_gem_object
**object_list
,
3598 struct drm_i915_gem_exec_object2
*exec_list
,
3601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3604 /* attempt to pin all of the buffers into the GTT */
3608 for (i
= 0; i
< count
; i
++) {
3609 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3610 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3612 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3613 obj
->tiling_mode
!= I915_TILING_NONE
;
3615 /* g33/pnv can't fence buffers in the unmappable part */
3616 bool need_mappable
=
3617 entry
->relocation_count
? true : need_fence
;
3619 /* Check fence reg constraints and rebind if necessary */
3620 if (need_mappable
&& !obj
->map_and_fenceable
) {
3621 ret
= i915_gem_object_unbind(&obj
->base
);
3626 ret
= i915_gem_object_pin(&obj
->base
,
3633 * Pre-965 chips need a fence register set up in order
3634 * to properly handle blits to/from tiled surfaces.
3637 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3639 i915_gem_object_unpin(&obj
->base
);
3643 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3646 entry
->offset
= obj
->gtt_offset
;
3650 i915_gem_object_unpin(object_list
[i
]);
3652 if (ret
!= -ENOSPC
|| retry
> 1)
3655 /* First attempt, just clear anything that is purgeable.
3656 * Second attempt, clear the entire GTT.
3658 ret
= i915_gem_evict_everything(dev
, retry
== 0);
3667 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
3668 struct drm_file
*file
,
3669 struct drm_gem_object
**object_list
,
3670 struct drm_i915_gem_exec_object2
*exec_list
,
3673 struct drm_i915_gem_relocation_entry
*reloc
;
3676 for (i
= 0; i
< count
; i
++) {
3677 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3678 obj
->in_execbuffer
= false;
3681 mutex_unlock(&dev
->struct_mutex
);
3684 for (i
= 0; i
< count
; i
++)
3685 total
+= exec_list
[i
].relocation_count
;
3687 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
3688 if (reloc
== NULL
) {
3689 mutex_lock(&dev
->struct_mutex
);
3694 for (i
= 0; i
< count
; i
++) {
3695 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3697 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3699 if (copy_from_user(reloc
+total
, user_relocs
,
3700 exec_list
[i
].relocation_count
*
3703 mutex_lock(&dev
->struct_mutex
);
3707 total
+= exec_list
[i
].relocation_count
;
3710 ret
= i915_mutex_lock_interruptible(dev
);
3712 mutex_lock(&dev
->struct_mutex
);
3716 ret
= i915_gem_execbuffer_reserve(dev
, file
,
3717 object_list
, exec_list
,
3723 for (i
= 0; i
< count
; i
++) {
3724 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3725 obj
->base
.pending_read_domains
= 0;
3726 obj
->base
.pending_write_domain
= 0;
3727 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, file
,
3733 total
+= exec_list
[i
].relocation_count
;
3736 /* Leave the user relocations as are, this is the painfully slow path,
3737 * and we want to avoid the complication of dropping the lock whilst
3738 * having buffers reserved in the aperture and so causing spurious
3739 * ENOSPC for random operations.
3743 drm_free_large(reloc
);
3748 i915_gem_execbuffer_move_to_gpu(struct drm_device
*dev
,
3749 struct drm_file
*file
,
3750 struct intel_ring_buffer
*ring
,
3751 struct drm_gem_object
**objects
,
3754 struct change_domains cd
;
3757 cd
.invalidate_domains
= 0;
3758 cd
.flush_domains
= 0;
3760 for (i
= 0; i
< count
; i
++)
3761 i915_gem_object_set_to_gpu_domain(objects
[i
], ring
, &cd
);
3763 if (cd
.invalidate_domains
| cd
.flush_domains
) {
3765 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3767 cd
.invalidate_domains
,
3770 i915_gem_flush(dev
, file
,
3771 cd
.invalidate_domains
,
3776 for (i
= 0; i
< count
; i
++) {
3777 struct drm_i915_gem_object
*obj
= to_intel_bo(objects
[i
]);
3778 /* XXX replace with semaphores */
3779 if (obj
->ring
&& ring
!= obj
->ring
) {
3780 ret
= i915_gem_object_wait_rendering(&obj
->base
, true);
3789 /* Throttle our rendering by waiting until the ring has completed our requests
3790 * emitted over 20 msec ago.
3792 * Note that if we were to use the current jiffies each time around the loop,
3793 * we wouldn't escape the function with any frames outstanding if the time to
3794 * render a frame was over 20ms.
3796 * This should get us reasonable parallelism between CPU and GPU but also
3797 * relatively low latency when blocking on a particular request to finish.
3800 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3803 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3804 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3805 struct drm_i915_gem_request
*request
;
3806 struct intel_ring_buffer
*ring
= NULL
;
3810 spin_lock(&file_priv
->mm
.lock
);
3811 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3812 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3815 ring
= request
->ring
;
3816 seqno
= request
->seqno
;
3818 spin_unlock(&file_priv
->mm
.lock
);
3824 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3825 /* And wait for the seqno passing without holding any locks and
3826 * causing extra latency for others. This is safe as the irq
3827 * generation is designed to be run atomically and so is
3830 ring
->user_irq_get(ring
);
3831 ret
= wait_event_interruptible(ring
->irq_queue
,
3832 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3833 || atomic_read(&dev_priv
->mm
.wedged
));
3834 ring
->user_irq_put(ring
);
3836 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3841 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3847 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3848 uint64_t exec_offset
)
3850 uint32_t exec_start
, exec_len
;
3852 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3853 exec_len
= (uint32_t) exec
->batch_len
;
3855 if ((exec_start
| exec_len
) & 0x7)
3865 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3870 for (i
= 0; i
< count
; i
++) {
3871 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3872 int length
; /* limited by fault_in_pages_readable() */
3874 /* First check for malicious input causing overflow */
3875 if (exec
[i
].relocation_count
>
3876 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
3879 length
= exec
[i
].relocation_count
*
3880 sizeof(struct drm_i915_gem_relocation_entry
);
3881 if (!access_ok(VERIFY_READ
, ptr
, length
))
3884 /* we may also need to update the presumed offsets */
3885 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3888 if (fault_in_pages_readable(ptr
, length
))
3896 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3897 struct drm_file
*file
,
3898 struct drm_i915_gem_execbuffer2
*args
,
3899 struct drm_i915_gem_exec_object2
*exec_list
)
3901 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3902 struct drm_gem_object
**object_list
= NULL
;
3903 struct drm_gem_object
*batch_obj
;
3904 struct drm_clip_rect
*cliprects
= NULL
;
3905 struct drm_i915_gem_request
*request
= NULL
;
3907 uint64_t exec_offset
;
3909 struct intel_ring_buffer
*ring
= NULL
;
3911 ret
= i915_gem_check_is_wedged(dev
);
3915 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3920 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3921 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3923 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3924 case I915_EXEC_DEFAULT
:
3925 case I915_EXEC_RENDER
:
3926 ring
= &dev_priv
->render_ring
;
3929 if (!HAS_BSD(dev
)) {
3930 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3933 ring
= &dev_priv
->bsd_ring
;
3936 if (!HAS_BLT(dev
)) {
3937 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3940 ring
= &dev_priv
->blt_ring
;
3943 DRM_ERROR("execbuf with unknown ring: %d\n",
3944 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3948 if (args
->buffer_count
< 1) {
3949 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3952 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3953 if (object_list
== NULL
) {
3954 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3955 args
->buffer_count
);
3960 if (args
->num_cliprects
!= 0) {
3961 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3963 if (cliprects
== NULL
) {
3968 ret
= copy_from_user(cliprects
,
3969 (struct drm_clip_rect __user
*)
3970 (uintptr_t) args
->cliprects_ptr
,
3971 sizeof(*cliprects
) * args
->num_cliprects
);
3973 DRM_ERROR("copy %d cliprects failed: %d\n",
3974 args
->num_cliprects
, ret
);
3980 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3981 if (request
== NULL
) {
3986 ret
= i915_mutex_lock_interruptible(dev
);
3990 if (dev_priv
->mm
.suspended
) {
3991 mutex_unlock(&dev
->struct_mutex
);
3996 /* Look up object handles */
3997 for (i
= 0; i
< args
->buffer_count
; i
++) {
3998 struct drm_i915_gem_object
*obj_priv
;
4000 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
4001 exec_list
[i
].handle
);
4002 if (object_list
[i
] == NULL
) {
4003 DRM_ERROR("Invalid object handle %d at index %d\n",
4004 exec_list
[i
].handle
, i
);
4005 /* prevent error path from reading uninitialized data */
4006 args
->buffer_count
= i
+ 1;
4011 obj_priv
= to_intel_bo(object_list
[i
]);
4012 if (obj_priv
->in_execbuffer
) {
4013 DRM_ERROR("Object %p appears more than once in object list\n",
4015 /* prevent error path from reading uninitialized data */
4016 args
->buffer_count
= i
+ 1;
4020 obj_priv
->in_execbuffer
= true;
4023 /* Move the objects en-masse into the GTT, evicting if necessary. */
4024 ret
= i915_gem_execbuffer_reserve(dev
, file
,
4025 object_list
, exec_list
,
4026 args
->buffer_count
);
4030 /* The objects are in their final locations, apply the relocations. */
4031 ret
= i915_gem_execbuffer_relocate(dev
, file
,
4032 object_list
, exec_list
,
4033 args
->buffer_count
);
4035 if (ret
== -EFAULT
) {
4036 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
,
4039 args
->buffer_count
);
4040 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
4046 /* Set the pending read domains for the batch buffer to COMMAND */
4047 batch_obj
= object_list
[args
->buffer_count
-1];
4048 if (batch_obj
->pending_write_domain
) {
4049 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
4053 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
4055 /* Sanity check the batch buffer */
4056 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
4057 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
4059 DRM_ERROR("execbuf with invalid offset/length\n");
4063 ret
= i915_gem_execbuffer_move_to_gpu(dev
, file
, ring
,
4064 object_list
, args
->buffer_count
);
4069 for (i
= 0; i
< args
->buffer_count
; i
++) {
4070 i915_gem_object_check_coherency(object_list
[i
],
4071 exec_list
[i
].handle
);
4076 i915_gem_dump_object(batch_obj
,
4082 /* Check for any pending flips. As we only maintain a flip queue depth
4083 * of 1, we can simply insert a WAIT for the next display flip prior
4084 * to executing the batch and avoid stalling the CPU.
4087 for (i
= 0; i
< args
->buffer_count
; i
++) {
4088 if (object_list
[i
]->write_domain
)
4089 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
4092 int plane
, flip_mask
;
4094 for (plane
= 0; flips
>> plane
; plane
++) {
4095 if (((flips
>> plane
) & 1) == 0)
4099 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
4101 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
4103 ret
= intel_ring_begin(ring
, 2);
4107 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
4108 intel_ring_emit(ring
, MI_NOOP
);
4109 intel_ring_advance(ring
);
4113 /* Exec the batchbuffer */
4114 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
4116 DRM_ERROR("dispatch failed %d\n", ret
);
4120 for (i
= 0; i
< args
->buffer_count
; i
++) {
4121 struct drm_gem_object
*obj
= object_list
[i
];
4123 obj
->read_domains
= obj
->pending_read_domains
;
4124 obj
->write_domain
= obj
->pending_write_domain
;
4126 i915_gem_object_move_to_active(obj
, ring
);
4127 if (obj
->write_domain
) {
4128 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4129 obj_priv
->dirty
= 1;
4130 list_move_tail(&obj_priv
->gpu_write_list
,
4131 &ring
->gpu_write_list
);
4132 intel_mark_busy(dev
, obj
);
4135 trace_i915_gem_object_change_domain(obj
,
4141 * Ensure that the commands in the batch buffer are
4142 * finished before the interrupt fires
4144 i915_retire_commands(dev
, ring
);
4146 if (i915_add_request(dev
, file
, request
, ring
))
4147 i915_gem_next_request_seqno(dev
, ring
);
4152 for (i
= 0; i
< args
->buffer_count
; i
++) {
4153 if (object_list
[i
] == NULL
)
4156 to_intel_bo(object_list
[i
])->in_execbuffer
= false;
4157 drm_gem_object_unreference(object_list
[i
]);
4160 mutex_unlock(&dev
->struct_mutex
);
4163 drm_free_large(object_list
);
4171 * Legacy execbuffer just creates an exec2 list from the original exec object
4172 * list array and passes it to the real function.
4175 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4176 struct drm_file
*file_priv
)
4178 struct drm_i915_gem_execbuffer
*args
= data
;
4179 struct drm_i915_gem_execbuffer2 exec2
;
4180 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4181 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4185 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4186 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4189 if (args
->buffer_count
< 1) {
4190 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4194 /* Copy in the exec list from userland */
4195 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4196 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4197 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4198 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4199 args
->buffer_count
);
4200 drm_free_large(exec_list
);
4201 drm_free_large(exec2_list
);
4204 ret
= copy_from_user(exec_list
,
4205 (struct drm_i915_relocation_entry __user
*)
4206 (uintptr_t) args
->buffers_ptr
,
4207 sizeof(*exec_list
) * args
->buffer_count
);
4209 DRM_ERROR("copy %d exec entries failed %d\n",
4210 args
->buffer_count
, ret
);
4211 drm_free_large(exec_list
);
4212 drm_free_large(exec2_list
);
4216 for (i
= 0; i
< args
->buffer_count
; i
++) {
4217 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4218 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4219 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4220 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4221 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4222 if (INTEL_INFO(dev
)->gen
< 4)
4223 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4225 exec2_list
[i
].flags
= 0;
4228 exec2
.buffers_ptr
= args
->buffers_ptr
;
4229 exec2
.buffer_count
= args
->buffer_count
;
4230 exec2
.batch_start_offset
= args
->batch_start_offset
;
4231 exec2
.batch_len
= args
->batch_len
;
4232 exec2
.DR1
= args
->DR1
;
4233 exec2
.DR4
= args
->DR4
;
4234 exec2
.num_cliprects
= args
->num_cliprects
;
4235 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4236 exec2
.flags
= I915_EXEC_RENDER
;
4238 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4240 /* Copy the new buffer offsets back to the user's exec list. */
4241 for (i
= 0; i
< args
->buffer_count
; i
++)
4242 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4243 /* ... and back out to userspace */
4244 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4245 (uintptr_t) args
->buffers_ptr
,
4247 sizeof(*exec_list
) * args
->buffer_count
);
4250 DRM_ERROR("failed to copy %d exec entries "
4251 "back to user (%d)\n",
4252 args
->buffer_count
, ret
);
4256 drm_free_large(exec_list
);
4257 drm_free_large(exec2_list
);
4262 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4263 struct drm_file
*file_priv
)
4265 struct drm_i915_gem_execbuffer2
*args
= data
;
4266 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4270 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4271 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4274 if (args
->buffer_count
< 1) {
4275 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4279 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4280 if (exec2_list
== NULL
) {
4281 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4282 args
->buffer_count
);
4285 ret
= copy_from_user(exec2_list
,
4286 (struct drm_i915_relocation_entry __user
*)
4287 (uintptr_t) args
->buffers_ptr
,
4288 sizeof(*exec2_list
) * args
->buffer_count
);
4290 DRM_ERROR("copy %d exec entries failed %d\n",
4291 args
->buffer_count
, ret
);
4292 drm_free_large(exec2_list
);
4296 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4298 /* Copy the new buffer offsets back to the user's exec list. */
4299 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4300 (uintptr_t) args
->buffers_ptr
,
4302 sizeof(*exec2_list
) * args
->buffer_count
);
4305 DRM_ERROR("failed to copy %d exec entries "
4306 "back to user (%d)\n",
4307 args
->buffer_count
, ret
);
4311 drm_free_large(exec2_list
);
4316 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
4317 bool map_and_fenceable
)
4319 struct drm_device
*dev
= obj
->dev
;
4320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4321 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4324 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4325 BUG_ON(map_and_fenceable
&& !map_and_fenceable
);
4326 WARN_ON(i915_verify_lists(dev
));
4328 if (obj_priv
->gtt_space
!= NULL
) {
4329 if ((alignment
&& obj_priv
->gtt_offset
& (alignment
- 1)) ||
4330 (map_and_fenceable
&& !obj_priv
->map_and_fenceable
)) {
4331 WARN(obj_priv
->pin_count
,
4332 "bo is already pinned with incorrect alignment:"
4333 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
4334 " obj->map_and_fenceable=%d\n",
4335 obj_priv
->gtt_offset
, alignment
,
4337 obj_priv
->map_and_fenceable
);
4338 ret
= i915_gem_object_unbind(obj
);
4344 if (obj_priv
->gtt_space
== NULL
) {
4345 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
4351 if (obj_priv
->pin_count
++ == 0) {
4352 i915_gem_info_add_pin(dev_priv
, obj_priv
, map_and_fenceable
);
4353 if (!obj_priv
->active
)
4354 list_move_tail(&obj_priv
->mm_list
,
4355 &dev_priv
->mm
.pinned_list
);
4357 BUG_ON(!obj_priv
->pin_mappable
&& map_and_fenceable
);
4359 WARN_ON(i915_verify_lists(dev
));
4364 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4366 struct drm_device
*dev
= obj
->dev
;
4367 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4368 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4370 WARN_ON(i915_verify_lists(dev
));
4371 BUG_ON(obj_priv
->pin_count
== 0);
4372 BUG_ON(obj_priv
->gtt_space
== NULL
);
4374 if (--obj_priv
->pin_count
== 0) {
4375 if (!obj_priv
->active
)
4376 list_move_tail(&obj_priv
->mm_list
,
4377 &dev_priv
->mm
.inactive_list
);
4378 i915_gem_info_remove_pin(dev_priv
, obj_priv
);
4380 WARN_ON(i915_verify_lists(dev
));
4384 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4385 struct drm_file
*file_priv
)
4387 struct drm_i915_gem_pin
*args
= data
;
4388 struct drm_gem_object
*obj
;
4389 struct drm_i915_gem_object
*obj_priv
;
4392 ret
= i915_mutex_lock_interruptible(dev
);
4396 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4401 obj_priv
= to_intel_bo(obj
);
4403 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4404 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4409 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4410 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4416 obj_priv
->user_pin_count
++;
4417 obj_priv
->pin_filp
= file_priv
;
4418 if (obj_priv
->user_pin_count
== 1) {
4419 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
4424 /* XXX - flush the CPU caches for pinned objects
4425 * as the X server doesn't manage domains yet
4427 i915_gem_object_flush_cpu_write_domain(obj
);
4428 args
->offset
= obj_priv
->gtt_offset
;
4430 drm_gem_object_unreference(obj
);
4432 mutex_unlock(&dev
->struct_mutex
);
4437 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4438 struct drm_file
*file_priv
)
4440 struct drm_i915_gem_pin
*args
= data
;
4441 struct drm_gem_object
*obj
;
4442 struct drm_i915_gem_object
*obj_priv
;
4445 ret
= i915_mutex_lock_interruptible(dev
);
4449 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4454 obj_priv
= to_intel_bo(obj
);
4456 if (obj_priv
->pin_filp
!= file_priv
) {
4457 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4462 obj_priv
->user_pin_count
--;
4463 if (obj_priv
->user_pin_count
== 0) {
4464 obj_priv
->pin_filp
= NULL
;
4465 i915_gem_object_unpin(obj
);
4469 drm_gem_object_unreference(obj
);
4471 mutex_unlock(&dev
->struct_mutex
);
4476 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4477 struct drm_file
*file_priv
)
4479 struct drm_i915_gem_busy
*args
= data
;
4480 struct drm_gem_object
*obj
;
4481 struct drm_i915_gem_object
*obj_priv
;
4484 ret
= i915_mutex_lock_interruptible(dev
);
4488 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4493 obj_priv
= to_intel_bo(obj
);
4495 /* Count all active objects as busy, even if they are currently not used
4496 * by the gpu. Users of this interface expect objects to eventually
4497 * become non-busy without any further actions, therefore emit any
4498 * necessary flushes here.
4500 args
->busy
= obj_priv
->active
;
4502 /* Unconditionally flush objects, even when the gpu still uses this
4503 * object. Userspace calling this function indicates that it wants to
4504 * use this buffer rather sooner than later, so issuing the required
4505 * flush earlier is beneficial.
4507 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4508 i915_gem_flush_ring(dev
, file_priv
,
4510 0, obj
->write_domain
);
4512 /* Update the active list for the hardware's current position.
4513 * Otherwise this only updates on a delayed timer or when irqs
4514 * are actually unmasked, and our working set ends up being
4515 * larger than required.
4517 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4519 args
->busy
= obj_priv
->active
;
4522 drm_gem_object_unreference(obj
);
4524 mutex_unlock(&dev
->struct_mutex
);
4529 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4530 struct drm_file
*file_priv
)
4532 return i915_gem_ring_throttle(dev
, file_priv
);
4536 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4537 struct drm_file
*file_priv
)
4539 struct drm_i915_gem_madvise
*args
= data
;
4540 struct drm_gem_object
*obj
;
4541 struct drm_i915_gem_object
*obj_priv
;
4544 switch (args
->madv
) {
4545 case I915_MADV_DONTNEED
:
4546 case I915_MADV_WILLNEED
:
4552 ret
= i915_mutex_lock_interruptible(dev
);
4556 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4561 obj_priv
= to_intel_bo(obj
);
4563 if (obj_priv
->pin_count
) {
4568 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4569 obj_priv
->madv
= args
->madv
;
4571 /* if the object is no longer bound, discard its backing storage */
4572 if (i915_gem_object_is_purgeable(obj_priv
) &&
4573 obj_priv
->gtt_space
== NULL
)
4574 i915_gem_object_truncate(obj
);
4576 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4579 drm_gem_object_unreference(obj
);
4581 mutex_unlock(&dev
->struct_mutex
);
4585 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4589 struct drm_i915_gem_object
*obj
;
4591 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4595 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4600 i915_gem_info_add_obj(dev_priv
, size
);
4602 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4603 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4605 obj
->agp_type
= AGP_USER_MEMORY
;
4606 obj
->base
.driver_private
= NULL
;
4607 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4608 INIT_LIST_HEAD(&obj
->mm_list
);
4609 INIT_LIST_HEAD(&obj
->ring_list
);
4610 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4611 obj
->madv
= I915_MADV_WILLNEED
;
4612 /* Avoid an unnecessary call to unbind on the first bind. */
4613 obj
->map_and_fenceable
= true;
4618 int i915_gem_init_object(struct drm_gem_object
*obj
)
4625 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4627 struct drm_device
*dev
= obj
->dev
;
4628 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4629 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4632 ret
= i915_gem_object_unbind(obj
);
4633 if (ret
== -ERESTARTSYS
) {
4634 list_move(&obj_priv
->mm_list
,
4635 &dev_priv
->mm
.deferred_free_list
);
4639 if (obj
->map_list
.map
)
4640 i915_gem_free_mmap_offset(obj
);
4642 drm_gem_object_release(obj
);
4643 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4645 kfree(obj_priv
->page_cpu_valid
);
4646 kfree(obj_priv
->bit_17
);
4650 void i915_gem_free_object(struct drm_gem_object
*obj
)
4652 struct drm_device
*dev
= obj
->dev
;
4653 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4655 trace_i915_gem_object_destroy(obj
);
4657 while (obj_priv
->pin_count
> 0)
4658 i915_gem_object_unpin(obj
);
4660 if (obj_priv
->phys_obj
)
4661 i915_gem_detach_phys_object(dev
, obj
);
4663 i915_gem_free_object_tail(obj
);
4667 i915_gem_idle(struct drm_device
*dev
)
4669 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4672 mutex_lock(&dev
->struct_mutex
);
4674 if (dev_priv
->mm
.suspended
) {
4675 mutex_unlock(&dev
->struct_mutex
);
4679 ret
= i915_gpu_idle(dev
);
4681 mutex_unlock(&dev
->struct_mutex
);
4685 /* Under UMS, be paranoid and evict. */
4686 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4687 ret
= i915_gem_evict_inactive(dev
, false);
4689 mutex_unlock(&dev
->struct_mutex
);
4694 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4695 * We need to replace this with a semaphore, or something.
4696 * And not confound mm.suspended!
4698 dev_priv
->mm
.suspended
= 1;
4699 del_timer_sync(&dev_priv
->hangcheck_timer
);
4701 i915_kernel_lost_context(dev
);
4702 i915_gem_cleanup_ringbuffer(dev
);
4704 mutex_unlock(&dev
->struct_mutex
);
4706 /* Cancel the retire work handler, which should be idle now. */
4707 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4713 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4714 * over cache flushing.
4717 i915_gem_init_pipe_control(struct drm_device
*dev
)
4719 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4720 struct drm_gem_object
*obj
;
4721 struct drm_i915_gem_object
*obj_priv
;
4724 obj
= i915_gem_alloc_object(dev
, 4096);
4726 DRM_ERROR("Failed to allocate seqno page\n");
4730 obj_priv
= to_intel_bo(obj
);
4731 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4733 ret
= i915_gem_object_pin(obj
, 4096, true);
4737 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4738 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4739 if (dev_priv
->seqno_page
== NULL
)
4742 dev_priv
->seqno_obj
= obj
;
4743 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4748 i915_gem_object_unpin(obj
);
4750 drm_gem_object_unreference(obj
);
4757 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4759 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4760 struct drm_gem_object
*obj
;
4761 struct drm_i915_gem_object
*obj_priv
;
4763 obj
= dev_priv
->seqno_obj
;
4764 obj_priv
= to_intel_bo(obj
);
4765 kunmap(obj_priv
->pages
[0]);
4766 i915_gem_object_unpin(obj
);
4767 drm_gem_object_unreference(obj
);
4768 dev_priv
->seqno_obj
= NULL
;
4770 dev_priv
->seqno_page
= NULL
;
4774 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4776 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4779 if (HAS_PIPE_CONTROL(dev
)) {
4780 ret
= i915_gem_init_pipe_control(dev
);
4785 ret
= intel_init_render_ring_buffer(dev
);
4787 goto cleanup_pipe_control
;
4790 ret
= intel_init_bsd_ring_buffer(dev
);
4792 goto cleanup_render_ring
;
4796 ret
= intel_init_blt_ring_buffer(dev
);
4798 goto cleanup_bsd_ring
;
4801 dev_priv
->next_seqno
= 1;
4806 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4807 cleanup_render_ring
:
4808 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4809 cleanup_pipe_control
:
4810 if (HAS_PIPE_CONTROL(dev
))
4811 i915_gem_cleanup_pipe_control(dev
);
4816 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4818 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4820 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4821 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4822 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4823 if (HAS_PIPE_CONTROL(dev
))
4824 i915_gem_cleanup_pipe_control(dev
);
4828 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4829 struct drm_file
*file_priv
)
4831 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4834 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4837 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4838 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4839 atomic_set(&dev_priv
->mm
.wedged
, 0);
4842 mutex_lock(&dev
->struct_mutex
);
4843 dev_priv
->mm
.suspended
= 0;
4845 ret
= i915_gem_init_ringbuffer(dev
);
4847 mutex_unlock(&dev
->struct_mutex
);
4851 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4852 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4853 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4854 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4855 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4856 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4857 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4858 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4859 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4860 mutex_unlock(&dev
->struct_mutex
);
4862 ret
= drm_irq_install(dev
);
4864 goto cleanup_ringbuffer
;
4869 mutex_lock(&dev
->struct_mutex
);
4870 i915_gem_cleanup_ringbuffer(dev
);
4871 dev_priv
->mm
.suspended
= 1;
4872 mutex_unlock(&dev
->struct_mutex
);
4878 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4879 struct drm_file
*file_priv
)
4881 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4884 drm_irq_uninstall(dev
);
4885 return i915_gem_idle(dev
);
4889 i915_gem_lastclose(struct drm_device
*dev
)
4893 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4896 ret
= i915_gem_idle(dev
);
4898 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4902 init_ring_lists(struct intel_ring_buffer
*ring
)
4904 INIT_LIST_HEAD(&ring
->active_list
);
4905 INIT_LIST_HEAD(&ring
->request_list
);
4906 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4910 i915_gem_load(struct drm_device
*dev
)
4913 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4915 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4916 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4917 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4918 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4919 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4920 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4921 init_ring_lists(&dev_priv
->render_ring
);
4922 init_ring_lists(&dev_priv
->bsd_ring
);
4923 init_ring_lists(&dev_priv
->blt_ring
);
4924 for (i
= 0; i
< 16; i
++)
4925 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4926 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4927 i915_gem_retire_work_handler
);
4928 init_completion(&dev_priv
->error_completion
);
4930 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4932 u32 tmp
= I915_READ(MI_ARB_STATE
);
4933 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4934 /* arb state is a masked write, so set bit + bit in mask */
4935 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4936 I915_WRITE(MI_ARB_STATE
, tmp
);
4940 /* Old X drivers will take 0-2 for front, back, depth buffers */
4941 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4942 dev_priv
->fence_reg_start
= 3;
4944 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4945 dev_priv
->num_fence_regs
= 16;
4947 dev_priv
->num_fence_regs
= 8;
4949 /* Initialize fence registers to zero */
4950 switch (INTEL_INFO(dev
)->gen
) {
4952 for (i
= 0; i
< 16; i
++)
4953 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4957 for (i
= 0; i
< 16; i
++)
4958 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4961 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4962 for (i
= 0; i
< 8; i
++)
4963 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4965 for (i
= 0; i
< 8; i
++)
4966 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4969 i915_gem_detect_bit_6_swizzle(dev
);
4970 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4972 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4973 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4974 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4978 * Create a physically contiguous memory object for this object
4979 * e.g. for cursor + overlay regs
4981 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4982 int id
, int size
, int align
)
4984 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4985 struct drm_i915_gem_phys_object
*phys_obj
;
4988 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4991 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4997 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4998 if (!phys_obj
->handle
) {
5003 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
5006 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
5014 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
5016 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5017 struct drm_i915_gem_phys_object
*phys_obj
;
5019 if (!dev_priv
->mm
.phys_objs
[id
- 1])
5022 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5023 if (phys_obj
->cur_obj
) {
5024 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
5028 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
5030 drm_pci_free(dev
, phys_obj
->handle
);
5032 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
5035 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
5039 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
5040 i915_gem_free_phys_object(dev
, i
);
5043 void i915_gem_detach_phys_object(struct drm_device
*dev
,
5044 struct drm_gem_object
*obj
)
5046 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
5047 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5052 if (!obj_priv
->phys_obj
)
5054 vaddr
= obj_priv
->phys_obj
->handle
->vaddr
;
5056 page_count
= obj
->size
/ PAGE_SIZE
;
5058 for (i
= 0; i
< page_count
; i
++) {
5059 struct page
*page
= read_cache_page_gfp(mapping
, i
,
5060 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
5061 if (!IS_ERR(page
)) {
5062 char *dst
= kmap_atomic(page
);
5063 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
5066 drm_clflush_pages(&page
, 1);
5068 set_page_dirty(page
);
5069 mark_page_accessed(page
);
5070 page_cache_release(page
);
5073 drm_agp_chipset_flush(dev
);
5075 obj_priv
->phys_obj
->cur_obj
= NULL
;
5076 obj_priv
->phys_obj
= NULL
;
5080 i915_gem_attach_phys_object(struct drm_device
*dev
,
5081 struct drm_gem_object
*obj
,
5085 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
5086 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5087 struct drm_i915_gem_object
*obj_priv
;
5092 if (id
> I915_MAX_PHYS_OBJECT
)
5095 obj_priv
= to_intel_bo(obj
);
5097 if (obj_priv
->phys_obj
) {
5098 if (obj_priv
->phys_obj
->id
== id
)
5100 i915_gem_detach_phys_object(dev
, obj
);
5103 /* create a new object */
5104 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
5105 ret
= i915_gem_init_phys_object(dev
, id
,
5108 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
5113 /* bind to the object */
5114 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5115 obj_priv
->phys_obj
->cur_obj
= obj
;
5117 page_count
= obj
->size
/ PAGE_SIZE
;
5119 for (i
= 0; i
< page_count
; i
++) {
5123 page
= read_cache_page_gfp(mapping
, i
,
5124 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
5126 return PTR_ERR(page
);
5128 src
= kmap_atomic(page
);
5129 dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
5130 memcpy(dst
, src
, PAGE_SIZE
);
5133 mark_page_accessed(page
);
5134 page_cache_release(page
);
5141 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5142 struct drm_i915_gem_pwrite
*args
,
5143 struct drm_file
*file_priv
)
5145 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5146 void *vaddr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5147 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5149 DRM_DEBUG_DRIVER("vaddr %p, %lld\n", vaddr
, args
->size
);
5151 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
5152 unsigned long unwritten
;
5154 /* The physical object once assigned is fixed for the lifetime
5155 * of the obj, so we can safely drop the lock and continue
5158 mutex_unlock(&dev
->struct_mutex
);
5159 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
5160 mutex_lock(&dev
->struct_mutex
);
5165 drm_agp_chipset_flush(dev
);
5169 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5171 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5173 /* Clean up our request list when the client is going away, so that
5174 * later retire_requests won't dereference our soon-to-be-gone
5177 spin_lock(&file_priv
->mm
.lock
);
5178 while (!list_empty(&file_priv
->mm
.request_list
)) {
5179 struct drm_i915_gem_request
*request
;
5181 request
= list_first_entry(&file_priv
->mm
.request_list
,
5182 struct drm_i915_gem_request
,
5184 list_del(&request
->client_list
);
5185 request
->file_priv
= NULL
;
5187 spin_unlock(&file_priv
->mm
.lock
);
5191 i915_gpu_is_active(struct drm_device
*dev
)
5193 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5196 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5197 list_empty(&dev_priv
->mm
.active_list
);
5199 return !lists_empty
;
5203 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
5207 struct drm_i915_private
*dev_priv
=
5208 container_of(shrinker
,
5209 struct drm_i915_private
,
5210 mm
.inactive_shrinker
);
5211 struct drm_device
*dev
= dev_priv
->dev
;
5212 struct drm_i915_gem_object
*obj
, *next
;
5215 if (!mutex_trylock(&dev
->struct_mutex
))
5218 /* "fast-path" to count number of available objects */
5219 if (nr_to_scan
== 0) {
5221 list_for_each_entry(obj
,
5222 &dev_priv
->mm
.inactive_list
,
5225 mutex_unlock(&dev
->struct_mutex
);
5226 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
5230 /* first scan for clean buffers */
5231 i915_gem_retire_requests(dev
);
5233 list_for_each_entry_safe(obj
, next
,
5234 &dev_priv
->mm
.inactive_list
,
5236 if (i915_gem_object_is_purgeable(obj
)) {
5237 i915_gem_object_unbind(&obj
->base
);
5238 if (--nr_to_scan
== 0)
5243 /* second pass, evict/count anything still on the inactive list */
5245 list_for_each_entry_safe(obj
, next
,
5246 &dev_priv
->mm
.inactive_list
,
5249 i915_gem_object_unbind(&obj
->base
);
5255 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
5257 * We are desperate for pages, so as a last resort, wait
5258 * for the GPU to finish and discard whatever we can.
5259 * This has a dramatic impact to reduce the number of
5260 * OOM-killer events whilst running the GPU aggressively.
5262 if (i915_gpu_idle(dev
) == 0)
5265 mutex_unlock(&dev
->struct_mutex
);
5266 return cnt
/ 100 * sysctl_vfs_cache_pressure
;