2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
51 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
52 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
53 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file_priv
);
57 static LIST_HEAD(shrink_list
);
58 static DEFINE_SPINLOCK(shrink_list_lock
);
60 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
63 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
66 (start
& (PAGE_SIZE
- 1)) != 0 ||
67 (end
& (PAGE_SIZE
- 1)) != 0) {
71 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
74 dev
->gtt_total
= (uint32_t) (end
- start
);
80 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
81 struct drm_file
*file_priv
)
83 struct drm_i915_gem_init
*args
= data
;
86 mutex_lock(&dev
->struct_mutex
);
87 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
88 mutex_unlock(&dev
->struct_mutex
);
94 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
95 struct drm_file
*file_priv
)
97 struct drm_i915_gem_get_aperture
*args
= data
;
99 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
102 args
->aper_size
= dev
->gtt_total
;
103 args
->aper_available_size
= (args
->aper_size
-
104 atomic_read(&dev
->pin_memory
));
111 * Creates a new mm object and returns a handle to it.
114 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
115 struct drm_file
*file_priv
)
117 struct drm_i915_gem_create
*args
= data
;
118 struct drm_gem_object
*obj
;
122 args
->size
= roundup(args
->size
, PAGE_SIZE
);
124 /* Allocate the new object */
125 obj
= i915_gem_alloc_object(dev
, args
->size
);
129 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
130 drm_gem_object_handle_unreference_unlocked(obj
);
135 args
->handle
= handle
;
141 fast_shmem_read(struct page
**pages
,
142 loff_t page_base
, int page_offset
,
149 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
152 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
153 kunmap_atomic(vaddr
, KM_USER0
);
161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
163 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
164 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
166 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
167 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
171 slow_shmem_copy(struct page
*dst_page
,
173 struct page
*src_page
,
177 char *dst_vaddr
, *src_vaddr
;
179 dst_vaddr
= kmap(dst_page
);
180 src_vaddr
= kmap(src_page
);
182 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
189 slow_shmem_bit17_copy(struct page
*gpu_page
,
191 struct page
*cpu_page
,
196 char *gpu_vaddr
, *cpu_vaddr
;
198 /* Use the unswizzled path if this page isn't affected. */
199 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
201 return slow_shmem_copy(cpu_page
, cpu_offset
,
202 gpu_page
, gpu_offset
, length
);
204 return slow_shmem_copy(gpu_page
, gpu_offset
,
205 cpu_page
, cpu_offset
, length
);
208 gpu_vaddr
= kmap(gpu_page
);
209 cpu_vaddr
= kmap(cpu_page
);
211 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
212 * XORing with the other bits (A9 for Y, A9 and A10 for X)
215 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
216 int this_length
= min(cacheline_end
- gpu_offset
, length
);
217 int swizzled_gpu_offset
= gpu_offset
^ 64;
220 memcpy(cpu_vaddr
+ cpu_offset
,
221 gpu_vaddr
+ swizzled_gpu_offset
,
224 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
225 cpu_vaddr
+ cpu_offset
,
228 cpu_offset
+= this_length
;
229 gpu_offset
+= this_length
;
230 length
-= this_length
;
238 * This is the fast shmem pread path, which attempts to copy_from_user directly
239 * from the backing pages of the object to the user's address space. On a
240 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
243 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
244 struct drm_i915_gem_pread
*args
,
245 struct drm_file
*file_priv
)
247 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
249 loff_t offset
, page_base
;
250 char __user
*user_data
;
251 int page_offset
, page_length
;
254 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
257 mutex_lock(&dev
->struct_mutex
);
259 ret
= i915_gem_object_get_pages(obj
, 0);
263 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
268 obj_priv
= to_intel_bo(obj
);
269 offset
= args
->offset
;
272 /* Operation in this page
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
278 page_base
= (offset
& ~(PAGE_SIZE
-1));
279 page_offset
= offset
& (PAGE_SIZE
-1);
280 page_length
= remain
;
281 if ((page_offset
+ remain
) > PAGE_SIZE
)
282 page_length
= PAGE_SIZE
- page_offset
;
284 ret
= fast_shmem_read(obj_priv
->pages
,
285 page_base
, page_offset
,
286 user_data
, page_length
);
290 remain
-= page_length
;
291 user_data
+= page_length
;
292 offset
+= page_length
;
296 i915_gem_object_put_pages(obj
);
298 mutex_unlock(&dev
->struct_mutex
);
304 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
308 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
310 /* If we've insufficient memory to map in the pages, attempt
311 * to make some space by throwing out some old buffers.
313 if (ret
== -ENOMEM
) {
314 struct drm_device
*dev
= obj
->dev
;
316 ret
= i915_gem_evict_something(dev
, obj
->size
);
320 ret
= i915_gem_object_get_pages(obj
, 0);
327 * This is the fallback shmem pread path, which allocates temporary storage
328 * in kernel space to copy_to_user into outside of the struct_mutex, so we
329 * can copy out of the object's backing pages while holding the struct mutex
330 * and not take page faults.
333 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
334 struct drm_i915_gem_pread
*args
,
335 struct drm_file
*file_priv
)
337 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
338 struct mm_struct
*mm
= current
->mm
;
339 struct page
**user_pages
;
341 loff_t offset
, pinned_pages
, i
;
342 loff_t first_data_page
, last_data_page
, num_pages
;
343 int shmem_page_index
, shmem_page_offset
;
344 int data_page_index
, data_page_offset
;
347 uint64_t data_ptr
= args
->data_ptr
;
348 int do_bit17_swizzling
;
352 /* Pin the user pages containing the data. We can't fault while
353 * holding the struct mutex, yet we want to hold it while
354 * dereferencing the user data.
356 first_data_page
= data_ptr
/ PAGE_SIZE
;
357 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
358 num_pages
= last_data_page
- first_data_page
+ 1;
360 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
361 if (user_pages
== NULL
)
364 down_read(&mm
->mmap_sem
);
365 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
366 num_pages
, 1, 0, user_pages
, NULL
);
367 up_read(&mm
->mmap_sem
);
368 if (pinned_pages
< num_pages
) {
370 goto fail_put_user_pages
;
373 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
375 mutex_lock(&dev
->struct_mutex
);
377 ret
= i915_gem_object_get_pages_or_evict(obj
);
381 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
386 obj_priv
= to_intel_bo(obj
);
387 offset
= args
->offset
;
390 /* Operation in this page
392 * shmem_page_index = page number within shmem file
393 * shmem_page_offset = offset within page in shmem file
394 * data_page_index = page number in get_user_pages return
395 * data_page_offset = offset with data_page_index page.
396 * page_length = bytes to copy for this page
398 shmem_page_index
= offset
/ PAGE_SIZE
;
399 shmem_page_offset
= offset
& ~PAGE_MASK
;
400 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
401 data_page_offset
= data_ptr
& ~PAGE_MASK
;
403 page_length
= remain
;
404 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
405 page_length
= PAGE_SIZE
- shmem_page_offset
;
406 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
407 page_length
= PAGE_SIZE
- data_page_offset
;
409 if (do_bit17_swizzling
) {
410 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
412 user_pages
[data_page_index
],
417 slow_shmem_copy(user_pages
[data_page_index
],
419 obj_priv
->pages
[shmem_page_index
],
424 remain
-= page_length
;
425 data_ptr
+= page_length
;
426 offset
+= page_length
;
430 i915_gem_object_put_pages(obj
);
432 mutex_unlock(&dev
->struct_mutex
);
434 for (i
= 0; i
< pinned_pages
; i
++) {
435 SetPageDirty(user_pages
[i
]);
436 page_cache_release(user_pages
[i
]);
438 drm_free_large(user_pages
);
444 * Reads data from the object referenced by handle.
446 * On error, the contents of *data are undefined.
449 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
450 struct drm_file
*file_priv
)
452 struct drm_i915_gem_pread
*args
= data
;
453 struct drm_gem_object
*obj
;
454 struct drm_i915_gem_object
*obj_priv
;
457 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
460 obj_priv
= to_intel_bo(obj
);
462 /* Bounds check source.
464 * XXX: This could use review for overflow issues...
466 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
467 args
->offset
+ args
->size
> obj
->size
) {
468 drm_gem_object_unreference_unlocked(obj
);
472 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
473 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
475 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
477 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
481 drm_gem_object_unreference_unlocked(obj
);
486 /* This is the fast write path which cannot handle
487 * page faults in the source data
491 fast_user_write(struct io_mapping
*mapping
,
492 loff_t page_base
, int page_offset
,
493 char __user
*user_data
,
497 unsigned long unwritten
;
499 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
500 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
502 io_mapping_unmap_atomic(vaddr_atomic
);
508 /* Here's the write path which can sleep for
513 slow_kernel_write(struct io_mapping
*mapping
,
514 loff_t gtt_base
, int gtt_offset
,
515 struct page
*user_page
, int user_offset
,
518 char __iomem
*dst_vaddr
;
521 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
522 src_vaddr
= kmap(user_page
);
524 memcpy_toio(dst_vaddr
+ gtt_offset
,
525 src_vaddr
+ user_offset
,
529 io_mapping_unmap(dst_vaddr
);
533 fast_shmem_write(struct page
**pages
,
534 loff_t page_base
, int page_offset
,
539 unsigned long unwritten
;
541 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
544 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
545 kunmap_atomic(vaddr
, KM_USER0
);
553 * This is the fast pwrite path, where we copy the data directly from the
554 * user into the GTT, uncached.
557 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
558 struct drm_i915_gem_pwrite
*args
,
559 struct drm_file
*file_priv
)
561 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
564 loff_t offset
, page_base
;
565 char __user
*user_data
;
566 int page_offset
, page_length
;
569 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
571 if (!access_ok(VERIFY_READ
, user_data
, remain
))
575 mutex_lock(&dev
->struct_mutex
);
576 ret
= i915_gem_object_pin(obj
, 0);
578 mutex_unlock(&dev
->struct_mutex
);
581 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
585 obj_priv
= to_intel_bo(obj
);
586 offset
= obj_priv
->gtt_offset
+ args
->offset
;
589 /* Operation in this page
591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
595 page_base
= (offset
& ~(PAGE_SIZE
-1));
596 page_offset
= offset
& (PAGE_SIZE
-1);
597 page_length
= remain
;
598 if ((page_offset
+ remain
) > PAGE_SIZE
)
599 page_length
= PAGE_SIZE
- page_offset
;
601 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
602 page_offset
, user_data
, page_length
);
604 /* If we get a fault while copying data, then (presumably) our
605 * source page isn't available. Return the error and we'll
606 * retry in the slow path.
611 remain
-= page_length
;
612 user_data
+= page_length
;
613 offset
+= page_length
;
617 i915_gem_object_unpin(obj
);
618 mutex_unlock(&dev
->struct_mutex
);
624 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
625 * the memory and maps it using kmap_atomic for copying.
627 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
628 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
631 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
632 struct drm_i915_gem_pwrite
*args
,
633 struct drm_file
*file_priv
)
635 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
636 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
638 loff_t gtt_page_base
, offset
;
639 loff_t first_data_page
, last_data_page
, num_pages
;
640 loff_t pinned_pages
, i
;
641 struct page
**user_pages
;
642 struct mm_struct
*mm
= current
->mm
;
643 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
645 uint64_t data_ptr
= args
->data_ptr
;
649 /* Pin the user pages containing the data. We can't fault while
650 * holding the struct mutex, and all of the pwrite implementations
651 * want to hold it while dereferencing the user data.
653 first_data_page
= data_ptr
/ PAGE_SIZE
;
654 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
655 num_pages
= last_data_page
- first_data_page
+ 1;
657 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
658 if (user_pages
== NULL
)
661 down_read(&mm
->mmap_sem
);
662 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
663 num_pages
, 0, 0, user_pages
, NULL
);
664 up_read(&mm
->mmap_sem
);
665 if (pinned_pages
< num_pages
) {
667 goto out_unpin_pages
;
670 mutex_lock(&dev
->struct_mutex
);
671 ret
= i915_gem_object_pin(obj
, 0);
675 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
677 goto out_unpin_object
;
679 obj_priv
= to_intel_bo(obj
);
680 offset
= obj_priv
->gtt_offset
+ args
->offset
;
683 /* Operation in this page
685 * gtt_page_base = page offset within aperture
686 * gtt_page_offset = offset within page in aperture
687 * data_page_index = page number in get_user_pages return
688 * data_page_offset = offset with data_page_index page.
689 * page_length = bytes to copy for this page
691 gtt_page_base
= offset
& PAGE_MASK
;
692 gtt_page_offset
= offset
& ~PAGE_MASK
;
693 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
694 data_page_offset
= data_ptr
& ~PAGE_MASK
;
696 page_length
= remain
;
697 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
698 page_length
= PAGE_SIZE
- gtt_page_offset
;
699 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
700 page_length
= PAGE_SIZE
- data_page_offset
;
702 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
703 gtt_page_base
, gtt_page_offset
,
704 user_pages
[data_page_index
],
708 remain
-= page_length
;
709 offset
+= page_length
;
710 data_ptr
+= page_length
;
714 i915_gem_object_unpin(obj
);
716 mutex_unlock(&dev
->struct_mutex
);
718 for (i
= 0; i
< pinned_pages
; i
++)
719 page_cache_release(user_pages
[i
]);
720 drm_free_large(user_pages
);
726 * This is the fast shmem pwrite path, which attempts to directly
727 * copy_from_user into the kmapped pages backing the object.
730 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
731 struct drm_i915_gem_pwrite
*args
,
732 struct drm_file
*file_priv
)
734 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
736 loff_t offset
, page_base
;
737 char __user
*user_data
;
738 int page_offset
, page_length
;
741 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
744 mutex_lock(&dev
->struct_mutex
);
746 ret
= i915_gem_object_get_pages(obj
, 0);
750 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
754 obj_priv
= to_intel_bo(obj
);
755 offset
= args
->offset
;
759 /* Operation in this page
761 * page_base = page offset within aperture
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
765 page_base
= (offset
& ~(PAGE_SIZE
-1));
766 page_offset
= offset
& (PAGE_SIZE
-1);
767 page_length
= remain
;
768 if ((page_offset
+ remain
) > PAGE_SIZE
)
769 page_length
= PAGE_SIZE
- page_offset
;
771 ret
= fast_shmem_write(obj_priv
->pages
,
772 page_base
, page_offset
,
773 user_data
, page_length
);
777 remain
-= page_length
;
778 user_data
+= page_length
;
779 offset
+= page_length
;
783 i915_gem_object_put_pages(obj
);
785 mutex_unlock(&dev
->struct_mutex
);
791 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
792 * the memory and maps it using kmap_atomic for copying.
794 * This avoids taking mmap_sem for faulting on the user's address while the
795 * struct_mutex is held.
798 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
799 struct drm_i915_gem_pwrite
*args
,
800 struct drm_file
*file_priv
)
802 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
803 struct mm_struct
*mm
= current
->mm
;
804 struct page
**user_pages
;
806 loff_t offset
, pinned_pages
, i
;
807 loff_t first_data_page
, last_data_page
, num_pages
;
808 int shmem_page_index
, shmem_page_offset
;
809 int data_page_index
, data_page_offset
;
812 uint64_t data_ptr
= args
->data_ptr
;
813 int do_bit17_swizzling
;
817 /* Pin the user pages containing the data. We can't fault while
818 * holding the struct mutex, and all of the pwrite implementations
819 * want to hold it while dereferencing the user data.
821 first_data_page
= data_ptr
/ PAGE_SIZE
;
822 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
823 num_pages
= last_data_page
- first_data_page
+ 1;
825 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
826 if (user_pages
== NULL
)
829 down_read(&mm
->mmap_sem
);
830 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
831 num_pages
, 0, 0, user_pages
, NULL
);
832 up_read(&mm
->mmap_sem
);
833 if (pinned_pages
< num_pages
) {
835 goto fail_put_user_pages
;
838 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
840 mutex_lock(&dev
->struct_mutex
);
842 ret
= i915_gem_object_get_pages_or_evict(obj
);
846 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
850 obj_priv
= to_intel_bo(obj
);
851 offset
= args
->offset
;
855 /* Operation in this page
857 * shmem_page_index = page number within shmem file
858 * shmem_page_offset = offset within page in shmem file
859 * data_page_index = page number in get_user_pages return
860 * data_page_offset = offset with data_page_index page.
861 * page_length = bytes to copy for this page
863 shmem_page_index
= offset
/ PAGE_SIZE
;
864 shmem_page_offset
= offset
& ~PAGE_MASK
;
865 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
866 data_page_offset
= data_ptr
& ~PAGE_MASK
;
868 page_length
= remain
;
869 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
870 page_length
= PAGE_SIZE
- shmem_page_offset
;
871 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
872 page_length
= PAGE_SIZE
- data_page_offset
;
874 if (do_bit17_swizzling
) {
875 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
877 user_pages
[data_page_index
],
882 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
884 user_pages
[data_page_index
],
889 remain
-= page_length
;
890 data_ptr
+= page_length
;
891 offset
+= page_length
;
895 i915_gem_object_put_pages(obj
);
897 mutex_unlock(&dev
->struct_mutex
);
899 for (i
= 0; i
< pinned_pages
; i
++)
900 page_cache_release(user_pages
[i
]);
901 drm_free_large(user_pages
);
907 * Writes data to the object referenced by handle.
909 * On error, the contents of the buffer that were to be modified are undefined.
912 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
913 struct drm_file
*file_priv
)
915 struct drm_i915_gem_pwrite
*args
= data
;
916 struct drm_gem_object
*obj
;
917 struct drm_i915_gem_object
*obj_priv
;
920 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
923 obj_priv
= to_intel_bo(obj
);
925 /* Bounds check destination.
927 * XXX: This could use review for overflow issues...
929 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
930 args
->offset
+ args
->size
> obj
->size
) {
931 drm_gem_object_unreference_unlocked(obj
);
935 /* We can only do the GTT pwrite on untiled buffers, as otherwise
936 * it would end up going through the fenced access, and we'll get
937 * different detiling behavior between reading and writing.
938 * pread/pwrite currently are reading and writing from the CPU
939 * perspective, requiring manual detiling by the client.
941 if (obj_priv
->phys_obj
)
942 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
943 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
944 dev
->gtt_total
!= 0 &&
945 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
946 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
947 if (ret
== -EFAULT
) {
948 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
951 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
952 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
954 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
955 if (ret
== -EFAULT
) {
956 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
963 DRM_INFO("pwrite failed %d\n", ret
);
966 drm_gem_object_unreference_unlocked(obj
);
972 * Called when user space prepares to use an object with the CPU, either
973 * through the mmap ioctl's mapping or a GTT mapping.
976 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
977 struct drm_file
*file_priv
)
979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
980 struct drm_i915_gem_set_domain
*args
= data
;
981 struct drm_gem_object
*obj
;
982 struct drm_i915_gem_object
*obj_priv
;
983 uint32_t read_domains
= args
->read_domains
;
984 uint32_t write_domain
= args
->write_domain
;
987 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
990 /* Only handle setting domains to types used by the CPU. */
991 if (write_domain
& I915_GEM_GPU_DOMAINS
)
994 if (read_domains
& I915_GEM_GPU_DOMAINS
)
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
1000 if (write_domain
!= 0 && read_domains
!= write_domain
)
1003 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1006 obj_priv
= to_intel_bo(obj
);
1008 mutex_lock(&dev
->struct_mutex
);
1010 intel_mark_busy(dev
, obj
);
1013 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1014 obj
, obj
->size
, read_domains
, write_domain
);
1016 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1017 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1019 /* Update the LRU on the fence for the CPU access that's
1022 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1023 struct drm_i915_fence_reg
*reg
=
1024 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1025 list_move_tail(®
->lru_list
,
1026 &dev_priv
->mm
.fence_list
);
1029 /* Silently promote "you're not bound, there was nothing to do"
1030 * to success, since the client was just asking us to
1031 * make sure everything was done.
1036 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1039 drm_gem_object_unreference(obj
);
1040 mutex_unlock(&dev
->struct_mutex
);
1045 * Called when user space has done writes to this buffer
1048 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1049 struct drm_file
*file_priv
)
1051 struct drm_i915_gem_sw_finish
*args
= data
;
1052 struct drm_gem_object
*obj
;
1053 struct drm_i915_gem_object
*obj_priv
;
1056 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1059 mutex_lock(&dev
->struct_mutex
);
1060 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1062 mutex_unlock(&dev
->struct_mutex
);
1067 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1068 __func__
, args
->handle
, obj
, obj
->size
);
1070 obj_priv
= to_intel_bo(obj
);
1072 /* Pinned buffers may be scanout, so flush the cache */
1073 if (obj_priv
->pin_count
)
1074 i915_gem_object_flush_cpu_write_domain(obj
);
1076 drm_gem_object_unreference(obj
);
1077 mutex_unlock(&dev
->struct_mutex
);
1082 * Maps the contents of an object, returning the address it is mapped
1085 * While the mapping holds a reference on the contents of the object, it doesn't
1086 * imply a ref on the object itself.
1089 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
)
1092 struct drm_i915_gem_mmap
*args
= data
;
1093 struct drm_gem_object
*obj
;
1097 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1100 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1104 offset
= args
->offset
;
1106 down_write(¤t
->mm
->mmap_sem
);
1107 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1108 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1110 up_write(¤t
->mm
->mmap_sem
);
1111 drm_gem_object_unreference_unlocked(obj
);
1112 if (IS_ERR((void *)addr
))
1115 args
->addr_ptr
= (uint64_t) addr
;
1121 * i915_gem_fault - fault a page into the GTT
1122 * vma: VMA in question
1125 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126 * from userspace. The fault handler takes care of binding the object to
1127 * the GTT (if needed), allocating and programming a fence register (again,
1128 * only if needed based on whether the old reg is still valid or the object
1129 * is tiled) and inserting a new PTE into the faulting process.
1131 * Note that the faulting process may involve evicting existing objects
1132 * from the GTT and/or fence registers to make room. So performance may
1133 * suffer if the GTT working set is large or there are few fence registers
1136 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1138 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1139 struct drm_device
*dev
= obj
->dev
;
1140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1141 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1142 pgoff_t page_offset
;
1145 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1147 /* We don't use vmf->pgoff since that has the fake offset */
1148 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1151 /* Now bind it into the GTT if needed */
1152 mutex_lock(&dev
->struct_mutex
);
1153 if (!obj_priv
->gtt_space
) {
1154 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1158 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1160 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1165 /* Need a new fence register? */
1166 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1167 ret
= i915_gem_object_get_fence_reg(obj
);
1172 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1175 /* Finally, remap it using the new GTT offset */
1176 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1178 mutex_unlock(&dev
->struct_mutex
);
1183 return VM_FAULT_NOPAGE
;
1186 return VM_FAULT_OOM
;
1188 return VM_FAULT_SIGBUS
;
1193 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194 * @obj: obj in question
1196 * GEM memory mapping works by handing back to userspace a fake mmap offset
1197 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1198 * up the object based on the offset and sets up the various memory mapping
1201 * This routine allocates and attaches a fake offset for @obj.
1204 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1206 struct drm_device
*dev
= obj
->dev
;
1207 struct drm_gem_mm
*mm
= dev
->mm_private
;
1208 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1209 struct drm_map_list
*list
;
1210 struct drm_local_map
*map
;
1213 /* Set the object up for mmap'ing */
1214 list
= &obj
->map_list
;
1215 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1220 map
->type
= _DRM_GEM
;
1221 map
->size
= obj
->size
;
1224 /* Get a DRM GEM mmap offset allocated... */
1225 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1226 obj
->size
/ PAGE_SIZE
, 0, 0);
1227 if (!list
->file_offset_node
) {
1228 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1233 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1234 obj
->size
/ PAGE_SIZE
, 0);
1235 if (!list
->file_offset_node
) {
1240 list
->hash
.key
= list
->file_offset_node
->start
;
1241 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1242 DRM_ERROR("failed to add to map hash\n");
1247 /* By now we should be all set, any drm_mmap request on the offset
1248 * below will get to our mmap & fault handler */
1249 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1254 drm_mm_put_block(list
->file_offset_node
);
1262 * i915_gem_release_mmap - remove physical page mappings
1263 * @obj: obj in question
1265 * Preserve the reservation of the mmapping with the DRM core code, but
1266 * relinquish ownership of the pages back to the system.
1268 * It is vital that we remove the page mapping if we have mapped a tiled
1269 * object through the GTT and then lose the fence register due to
1270 * resource pressure. Similarly if the object has been moved out of the
1271 * aperture, than pages mapped into userspace must be revoked. Removing the
1272 * mapping will then trigger a page fault on the next user access, allowing
1273 * fixup by i915_gem_fault().
1276 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1278 struct drm_device
*dev
= obj
->dev
;
1279 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1281 if (dev
->dev_mapping
)
1282 unmap_mapping_range(dev
->dev_mapping
,
1283 obj_priv
->mmap_offset
, obj
->size
, 1);
1287 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1289 struct drm_device
*dev
= obj
->dev
;
1290 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1291 struct drm_gem_mm
*mm
= dev
->mm_private
;
1292 struct drm_map_list
*list
;
1294 list
= &obj
->map_list
;
1295 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1297 if (list
->file_offset_node
) {
1298 drm_mm_put_block(list
->file_offset_node
);
1299 list
->file_offset_node
= NULL
;
1307 obj_priv
->mmap_offset
= 0;
1311 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312 * @obj: object to check
1314 * Return the required GTT alignment for an object, taking into account
1315 * potential fence register mapping if needed.
1318 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1320 struct drm_device
*dev
= obj
->dev
;
1321 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1325 * Minimum alignment is 4k (GTT page size), but might be greater
1326 * if a fence register is needed for the object.
1328 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1332 * Previous chips need to be aligned to the size of the smallest
1333 * fence register that can contain the object.
1340 for (i
= start
; i
< obj
->size
; i
<<= 1)
1347 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1349 * @data: GTT mapping ioctl data
1350 * @file_priv: GEM object info
1352 * Simply returns the fake offset to userspace so it can mmap it.
1353 * The mmap call will end up in drm_gem_mmap(), which will set things
1354 * up so we can get faults in the handler above.
1356 * The fault handler will take care of binding the object into the GTT
1357 * (since it may have been evicted to make room for something), allocating
1358 * a fence register, and mapping the appropriate aperture address into
1362 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1363 struct drm_file
*file_priv
)
1365 struct drm_i915_gem_mmap_gtt
*args
= data
;
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 struct drm_gem_object
*obj
;
1368 struct drm_i915_gem_object
*obj_priv
;
1371 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1374 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1378 mutex_lock(&dev
->struct_mutex
);
1380 obj_priv
= to_intel_bo(obj
);
1382 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1383 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384 drm_gem_object_unreference(obj
);
1385 mutex_unlock(&dev
->struct_mutex
);
1390 if (!obj_priv
->mmap_offset
) {
1391 ret
= i915_gem_create_mmap_offset(obj
);
1393 drm_gem_object_unreference(obj
);
1394 mutex_unlock(&dev
->struct_mutex
);
1399 args
->offset
= obj_priv
->mmap_offset
;
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1405 if (!obj_priv
->agp_mem
) {
1406 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1408 drm_gem_object_unreference(obj
);
1409 mutex_unlock(&dev
->struct_mutex
);
1412 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1415 drm_gem_object_unreference(obj
);
1416 mutex_unlock(&dev
->struct_mutex
);
1422 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1424 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1425 int page_count
= obj
->size
/ PAGE_SIZE
;
1428 BUG_ON(obj_priv
->pages_refcount
== 0);
1429 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1431 if (--obj_priv
->pages_refcount
!= 0)
1434 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1435 i915_gem_object_save_bit_17_swizzle(obj
);
1437 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1438 obj_priv
->dirty
= 0;
1440 for (i
= 0; i
< page_count
; i
++) {
1441 if (obj_priv
->dirty
)
1442 set_page_dirty(obj_priv
->pages
[i
]);
1444 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1445 mark_page_accessed(obj_priv
->pages
[i
]);
1447 page_cache_release(obj_priv
->pages
[i
]);
1449 obj_priv
->dirty
= 0;
1451 drm_free_large(obj_priv
->pages
);
1452 obj_priv
->pages
= NULL
;
1456 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
,
1457 struct intel_ring_buffer
*ring
)
1459 struct drm_device
*dev
= obj
->dev
;
1460 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1461 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1462 BUG_ON(ring
== NULL
);
1463 obj_priv
->ring
= ring
;
1465 /* Add a reference if we're newly entering the active list. */
1466 if (!obj_priv
->active
) {
1467 drm_gem_object_reference(obj
);
1468 obj_priv
->active
= 1;
1470 /* Move from whatever list we were on to the tail of execution. */
1471 spin_lock(&dev_priv
->mm
.active_list_lock
);
1472 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1473 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1474 obj_priv
->last_rendering_seqno
= seqno
;
1478 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1480 struct drm_device
*dev
= obj
->dev
;
1481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1482 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1484 BUG_ON(!obj_priv
->active
);
1485 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1486 obj_priv
->last_rendering_seqno
= 0;
1489 /* Immediately discard the backing storage */
1491 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1493 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1494 struct inode
*inode
;
1496 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1497 if (inode
->i_op
->truncate
)
1498 inode
->i_op
->truncate (inode
);
1500 obj_priv
->madv
= __I915_MADV_PURGED
;
1504 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1506 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1510 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1512 struct drm_device
*dev
= obj
->dev
;
1513 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1514 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1516 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1517 if (obj_priv
->pin_count
!= 0)
1518 list_del_init(&obj_priv
->list
);
1520 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1522 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1524 obj_priv
->last_rendering_seqno
= 0;
1525 obj_priv
->ring
= NULL
;
1526 if (obj_priv
->active
) {
1527 obj_priv
->active
= 0;
1528 drm_gem_object_unreference(obj
);
1530 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1534 i915_gem_process_flushing_list(struct drm_device
*dev
,
1535 uint32_t flush_domains
, uint32_t seqno
,
1536 struct intel_ring_buffer
*ring
)
1538 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1539 struct drm_i915_gem_object
*obj_priv
, *next
;
1541 list_for_each_entry_safe(obj_priv
, next
,
1542 &dev_priv
->mm
.gpu_write_list
,
1544 struct drm_gem_object
*obj
= &obj_priv
->base
;
1546 if ((obj
->write_domain
& flush_domains
) ==
1547 obj
->write_domain
&&
1548 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1549 uint32_t old_write_domain
= obj
->write_domain
;
1551 obj
->write_domain
= 0;
1552 list_del_init(&obj_priv
->gpu_write_list
);
1553 i915_gem_object_move_to_active(obj
, seqno
, ring
);
1555 /* update the fence lru list */
1556 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1557 struct drm_i915_fence_reg
*reg
=
1558 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1559 list_move_tail(®
->lru_list
,
1560 &dev_priv
->mm
.fence_list
);
1563 trace_i915_gem_object_change_domain(obj
,
1571 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1572 uint32_t flush_domains
, struct intel_ring_buffer
*ring
)
1574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1575 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1576 struct drm_i915_gem_request
*request
;
1580 if (file_priv
!= NULL
)
1581 i915_file_priv
= file_priv
->driver_priv
;
1583 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1584 if (request
== NULL
)
1587 seqno
= ring
->add_request(dev
, ring
, file_priv
, flush_domains
);
1589 request
->seqno
= seqno
;
1590 request
->ring
= ring
;
1591 request
->emitted_jiffies
= jiffies
;
1592 was_empty
= list_empty(&ring
->request_list
);
1593 list_add_tail(&request
->list
, &ring
->request_list
);
1595 if (i915_file_priv
) {
1596 list_add_tail(&request
->client_list
,
1597 &i915_file_priv
->mm
.request_list
);
1599 INIT_LIST_HEAD(&request
->client_list
);
1602 /* Associate any objects on the flushing list matching the write
1603 * domain we're flushing with our flush.
1605 if (flush_domains
!= 0)
1606 i915_gem_process_flushing_list(dev
, flush_domains
, seqno
, ring
);
1608 if (!dev_priv
->mm
.suspended
) {
1609 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1611 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1617 * Command execution barrier
1619 * Ensures that all commands in the ring are finished
1620 * before signalling the CPU
1623 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1625 uint32_t flush_domains
= 0;
1627 /* The sampler always gets flushed on i965 (sigh) */
1629 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1631 ring
->flush(dev
, ring
,
1632 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1633 return flush_domains
;
1637 * Moves buffers associated only with the given active seqno from the active
1638 * to inactive list, potentially freeing them.
1641 i915_gem_retire_request(struct drm_device
*dev
,
1642 struct drm_i915_gem_request
*request
)
1644 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1646 trace_i915_gem_request_retire(dev
, request
->seqno
);
1648 /* Move any buffers on the active list that are no longer referenced
1649 * by the ringbuffer to the flushing/inactive lists as appropriate.
1651 spin_lock(&dev_priv
->mm
.active_list_lock
);
1652 while (!list_empty(&request
->ring
->active_list
)) {
1653 struct drm_gem_object
*obj
;
1654 struct drm_i915_gem_object
*obj_priv
;
1656 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1657 struct drm_i915_gem_object
,
1659 obj
= &obj_priv
->base
;
1661 /* If the seqno being retired doesn't match the oldest in the
1662 * list, then the oldest in the list must still be newer than
1665 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1669 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670 __func__
, request
->seqno
, obj
);
1673 if (obj
->write_domain
!= 0)
1674 i915_gem_object_move_to_flushing(obj
);
1676 /* Take a reference on the object so it won't be
1677 * freed while the spinlock is held. The list
1678 * protection for this spinlock is safe when breaking
1679 * the lock like this since the next thing we do
1680 * is just get the head of the list again.
1682 drm_gem_object_reference(obj
);
1683 i915_gem_object_move_to_inactive(obj
);
1684 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1685 drm_gem_object_unreference(obj
);
1686 spin_lock(&dev_priv
->mm
.active_list_lock
);
1690 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1694 * Returns true if seq1 is later than seq2.
1697 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1699 return (int32_t)(seq1
- seq2
) >= 0;
1703 i915_get_gem_seqno(struct drm_device
*dev
,
1704 struct intel_ring_buffer
*ring
)
1706 return ring
->get_gem_seqno(dev
, ring
);
1710 * This function clears the request list as sequence numbers are passed.
1713 i915_gem_retire_requests(struct drm_device
*dev
,
1714 struct intel_ring_buffer
*ring
)
1716 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1719 if (!ring
->status_page
.page_addr
1720 || list_empty(&ring
->request_list
))
1723 seqno
= i915_get_gem_seqno(dev
, ring
);
1725 while (!list_empty(&ring
->request_list
)) {
1726 struct drm_i915_gem_request
*request
;
1727 uint32_t retiring_seqno
;
1729 request
= list_first_entry(&ring
->request_list
,
1730 struct drm_i915_gem_request
,
1732 retiring_seqno
= request
->seqno
;
1734 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1735 atomic_read(&dev_priv
->mm
.wedged
)) {
1736 i915_gem_retire_request(dev
, request
);
1738 list_del(&request
->list
);
1739 list_del(&request
->client_list
);
1745 if (unlikely (dev_priv
->trace_irq_seqno
&&
1746 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1748 ring
->user_irq_put(dev
, ring
);
1749 dev_priv
->trace_irq_seqno
= 0;
1754 i915_gem_retire_work_handler(struct work_struct
*work
)
1756 drm_i915_private_t
*dev_priv
;
1757 struct drm_device
*dev
;
1759 dev_priv
= container_of(work
, drm_i915_private_t
,
1760 mm
.retire_work
.work
);
1761 dev
= dev_priv
->dev
;
1763 mutex_lock(&dev
->struct_mutex
);
1764 i915_gem_retire_requests(dev
, &dev_priv
->render_ring
);
1767 i915_gem_retire_requests(dev
, &dev_priv
->bsd_ring
);
1769 if (!dev_priv
->mm
.suspended
&&
1770 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1772 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1773 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1774 mutex_unlock(&dev
->struct_mutex
);
1778 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1779 int interruptible
, struct intel_ring_buffer
*ring
)
1781 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1787 if (atomic_read(&dev_priv
->mm
.wedged
))
1790 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1791 if (HAS_PCH_SPLIT(dev
))
1792 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1794 ier
= I915_READ(IER
);
1796 DRM_ERROR("something (likely vbetool) disabled "
1797 "interrupts, re-enabling\n");
1798 i915_driver_irq_preinstall(dev
);
1799 i915_driver_irq_postinstall(dev
);
1802 trace_i915_gem_request_wait_begin(dev
, seqno
);
1804 ring
->waiting_gem_seqno
= seqno
;
1805 ring
->user_irq_get(dev
, ring
);
1807 ret
= wait_event_interruptible(ring
->irq_queue
,
1809 ring
->get_gem_seqno(dev
, ring
), seqno
)
1810 || atomic_read(&dev_priv
->mm
.wedged
));
1812 wait_event(ring
->irq_queue
,
1814 ring
->get_gem_seqno(dev
, ring
), seqno
)
1815 || atomic_read(&dev_priv
->mm
.wedged
));
1817 ring
->user_irq_put(dev
, ring
);
1818 ring
->waiting_gem_seqno
= 0;
1820 trace_i915_gem_request_wait_end(dev
, seqno
);
1822 if (atomic_read(&dev_priv
->mm
.wedged
))
1825 if (ret
&& ret
!= -ERESTARTSYS
)
1826 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1827 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
));
1829 /* Directly dispatch request retiring. While we have the work queue
1830 * to handle this, the waiter on a request often wants an associated
1831 * buffer to have made it to the inactive list, and we would need
1832 * a separate wait queue to handle that.
1835 i915_gem_retire_requests(dev
, ring
);
1841 * Waits for a sequence number to be signaled, and cleans up the
1842 * request and object lists appropriately for that event.
1845 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1846 struct intel_ring_buffer
*ring
)
1848 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1852 i915_gem_flush(struct drm_device
*dev
,
1853 uint32_t invalidate_domains
,
1854 uint32_t flush_domains
)
1856 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1857 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1858 drm_agp_chipset_flush(dev
);
1859 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1864 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1870 i915_gem_flush_ring(struct drm_device
*dev
,
1871 uint32_t invalidate_domains
,
1872 uint32_t flush_domains
,
1873 struct intel_ring_buffer
*ring
)
1875 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1876 drm_agp_chipset_flush(dev
);
1877 ring
->flush(dev
, ring
,
1883 * Ensures that all rendering to the object has completed and the object is
1884 * safe to unbind from the GTT or access from the CPU.
1887 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1889 struct drm_device
*dev
= obj
->dev
;
1890 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1893 /* This function only exists to support waiting for existing rendering,
1894 * not for emitting required flushes.
1896 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1898 /* If there is rendering queued on the buffer being evicted, wait for
1901 if (obj_priv
->active
) {
1903 DRM_INFO("%s: object %p wait for seqno %08x\n",
1904 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1906 ret
= i915_wait_request(dev
,
1907 obj_priv
->last_rendering_seqno
, obj_priv
->ring
);
1916 * Unbinds an object from the GTT aperture.
1919 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1921 struct drm_device
*dev
= obj
->dev
;
1922 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1923 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1927 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1928 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1930 if (obj_priv
->gtt_space
== NULL
)
1933 if (obj_priv
->pin_count
!= 0) {
1934 DRM_ERROR("Attempting to unbind pinned buffer\n");
1938 /* blow away mappings if mapped through GTT */
1939 i915_gem_release_mmap(obj
);
1941 /* Move the object to the CPU domain to ensure that
1942 * any possible CPU writes while it's not in the GTT
1943 * are flushed when we go to remap it. This will
1944 * also ensure that all pending GPU writes are finished
1947 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1949 if (ret
!= -ERESTARTSYS
)
1950 DRM_ERROR("set_domain failed: %d\n", ret
);
1954 BUG_ON(obj_priv
->active
);
1956 /* release the fence reg _after_ flushing */
1957 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1958 i915_gem_clear_fence_reg(obj
);
1960 if (obj_priv
->agp_mem
!= NULL
) {
1961 drm_unbind_agp(obj_priv
->agp_mem
);
1962 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1963 obj_priv
->agp_mem
= NULL
;
1966 i915_gem_object_put_pages(obj
);
1967 BUG_ON(obj_priv
->pages_refcount
);
1969 if (obj_priv
->gtt_space
) {
1970 atomic_dec(&dev
->gtt_count
);
1971 atomic_sub(obj
->size
, &dev
->gtt_memory
);
1973 drm_mm_put_block(obj_priv
->gtt_space
);
1974 obj_priv
->gtt_space
= NULL
;
1977 /* Remove ourselves from the LRU list if present. */
1978 spin_lock(&dev_priv
->mm
.active_list_lock
);
1979 if (!list_empty(&obj_priv
->list
))
1980 list_del_init(&obj_priv
->list
);
1981 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1983 if (i915_gem_object_is_purgeable(obj_priv
))
1984 i915_gem_object_truncate(obj
);
1986 trace_i915_gem_object_unbind(obj
);
1991 static struct drm_gem_object
*
1992 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
1994 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1995 struct drm_i915_gem_object
*obj_priv
;
1996 struct drm_gem_object
*best
= NULL
;
1997 struct drm_gem_object
*first
= NULL
;
1999 /* Try to find the smallest clean object */
2000 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2001 struct drm_gem_object
*obj
= &obj_priv
->base
;
2002 if (obj
->size
>= min_size
) {
2003 if ((!obj_priv
->dirty
||
2004 i915_gem_object_is_purgeable(obj_priv
)) &&
2005 (!best
|| obj
->size
< best
->size
)) {
2007 if (best
->size
== min_size
)
2015 return best
? best
: first
;
2019 i915_gpu_idle(struct drm_device
*dev
)
2021 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2023 uint32_t seqno1
, seqno2
;
2026 spin_lock(&dev_priv
->mm
.active_list_lock
);
2027 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2028 list_empty(&dev_priv
->render_ring
.active_list
) &&
2030 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2031 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2036 /* Flush everything onto the inactive list. */
2037 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2038 seqno1
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2039 &dev_priv
->render_ring
);
2042 ret
= i915_wait_request(dev
, seqno1
, &dev_priv
->render_ring
);
2045 seqno2
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2046 &dev_priv
->bsd_ring
);
2050 ret
= i915_wait_request(dev
, seqno2
, &dev_priv
->bsd_ring
);
2060 i915_gem_evict_everything(struct drm_device
*dev
)
2062 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2066 spin_lock(&dev_priv
->mm
.active_list_lock
);
2067 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2068 list_empty(&dev_priv
->mm
.flushing_list
) &&
2069 list_empty(&dev_priv
->render_ring
.active_list
) &&
2071 || list_empty(&dev_priv
->bsd_ring
.active_list
)));
2072 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2077 /* Flush everything (on to the inactive lists) and evict */
2078 ret
= i915_gpu_idle(dev
);
2082 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2084 ret
= i915_gem_evict_from_inactive_list(dev
);
2088 spin_lock(&dev_priv
->mm
.active_list_lock
);
2089 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2090 list_empty(&dev_priv
->mm
.flushing_list
) &&
2091 list_empty(&dev_priv
->render_ring
.active_list
) &&
2093 || list_empty(&dev_priv
->bsd_ring
.active_list
)));
2094 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2095 BUG_ON(!lists_empty
);
2101 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2103 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2104 struct drm_gem_object
*obj
;
2107 struct intel_ring_buffer
*render_ring
= &dev_priv
->render_ring
;
2108 struct intel_ring_buffer
*bsd_ring
= &dev_priv
->bsd_ring
;
2110 i915_gem_retire_requests(dev
, render_ring
);
2113 i915_gem_retire_requests(dev
, bsd_ring
);
2115 /* If there's an inactive buffer available now, grab it
2118 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2120 struct drm_i915_gem_object
*obj_priv
;
2123 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2125 obj_priv
= to_intel_bo(obj
);
2126 BUG_ON(obj_priv
->pin_count
!= 0);
2127 BUG_ON(obj_priv
->active
);
2129 /* Wait on the rendering and unbind the buffer. */
2130 return i915_gem_object_unbind(obj
);
2133 /* If we didn't get anything, but the ring is still processing
2134 * things, wait for the next to finish and hopefully leave us
2135 * a buffer to evict.
2137 if (!list_empty(&render_ring
->request_list
)) {
2138 struct drm_i915_gem_request
*request
;
2140 request
= list_first_entry(&render_ring
->request_list
,
2141 struct drm_i915_gem_request
,
2144 ret
= i915_wait_request(dev
,
2145 request
->seqno
, request
->ring
);
2152 if (HAS_BSD(dev
) && !list_empty(&bsd_ring
->request_list
)) {
2153 struct drm_i915_gem_request
*request
;
2155 request
= list_first_entry(&bsd_ring
->request_list
,
2156 struct drm_i915_gem_request
,
2159 ret
= i915_wait_request(dev
,
2160 request
->seqno
, request
->ring
);
2167 /* If we didn't have anything on the request list but there
2168 * are buffers awaiting a flush, emit one and try again.
2169 * When we wait on it, those buffers waiting for that flush
2170 * will get moved to inactive.
2172 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2173 struct drm_i915_gem_object
*obj_priv
;
2175 /* Find an object that we can immediately reuse */
2176 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2177 obj
= &obj_priv
->base
;
2178 if (obj
->size
>= min_size
)
2187 i915_gem_flush_ring(dev
,
2191 seqno
= i915_add_request(dev
, NULL
,
2200 /* If we didn't do any of the above, there's no single buffer
2201 * large enough to swap out for the new one, so just evict
2202 * everything and start again. (This should be rare.)
2204 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2205 return i915_gem_evict_from_inactive_list(dev
);
2207 return i915_gem_evict_everything(dev
);
2212 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2215 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2217 struct address_space
*mapping
;
2218 struct inode
*inode
;
2221 BUG_ON(obj_priv
->pages_refcount
2222 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2224 if (obj_priv
->pages_refcount
++ != 0)
2227 /* Get the list of pages out of our struct file. They'll be pinned
2228 * at this point until we release them.
2230 page_count
= obj
->size
/ PAGE_SIZE
;
2231 BUG_ON(obj_priv
->pages
!= NULL
);
2232 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2233 if (obj_priv
->pages
== NULL
) {
2234 obj_priv
->pages_refcount
--;
2238 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2239 mapping
= inode
->i_mapping
;
2240 for (i
= 0; i
< page_count
; i
++) {
2241 page
= read_cache_page_gfp(mapping
, i
,
2249 obj_priv
->pages
[i
] = page
;
2252 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2253 i915_gem_object_do_bit_17_swizzle(obj
);
2259 page_cache_release(obj_priv
->pages
[i
]);
2261 drm_free_large(obj_priv
->pages
);
2262 obj_priv
->pages
= NULL
;
2263 obj_priv
->pages_refcount
--;
2264 return PTR_ERR(page
);
2267 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2269 struct drm_gem_object
*obj
= reg
->obj
;
2270 struct drm_device
*dev
= obj
->dev
;
2271 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2272 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2273 int regnum
= obj_priv
->fence_reg
;
2276 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2278 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2279 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2280 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2282 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2283 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2284 val
|= I965_FENCE_REG_VALID
;
2286 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2289 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2291 struct drm_gem_object
*obj
= reg
->obj
;
2292 struct drm_device
*dev
= obj
->dev
;
2293 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2294 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2295 int regnum
= obj_priv
->fence_reg
;
2298 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2300 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2301 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2302 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2303 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2304 val
|= I965_FENCE_REG_VALID
;
2306 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2309 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2311 struct drm_gem_object
*obj
= reg
->obj
;
2312 struct drm_device
*dev
= obj
->dev
;
2313 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2314 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2315 int regnum
= obj_priv
->fence_reg
;
2317 uint32_t fence_reg
, val
;
2320 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2321 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2322 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2323 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2327 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2328 HAS_128_BYTE_Y_TILING(dev
))
2333 /* Note: pitch better be a power of two tile widths */
2334 pitch_val
= obj_priv
->stride
/ tile_width
;
2335 pitch_val
= ffs(pitch_val
) - 1;
2337 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2338 HAS_128_BYTE_Y_TILING(dev
))
2339 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2341 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2343 val
= obj_priv
->gtt_offset
;
2344 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2345 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2346 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2347 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2348 val
|= I830_FENCE_REG_VALID
;
2351 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2353 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2354 I915_WRITE(fence_reg
, val
);
2357 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2359 struct drm_gem_object
*obj
= reg
->obj
;
2360 struct drm_device
*dev
= obj
->dev
;
2361 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2362 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2363 int regnum
= obj_priv
->fence_reg
;
2366 uint32_t fence_size_bits
;
2368 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2369 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2370 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2371 __func__
, obj_priv
->gtt_offset
);
2375 pitch_val
= obj_priv
->stride
/ 128;
2376 pitch_val
= ffs(pitch_val
) - 1;
2377 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2379 val
= obj_priv
->gtt_offset
;
2380 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2381 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2382 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2383 WARN_ON(fence_size_bits
& ~0x00000f00);
2384 val
|= fence_size_bits
;
2385 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2386 val
|= I830_FENCE_REG_VALID
;
2388 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2391 static int i915_find_fence_reg(struct drm_device
*dev
)
2393 struct drm_i915_fence_reg
*reg
= NULL
;
2394 struct drm_i915_gem_object
*obj_priv
= NULL
;
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2396 struct drm_gem_object
*obj
= NULL
;
2399 /* First try to find a free reg */
2401 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2402 reg
= &dev_priv
->fence_regs
[i
];
2406 obj_priv
= to_intel_bo(reg
->obj
);
2407 if (!obj_priv
->pin_count
)
2414 /* None available, try to steal one or wait for a user to finish */
2415 i
= I915_FENCE_REG_NONE
;
2416 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2419 obj_priv
= to_intel_bo(obj
);
2421 if (obj_priv
->pin_count
)
2425 i
= obj_priv
->fence_reg
;
2429 BUG_ON(i
== I915_FENCE_REG_NONE
);
2431 /* We only have a reference on obj from the active list. put_fence_reg
2432 * might drop that one, causing a use-after-free in it. So hold a
2433 * private reference to obj like the other callers of put_fence_reg
2434 * (set_tiling ioctl) do. */
2435 drm_gem_object_reference(obj
);
2436 ret
= i915_gem_object_put_fence_reg(obj
);
2437 drm_gem_object_unreference(obj
);
2445 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2446 * @obj: object to map through a fence reg
2448 * When mapping objects through the GTT, userspace wants to be able to write
2449 * to them without having to worry about swizzling if the object is tiled.
2451 * This function walks the fence regs looking for a free one for @obj,
2452 * stealing one if it can't find any.
2454 * It then sets up the reg based on the object's properties: address, pitch
2455 * and tiling format.
2458 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2460 struct drm_device
*dev
= obj
->dev
;
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2463 struct drm_i915_fence_reg
*reg
= NULL
;
2466 /* Just update our place in the LRU if our fence is getting used. */
2467 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2468 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2469 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2473 switch (obj_priv
->tiling_mode
) {
2474 case I915_TILING_NONE
:
2475 WARN(1, "allocating a fence for non-tiled object?\n");
2478 if (!obj_priv
->stride
)
2480 WARN((obj_priv
->stride
& (512 - 1)),
2481 "object 0x%08x is X tiled but has non-512B pitch\n",
2482 obj_priv
->gtt_offset
);
2485 if (!obj_priv
->stride
)
2487 WARN((obj_priv
->stride
& (128 - 1)),
2488 "object 0x%08x is Y tiled but has non-128B pitch\n",
2489 obj_priv
->gtt_offset
);
2493 ret
= i915_find_fence_reg(dev
);
2497 obj_priv
->fence_reg
= ret
;
2498 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2499 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2504 sandybridge_write_fence_reg(reg
);
2505 else if (IS_I965G(dev
))
2506 i965_write_fence_reg(reg
);
2507 else if (IS_I9XX(dev
))
2508 i915_write_fence_reg(reg
);
2510 i830_write_fence_reg(reg
);
2512 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2513 obj_priv
->tiling_mode
);
2519 * i915_gem_clear_fence_reg - clear out fence register info
2520 * @obj: object to clear
2522 * Zeroes out the fence register itself and clears out the associated
2523 * data structures in dev_priv and obj_priv.
2526 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2528 struct drm_device
*dev
= obj
->dev
;
2529 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2530 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2531 struct drm_i915_fence_reg
*reg
=
2532 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2535 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2536 (obj_priv
->fence_reg
* 8), 0);
2537 } else if (IS_I965G(dev
)) {
2538 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2542 if (obj_priv
->fence_reg
< 8)
2543 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2545 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2548 I915_WRITE(fence_reg
, 0);
2552 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2553 list_del_init(®
->lru_list
);
2557 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2558 * to the buffer to finish, and then resets the fence register.
2559 * @obj: tiled object holding a fence register.
2561 * Zeroes out the fence register itself and clears out the associated
2562 * data structures in dev_priv and obj_priv.
2565 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2567 struct drm_device
*dev
= obj
->dev
;
2568 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2570 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2573 /* If we've changed tiling, GTT-mappings of the object
2574 * need to re-fault to ensure that the correct fence register
2575 * setup is in place.
2577 i915_gem_release_mmap(obj
);
2579 /* On the i915, GPU access to tiled buffers is via a fence,
2580 * therefore we must wait for any outstanding access to complete
2581 * before clearing the fence.
2583 if (!IS_I965G(dev
)) {
2586 i915_gem_object_flush_gpu_write_domain(obj
);
2587 ret
= i915_gem_object_wait_rendering(obj
);
2592 i915_gem_object_flush_gtt_write_domain(obj
);
2593 i915_gem_clear_fence_reg (obj
);
2599 * Finds free space in the GTT aperture and binds the object there.
2602 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2604 struct drm_device
*dev
= obj
->dev
;
2605 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2606 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2607 struct drm_mm_node
*free_space
;
2608 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2611 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2612 DRM_ERROR("Attempting to bind a purgeable object\n");
2617 alignment
= i915_gem_get_gtt_alignment(obj
);
2618 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2619 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2623 /* If the object is bigger than the entire aperture, reject it early
2624 * before evicting everything in a vain attempt to find space.
2626 if (obj
->size
> dev
->gtt_total
) {
2627 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2632 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2633 obj
->size
, alignment
, 0);
2634 if (free_space
!= NULL
) {
2635 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2637 if (obj_priv
->gtt_space
!= NULL
) {
2638 obj_priv
->gtt_space
->private = obj
;
2639 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2642 if (obj_priv
->gtt_space
== NULL
) {
2643 /* If the gtt is empty and we're still having trouble
2644 * fitting our object in, we're out of memory.
2647 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2649 ret
= i915_gem_evict_something(dev
, obj
->size
);
2657 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2658 obj
->size
, obj_priv
->gtt_offset
);
2660 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2662 drm_mm_put_block(obj_priv
->gtt_space
);
2663 obj_priv
->gtt_space
= NULL
;
2665 if (ret
== -ENOMEM
) {
2666 /* first try to clear up some space from the GTT */
2667 ret
= i915_gem_evict_something(dev
, obj
->size
);
2669 /* now try to shrink everyone else */
2684 /* Create an AGP memory structure pointing at our pages, and bind it
2687 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2689 obj
->size
>> PAGE_SHIFT
,
2690 obj_priv
->gtt_offset
,
2691 obj_priv
->agp_type
);
2692 if (obj_priv
->agp_mem
== NULL
) {
2693 i915_gem_object_put_pages(obj
);
2694 drm_mm_put_block(obj_priv
->gtt_space
);
2695 obj_priv
->gtt_space
= NULL
;
2697 ret
= i915_gem_evict_something(dev
, obj
->size
);
2703 atomic_inc(&dev
->gtt_count
);
2704 atomic_add(obj
->size
, &dev
->gtt_memory
);
2706 /* Assert that the object is not currently in any GPU domain. As it
2707 * wasn't in the GTT, there shouldn't be any way it could have been in
2710 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2711 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2713 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2719 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2721 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2723 /* If we don't have a page list set up, then we're not pinned
2724 * to GPU, and we can ignore the cache flush because it'll happen
2725 * again at bind time.
2727 if (obj_priv
->pages
== NULL
)
2730 trace_i915_gem_object_clflush(obj
);
2732 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2735 /** Flushes any GPU write domain for the object if it's dirty. */
2737 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2739 struct drm_device
*dev
= obj
->dev
;
2740 uint32_t old_write_domain
;
2741 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2743 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2746 /* Queue the GPU write cache flushing we need. */
2747 old_write_domain
= obj
->write_domain
;
2748 i915_gem_flush(dev
, 0, obj
->write_domain
);
2749 (void) i915_add_request(dev
, NULL
, obj
->write_domain
, obj_priv
->ring
);
2750 BUG_ON(obj
->write_domain
);
2752 trace_i915_gem_object_change_domain(obj
,
2757 /** Flushes the GTT write domain for the object if it's dirty. */
2759 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2761 uint32_t old_write_domain
;
2763 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2766 /* No actual flushing is required for the GTT write domain. Writes
2767 * to it immediately go to main memory as far as we know, so there's
2768 * no chipset flush. It also doesn't land in render cache.
2770 old_write_domain
= obj
->write_domain
;
2771 obj
->write_domain
= 0;
2773 trace_i915_gem_object_change_domain(obj
,
2778 /** Flushes the CPU write domain for the object if it's dirty. */
2780 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2782 struct drm_device
*dev
= obj
->dev
;
2783 uint32_t old_write_domain
;
2785 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2788 i915_gem_clflush_object(obj
);
2789 drm_agp_chipset_flush(dev
);
2790 old_write_domain
= obj
->write_domain
;
2791 obj
->write_domain
= 0;
2793 trace_i915_gem_object_change_domain(obj
,
2799 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2801 switch (obj
->write_domain
) {
2802 case I915_GEM_DOMAIN_GTT
:
2803 i915_gem_object_flush_gtt_write_domain(obj
);
2805 case I915_GEM_DOMAIN_CPU
:
2806 i915_gem_object_flush_cpu_write_domain(obj
);
2809 i915_gem_object_flush_gpu_write_domain(obj
);
2815 * Moves a single object to the GTT read, and possibly write domain.
2817 * This function returns when the move is complete, including waiting on
2821 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2823 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2824 uint32_t old_write_domain
, old_read_domains
;
2827 /* Not valid to be called on unbound objects. */
2828 if (obj_priv
->gtt_space
== NULL
)
2831 i915_gem_object_flush_gpu_write_domain(obj
);
2832 /* Wait on any GPU rendering and flushing to occur. */
2833 ret
= i915_gem_object_wait_rendering(obj
);
2837 old_write_domain
= obj
->write_domain
;
2838 old_read_domains
= obj
->read_domains
;
2840 /* If we're writing through the GTT domain, then CPU and GPU caches
2841 * will need to be invalidated at next use.
2844 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2846 i915_gem_object_flush_cpu_write_domain(obj
);
2848 /* It should now be out of any other write domains, and we can update
2849 * the domain values for our changes.
2851 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2852 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2854 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2855 obj_priv
->dirty
= 1;
2858 trace_i915_gem_object_change_domain(obj
,
2866 * Prepare buffer for display plane. Use uninterruptible for possible flush
2867 * wait, as in modesetting process we're not supposed to be interrupted.
2870 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2872 struct drm_device
*dev
= obj
->dev
;
2873 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2874 uint32_t old_write_domain
, old_read_domains
;
2877 /* Not valid to be called on unbound objects. */
2878 if (obj_priv
->gtt_space
== NULL
)
2881 i915_gem_object_flush_gpu_write_domain(obj
);
2883 /* Wait on any GPU rendering and flushing to occur. */
2884 if (obj_priv
->active
) {
2886 DRM_INFO("%s: object %p wait for seqno %08x\n",
2887 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2889 ret
= i915_do_wait_request(dev
,
2890 obj_priv
->last_rendering_seqno
,
2897 i915_gem_object_flush_cpu_write_domain(obj
);
2899 old_write_domain
= obj
->write_domain
;
2900 old_read_domains
= obj
->read_domains
;
2902 /* It should now be out of any other write domains, and we can update
2903 * the domain values for our changes.
2905 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2906 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2907 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2908 obj_priv
->dirty
= 1;
2910 trace_i915_gem_object_change_domain(obj
,
2918 * Moves a single object to the CPU read, and possibly write domain.
2920 * This function returns when the move is complete, including waiting on
2924 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2926 uint32_t old_write_domain
, old_read_domains
;
2929 i915_gem_object_flush_gpu_write_domain(obj
);
2930 /* Wait on any GPU rendering and flushing to occur. */
2931 ret
= i915_gem_object_wait_rendering(obj
);
2935 i915_gem_object_flush_gtt_write_domain(obj
);
2937 /* If we have a partially-valid cache of the object in the CPU,
2938 * finish invalidating it and free the per-page flags.
2940 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2942 old_write_domain
= obj
->write_domain
;
2943 old_read_domains
= obj
->read_domains
;
2945 /* Flush the CPU cache if it's still invalid. */
2946 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2947 i915_gem_clflush_object(obj
);
2949 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2952 /* It should now be out of any other write domains, and we can update
2953 * the domain values for our changes.
2955 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2957 /* If we're writing through the CPU, then the GPU read domains will
2958 * need to be invalidated at next use.
2961 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2962 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2965 trace_i915_gem_object_change_domain(obj
,
2973 * Set the next domain for the specified object. This
2974 * may not actually perform the necessary flushing/invaliding though,
2975 * as that may want to be batched with other set_domain operations
2977 * This is (we hope) the only really tricky part of gem. The goal
2978 * is fairly simple -- track which caches hold bits of the object
2979 * and make sure they remain coherent. A few concrete examples may
2980 * help to explain how it works. For shorthand, we use the notation
2981 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2982 * a pair of read and write domain masks.
2984 * Case 1: the batch buffer
2990 * 5. Unmapped from GTT
2993 * Let's take these a step at a time
2996 * Pages allocated from the kernel may still have
2997 * cache contents, so we set them to (CPU, CPU) always.
2998 * 2. Written by CPU (using pwrite)
2999 * The pwrite function calls set_domain (CPU, CPU) and
3000 * this function does nothing (as nothing changes)
3002 * This function asserts that the object is not
3003 * currently in any GPU-based read or write domains
3005 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3006 * As write_domain is zero, this function adds in the
3007 * current read domains (CPU+COMMAND, 0).
3008 * flush_domains is set to CPU.
3009 * invalidate_domains is set to COMMAND
3010 * clflush is run to get data out of the CPU caches
3011 * then i915_dev_set_domain calls i915_gem_flush to
3012 * emit an MI_FLUSH and drm_agp_chipset_flush
3013 * 5. Unmapped from GTT
3014 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3015 * flush_domains and invalidate_domains end up both zero
3016 * so no flushing/invalidating happens
3020 * Case 2: The shared render buffer
3024 * 3. Read/written by GPU
3025 * 4. set_domain to (CPU,CPU)
3026 * 5. Read/written by CPU
3027 * 6. Read/written by GPU
3030 * Same as last example, (CPU, CPU)
3032 * Nothing changes (assertions find that it is not in the GPU)
3033 * 3. Read/written by GPU
3034 * execbuffer calls set_domain (RENDER, RENDER)
3035 * flush_domains gets CPU
3036 * invalidate_domains gets GPU
3038 * MI_FLUSH and drm_agp_chipset_flush
3039 * 4. set_domain (CPU, CPU)
3040 * flush_domains gets GPU
3041 * invalidate_domains gets CPU
3042 * wait_rendering (obj) to make sure all drawing is complete.
3043 * This will include an MI_FLUSH to get the data from GPU
3045 * clflush (obj) to invalidate the CPU cache
3046 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3047 * 5. Read/written by CPU
3048 * cache lines are loaded and dirtied
3049 * 6. Read written by GPU
3050 * Same as last GPU access
3052 * Case 3: The constant buffer
3057 * 4. Updated (written) by CPU again
3066 * flush_domains = CPU
3067 * invalidate_domains = RENDER
3070 * drm_agp_chipset_flush
3071 * 4. Updated (written) by CPU again
3073 * flush_domains = 0 (no previous write domain)
3074 * invalidate_domains = 0 (no new read domains)
3077 * flush_domains = CPU
3078 * invalidate_domains = RENDER
3081 * drm_agp_chipset_flush
3084 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3086 struct drm_device
*dev
= obj
->dev
;
3087 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3088 uint32_t invalidate_domains
= 0;
3089 uint32_t flush_domains
= 0;
3090 uint32_t old_read_domains
;
3092 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3093 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3095 intel_mark_busy(dev
, obj
);
3098 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3100 obj
->read_domains
, obj
->pending_read_domains
,
3101 obj
->write_domain
, obj
->pending_write_domain
);
3104 * If the object isn't moving to a new write domain,
3105 * let the object stay in multiple read domains
3107 if (obj
->pending_write_domain
== 0)
3108 obj
->pending_read_domains
|= obj
->read_domains
;
3110 obj_priv
->dirty
= 1;
3113 * Flush the current write domain if
3114 * the new read domains don't match. Invalidate
3115 * any read domains which differ from the old
3118 if (obj
->write_domain
&&
3119 obj
->write_domain
!= obj
->pending_read_domains
) {
3120 flush_domains
|= obj
->write_domain
;
3121 invalidate_domains
|=
3122 obj
->pending_read_domains
& ~obj
->write_domain
;
3125 * Invalidate any read caches which may have
3126 * stale data. That is, any new read domains.
3128 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3129 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3131 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3132 __func__
, flush_domains
, invalidate_domains
);
3134 i915_gem_clflush_object(obj
);
3137 old_read_domains
= obj
->read_domains
;
3139 /* The actual obj->write_domain will be updated with
3140 * pending_write_domain after we emit the accumulated flush for all
3141 * of our domain changes in execbuffers (which clears objects'
3142 * write_domains). So if we have a current write domain that we
3143 * aren't changing, set pending_write_domain to that.
3145 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3146 obj
->pending_write_domain
= obj
->write_domain
;
3147 obj
->read_domains
= obj
->pending_read_domains
;
3149 dev
->invalidate_domains
|= invalidate_domains
;
3150 dev
->flush_domains
|= flush_domains
;
3152 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3154 obj
->read_domains
, obj
->write_domain
,
3155 dev
->invalidate_domains
, dev
->flush_domains
);
3158 trace_i915_gem_object_change_domain(obj
,
3164 * Moves the object from a partially CPU read to a full one.
3166 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3167 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3170 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3172 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3174 if (!obj_priv
->page_cpu_valid
)
3177 /* If we're partially in the CPU read domain, finish moving it in.
3179 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3182 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3183 if (obj_priv
->page_cpu_valid
[i
])
3185 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3189 /* Free the page_cpu_valid mappings which are now stale, whether
3190 * or not we've got I915_GEM_DOMAIN_CPU.
3192 kfree(obj_priv
->page_cpu_valid
);
3193 obj_priv
->page_cpu_valid
= NULL
;
3197 * Set the CPU read domain on a range of the object.
3199 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3200 * not entirely valid. The page_cpu_valid member of the object flags which
3201 * pages have been flushed, and will be respected by
3202 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3203 * of the whole object.
3205 * This function returns when the move is complete, including waiting on
3209 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3210 uint64_t offset
, uint64_t size
)
3212 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3213 uint32_t old_read_domains
;
3216 if (offset
== 0 && size
== obj
->size
)
3217 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3219 i915_gem_object_flush_gpu_write_domain(obj
);
3220 /* Wait on any GPU rendering and flushing to occur. */
3221 ret
= i915_gem_object_wait_rendering(obj
);
3224 i915_gem_object_flush_gtt_write_domain(obj
);
3226 /* If we're already fully in the CPU read domain, we're done. */
3227 if (obj_priv
->page_cpu_valid
== NULL
&&
3228 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3231 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3232 * newly adding I915_GEM_DOMAIN_CPU
3234 if (obj_priv
->page_cpu_valid
== NULL
) {
3235 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3237 if (obj_priv
->page_cpu_valid
== NULL
)
3239 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3240 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3242 /* Flush the cache on any pages that are still invalid from the CPU's
3245 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3247 if (obj_priv
->page_cpu_valid
[i
])
3250 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3252 obj_priv
->page_cpu_valid
[i
] = 1;
3255 /* It should now be out of any other write domains, and we can update
3256 * the domain values for our changes.
3258 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3260 old_read_domains
= obj
->read_domains
;
3261 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3263 trace_i915_gem_object_change_domain(obj
,
3271 * Pin an object to the GTT and evaluate the relocations landing in it.
3274 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3275 struct drm_file
*file_priv
,
3276 struct drm_i915_gem_exec_object2
*entry
,
3277 struct drm_i915_gem_relocation_entry
*relocs
)
3279 struct drm_device
*dev
= obj
->dev
;
3280 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3281 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3283 void __iomem
*reloc_page
;
3286 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3287 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3289 /* Check fence reg constraints and rebind if necessary */
3291 !i915_gem_object_fence_offset_ok(obj
,
3292 obj_priv
->tiling_mode
)) {
3293 ret
= i915_gem_object_unbind(obj
);
3298 /* Choose the GTT offset for our buffer and put it there. */
3299 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3304 * Pre-965 chips need a fence register set up in order to
3305 * properly handle blits to/from tiled surfaces.
3308 ret
= i915_gem_object_get_fence_reg(obj
);
3310 i915_gem_object_unpin(obj
);
3315 entry
->offset
= obj_priv
->gtt_offset
;
3317 /* Apply the relocations, using the GTT aperture to avoid cache
3318 * flushing requirements.
3320 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3321 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3322 struct drm_gem_object
*target_obj
;
3323 struct drm_i915_gem_object
*target_obj_priv
;
3324 uint32_t reloc_val
, reloc_offset
;
3325 uint32_t __iomem
*reloc_entry
;
3327 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3328 reloc
->target_handle
);
3329 if (target_obj
== NULL
) {
3330 i915_gem_object_unpin(obj
);
3333 target_obj_priv
= to_intel_bo(target_obj
);
3336 DRM_INFO("%s: obj %p offset %08x target %d "
3337 "read %08x write %08x gtt %08x "
3338 "presumed %08x delta %08x\n",
3341 (int) reloc
->offset
,
3342 (int) reloc
->target_handle
,
3343 (int) reloc
->read_domains
,
3344 (int) reloc
->write_domain
,
3345 (int) target_obj_priv
->gtt_offset
,
3346 (int) reloc
->presumed_offset
,
3350 /* The target buffer should have appeared before us in the
3351 * exec_object list, so it should have a GTT space bound by now.
3353 if (target_obj_priv
->gtt_space
== NULL
) {
3354 DRM_ERROR("No GTT space found for object %d\n",
3355 reloc
->target_handle
);
3356 drm_gem_object_unreference(target_obj
);
3357 i915_gem_object_unpin(obj
);
3361 /* Validate that the target is in a valid r/w GPU domain */
3362 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3363 DRM_ERROR("reloc with multiple write domains: "
3364 "obj %p target %d offset %d "
3365 "read %08x write %08x",
3366 obj
, reloc
->target_handle
,
3367 (int) reloc
->offset
,
3368 reloc
->read_domains
,
3369 reloc
->write_domain
);
3372 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3373 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3374 DRM_ERROR("reloc with read/write CPU domains: "
3375 "obj %p target %d offset %d "
3376 "read %08x write %08x",
3377 obj
, reloc
->target_handle
,
3378 (int) reloc
->offset
,
3379 reloc
->read_domains
,
3380 reloc
->write_domain
);
3381 drm_gem_object_unreference(target_obj
);
3382 i915_gem_object_unpin(obj
);
3385 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3386 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3387 DRM_ERROR("Write domain conflict: "
3388 "obj %p target %d offset %d "
3389 "new %08x old %08x\n",
3390 obj
, reloc
->target_handle
,
3391 (int) reloc
->offset
,
3392 reloc
->write_domain
,
3393 target_obj
->pending_write_domain
);
3394 drm_gem_object_unreference(target_obj
);
3395 i915_gem_object_unpin(obj
);
3399 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3400 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3402 /* If the relocation already has the right value in it, no
3403 * more work needs to be done.
3405 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3406 drm_gem_object_unreference(target_obj
);
3410 /* Check that the relocation address is valid... */
3411 if (reloc
->offset
> obj
->size
- 4) {
3412 DRM_ERROR("Relocation beyond object bounds: "
3413 "obj %p target %d offset %d size %d.\n",
3414 obj
, reloc
->target_handle
,
3415 (int) reloc
->offset
, (int) obj
->size
);
3416 drm_gem_object_unreference(target_obj
);
3417 i915_gem_object_unpin(obj
);
3420 if (reloc
->offset
& 3) {
3421 DRM_ERROR("Relocation not 4-byte aligned: "
3422 "obj %p target %d offset %d.\n",
3423 obj
, reloc
->target_handle
,
3424 (int) reloc
->offset
);
3425 drm_gem_object_unreference(target_obj
);
3426 i915_gem_object_unpin(obj
);
3430 /* and points to somewhere within the target object. */
3431 if (reloc
->delta
>= target_obj
->size
) {
3432 DRM_ERROR("Relocation beyond target object bounds: "
3433 "obj %p target %d delta %d size %d.\n",
3434 obj
, reloc
->target_handle
,
3435 (int) reloc
->delta
, (int) target_obj
->size
);
3436 drm_gem_object_unreference(target_obj
);
3437 i915_gem_object_unpin(obj
);
3441 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3443 drm_gem_object_unreference(target_obj
);
3444 i915_gem_object_unpin(obj
);
3448 /* Map the page containing the relocation we're going to
3451 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3452 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3455 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3456 (reloc_offset
& (PAGE_SIZE
- 1)));
3457 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3460 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3461 obj
, (unsigned int) reloc
->offset
,
3462 readl(reloc_entry
), reloc_val
);
3464 writel(reloc_val
, reloc_entry
);
3465 io_mapping_unmap_atomic(reloc_page
);
3467 /* The updated presumed offset for this entry will be
3468 * copied back out to the user.
3470 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3472 drm_gem_object_unreference(target_obj
);
3477 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3482 /* Throttle our rendering by waiting until the ring has completed our requests
3483 * emitted over 20 msec ago.
3485 * Note that if we were to use the current jiffies each time around the loop,
3486 * we wouldn't escape the function with any frames outstanding if the time to
3487 * render a frame was over 20ms.
3489 * This should get us reasonable parallelism between CPU and GPU but also
3490 * relatively low latency when blocking on a particular request to finish.
3493 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3495 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3497 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3499 mutex_lock(&dev
->struct_mutex
);
3500 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3501 struct drm_i915_gem_request
*request
;
3503 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3504 struct drm_i915_gem_request
,
3507 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3510 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3514 mutex_unlock(&dev
->struct_mutex
);
3520 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3521 uint32_t buffer_count
,
3522 struct drm_i915_gem_relocation_entry
**relocs
)
3524 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3528 for (i
= 0; i
< buffer_count
; i
++) {
3529 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3531 reloc_count
+= exec_list
[i
].relocation_count
;
3534 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3535 if (*relocs
== NULL
) {
3536 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3540 for (i
= 0; i
< buffer_count
; i
++) {
3541 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3543 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3545 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3547 exec_list
[i
].relocation_count
*
3550 drm_free_large(*relocs
);
3555 reloc_index
+= exec_list
[i
].relocation_count
;
3562 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3563 uint32_t buffer_count
,
3564 struct drm_i915_gem_relocation_entry
*relocs
)
3566 uint32_t reloc_count
= 0, i
;
3572 for (i
= 0; i
< buffer_count
; i
++) {
3573 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3576 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3578 unwritten
= copy_to_user(user_relocs
,
3579 &relocs
[reloc_count
],
3580 exec_list
[i
].relocation_count
*
3588 reloc_count
+= exec_list
[i
].relocation_count
;
3592 drm_free_large(relocs
);
3598 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3599 uint64_t exec_offset
)
3601 uint32_t exec_start
, exec_len
;
3603 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3604 exec_len
= (uint32_t) exec
->batch_len
;
3606 if ((exec_start
| exec_len
) & 0x7)
3616 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3617 struct drm_gem_object
**object_list
,
3620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3621 struct drm_i915_gem_object
*obj_priv
;
3626 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3627 &wait
, TASK_INTERRUPTIBLE
);
3628 for (i
= 0; i
< count
; i
++) {
3629 obj_priv
= to_intel_bo(object_list
[i
]);
3630 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3636 if (!signal_pending(current
)) {
3637 mutex_unlock(&dev
->struct_mutex
);
3639 mutex_lock(&dev
->struct_mutex
);
3645 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3652 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3653 struct drm_file
*file_priv
,
3654 struct drm_i915_gem_execbuffer2
*args
,
3655 struct drm_i915_gem_exec_object2
*exec_list
)
3657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3658 struct drm_gem_object
**object_list
= NULL
;
3659 struct drm_gem_object
*batch_obj
;
3660 struct drm_i915_gem_object
*obj_priv
;
3661 struct drm_clip_rect
*cliprects
= NULL
;
3662 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3663 int ret
= 0, ret2
, i
, pinned
= 0;
3664 uint64_t exec_offset
;
3665 uint32_t seqno
, flush_domains
, reloc_index
;
3666 int pin_tries
, flips
;
3668 struct intel_ring_buffer
*ring
= NULL
;
3671 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3672 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3674 if (args
->flags
& I915_EXEC_BSD
) {
3675 if (!HAS_BSD(dev
)) {
3676 DRM_ERROR("execbuf with wrong flag\n");
3679 ring
= &dev_priv
->bsd_ring
;
3681 ring
= &dev_priv
->render_ring
;
3685 if (args
->buffer_count
< 1) {
3686 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3689 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3690 if (object_list
== NULL
) {
3691 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3692 args
->buffer_count
);
3697 if (args
->num_cliprects
!= 0) {
3698 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3700 if (cliprects
== NULL
) {
3705 ret
= copy_from_user(cliprects
,
3706 (struct drm_clip_rect __user
*)
3707 (uintptr_t) args
->cliprects_ptr
,
3708 sizeof(*cliprects
) * args
->num_cliprects
);
3710 DRM_ERROR("copy %d cliprects failed: %d\n",
3711 args
->num_cliprects
, ret
);
3716 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3721 mutex_lock(&dev
->struct_mutex
);
3723 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3725 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3726 mutex_unlock(&dev
->struct_mutex
);
3731 if (dev_priv
->mm
.suspended
) {
3732 mutex_unlock(&dev
->struct_mutex
);
3737 /* Look up object handles */
3739 for (i
= 0; i
< args
->buffer_count
; i
++) {
3740 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3741 exec_list
[i
].handle
);
3742 if (object_list
[i
] == NULL
) {
3743 DRM_ERROR("Invalid object handle %d at index %d\n",
3744 exec_list
[i
].handle
, i
);
3745 /* prevent error path from reading uninitialized data */
3746 args
->buffer_count
= i
+ 1;
3751 obj_priv
= to_intel_bo(object_list
[i
]);
3752 if (obj_priv
->in_execbuffer
) {
3753 DRM_ERROR("Object %p appears more than once in object list\n",
3755 /* prevent error path from reading uninitialized data */
3756 args
->buffer_count
= i
+ 1;
3760 obj_priv
->in_execbuffer
= true;
3761 flips
+= atomic_read(&obj_priv
->pending_flip
);
3765 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3766 args
->buffer_count
);
3771 /* Pin and relocate */
3772 for (pin_tries
= 0; ; pin_tries
++) {
3776 for (i
= 0; i
< args
->buffer_count
; i
++) {
3777 object_list
[i
]->pending_read_domains
= 0;
3778 object_list
[i
]->pending_write_domain
= 0;
3779 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3782 &relocs
[reloc_index
]);
3786 reloc_index
+= exec_list
[i
].relocation_count
;
3792 /* error other than GTT full, or we've already tried again */
3793 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3794 if (ret
!= -ERESTARTSYS
) {
3795 unsigned long long total_size
= 0;
3797 for (i
= 0; i
< args
->buffer_count
; i
++) {
3798 obj_priv
= to_intel_bo(object_list
[i
]);
3800 total_size
+= object_list
[i
]->size
;
3802 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3803 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3805 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3806 pinned
+1, args
->buffer_count
,
3807 total_size
, num_fences
,
3809 DRM_ERROR("%d objects [%d pinned], "
3810 "%d object bytes [%d pinned], "
3811 "%d/%d gtt bytes\n",
3812 atomic_read(&dev
->object_count
),
3813 atomic_read(&dev
->pin_count
),
3814 atomic_read(&dev
->object_memory
),
3815 atomic_read(&dev
->pin_memory
),
3816 atomic_read(&dev
->gtt_memory
),
3822 /* unpin all of our buffers */
3823 for (i
= 0; i
< pinned
; i
++)
3824 i915_gem_object_unpin(object_list
[i
]);
3827 /* evict everyone we can from the aperture */
3828 ret
= i915_gem_evict_everything(dev
);
3829 if (ret
&& ret
!= -ENOSPC
)
3833 /* Set the pending read domains for the batch buffer to COMMAND */
3834 batch_obj
= object_list
[args
->buffer_count
-1];
3835 if (batch_obj
->pending_write_domain
) {
3836 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3840 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3842 /* Sanity check the batch buffer, prior to moving objects */
3843 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3844 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3846 DRM_ERROR("execbuf with invalid offset/length\n");
3850 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3852 /* Zero the global flush/invalidate flags. These
3853 * will be modified as new domains are computed
3856 dev
->invalidate_domains
= 0;
3857 dev
->flush_domains
= 0;
3859 for (i
= 0; i
< args
->buffer_count
; i
++) {
3860 struct drm_gem_object
*obj
= object_list
[i
];
3862 /* Compute new gpu domains and update invalidate/flush */
3863 i915_gem_object_set_to_gpu_domain(obj
);
3866 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3868 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3870 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3872 dev
->invalidate_domains
,
3873 dev
->flush_domains
);
3876 dev
->invalidate_domains
,
3877 dev
->flush_domains
);
3878 if (dev
->flush_domains
& I915_GEM_GPU_DOMAINS
) {
3879 (void)i915_add_request(dev
, file_priv
,
3881 &dev_priv
->render_ring
);
3884 (void)i915_add_request(dev
, file_priv
,
3886 &dev_priv
->bsd_ring
);
3890 for (i
= 0; i
< args
->buffer_count
; i
++) {
3891 struct drm_gem_object
*obj
= object_list
[i
];
3892 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3893 uint32_t old_write_domain
= obj
->write_domain
;
3895 obj
->write_domain
= obj
->pending_write_domain
;
3896 if (obj
->write_domain
)
3897 list_move_tail(&obj_priv
->gpu_write_list
,
3898 &dev_priv
->mm
.gpu_write_list
);
3900 list_del_init(&obj_priv
->gpu_write_list
);
3902 trace_i915_gem_object_change_domain(obj
,
3907 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3910 for (i
= 0; i
< args
->buffer_count
; i
++) {
3911 i915_gem_object_check_coherency(object_list
[i
],
3912 exec_list
[i
].handle
);
3917 i915_gem_dump_object(batch_obj
,
3923 /* Exec the batchbuffer */
3924 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3925 cliprects
, exec_offset
);
3927 DRM_ERROR("dispatch failed %d\n", ret
);
3932 * Ensure that the commands in the batch buffer are
3933 * finished before the interrupt fires
3935 flush_domains
= i915_retire_commands(dev
, ring
);
3937 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3940 * Get a seqno representing the execution of the current buffer,
3941 * which we can wait on. We would like to mitigate these interrupts,
3942 * likely by only creating seqnos occasionally (so that we have
3943 * *some* interrupts representing completion of buffers that we can
3944 * wait on when trying to clear up gtt space).
3946 seqno
= i915_add_request(dev
, file_priv
, flush_domains
, ring
);
3948 for (i
= 0; i
< args
->buffer_count
; i
++) {
3949 struct drm_gem_object
*obj
= object_list
[i
];
3950 obj_priv
= to_intel_bo(obj
);
3952 i915_gem_object_move_to_active(obj
, seqno
, ring
);
3954 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3958 i915_dump_lru(dev
, __func__
);
3961 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3964 for (i
= 0; i
< pinned
; i
++)
3965 i915_gem_object_unpin(object_list
[i
]);
3967 for (i
= 0; i
< args
->buffer_count
; i
++) {
3968 if (object_list
[i
]) {
3969 obj_priv
= to_intel_bo(object_list
[i
]);
3970 obj_priv
->in_execbuffer
= false;
3972 drm_gem_object_unreference(object_list
[i
]);
3975 mutex_unlock(&dev
->struct_mutex
);
3978 /* Copy the updated relocations out regardless of current error
3979 * state. Failure to update the relocs would mean that the next
3980 * time userland calls execbuf, it would do so with presumed offset
3981 * state that didn't match the actual object state.
3983 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3986 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3992 drm_free_large(object_list
);
3999 * Legacy execbuffer just creates an exec2 list from the original exec object
4000 * list array and passes it to the real function.
4003 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4004 struct drm_file
*file_priv
)
4006 struct drm_i915_gem_execbuffer
*args
= data
;
4007 struct drm_i915_gem_execbuffer2 exec2
;
4008 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4009 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4013 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4014 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4017 if (args
->buffer_count
< 1) {
4018 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4022 /* Copy in the exec list from userland */
4023 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4024 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4025 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4026 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4027 args
->buffer_count
);
4028 drm_free_large(exec_list
);
4029 drm_free_large(exec2_list
);
4032 ret
= copy_from_user(exec_list
,
4033 (struct drm_i915_relocation_entry __user
*)
4034 (uintptr_t) args
->buffers_ptr
,
4035 sizeof(*exec_list
) * args
->buffer_count
);
4037 DRM_ERROR("copy %d exec entries failed %d\n",
4038 args
->buffer_count
, ret
);
4039 drm_free_large(exec_list
);
4040 drm_free_large(exec2_list
);
4044 for (i
= 0; i
< args
->buffer_count
; i
++) {
4045 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4046 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4047 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4048 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4049 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4051 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4053 exec2_list
[i
].flags
= 0;
4056 exec2
.buffers_ptr
= args
->buffers_ptr
;
4057 exec2
.buffer_count
= args
->buffer_count
;
4058 exec2
.batch_start_offset
= args
->batch_start_offset
;
4059 exec2
.batch_len
= args
->batch_len
;
4060 exec2
.DR1
= args
->DR1
;
4061 exec2
.DR4
= args
->DR4
;
4062 exec2
.num_cliprects
= args
->num_cliprects
;
4063 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4064 exec2
.flags
= I915_EXEC_RENDER
;
4066 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4068 /* Copy the new buffer offsets back to the user's exec list. */
4069 for (i
= 0; i
< args
->buffer_count
; i
++)
4070 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4071 /* ... and back out to userspace */
4072 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4073 (uintptr_t) args
->buffers_ptr
,
4075 sizeof(*exec_list
) * args
->buffer_count
);
4078 DRM_ERROR("failed to copy %d exec entries "
4079 "back to user (%d)\n",
4080 args
->buffer_count
, ret
);
4084 drm_free_large(exec_list
);
4085 drm_free_large(exec2_list
);
4090 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4091 struct drm_file
*file_priv
)
4093 struct drm_i915_gem_execbuffer2
*args
= data
;
4094 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4098 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4099 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4102 if (args
->buffer_count
< 1) {
4103 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4107 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4108 if (exec2_list
== NULL
) {
4109 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4110 args
->buffer_count
);
4113 ret
= copy_from_user(exec2_list
,
4114 (struct drm_i915_relocation_entry __user
*)
4115 (uintptr_t) args
->buffers_ptr
,
4116 sizeof(*exec2_list
) * args
->buffer_count
);
4118 DRM_ERROR("copy %d exec entries failed %d\n",
4119 args
->buffer_count
, ret
);
4120 drm_free_large(exec2_list
);
4124 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4126 /* Copy the new buffer offsets back to the user's exec list. */
4127 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4128 (uintptr_t) args
->buffers_ptr
,
4130 sizeof(*exec2_list
) * args
->buffer_count
);
4133 DRM_ERROR("failed to copy %d exec entries "
4134 "back to user (%d)\n",
4135 args
->buffer_count
, ret
);
4139 drm_free_large(exec2_list
);
4144 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4146 struct drm_device
*dev
= obj
->dev
;
4147 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4150 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4152 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4154 if (obj_priv
->gtt_space
!= NULL
) {
4156 alignment
= i915_gem_get_gtt_alignment(obj
);
4157 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4158 ret
= i915_gem_object_unbind(obj
);
4164 if (obj_priv
->gtt_space
== NULL
) {
4165 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4170 obj_priv
->pin_count
++;
4172 /* If the object is not active and not pending a flush,
4173 * remove it from the inactive list
4175 if (obj_priv
->pin_count
== 1) {
4176 atomic_inc(&dev
->pin_count
);
4177 atomic_add(obj
->size
, &dev
->pin_memory
);
4178 if (!obj_priv
->active
&&
4179 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4180 !list_empty(&obj_priv
->list
))
4181 list_del_init(&obj_priv
->list
);
4183 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4189 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4191 struct drm_device
*dev
= obj
->dev
;
4192 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4193 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4195 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4196 obj_priv
->pin_count
--;
4197 BUG_ON(obj_priv
->pin_count
< 0);
4198 BUG_ON(obj_priv
->gtt_space
== NULL
);
4200 /* If the object is no longer pinned, and is
4201 * neither active nor being flushed, then stick it on
4204 if (obj_priv
->pin_count
== 0) {
4205 if (!obj_priv
->active
&&
4206 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4207 list_move_tail(&obj_priv
->list
,
4208 &dev_priv
->mm
.inactive_list
);
4209 atomic_dec(&dev
->pin_count
);
4210 atomic_sub(obj
->size
, &dev
->pin_memory
);
4212 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4216 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4217 struct drm_file
*file_priv
)
4219 struct drm_i915_gem_pin
*args
= data
;
4220 struct drm_gem_object
*obj
;
4221 struct drm_i915_gem_object
*obj_priv
;
4224 mutex_lock(&dev
->struct_mutex
);
4226 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4228 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4230 mutex_unlock(&dev
->struct_mutex
);
4233 obj_priv
= to_intel_bo(obj
);
4235 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4236 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4237 drm_gem_object_unreference(obj
);
4238 mutex_unlock(&dev
->struct_mutex
);
4242 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4243 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4245 drm_gem_object_unreference(obj
);
4246 mutex_unlock(&dev
->struct_mutex
);
4250 obj_priv
->user_pin_count
++;
4251 obj_priv
->pin_filp
= file_priv
;
4252 if (obj_priv
->user_pin_count
== 1) {
4253 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4255 drm_gem_object_unreference(obj
);
4256 mutex_unlock(&dev
->struct_mutex
);
4261 /* XXX - flush the CPU caches for pinned objects
4262 * as the X server doesn't manage domains yet
4264 i915_gem_object_flush_cpu_write_domain(obj
);
4265 args
->offset
= obj_priv
->gtt_offset
;
4266 drm_gem_object_unreference(obj
);
4267 mutex_unlock(&dev
->struct_mutex
);
4273 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4274 struct drm_file
*file_priv
)
4276 struct drm_i915_gem_pin
*args
= data
;
4277 struct drm_gem_object
*obj
;
4278 struct drm_i915_gem_object
*obj_priv
;
4280 mutex_lock(&dev
->struct_mutex
);
4282 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4284 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4286 mutex_unlock(&dev
->struct_mutex
);
4290 obj_priv
= to_intel_bo(obj
);
4291 if (obj_priv
->pin_filp
!= file_priv
) {
4292 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4294 drm_gem_object_unreference(obj
);
4295 mutex_unlock(&dev
->struct_mutex
);
4298 obj_priv
->user_pin_count
--;
4299 if (obj_priv
->user_pin_count
== 0) {
4300 obj_priv
->pin_filp
= NULL
;
4301 i915_gem_object_unpin(obj
);
4304 drm_gem_object_unreference(obj
);
4305 mutex_unlock(&dev
->struct_mutex
);
4310 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4311 struct drm_file
*file_priv
)
4313 struct drm_i915_gem_busy
*args
= data
;
4314 struct drm_gem_object
*obj
;
4315 struct drm_i915_gem_object
*obj_priv
;
4316 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4318 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4320 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4325 mutex_lock(&dev
->struct_mutex
);
4326 /* Update the active list for the hardware's current position.
4327 * Otherwise this only updates on a delayed timer or when irqs are
4328 * actually unmasked, and our working set ends up being larger than
4331 i915_gem_retire_requests(dev
, &dev_priv
->render_ring
);
4334 i915_gem_retire_requests(dev
, &dev_priv
->bsd_ring
);
4336 obj_priv
= to_intel_bo(obj
);
4337 /* Don't count being on the flushing list against the object being
4338 * done. Otherwise, a buffer left on the flushing list but not getting
4339 * flushed (because nobody's flushing that domain) won't ever return
4340 * unbusy and get reused by libdrm's bo cache. The other expected
4341 * consumer of this interface, OpenGL's occlusion queries, also specs
4342 * that the objects get unbusy "eventually" without any interference.
4344 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4346 drm_gem_object_unreference(obj
);
4347 mutex_unlock(&dev
->struct_mutex
);
4352 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4353 struct drm_file
*file_priv
)
4355 return i915_gem_ring_throttle(dev
, file_priv
);
4359 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4360 struct drm_file
*file_priv
)
4362 struct drm_i915_gem_madvise
*args
= data
;
4363 struct drm_gem_object
*obj
;
4364 struct drm_i915_gem_object
*obj_priv
;
4366 switch (args
->madv
) {
4367 case I915_MADV_DONTNEED
:
4368 case I915_MADV_WILLNEED
:
4374 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4376 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4381 mutex_lock(&dev
->struct_mutex
);
4382 obj_priv
= to_intel_bo(obj
);
4384 if (obj_priv
->pin_count
) {
4385 drm_gem_object_unreference(obj
);
4386 mutex_unlock(&dev
->struct_mutex
);
4388 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4392 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4393 obj_priv
->madv
= args
->madv
;
4395 /* if the object is no longer bound, discard its backing storage */
4396 if (i915_gem_object_is_purgeable(obj_priv
) &&
4397 obj_priv
->gtt_space
== NULL
)
4398 i915_gem_object_truncate(obj
);
4400 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4402 drm_gem_object_unreference(obj
);
4403 mutex_unlock(&dev
->struct_mutex
);
4408 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4411 struct drm_i915_gem_object
*obj
;
4413 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4417 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4422 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4423 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4425 obj
->agp_type
= AGP_USER_MEMORY
;
4426 obj
->base
.driver_private
= NULL
;
4427 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4428 INIT_LIST_HEAD(&obj
->list
);
4429 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4430 obj
->madv
= I915_MADV_WILLNEED
;
4432 trace_i915_gem_object_create(&obj
->base
);
4437 int i915_gem_init_object(struct drm_gem_object
*obj
)
4444 void i915_gem_free_object(struct drm_gem_object
*obj
)
4446 struct drm_device
*dev
= obj
->dev
;
4447 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4449 trace_i915_gem_object_destroy(obj
);
4451 while (obj_priv
->pin_count
> 0)
4452 i915_gem_object_unpin(obj
);
4454 if (obj_priv
->phys_obj
)
4455 i915_gem_detach_phys_object(dev
, obj
);
4457 i915_gem_object_unbind(obj
);
4459 if (obj_priv
->mmap_offset
)
4460 i915_gem_free_mmap_offset(obj
);
4462 drm_gem_object_release(obj
);
4464 kfree(obj_priv
->page_cpu_valid
);
4465 kfree(obj_priv
->bit_17
);
4469 /** Unbinds all inactive objects. */
4471 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4473 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4475 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4476 struct drm_gem_object
*obj
;
4479 obj
= &list_first_entry(&dev_priv
->mm
.inactive_list
,
4480 struct drm_i915_gem_object
,
4483 ret
= i915_gem_object_unbind(obj
);
4485 DRM_ERROR("Error unbinding object: %d\n", ret
);
4494 i915_gem_idle(struct drm_device
*dev
)
4496 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4499 mutex_lock(&dev
->struct_mutex
);
4501 if (dev_priv
->mm
.suspended
||
4502 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4504 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4505 mutex_unlock(&dev
->struct_mutex
);
4509 ret
= i915_gpu_idle(dev
);
4511 mutex_unlock(&dev
->struct_mutex
);
4515 /* Under UMS, be paranoid and evict. */
4516 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4517 ret
= i915_gem_evict_from_inactive_list(dev
);
4519 mutex_unlock(&dev
->struct_mutex
);
4524 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4525 * We need to replace this with a semaphore, or something.
4526 * And not confound mm.suspended!
4528 dev_priv
->mm
.suspended
= 1;
4529 del_timer(&dev_priv
->hangcheck_timer
);
4531 i915_kernel_lost_context(dev
);
4532 i915_gem_cleanup_ringbuffer(dev
);
4534 mutex_unlock(&dev
->struct_mutex
);
4536 /* Cancel the retire work handler, which should be idle now. */
4537 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4543 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4544 * over cache flushing.
4547 i915_gem_init_pipe_control(struct drm_device
*dev
)
4549 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4550 struct drm_gem_object
*obj
;
4551 struct drm_i915_gem_object
*obj_priv
;
4554 obj
= i915_gem_alloc_object(dev
, 4096);
4556 DRM_ERROR("Failed to allocate seqno page\n");
4560 obj_priv
= to_intel_bo(obj
);
4561 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4563 ret
= i915_gem_object_pin(obj
, 4096);
4567 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4568 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4569 if (dev_priv
->seqno_page
== NULL
)
4572 dev_priv
->seqno_obj
= obj
;
4573 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4578 i915_gem_object_unpin(obj
);
4580 drm_gem_object_unreference(obj
);
4587 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4589 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4590 struct drm_gem_object
*obj
;
4591 struct drm_i915_gem_object
*obj_priv
;
4593 obj
= dev_priv
->seqno_obj
;
4594 obj_priv
= to_intel_bo(obj
);
4595 kunmap(obj_priv
->pages
[0]);
4596 i915_gem_object_unpin(obj
);
4597 drm_gem_object_unreference(obj
);
4598 dev_priv
->seqno_obj
= NULL
;
4600 dev_priv
->seqno_page
= NULL
;
4604 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4606 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4609 dev_priv
->render_ring
= render_ring
;
4611 if (!I915_NEED_GFX_HWS(dev
)) {
4612 dev_priv
->render_ring
.status_page
.page_addr
4613 = dev_priv
->status_page_dmah
->vaddr
;
4614 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4618 if (HAS_PIPE_CONTROL(dev
)) {
4619 ret
= i915_gem_init_pipe_control(dev
);
4624 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4626 goto cleanup_pipe_control
;
4629 dev_priv
->bsd_ring
= bsd_ring
;
4630 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4632 goto cleanup_render_ring
;
4637 cleanup_render_ring
:
4638 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4639 cleanup_pipe_control
:
4640 if (HAS_PIPE_CONTROL(dev
))
4641 i915_gem_cleanup_pipe_control(dev
);
4646 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4648 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4650 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4652 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4653 if (HAS_PIPE_CONTROL(dev
))
4654 i915_gem_cleanup_pipe_control(dev
);
4658 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4659 struct drm_file
*file_priv
)
4661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4664 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4667 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4668 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4669 atomic_set(&dev_priv
->mm
.wedged
, 0);
4672 mutex_lock(&dev
->struct_mutex
);
4673 dev_priv
->mm
.suspended
= 0;
4675 ret
= i915_gem_init_ringbuffer(dev
);
4677 mutex_unlock(&dev
->struct_mutex
);
4681 spin_lock(&dev_priv
->mm
.active_list_lock
);
4682 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4683 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4684 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4686 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4687 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4688 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4689 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4690 mutex_unlock(&dev
->struct_mutex
);
4692 drm_irq_install(dev
);
4698 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4699 struct drm_file
*file_priv
)
4701 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4704 drm_irq_uninstall(dev
);
4705 return i915_gem_idle(dev
);
4709 i915_gem_lastclose(struct drm_device
*dev
)
4713 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4716 ret
= i915_gem_idle(dev
);
4718 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4722 i915_gem_load(struct drm_device
*dev
)
4725 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4727 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4728 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4729 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4730 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4731 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4732 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4733 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4735 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4736 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4738 for (i
= 0; i
< 16; i
++)
4739 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4740 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4741 i915_gem_retire_work_handler
);
4742 spin_lock(&shrink_list_lock
);
4743 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4744 spin_unlock(&shrink_list_lock
);
4746 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4748 u32 tmp
= I915_READ(MI_ARB_STATE
);
4749 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4750 /* arb state is a masked write, so set bit + bit in mask */
4751 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4752 I915_WRITE(MI_ARB_STATE
, tmp
);
4756 /* Old X drivers will take 0-2 for front, back, depth buffers */
4757 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4758 dev_priv
->fence_reg_start
= 3;
4760 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4761 dev_priv
->num_fence_regs
= 16;
4763 dev_priv
->num_fence_regs
= 8;
4765 /* Initialize fence registers to zero */
4766 if (IS_I965G(dev
)) {
4767 for (i
= 0; i
< 16; i
++)
4768 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4770 for (i
= 0; i
< 8; i
++)
4771 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4772 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4773 for (i
= 0; i
< 8; i
++)
4774 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4776 i915_gem_detect_bit_6_swizzle(dev
);
4777 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4781 * Create a physically contiguous memory object for this object
4782 * e.g. for cursor + overlay regs
4784 int i915_gem_init_phys_object(struct drm_device
*dev
,
4787 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4788 struct drm_i915_gem_phys_object
*phys_obj
;
4791 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4794 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4800 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4801 if (!phys_obj
->handle
) {
4806 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4809 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4817 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4819 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4820 struct drm_i915_gem_phys_object
*phys_obj
;
4822 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4825 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4826 if (phys_obj
->cur_obj
) {
4827 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4831 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4833 drm_pci_free(dev
, phys_obj
->handle
);
4835 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4838 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4842 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4843 i915_gem_free_phys_object(dev
, i
);
4846 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4847 struct drm_gem_object
*obj
)
4849 struct drm_i915_gem_object
*obj_priv
;
4854 obj_priv
= to_intel_bo(obj
);
4855 if (!obj_priv
->phys_obj
)
4858 ret
= i915_gem_object_get_pages(obj
, 0);
4862 page_count
= obj
->size
/ PAGE_SIZE
;
4864 for (i
= 0; i
< page_count
; i
++) {
4865 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4866 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4868 memcpy(dst
, src
, PAGE_SIZE
);
4869 kunmap_atomic(dst
, KM_USER0
);
4871 drm_clflush_pages(obj_priv
->pages
, page_count
);
4872 drm_agp_chipset_flush(dev
);
4874 i915_gem_object_put_pages(obj
);
4876 obj_priv
->phys_obj
->cur_obj
= NULL
;
4877 obj_priv
->phys_obj
= NULL
;
4881 i915_gem_attach_phys_object(struct drm_device
*dev
,
4882 struct drm_gem_object
*obj
, int id
)
4884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4885 struct drm_i915_gem_object
*obj_priv
;
4890 if (id
> I915_MAX_PHYS_OBJECT
)
4893 obj_priv
= to_intel_bo(obj
);
4895 if (obj_priv
->phys_obj
) {
4896 if (obj_priv
->phys_obj
->id
== id
)
4898 i915_gem_detach_phys_object(dev
, obj
);
4902 /* create a new object */
4903 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4904 ret
= i915_gem_init_phys_object(dev
, id
,
4907 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4912 /* bind to the object */
4913 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4914 obj_priv
->phys_obj
->cur_obj
= obj
;
4916 ret
= i915_gem_object_get_pages(obj
, 0);
4918 DRM_ERROR("failed to get page list\n");
4922 page_count
= obj
->size
/ PAGE_SIZE
;
4924 for (i
= 0; i
< page_count
; i
++) {
4925 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4926 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4928 memcpy(dst
, src
, PAGE_SIZE
);
4929 kunmap_atomic(src
, KM_USER0
);
4932 i915_gem_object_put_pages(obj
);
4940 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4941 struct drm_i915_gem_pwrite
*args
,
4942 struct drm_file
*file_priv
)
4944 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4947 char __user
*user_data
;
4949 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4950 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4952 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4953 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4957 drm_agp_chipset_flush(dev
);
4961 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4963 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4965 /* Clean up our request list when the client is going away, so that
4966 * later retire_requests won't dereference our soon-to-be-gone
4969 mutex_lock(&dev
->struct_mutex
);
4970 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4971 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4972 mutex_unlock(&dev
->struct_mutex
);
4976 i915_gpu_is_active(struct drm_device
*dev
)
4978 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4981 spin_lock(&dev_priv
->mm
.active_list_lock
);
4982 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4983 list_empty(&dev_priv
->render_ring
.active_list
);
4985 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4986 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4988 return !lists_empty
;
4992 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4994 drm_i915_private_t
*dev_priv
, *next_dev
;
4995 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4997 int would_deadlock
= 1;
4999 /* "fast-path" to count number of available objects */
5000 if (nr_to_scan
== 0) {
5001 spin_lock(&shrink_list_lock
);
5002 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5003 struct drm_device
*dev
= dev_priv
->dev
;
5005 if (mutex_trylock(&dev
->struct_mutex
)) {
5006 list_for_each_entry(obj_priv
,
5007 &dev_priv
->mm
.inactive_list
,
5010 mutex_unlock(&dev
->struct_mutex
);
5013 spin_unlock(&shrink_list_lock
);
5015 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5018 spin_lock(&shrink_list_lock
);
5021 /* first scan for clean buffers */
5022 list_for_each_entry_safe(dev_priv
, next_dev
,
5023 &shrink_list
, mm
.shrink_list
) {
5024 struct drm_device
*dev
= dev_priv
->dev
;
5026 if (! mutex_trylock(&dev
->struct_mutex
))
5029 spin_unlock(&shrink_list_lock
);
5030 i915_gem_retire_requests(dev
, &dev_priv
->render_ring
);
5033 i915_gem_retire_requests(dev
, &dev_priv
->bsd_ring
);
5035 list_for_each_entry_safe(obj_priv
, next_obj
,
5036 &dev_priv
->mm
.inactive_list
,
5038 if (i915_gem_object_is_purgeable(obj_priv
)) {
5039 i915_gem_object_unbind(&obj_priv
->base
);
5040 if (--nr_to_scan
<= 0)
5045 spin_lock(&shrink_list_lock
);
5046 mutex_unlock(&dev
->struct_mutex
);
5050 if (nr_to_scan
<= 0)
5054 /* second pass, evict/count anything still on the inactive list */
5055 list_for_each_entry_safe(dev_priv
, next_dev
,
5056 &shrink_list
, mm
.shrink_list
) {
5057 struct drm_device
*dev
= dev_priv
->dev
;
5059 if (! mutex_trylock(&dev
->struct_mutex
))
5062 spin_unlock(&shrink_list_lock
);
5064 list_for_each_entry_safe(obj_priv
, next_obj
,
5065 &dev_priv
->mm
.inactive_list
,
5067 if (nr_to_scan
> 0) {
5068 i915_gem_object_unbind(&obj_priv
->base
);
5074 spin_lock(&shrink_list_lock
);
5075 mutex_unlock(&dev
->struct_mutex
);
5084 * We are desperate for pages, so as a last resort, wait
5085 * for the GPU to finish and discard whatever we can.
5086 * This has a dramatic impact to reduce the number of
5087 * OOM-killer events whilst running the GPU aggressively.
5089 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5090 struct drm_device
*dev
= dev_priv
->dev
;
5092 if (!mutex_trylock(&dev
->struct_mutex
))
5095 spin_unlock(&shrink_list_lock
);
5097 if (i915_gpu_is_active(dev
)) {
5102 spin_lock(&shrink_list_lock
);
5103 mutex_unlock(&dev
->struct_mutex
);
5110 spin_unlock(&shrink_list_lock
);
5115 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5120 static struct shrinker shrinker
= {
5121 .shrink
= i915_gem_shrink
,
5122 .seeks
= DEFAULT_SEEKS
,
5126 i915_gem_shrinker_init(void)
5128 register_shrinker(&shrinker
);
5132 i915_gem_shrinker_exit(void)
5134 unregister_shrinker(&shrinker
);