2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/oom.h>
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
44 static __must_check
int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
48 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static unsigned long i915_gem_shrinker_count(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker
*shrinker
,
59 struct shrink_control
*sc
);
60 static int i915_gem_shrinker_oom(struct notifier_block
*nb
,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
65 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
66 enum i915_cache_level level
)
68 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
73 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
76 return obj
->pin_display
;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
82 i915_gem_release_mmap(obj
);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj
->fence_dirty
= false;
88 obj
->fence_reg
= I915_FENCE_REG_NONE
;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
95 spin_lock(&dev_priv
->mm
.object_stat_lock
);
96 dev_priv
->mm
.object_count
++;
97 dev_priv
->mm
.object_memory
+= size
;
98 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
104 spin_lock(&dev_priv
->mm
.object_stat_lock
);
105 dev_priv
->mm
.object_count
--;
106 dev_priv
->mm
.object_memory
-= size
;
107 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
111 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret
< 0) {
139 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
148 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
152 WARN_ON(i915_verify_lists(dev
));
157 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
158 struct drm_file
*file
)
160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 struct drm_i915_gem_get_aperture
*args
= data
;
162 struct drm_i915_gem_object
*obj
;
166 mutex_lock(&dev
->struct_mutex
);
167 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
168 if (i915_gem_obj_is_pinned(obj
))
169 pinned
+= i915_gem_obj_ggtt_size(obj
);
170 mutex_unlock(&dev
->struct_mutex
);
172 args
->aper_size
= dev_priv
->gtt
.base
.total
;
173 args
->aper_available_size
= args
->aper_size
- pinned
;
179 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
181 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
182 char *vaddr
= obj
->phys_handle
->vaddr
;
184 struct scatterlist
*sg
;
187 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
190 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
194 page
= shmem_read_mapping_page(mapping
, i
);
196 return PTR_ERR(page
);
198 src
= kmap_atomic(page
);
199 memcpy(vaddr
, src
, PAGE_SIZE
);
200 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
203 page_cache_release(page
);
207 i915_gem_chipset_flush(obj
->base
.dev
);
209 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
213 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
220 sg
->length
= obj
->base
.size
;
222 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
223 sg_dma_len(sg
) = obj
->base
.size
;
226 obj
->has_dma_mapping
= true;
231 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
235 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
237 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
239 /* In the event of a disaster, abandon all caches and
242 WARN_ON(ret
!= -EIO
);
243 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
246 if (obj
->madv
== I915_MADV_DONTNEED
)
250 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
251 char *vaddr
= obj
->phys_handle
->vaddr
;
254 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
258 page
= shmem_read_mapping_page(mapping
, i
);
262 dst
= kmap_atomic(page
);
263 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
264 memcpy(dst
, vaddr
, PAGE_SIZE
);
267 set_page_dirty(page
);
268 if (obj
->madv
== I915_MADV_WILLNEED
)
269 mark_page_accessed(page
);
270 page_cache_release(page
);
276 sg_free_table(obj
->pages
);
279 obj
->has_dma_mapping
= false;
283 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
285 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
288 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
289 .get_pages
= i915_gem_object_get_pages_phys
,
290 .put_pages
= i915_gem_object_put_pages_phys
,
291 .release
= i915_gem_object_release_phys
,
295 drop_pages(struct drm_i915_gem_object
*obj
)
297 struct i915_vma
*vma
, *next
;
300 drm_gem_object_reference(&obj
->base
);
301 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
302 if (i915_vma_unbind(vma
))
305 ret
= i915_gem_object_put_pages(obj
);
306 drm_gem_object_unreference(&obj
->base
);
312 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
315 drm_dma_handle_t
*phys
;
318 if (obj
->phys_handle
) {
319 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
325 if (obj
->madv
!= I915_MADV_WILLNEED
)
328 if (obj
->base
.filp
== NULL
)
331 ret
= drop_pages(obj
);
335 /* create a new object */
336 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
340 obj
->phys_handle
= phys
;
341 obj
->ops
= &i915_gem_phys_ops
;
343 return i915_gem_object_get_pages(obj
);
347 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
348 struct drm_i915_gem_pwrite
*args
,
349 struct drm_file
*file_priv
)
351 struct drm_device
*dev
= obj
->base
.dev
;
352 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
353 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
356 /* We manually control the domain here and pretend that it
357 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
359 ret
= i915_gem_object_wait_rendering(obj
, false);
363 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
364 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
365 unsigned long unwritten
;
367 /* The physical object once assigned is fixed for the lifetime
368 * of the obj, so we can safely drop the lock and continue
371 mutex_unlock(&dev
->struct_mutex
);
372 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
373 mutex_lock(&dev
->struct_mutex
);
380 drm_clflush_virt_range(vaddr
, args
->size
);
381 i915_gem_chipset_flush(dev
);
384 intel_fb_obj_flush(obj
, false);
388 void *i915_gem_object_alloc(struct drm_device
*dev
)
390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
394 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
396 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
397 kmem_cache_free(dev_priv
->slab
, obj
);
401 i915_gem_create(struct drm_file
*file
,
402 struct drm_device
*dev
,
406 struct drm_i915_gem_object
*obj
;
410 size
= roundup(size
, PAGE_SIZE
);
414 /* Allocate the new object */
415 obj
= i915_gem_alloc_object(dev
, size
);
419 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
420 /* drop reference from allocate - handle holds it now */
421 drm_gem_object_unreference_unlocked(&obj
->base
);
430 i915_gem_dumb_create(struct drm_file
*file
,
431 struct drm_device
*dev
,
432 struct drm_mode_create_dumb
*args
)
434 /* have to work out size/pitch and return them */
435 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
436 args
->size
= args
->pitch
* args
->height
;
437 return i915_gem_create(file
, dev
,
438 args
->size
, &args
->handle
);
442 * Creates a new mm object and returns a handle to it.
445 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
446 struct drm_file
*file
)
448 struct drm_i915_gem_create
*args
= data
;
450 return i915_gem_create(file
, dev
,
451 args
->size
, &args
->handle
);
455 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
456 const char *gpu_vaddr
, int gpu_offset
,
459 int ret
, cpu_offset
= 0;
462 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
463 int this_length
= min(cacheline_end
- gpu_offset
, length
);
464 int swizzled_gpu_offset
= gpu_offset
^ 64;
466 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
467 gpu_vaddr
+ swizzled_gpu_offset
,
472 cpu_offset
+= this_length
;
473 gpu_offset
+= this_length
;
474 length
-= this_length
;
481 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
482 const char __user
*cpu_vaddr
,
485 int ret
, cpu_offset
= 0;
488 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
489 int this_length
= min(cacheline_end
- gpu_offset
, length
);
490 int swizzled_gpu_offset
= gpu_offset
^ 64;
492 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
493 cpu_vaddr
+ cpu_offset
,
498 cpu_offset
+= this_length
;
499 gpu_offset
+= this_length
;
500 length
-= this_length
;
507 * Pins the specified object's pages and synchronizes the object with
508 * GPU accesses. Sets needs_clflush to non-zero if the caller should
509 * flush the object from the CPU cache.
511 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
521 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
522 /* If we're not in the cpu read domain, set ourself into the gtt
523 * read domain and manually flush cachelines (if required). This
524 * optimizes for the case when the gpu will dirty the data
525 * anyway again before the next pread happens. */
526 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
528 ret
= i915_gem_object_wait_rendering(obj
, true);
532 i915_gem_object_retire(obj
);
535 ret
= i915_gem_object_get_pages(obj
);
539 i915_gem_object_pin_pages(obj
);
544 /* Per-page copy function for the shmem pread fastpath.
545 * Flushes invalid cachelines before reading the target if
546 * needs_clflush is set. */
548 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
549 char __user
*user_data
,
550 bool page_do_bit17_swizzling
, bool needs_clflush
)
555 if (unlikely(page_do_bit17_swizzling
))
558 vaddr
= kmap_atomic(page
);
560 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
562 ret
= __copy_to_user_inatomic(user_data
,
563 vaddr
+ shmem_page_offset
,
565 kunmap_atomic(vaddr
);
567 return ret
? -EFAULT
: 0;
571 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
574 if (unlikely(swizzled
)) {
575 unsigned long start
= (unsigned long) addr
;
576 unsigned long end
= (unsigned long) addr
+ length
;
578 /* For swizzling simply ensure that we always flush both
579 * channels. Lame, but simple and it works. Swizzled
580 * pwrite/pread is far from a hotpath - current userspace
581 * doesn't use it at all. */
582 start
= round_down(start
, 128);
583 end
= round_up(end
, 128);
585 drm_clflush_virt_range((void *)start
, end
- start
);
587 drm_clflush_virt_range(addr
, length
);
592 /* Only difference to the fast-path function is that this can handle bit17
593 * and uses non-atomic copy and kmap functions. */
595 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
596 char __user
*user_data
,
597 bool page_do_bit17_swizzling
, bool needs_clflush
)
604 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
606 page_do_bit17_swizzling
);
608 if (page_do_bit17_swizzling
)
609 ret
= __copy_to_user_swizzled(user_data
,
610 vaddr
, shmem_page_offset
,
613 ret
= __copy_to_user(user_data
,
614 vaddr
+ shmem_page_offset
,
618 return ret
? - EFAULT
: 0;
622 i915_gem_shmem_pread(struct drm_device
*dev
,
623 struct drm_i915_gem_object
*obj
,
624 struct drm_i915_gem_pread
*args
,
625 struct drm_file
*file
)
627 char __user
*user_data
;
630 int shmem_page_offset
, page_length
, ret
= 0;
631 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
633 int needs_clflush
= 0;
634 struct sg_page_iter sg_iter
;
636 user_data
= to_user_ptr(args
->data_ptr
);
639 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
641 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
645 offset
= args
->offset
;
647 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
648 offset
>> PAGE_SHIFT
) {
649 struct page
*page
= sg_page_iter_page(&sg_iter
);
654 /* Operation in this page
656 * shmem_page_offset = offset within page in shmem file
657 * page_length = bytes to copy for this page
659 shmem_page_offset
= offset_in_page(offset
);
660 page_length
= remain
;
661 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
662 page_length
= PAGE_SIZE
- shmem_page_offset
;
664 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
665 (page_to_phys(page
) & (1 << 17)) != 0;
667 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
668 user_data
, page_do_bit17_swizzling
,
673 mutex_unlock(&dev
->struct_mutex
);
675 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
676 ret
= fault_in_multipages_writeable(user_data
, remain
);
677 /* Userspace is tricking us, but we've already clobbered
678 * its pages with the prefault and promised to write the
679 * data up to the first fault. Hence ignore any errors
680 * and just continue. */
685 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
686 user_data
, page_do_bit17_swizzling
,
689 mutex_lock(&dev
->struct_mutex
);
695 remain
-= page_length
;
696 user_data
+= page_length
;
697 offset
+= page_length
;
701 i915_gem_object_unpin_pages(obj
);
707 * Reads data from the object referenced by handle.
709 * On error, the contents of *data are undefined.
712 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
713 struct drm_file
*file
)
715 struct drm_i915_gem_pread
*args
= data
;
716 struct drm_i915_gem_object
*obj
;
722 if (!access_ok(VERIFY_WRITE
,
723 to_user_ptr(args
->data_ptr
),
727 ret
= i915_mutex_lock_interruptible(dev
);
731 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
732 if (&obj
->base
== NULL
) {
737 /* Bounds check source. */
738 if (args
->offset
> obj
->base
.size
||
739 args
->size
> obj
->base
.size
- args
->offset
) {
744 /* prime objects have no backing filp to GEM pread/pwrite
747 if (!obj
->base
.filp
) {
752 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
754 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
757 drm_gem_object_unreference(&obj
->base
);
759 mutex_unlock(&dev
->struct_mutex
);
763 /* This is the fast write path which cannot handle
764 * page faults in the source data
768 fast_user_write(struct io_mapping
*mapping
,
769 loff_t page_base
, int page_offset
,
770 char __user
*user_data
,
773 void __iomem
*vaddr_atomic
;
775 unsigned long unwritten
;
777 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
778 /* We can use the cpu mem copy function because this is X86. */
779 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
780 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
782 io_mapping_unmap_atomic(vaddr_atomic
);
787 * This is the fast pwrite path, where we copy the data directly from the
788 * user into the GTT, uncached.
791 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
792 struct drm_i915_gem_object
*obj
,
793 struct drm_i915_gem_pwrite
*args
,
794 struct drm_file
*file
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
798 loff_t offset
, page_base
;
799 char __user
*user_data
;
800 int page_offset
, page_length
, ret
;
802 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
806 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
810 ret
= i915_gem_object_put_fence(obj
);
814 user_data
= to_user_ptr(args
->data_ptr
);
817 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
819 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
822 /* Operation in this page
824 * page_base = page offset within aperture
825 * page_offset = offset within page
826 * page_length = bytes to copy for this page
828 page_base
= offset
& PAGE_MASK
;
829 page_offset
= offset_in_page(offset
);
830 page_length
= remain
;
831 if ((page_offset
+ remain
) > PAGE_SIZE
)
832 page_length
= PAGE_SIZE
- page_offset
;
834 /* If we get a fault while copying data, then (presumably) our
835 * source page isn't available. Return the error and we'll
836 * retry in the slow path.
838 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
839 page_offset
, user_data
, page_length
)) {
844 remain
-= page_length
;
845 user_data
+= page_length
;
846 offset
+= page_length
;
850 intel_fb_obj_flush(obj
, false);
852 i915_gem_object_ggtt_unpin(obj
);
857 /* Per-page copy function for the shmem pwrite fastpath.
858 * Flushes invalid cachelines before writing to the target if
859 * needs_clflush_before is set and flushes out any written cachelines after
860 * writing if needs_clflush is set. */
862 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
863 char __user
*user_data
,
864 bool page_do_bit17_swizzling
,
865 bool needs_clflush_before
,
866 bool needs_clflush_after
)
871 if (unlikely(page_do_bit17_swizzling
))
874 vaddr
= kmap_atomic(page
);
875 if (needs_clflush_before
)
876 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
878 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
879 user_data
, page_length
);
880 if (needs_clflush_after
)
881 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
883 kunmap_atomic(vaddr
);
885 return ret
? -EFAULT
: 0;
888 /* Only difference to the fast-path function is that this can handle bit17
889 * and uses non-atomic copy and kmap functions. */
891 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
892 char __user
*user_data
,
893 bool page_do_bit17_swizzling
,
894 bool needs_clflush_before
,
895 bool needs_clflush_after
)
901 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
902 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
904 page_do_bit17_swizzling
);
905 if (page_do_bit17_swizzling
)
906 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
910 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
913 if (needs_clflush_after
)
914 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
916 page_do_bit17_swizzling
);
919 return ret
? -EFAULT
: 0;
923 i915_gem_shmem_pwrite(struct drm_device
*dev
,
924 struct drm_i915_gem_object
*obj
,
925 struct drm_i915_gem_pwrite
*args
,
926 struct drm_file
*file
)
930 char __user
*user_data
;
931 int shmem_page_offset
, page_length
, ret
= 0;
932 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
933 int hit_slowpath
= 0;
934 int needs_clflush_after
= 0;
935 int needs_clflush_before
= 0;
936 struct sg_page_iter sg_iter
;
938 user_data
= to_user_ptr(args
->data_ptr
);
941 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
943 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
944 /* If we're not in the cpu write domain, set ourself into the gtt
945 * write domain and manually flush cachelines (if required). This
946 * optimizes for the case when the gpu will use the data
947 * right away and we therefore have to clflush anyway. */
948 needs_clflush_after
= cpu_write_needs_clflush(obj
);
949 ret
= i915_gem_object_wait_rendering(obj
, false);
953 i915_gem_object_retire(obj
);
955 /* Same trick applies to invalidate partially written cachelines read
957 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
958 needs_clflush_before
=
959 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
961 ret
= i915_gem_object_get_pages(obj
);
965 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
967 i915_gem_object_pin_pages(obj
);
969 offset
= args
->offset
;
972 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
973 offset
>> PAGE_SHIFT
) {
974 struct page
*page
= sg_page_iter_page(&sg_iter
);
975 int partial_cacheline_write
;
980 /* Operation in this page
982 * shmem_page_offset = offset within page in shmem file
983 * page_length = bytes to copy for this page
985 shmem_page_offset
= offset_in_page(offset
);
987 page_length
= remain
;
988 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
989 page_length
= PAGE_SIZE
- shmem_page_offset
;
991 /* If we don't overwrite a cacheline completely we need to be
992 * careful to have up-to-date data by first clflushing. Don't
993 * overcomplicate things and flush the entire patch. */
994 partial_cacheline_write
= needs_clflush_before
&&
995 ((shmem_page_offset
| page_length
)
996 & (boot_cpu_data
.x86_clflush_size
- 1));
998 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
999 (page_to_phys(page
) & (1 << 17)) != 0;
1001 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
1002 user_data
, page_do_bit17_swizzling
,
1003 partial_cacheline_write
,
1004 needs_clflush_after
);
1009 mutex_unlock(&dev
->struct_mutex
);
1010 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1011 user_data
, page_do_bit17_swizzling
,
1012 partial_cacheline_write
,
1013 needs_clflush_after
);
1015 mutex_lock(&dev
->struct_mutex
);
1021 remain
-= page_length
;
1022 user_data
+= page_length
;
1023 offset
+= page_length
;
1027 i915_gem_object_unpin_pages(obj
);
1031 * Fixup: Flush cpu caches in case we didn't flush the dirty
1032 * cachelines in-line while writing and the object moved
1033 * out of the cpu write domain while we've dropped the lock.
1035 if (!needs_clflush_after
&&
1036 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1037 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1038 i915_gem_chipset_flush(dev
);
1042 if (needs_clflush_after
)
1043 i915_gem_chipset_flush(dev
);
1045 intel_fb_obj_flush(obj
, false);
1050 * Writes data to the object referenced by handle.
1052 * On error, the contents of the buffer that were to be modified are undefined.
1055 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1056 struct drm_file
*file
)
1058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1059 struct drm_i915_gem_pwrite
*args
= data
;
1060 struct drm_i915_gem_object
*obj
;
1063 if (args
->size
== 0)
1066 if (!access_ok(VERIFY_READ
,
1067 to_user_ptr(args
->data_ptr
),
1071 if (likely(!i915
.prefault_disable
)) {
1072 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1078 intel_runtime_pm_get(dev_priv
);
1080 ret
= i915_mutex_lock_interruptible(dev
);
1084 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1085 if (&obj
->base
== NULL
) {
1090 /* Bounds check destination. */
1091 if (args
->offset
> obj
->base
.size
||
1092 args
->size
> obj
->base
.size
- args
->offset
) {
1097 /* prime objects have no backing filp to GEM pread/pwrite
1100 if (!obj
->base
.filp
) {
1105 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1108 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1109 * it would end up going through the fenced access, and we'll get
1110 * different detiling behavior between reading and writing.
1111 * pread/pwrite currently are reading and writing from the CPU
1112 * perspective, requiring manual detiling by the client.
1114 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1115 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1116 cpu_write_needs_clflush(obj
)) {
1117 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1118 /* Note that the gtt paths might fail with non-page-backed user
1119 * pointers (e.g. gtt mappings when moving data between
1120 * textures). Fallback to the shmem path in that case. */
1123 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1124 if (obj
->phys_handle
)
1125 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1127 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1131 drm_gem_object_unreference(&obj
->base
);
1133 mutex_unlock(&dev
->struct_mutex
);
1135 intel_runtime_pm_put(dev_priv
);
1141 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1144 if (i915_reset_in_progress(error
)) {
1145 /* Non-interruptible callers can't handle -EAGAIN, hence return
1146 * -EIO unconditionally for these. */
1150 /* Recovery complete, but the reset failed ... */
1151 if (i915_terminally_wedged(error
))
1155 * Check if GPU Reset is in progress - we need intel_ring_begin
1156 * to work properly to reinit the hw state while the gpu is
1157 * still marked as reset-in-progress. Handle this with a flag.
1159 if (!error
->reload_in_reset
)
1167 * Compare arbitrary request against outstanding lazy request. Emit on match.
1170 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1174 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1177 if (req
== req
->ring
->outstanding_lazy_request
)
1178 ret
= i915_add_request(req
->ring
);
1183 static void fake_irq(unsigned long data
)
1185 wake_up_process((struct task_struct
*)data
);
1188 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1189 struct intel_engine_cs
*ring
)
1191 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1194 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1196 if (file_priv
== NULL
)
1199 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1203 * __i915_wait_request - wait until execution of request has finished
1205 * @reset_counter: reset sequence associated with the given request
1206 * @interruptible: do an interruptible wait (normally yes)
1207 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1209 * Note: It is of utmost importance that the passed in seqno and reset_counter
1210 * values have been read by the caller in an smp safe manner. Where read-side
1211 * locks are involved, it is sufficient to read the reset_counter before
1212 * unlocking the lock that protects the seqno. For lockless tricks, the
1213 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1216 * Returns 0 if the request was found within the alloted time. Else returns the
1217 * errno with remaining time filled in timeout argument.
1219 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1220 unsigned reset_counter
,
1223 struct drm_i915_file_private
*file_priv
)
1225 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1226 struct drm_device
*dev
= ring
->dev
;
1227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1228 const bool irq_test_in_progress
=
1229 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1231 unsigned long timeout_expire
;
1235 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1237 if (i915_gem_request_completed(req
, true))
1240 timeout_expire
= timeout
?
1241 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1243 if (INTEL_INFO(dev
)->gen
>= 6 && ring
->id
== RCS
&& can_wait_boost(file_priv
)) {
1244 gen6_rps_boost(dev_priv
);
1246 mod_delayed_work(dev_priv
->wq
,
1247 &file_priv
->mm
.idle_work
,
1248 msecs_to_jiffies(100));
1251 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1254 /* Record current time in case interrupted by signal, or wedged */
1255 trace_i915_gem_request_wait_begin(req
);
1256 before
= ktime_get_raw_ns();
1258 struct timer_list timer
;
1260 prepare_to_wait(&ring
->irq_queue
, &wait
,
1261 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1263 /* We need to check whether any gpu reset happened in between
1264 * the caller grabbing the seqno and now ... */
1265 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1266 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1267 * is truely gone. */
1268 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1274 if (i915_gem_request_completed(req
, false)) {
1279 if (interruptible
&& signal_pending(current
)) {
1284 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1289 timer
.function
= NULL
;
1290 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1291 unsigned long expire
;
1293 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1294 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1295 mod_timer(&timer
, expire
);
1300 if (timer
.function
) {
1301 del_singleshot_timer_sync(&timer
);
1302 destroy_timer_on_stack(&timer
);
1305 now
= ktime_get_raw_ns();
1306 trace_i915_gem_request_wait_end(req
);
1308 if (!irq_test_in_progress
)
1309 ring
->irq_put(ring
);
1311 finish_wait(&ring
->irq_queue
, &wait
);
1314 s64 tres
= *timeout
- (now
- before
);
1316 *timeout
= tres
< 0 ? 0 : tres
;
1319 * Apparently ktime isn't accurate enough and occasionally has a
1320 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1321 * things up to make the test happy. We allow up to 1 jiffy.
1323 * This is a regrssion from the timespec->ktime conversion.
1325 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1333 * Waits for a request to be signaled, and cleans up the
1334 * request and object lists appropriately for that event.
1337 i915_wait_request(struct drm_i915_gem_request
*req
)
1339 struct drm_device
*dev
;
1340 struct drm_i915_private
*dev_priv
;
1342 unsigned reset_counter
;
1345 BUG_ON(req
== NULL
);
1347 dev
= req
->ring
->dev
;
1348 dev_priv
= dev
->dev_private
;
1349 interruptible
= dev_priv
->mm
.interruptible
;
1351 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1353 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1357 ret
= i915_gem_check_olr(req
);
1361 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1362 i915_gem_request_reference(req
);
1363 ret
= __i915_wait_request(req
, reset_counter
,
1364 interruptible
, NULL
, NULL
);
1365 i915_gem_request_unreference(req
);
1370 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1375 /* Manually manage the write flush as we may have not yet
1376 * retired the buffer.
1378 * Note that the last_write_req is always the earlier of
1379 * the two (read/write) requests, so if we haved successfully waited,
1380 * we know we have passed the last write.
1382 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1388 * Ensures that all rendering to the object has completed and the object is
1389 * safe to unbind from the GTT or access from the CPU.
1391 static __must_check
int
1392 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1395 struct drm_i915_gem_request
*req
;
1398 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1402 ret
= i915_wait_request(req
);
1406 return i915_gem_object_wait_rendering__tail(obj
);
1409 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1410 * as the object state may change during this call.
1412 static __must_check
int
1413 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1414 struct drm_i915_file_private
*file_priv
,
1417 struct drm_i915_gem_request
*req
;
1418 struct drm_device
*dev
= obj
->base
.dev
;
1419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1420 unsigned reset_counter
;
1423 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1424 BUG_ON(!dev_priv
->mm
.interruptible
);
1426 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1430 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1434 ret
= i915_gem_check_olr(req
);
1438 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1439 i915_gem_request_reference(req
);
1440 mutex_unlock(&dev
->struct_mutex
);
1441 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1442 mutex_lock(&dev
->struct_mutex
);
1443 i915_gem_request_unreference(req
);
1447 return i915_gem_object_wait_rendering__tail(obj
);
1451 * Called when user space prepares to use an object with the CPU, either
1452 * through the mmap ioctl's mapping or a GTT mapping.
1455 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1456 struct drm_file
*file
)
1458 struct drm_i915_gem_set_domain
*args
= data
;
1459 struct drm_i915_gem_object
*obj
;
1460 uint32_t read_domains
= args
->read_domains
;
1461 uint32_t write_domain
= args
->write_domain
;
1464 /* Only handle setting domains to types used by the CPU. */
1465 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1468 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1471 /* Having something in the write domain implies it's in the read
1472 * domain, and only that read domain. Enforce that in the request.
1474 if (write_domain
!= 0 && read_domains
!= write_domain
)
1477 ret
= i915_mutex_lock_interruptible(dev
);
1481 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1482 if (&obj
->base
== NULL
) {
1487 /* Try to flush the object off the GPU without holding the lock.
1488 * We will repeat the flush holding the lock in the normal manner
1489 * to catch cases where we are gazumped.
1491 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1497 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1498 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1500 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1503 drm_gem_object_unreference(&obj
->base
);
1505 mutex_unlock(&dev
->struct_mutex
);
1510 * Called when user space has done writes to this buffer
1513 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1514 struct drm_file
*file
)
1516 struct drm_i915_gem_sw_finish
*args
= data
;
1517 struct drm_i915_gem_object
*obj
;
1520 ret
= i915_mutex_lock_interruptible(dev
);
1524 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1525 if (&obj
->base
== NULL
) {
1530 /* Pinned buffers may be scanout, so flush the cache */
1531 if (obj
->pin_display
)
1532 i915_gem_object_flush_cpu_write_domain(obj
);
1534 drm_gem_object_unreference(&obj
->base
);
1536 mutex_unlock(&dev
->struct_mutex
);
1541 * Maps the contents of an object, returning the address it is mapped
1544 * While the mapping holds a reference on the contents of the object, it doesn't
1545 * imply a ref on the object itself.
1549 * DRM driver writers who look a this function as an example for how to do GEM
1550 * mmap support, please don't implement mmap support like here. The modern way
1551 * to implement DRM mmap support is with an mmap offset ioctl (like
1552 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1553 * That way debug tooling like valgrind will understand what's going on, hiding
1554 * the mmap call in a driver private ioctl will break that. The i915 driver only
1555 * does cpu mmaps this way because we didn't know better.
1558 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1559 struct drm_file
*file
)
1561 struct drm_i915_gem_mmap
*args
= data
;
1562 struct drm_gem_object
*obj
;
1565 if (args
->flags
& ~(I915_MMAP_WC
))
1568 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1571 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1575 /* prime objects have no backing filp to GEM mmap
1579 drm_gem_object_unreference_unlocked(obj
);
1583 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1584 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1586 if (args
->flags
& I915_MMAP_WC
) {
1587 struct mm_struct
*mm
= current
->mm
;
1588 struct vm_area_struct
*vma
;
1590 down_write(&mm
->mmap_sem
);
1591 vma
= find_vma(mm
, addr
);
1594 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1597 up_write(&mm
->mmap_sem
);
1599 drm_gem_object_unreference_unlocked(obj
);
1600 if (IS_ERR((void *)addr
))
1603 args
->addr_ptr
= (uint64_t) addr
;
1609 * i915_gem_fault - fault a page into the GTT
1610 * vma: VMA in question
1613 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1614 * from userspace. The fault handler takes care of binding the object to
1615 * the GTT (if needed), allocating and programming a fence register (again,
1616 * only if needed based on whether the old reg is still valid or the object
1617 * is tiled) and inserting a new PTE into the faulting process.
1619 * Note that the faulting process may involve evicting existing objects
1620 * from the GTT and/or fence registers to make room. So performance may
1621 * suffer if the GTT working set is large or there are few fence registers
1624 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1626 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1627 struct drm_device
*dev
= obj
->base
.dev
;
1628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1629 pgoff_t page_offset
;
1632 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1634 intel_runtime_pm_get(dev_priv
);
1636 /* We don't use vmf->pgoff since that has the fake offset */
1637 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1640 ret
= i915_mutex_lock_interruptible(dev
);
1644 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1646 /* Try to flush the object off the GPU first without holding the lock.
1647 * Upon reacquiring the lock, we will perform our sanity checks and then
1648 * repeat the flush holding the lock in the normal manner to catch cases
1649 * where we are gazumped.
1651 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1655 /* Access to snoopable pages through the GTT is incoherent. */
1656 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1661 /* Now bind it into the GTT if needed */
1662 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1666 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1670 ret
= i915_gem_object_get_fence(obj
);
1674 /* Finally, remap it using the new GTT offset */
1675 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1678 if (!obj
->fault_mappable
) {
1679 unsigned long size
= min_t(unsigned long,
1680 vma
->vm_end
- vma
->vm_start
,
1684 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1685 ret
= vm_insert_pfn(vma
,
1686 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1692 obj
->fault_mappable
= true;
1694 ret
= vm_insert_pfn(vma
,
1695 (unsigned long)vmf
->virtual_address
,
1698 i915_gem_object_ggtt_unpin(obj
);
1700 mutex_unlock(&dev
->struct_mutex
);
1705 * We eat errors when the gpu is terminally wedged to avoid
1706 * userspace unduly crashing (gl has no provisions for mmaps to
1707 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1708 * and so needs to be reported.
1710 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1711 ret
= VM_FAULT_SIGBUS
;
1716 * EAGAIN means the gpu is hung and we'll wait for the error
1717 * handler to reset everything when re-faulting in
1718 * i915_mutex_lock_interruptible.
1725 * EBUSY is ok: this just means that another thread
1726 * already did the job.
1728 ret
= VM_FAULT_NOPAGE
;
1735 ret
= VM_FAULT_SIGBUS
;
1738 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1739 ret
= VM_FAULT_SIGBUS
;
1743 intel_runtime_pm_put(dev_priv
);
1748 * i915_gem_release_mmap - remove physical page mappings
1749 * @obj: obj in question
1751 * Preserve the reservation of the mmapping with the DRM core code, but
1752 * relinquish ownership of the pages back to the system.
1754 * It is vital that we remove the page mapping if we have mapped a tiled
1755 * object through the GTT and then lose the fence register due to
1756 * resource pressure. Similarly if the object has been moved out of the
1757 * aperture, than pages mapped into userspace must be revoked. Removing the
1758 * mapping will then trigger a page fault on the next user access, allowing
1759 * fixup by i915_gem_fault().
1762 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1764 if (!obj
->fault_mappable
)
1767 drm_vma_node_unmap(&obj
->base
.vma_node
,
1768 obj
->base
.dev
->anon_inode
->i_mapping
);
1769 obj
->fault_mappable
= false;
1773 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1775 struct drm_i915_gem_object
*obj
;
1777 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1778 i915_gem_release_mmap(obj
);
1782 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1786 if (INTEL_INFO(dev
)->gen
>= 4 ||
1787 tiling_mode
== I915_TILING_NONE
)
1790 /* Previous chips need a power-of-two fence region when tiling */
1791 if (INTEL_INFO(dev
)->gen
== 3)
1792 gtt_size
= 1024*1024;
1794 gtt_size
= 512*1024;
1796 while (gtt_size
< size
)
1803 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1804 * @obj: object to check
1806 * Return the required GTT alignment for an object, taking into account
1807 * potential fence register mapping.
1810 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1811 int tiling_mode
, bool fenced
)
1814 * Minimum alignment is 4k (GTT page size), but might be greater
1815 * if a fence register is needed for the object.
1817 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1818 tiling_mode
== I915_TILING_NONE
)
1822 * Previous chips need to be aligned to the size of the smallest
1823 * fence register that can contain the object.
1825 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1828 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1830 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1833 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1836 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1838 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1842 /* Badly fragmented mmap space? The only way we can recover
1843 * space is by destroying unwanted objects. We can't randomly release
1844 * mmap_offsets as userspace expects them to be persistent for the
1845 * lifetime of the objects. The closest we can is to release the
1846 * offsets on purgeable objects by truncating it and marking it purged,
1847 * which prevents userspace from ever using that object again.
1849 i915_gem_shrink(dev_priv
,
1850 obj
->base
.size
>> PAGE_SHIFT
,
1852 I915_SHRINK_UNBOUND
|
1853 I915_SHRINK_PURGEABLE
);
1854 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1858 i915_gem_shrink_all(dev_priv
);
1859 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1861 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1866 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1868 drm_gem_free_mmap_offset(&obj
->base
);
1872 i915_gem_mmap_gtt(struct drm_file
*file
,
1873 struct drm_device
*dev
,
1877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1878 struct drm_i915_gem_object
*obj
;
1881 ret
= i915_mutex_lock_interruptible(dev
);
1885 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1886 if (&obj
->base
== NULL
) {
1891 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1896 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1897 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1902 ret
= i915_gem_object_create_mmap_offset(obj
);
1906 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1909 drm_gem_object_unreference(&obj
->base
);
1911 mutex_unlock(&dev
->struct_mutex
);
1916 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1918 * @data: GTT mapping ioctl data
1919 * @file: GEM object info
1921 * Simply returns the fake offset to userspace so it can mmap it.
1922 * The mmap call will end up in drm_gem_mmap(), which will set things
1923 * up so we can get faults in the handler above.
1925 * The fault handler will take care of binding the object into the GTT
1926 * (since it may have been evicted to make room for something), allocating
1927 * a fence register, and mapping the appropriate aperture address into
1931 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1932 struct drm_file
*file
)
1934 struct drm_i915_gem_mmap_gtt
*args
= data
;
1936 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1940 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1942 return obj
->madv
== I915_MADV_DONTNEED
;
1945 /* Immediately discard the backing storage */
1947 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1949 i915_gem_object_free_mmap_offset(obj
);
1951 if (obj
->base
.filp
== NULL
)
1954 /* Our goal here is to return as much of the memory as
1955 * is possible back to the system as we are called from OOM.
1956 * To do this we must instruct the shmfs to drop all of its
1957 * backing pages, *now*.
1959 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1960 obj
->madv
= __I915_MADV_PURGED
;
1963 /* Try to discard unwanted pages */
1965 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1967 struct address_space
*mapping
;
1969 switch (obj
->madv
) {
1970 case I915_MADV_DONTNEED
:
1971 i915_gem_object_truncate(obj
);
1972 case __I915_MADV_PURGED
:
1976 if (obj
->base
.filp
== NULL
)
1979 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1980 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1984 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1986 struct sg_page_iter sg_iter
;
1989 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1991 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1993 /* In the event of a disaster, abandon all caches and
1994 * hope for the best.
1996 WARN_ON(ret
!= -EIO
);
1997 i915_gem_clflush_object(obj
, true);
1998 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2001 if (i915_gem_object_needs_bit17_swizzle(obj
))
2002 i915_gem_object_save_bit_17_swizzle(obj
);
2004 if (obj
->madv
== I915_MADV_DONTNEED
)
2007 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2008 struct page
*page
= sg_page_iter_page(&sg_iter
);
2011 set_page_dirty(page
);
2013 if (obj
->madv
== I915_MADV_WILLNEED
)
2014 mark_page_accessed(page
);
2016 page_cache_release(page
);
2020 sg_free_table(obj
->pages
);
2025 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2027 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2029 if (obj
->pages
== NULL
)
2032 if (obj
->pages_pin_count
)
2035 BUG_ON(i915_gem_obj_bound_any(obj
));
2037 /* ->put_pages might need to allocate memory for the bit17 swizzle
2038 * array, hence protect them from being reaped by removing them from gtt
2040 list_del(&obj
->global_list
);
2042 ops
->put_pages(obj
);
2045 i915_gem_object_invalidate(obj
);
2051 i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2052 long target
, unsigned flags
)
2055 struct list_head
*list
;
2058 { &dev_priv
->mm
.unbound_list
, I915_SHRINK_UNBOUND
},
2059 { &dev_priv
->mm
.bound_list
, I915_SHRINK_BOUND
},
2062 unsigned long count
= 0;
2065 * As we may completely rewrite the (un)bound list whilst unbinding
2066 * (due to retiring requests) we have to strictly process only
2067 * one element of the list at the time, and recheck the list
2068 * on every iteration.
2070 * In particular, we must hold a reference whilst removing the
2071 * object as we may end up waiting for and/or retiring the objects.
2072 * This might release the final reference (held by the active list)
2073 * and result in the object being freed from under us. This is
2074 * similar to the precautions the eviction code must take whilst
2077 * Also note that although these lists do not hold a reference to
2078 * the object we can safely grab one here: The final object
2079 * unreferencing and the bound_list are both protected by the
2080 * dev->struct_mutex and so we won't ever be able to observe an
2081 * object on the bound_list with a reference count equals 0.
2083 for (phase
= phases
; phase
->list
; phase
++) {
2084 struct list_head still_in_list
;
2086 if ((flags
& phase
->bit
) == 0)
2089 INIT_LIST_HEAD(&still_in_list
);
2090 while (count
< target
&& !list_empty(phase
->list
)) {
2091 struct drm_i915_gem_object
*obj
;
2092 struct i915_vma
*vma
, *v
;
2094 obj
= list_first_entry(phase
->list
,
2095 typeof(*obj
), global_list
);
2096 list_move_tail(&obj
->global_list
, &still_in_list
);
2098 if (flags
& I915_SHRINK_PURGEABLE
&&
2099 !i915_gem_object_is_purgeable(obj
))
2102 drm_gem_object_reference(&obj
->base
);
2104 /* For the unbound phase, this should be a no-op! */
2105 list_for_each_entry_safe(vma
, v
,
2106 &obj
->vma_list
, vma_link
)
2107 if (i915_vma_unbind(vma
))
2110 if (i915_gem_object_put_pages(obj
) == 0)
2111 count
+= obj
->base
.size
>> PAGE_SHIFT
;
2113 drm_gem_object_unreference(&obj
->base
);
2115 list_splice(&still_in_list
, phase
->list
);
2121 static unsigned long
2122 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
2124 i915_gem_evict_everything(dev_priv
->dev
);
2125 return i915_gem_shrink(dev_priv
, LONG_MAX
,
2126 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
);
2130 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2132 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2134 struct address_space
*mapping
;
2135 struct sg_table
*st
;
2136 struct scatterlist
*sg
;
2137 struct sg_page_iter sg_iter
;
2139 unsigned long last_pfn
= 0; /* suppress gcc warning */
2142 /* Assert that the object is not currently in any GPU domain. As it
2143 * wasn't in the GTT, there shouldn't be any way it could have been in
2146 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2147 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2149 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2153 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2154 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2159 /* Get the list of pages out of our struct file. They'll be pinned
2160 * at this point until we release them.
2162 * Fail silently without starting the shrinker
2164 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2165 gfp
= mapping_gfp_mask(mapping
);
2166 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2167 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2170 for (i
= 0; i
< page_count
; i
++) {
2171 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2173 i915_gem_shrink(dev_priv
,
2176 I915_SHRINK_UNBOUND
|
2177 I915_SHRINK_PURGEABLE
);
2178 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2181 /* We've tried hard to allocate the memory by reaping
2182 * our own buffer, now let the real VM do its job and
2183 * go down in flames if truly OOM.
2185 i915_gem_shrink_all(dev_priv
);
2186 page
= shmem_read_mapping_page(mapping
, i
);
2190 #ifdef CONFIG_SWIOTLB
2191 if (swiotlb_nr_tbl()) {
2193 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2198 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2202 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2204 sg
->length
+= PAGE_SIZE
;
2206 last_pfn
= page_to_pfn(page
);
2208 /* Check that the i965g/gm workaround works. */
2209 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2211 #ifdef CONFIG_SWIOTLB
2212 if (!swiotlb_nr_tbl())
2217 if (i915_gem_object_needs_bit17_swizzle(obj
))
2218 i915_gem_object_do_bit_17_swizzle(obj
);
2220 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2221 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2222 i915_gem_object_pin_pages(obj
);
2228 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2229 page_cache_release(sg_page_iter_page(&sg_iter
));
2233 /* shmemfs first checks if there is enough memory to allocate the page
2234 * and reports ENOSPC should there be insufficient, along with the usual
2235 * ENOMEM for a genuine allocation failure.
2237 * We use ENOSPC in our driver to mean that we have run out of aperture
2238 * space and so want to translate the error from shmemfs back to our
2239 * usual understanding of ENOMEM.
2241 if (PTR_ERR(page
) == -ENOSPC
)
2244 return PTR_ERR(page
);
2247 /* Ensure that the associated pages are gathered from the backing storage
2248 * and pinned into our object. i915_gem_object_get_pages() may be called
2249 * multiple times before they are released by a single call to
2250 * i915_gem_object_put_pages() - once the pages are no longer referenced
2251 * either as a result of memory pressure (reaping pages under the shrinker)
2252 * or as the object is itself released.
2255 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2257 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2258 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2264 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2265 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2269 BUG_ON(obj
->pages_pin_count
);
2271 ret
= ops
->get_pages(obj
);
2275 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2280 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2281 struct intel_engine_cs
*ring
)
2283 struct drm_i915_gem_request
*req
;
2284 struct intel_engine_cs
*old_ring
;
2286 BUG_ON(ring
== NULL
);
2288 req
= intel_ring_get_request(ring
);
2289 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2291 if (old_ring
!= ring
&& obj
->last_write_req
) {
2292 /* Keep the request relative to the current ring */
2293 i915_gem_request_assign(&obj
->last_write_req
, req
);
2296 /* Add a reference if we're newly entering the active list. */
2298 drm_gem_object_reference(&obj
->base
);
2302 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2304 i915_gem_request_assign(&obj
->last_read_req
, req
);
2307 void i915_vma_move_to_active(struct i915_vma
*vma
,
2308 struct intel_engine_cs
*ring
)
2310 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2311 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2315 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2317 struct i915_vma
*vma
;
2319 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2320 BUG_ON(!obj
->active
);
2322 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2323 if (!list_empty(&vma
->mm_list
))
2324 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2327 intel_fb_obj_flush(obj
, true);
2329 list_del_init(&obj
->ring_list
);
2331 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2332 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2333 obj
->base
.write_domain
= 0;
2335 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2338 drm_gem_object_unreference(&obj
->base
);
2340 WARN_ON(i915_verify_lists(dev
));
2344 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2346 if (obj
->last_read_req
== NULL
)
2349 if (i915_gem_request_completed(obj
->last_read_req
, true))
2350 i915_gem_object_move_to_inactive(obj
);
2354 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2357 struct intel_engine_cs
*ring
;
2360 /* Carefully retire all requests without writing to the rings */
2361 for_each_ring(ring
, dev_priv
, i
) {
2362 ret
= intel_ring_idle(ring
);
2366 i915_gem_retire_requests(dev
);
2368 /* Finally reset hw state */
2369 for_each_ring(ring
, dev_priv
, i
) {
2370 intel_ring_init_seqno(ring
, seqno
);
2372 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2373 ring
->semaphore
.sync_seqno
[j
] = 0;
2379 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2387 /* HWS page needs to be set less than what we
2388 * will inject to ring
2390 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2394 /* Carefully set the last_seqno value so that wrap
2395 * detection still works
2397 dev_priv
->next_seqno
= seqno
;
2398 dev_priv
->last_seqno
= seqno
- 1;
2399 if (dev_priv
->last_seqno
== 0)
2400 dev_priv
->last_seqno
--;
2406 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2410 /* reserve 0 for non-seqno */
2411 if (dev_priv
->next_seqno
== 0) {
2412 int ret
= i915_gem_init_seqno(dev
, 0);
2416 dev_priv
->next_seqno
= 1;
2419 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2423 int __i915_add_request(struct intel_engine_cs
*ring
,
2424 struct drm_file
*file
,
2425 struct drm_i915_gem_object
*obj
)
2427 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2428 struct drm_i915_gem_request
*request
;
2429 struct intel_ringbuffer
*ringbuf
;
2433 request
= ring
->outstanding_lazy_request
;
2434 if (WARN_ON(request
== NULL
))
2437 if (i915
.enable_execlists
) {
2438 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2440 ringbuf
= ring
->buffer
;
2442 request_start
= intel_ring_get_tail(ringbuf
);
2444 * Emit any outstanding flushes - execbuf can fail to emit the flush
2445 * after having emitted the batchbuffer command. Hence we need to fix
2446 * things up similar to emitting the lazy request. The difference here
2447 * is that the flush _must_ happen before the next request, no matter
2450 if (i915
.enable_execlists
) {
2451 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2455 ret
= intel_ring_flush_all_caches(ring
);
2460 /* Record the position of the start of the request so that
2461 * should we detect the updated seqno part-way through the
2462 * GPU processing the request, we never over-estimate the
2463 * position of the head.
2465 request
->postfix
= intel_ring_get_tail(ringbuf
);
2467 if (i915
.enable_execlists
) {
2468 ret
= ring
->emit_request(ringbuf
, request
);
2472 ret
= ring
->add_request(ring
);
2477 request
->head
= request_start
;
2478 request
->tail
= intel_ring_get_tail(ringbuf
);
2480 /* Whilst this request exists, batch_obj will be on the
2481 * active_list, and so will hold the active reference. Only when this
2482 * request is retired will the the batch_obj be moved onto the
2483 * inactive_list and lose its active reference. Hence we do not need
2484 * to explicitly hold another reference here.
2486 request
->batch_obj
= obj
;
2488 if (!i915
.enable_execlists
) {
2489 /* Hold a reference to the current context so that we can inspect
2490 * it later in case a hangcheck error event fires.
2492 request
->ctx
= ring
->last_context
;
2494 i915_gem_context_reference(request
->ctx
);
2497 request
->emitted_jiffies
= jiffies
;
2498 list_add_tail(&request
->list
, &ring
->request_list
);
2499 request
->file_priv
= NULL
;
2502 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2504 spin_lock(&file_priv
->mm
.lock
);
2505 request
->file_priv
= file_priv
;
2506 list_add_tail(&request
->client_list
,
2507 &file_priv
->mm
.request_list
);
2508 spin_unlock(&file_priv
->mm
.lock
);
2510 request
->pid
= get_pid(task_pid(current
));
2513 trace_i915_gem_request_add(request
);
2514 ring
->outstanding_lazy_request
= NULL
;
2516 i915_queue_hangcheck(ring
->dev
);
2518 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2519 queue_delayed_work(dev_priv
->wq
,
2520 &dev_priv
->mm
.retire_work
,
2521 round_jiffies_up_relative(HZ
));
2522 intel_mark_busy(dev_priv
->dev
);
2528 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2530 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2535 spin_lock(&file_priv
->mm
.lock
);
2536 list_del(&request
->client_list
);
2537 request
->file_priv
= NULL
;
2538 spin_unlock(&file_priv
->mm
.lock
);
2541 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2542 const struct intel_context
*ctx
)
2544 unsigned long elapsed
;
2546 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2548 if (ctx
->hang_stats
.banned
)
2551 if (ctx
->hang_stats
.ban_period_seconds
&&
2552 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2553 if (!i915_gem_context_is_default(ctx
)) {
2554 DRM_DEBUG("context hanging too fast, banning!\n");
2556 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2557 if (i915_stop_ring_allow_warn(dev_priv
))
2558 DRM_ERROR("gpu hanging too fast, banning!\n");
2566 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2567 struct intel_context
*ctx
,
2570 struct i915_ctx_hang_stats
*hs
;
2575 hs
= &ctx
->hang_stats
;
2578 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2580 hs
->guilty_ts
= get_seconds();
2582 hs
->batch_pending
++;
2586 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2588 list_del(&request
->list
);
2589 i915_gem_request_remove_from_client(request
);
2591 put_pid(request
->pid
);
2593 i915_gem_request_unreference(request
);
2596 void i915_gem_request_free(struct kref
*req_ref
)
2598 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2600 struct intel_context
*ctx
= req
->ctx
;
2603 if (i915
.enable_execlists
) {
2604 struct intel_engine_cs
*ring
= req
->ring
;
2606 if (ctx
!= ring
->default_context
)
2607 intel_lr_context_unpin(ring
, ctx
);
2610 i915_gem_context_unreference(ctx
);
2616 struct drm_i915_gem_request
*
2617 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2619 struct drm_i915_gem_request
*request
;
2621 list_for_each_entry(request
, &ring
->request_list
, list
) {
2622 if (i915_gem_request_completed(request
, false))
2631 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2632 struct intel_engine_cs
*ring
)
2634 struct drm_i915_gem_request
*request
;
2637 request
= i915_gem_find_active_request(ring
);
2639 if (request
== NULL
)
2642 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2644 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2646 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2647 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2650 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2651 struct intel_engine_cs
*ring
)
2653 while (!list_empty(&ring
->active_list
)) {
2654 struct drm_i915_gem_object
*obj
;
2656 obj
= list_first_entry(&ring
->active_list
,
2657 struct drm_i915_gem_object
,
2660 i915_gem_object_move_to_inactive(obj
);
2664 * Clear the execlists queue up before freeing the requests, as those
2665 * are the ones that keep the context and ringbuffer backing objects
2668 while (!list_empty(&ring
->execlist_queue
)) {
2669 struct drm_i915_gem_request
*submit_req
;
2671 submit_req
= list_first_entry(&ring
->execlist_queue
,
2672 struct drm_i915_gem_request
,
2674 list_del(&submit_req
->execlist_link
);
2675 intel_runtime_pm_put(dev_priv
);
2677 if (submit_req
->ctx
!= ring
->default_context
)
2678 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2680 i915_gem_request_unreference(submit_req
);
2684 * We must free the requests after all the corresponding objects have
2685 * been moved off active lists. Which is the same order as the normal
2686 * retire_requests function does. This is important if object hold
2687 * implicit references on things like e.g. ppgtt address spaces through
2690 while (!list_empty(&ring
->request_list
)) {
2691 struct drm_i915_gem_request
*request
;
2693 request
= list_first_entry(&ring
->request_list
,
2694 struct drm_i915_gem_request
,
2697 i915_gem_free_request(request
);
2700 /* This may not have been flushed before the reset, so clean it now */
2701 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2704 void i915_gem_restore_fences(struct drm_device
*dev
)
2706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2709 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2710 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2713 * Commit delayed tiling changes if we have an object still
2714 * attached to the fence, otherwise just clear the fence.
2717 i915_gem_object_update_fence(reg
->obj
, reg
,
2718 reg
->obj
->tiling_mode
);
2720 i915_gem_write_fence(dev
, i
, NULL
);
2725 void i915_gem_reset(struct drm_device
*dev
)
2727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2728 struct intel_engine_cs
*ring
;
2732 * Before we free the objects from the requests, we need to inspect
2733 * them for finding the guilty party. As the requests only borrow
2734 * their reference to the objects, the inspection must be done first.
2736 for_each_ring(ring
, dev_priv
, i
)
2737 i915_gem_reset_ring_status(dev_priv
, ring
);
2739 for_each_ring(ring
, dev_priv
, i
)
2740 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2742 i915_gem_context_reset(dev
);
2744 i915_gem_restore_fences(dev
);
2748 * This function clears the request list as sequence numbers are passed.
2751 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2753 if (list_empty(&ring
->request_list
))
2756 WARN_ON(i915_verify_lists(ring
->dev
));
2758 /* Move any buffers on the active list that are no longer referenced
2759 * by the ringbuffer to the flushing/inactive lists as appropriate,
2760 * before we free the context associated with the requests.
2762 while (!list_empty(&ring
->active_list
)) {
2763 struct drm_i915_gem_object
*obj
;
2765 obj
= list_first_entry(&ring
->active_list
,
2766 struct drm_i915_gem_object
,
2769 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2772 i915_gem_object_move_to_inactive(obj
);
2776 while (!list_empty(&ring
->request_list
)) {
2777 struct drm_i915_gem_request
*request
;
2779 request
= list_first_entry(&ring
->request_list
,
2780 struct drm_i915_gem_request
,
2783 if (!i915_gem_request_completed(request
, true))
2786 trace_i915_gem_request_retire(request
);
2788 /* We know the GPU must have read the request to have
2789 * sent us the seqno + interrupt, so use the position
2790 * of tail of the request to update the last known position
2793 request
->ringbuf
->last_retired_head
= request
->postfix
;
2795 i915_gem_free_request(request
);
2798 if (unlikely(ring
->trace_irq_req
&&
2799 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2800 ring
->irq_put(ring
);
2801 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2804 WARN_ON(i915_verify_lists(ring
->dev
));
2808 i915_gem_retire_requests(struct drm_device
*dev
)
2810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2811 struct intel_engine_cs
*ring
;
2815 for_each_ring(ring
, dev_priv
, i
) {
2816 i915_gem_retire_requests_ring(ring
);
2817 idle
&= list_empty(&ring
->request_list
);
2818 if (i915
.enable_execlists
) {
2819 unsigned long flags
;
2821 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2822 idle
&= list_empty(&ring
->execlist_queue
);
2823 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2825 intel_execlists_retire_requests(ring
);
2830 mod_delayed_work(dev_priv
->wq
,
2831 &dev_priv
->mm
.idle_work
,
2832 msecs_to_jiffies(100));
2838 i915_gem_retire_work_handler(struct work_struct
*work
)
2840 struct drm_i915_private
*dev_priv
=
2841 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2842 struct drm_device
*dev
= dev_priv
->dev
;
2845 /* Come back later if the device is busy... */
2847 if (mutex_trylock(&dev
->struct_mutex
)) {
2848 idle
= i915_gem_retire_requests(dev
);
2849 mutex_unlock(&dev
->struct_mutex
);
2852 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2853 round_jiffies_up_relative(HZ
));
2857 i915_gem_idle_work_handler(struct work_struct
*work
)
2859 struct drm_i915_private
*dev_priv
=
2860 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2862 intel_mark_idle(dev_priv
->dev
);
2866 * Ensures that an object will eventually get non-busy by flushing any required
2867 * write domains, emitting any outstanding lazy request and retiring and
2868 * completed requests.
2871 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2873 struct intel_engine_cs
*ring
;
2877 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2879 ret
= i915_gem_check_olr(obj
->last_read_req
);
2883 i915_gem_retire_requests_ring(ring
);
2890 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2891 * @DRM_IOCTL_ARGS: standard ioctl arguments
2893 * Returns 0 if successful, else an error is returned with the remaining time in
2894 * the timeout parameter.
2895 * -ETIME: object is still busy after timeout
2896 * -ERESTARTSYS: signal interrupted the wait
2897 * -ENONENT: object doesn't exist
2898 * Also possible, but rare:
2899 * -EAGAIN: GPU wedged
2901 * -ENODEV: Internal IRQ fail
2902 * -E?: The add request failed
2904 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2905 * non-zero timeout parameter the wait ioctl will wait for the given number of
2906 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2907 * without holding struct_mutex the object may become re-busied before this
2908 * function completes. A similar but shorter * race condition exists in the busy
2912 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2915 struct drm_i915_gem_wait
*args
= data
;
2916 struct drm_i915_gem_object
*obj
;
2917 struct drm_i915_gem_request
*req
;
2918 unsigned reset_counter
;
2921 if (args
->flags
!= 0)
2924 ret
= i915_mutex_lock_interruptible(dev
);
2928 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2929 if (&obj
->base
== NULL
) {
2930 mutex_unlock(&dev
->struct_mutex
);
2934 /* Need to make sure the object gets inactive eventually. */
2935 ret
= i915_gem_object_flush_active(obj
);
2939 if (!obj
->active
|| !obj
->last_read_req
)
2942 req
= obj
->last_read_req
;
2944 /* Do this after OLR check to make sure we make forward progress polling
2945 * on this IOCTL with a timeout == 0 (like busy ioctl)
2947 if (args
->timeout_ns
== 0) {
2952 drm_gem_object_unreference(&obj
->base
);
2953 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2954 i915_gem_request_reference(req
);
2955 mutex_unlock(&dev
->struct_mutex
);
2957 ret
= __i915_wait_request(req
, reset_counter
, true,
2958 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
2960 mutex_lock(&dev
->struct_mutex
);
2961 i915_gem_request_unreference(req
);
2962 mutex_unlock(&dev
->struct_mutex
);
2966 drm_gem_object_unreference(&obj
->base
);
2967 mutex_unlock(&dev
->struct_mutex
);
2972 * i915_gem_object_sync - sync an object to a ring.
2974 * @obj: object which may be in use on another ring.
2975 * @to: ring we wish to use the object on. May be NULL.
2977 * This code is meant to abstract object synchronization with the GPU.
2978 * Calling with NULL implies synchronizing the object with the CPU
2979 * rather than a particular GPU ring.
2981 * Returns 0 if successful, else propagates up the lower layer error.
2984 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2985 struct intel_engine_cs
*to
)
2987 struct intel_engine_cs
*from
;
2991 from
= i915_gem_request_get_ring(obj
->last_read_req
);
2993 if (from
== NULL
|| to
== from
)
2996 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2997 return i915_gem_object_wait_rendering(obj
, false);
2999 idx
= intel_ring_sync_index(from
, to
);
3001 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
3002 /* Optimization: Avoid semaphore sync when we are sure we already
3003 * waited for an object with higher seqno */
3004 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3007 ret
= i915_gem_check_olr(obj
->last_read_req
);
3011 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
3012 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3014 /* We use last_read_req because sync_to()
3015 * might have just caused seqno wrap under
3018 from
->semaphore
.sync_seqno
[idx
] =
3019 i915_gem_request_get_seqno(obj
->last_read_req
);
3024 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3026 u32 old_write_domain
, old_read_domains
;
3028 /* Force a pagefault for domain tracking on next user access */
3029 i915_gem_release_mmap(obj
);
3031 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3034 /* Wait for any direct GTT access to complete */
3037 old_read_domains
= obj
->base
.read_domains
;
3038 old_write_domain
= obj
->base
.write_domain
;
3040 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3041 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3043 trace_i915_gem_object_change_domain(obj
,
3048 int i915_vma_unbind(struct i915_vma
*vma
)
3050 struct drm_i915_gem_object
*obj
= vma
->obj
;
3051 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3054 if (list_empty(&vma
->vma_link
))
3057 if (!drm_mm_node_allocated(&vma
->node
)) {
3058 i915_gem_vma_destroy(vma
);
3065 BUG_ON(obj
->pages
== NULL
);
3067 ret
= i915_gem_object_finish_gpu(obj
);
3070 /* Continue on if we fail due to EIO, the GPU is hung so we
3071 * should be safe and we need to cleanup or else we might
3072 * cause memory corruption through use-after-free.
3075 if (i915_is_ggtt(vma
->vm
) &&
3076 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3077 i915_gem_object_finish_gtt(obj
);
3079 /* release the fence reg _after_ flushing */
3080 ret
= i915_gem_object_put_fence(obj
);
3085 trace_i915_vma_unbind(vma
);
3087 vma
->unbind_vma(vma
);
3089 list_del_init(&vma
->mm_list
);
3090 if (i915_is_ggtt(vma
->vm
)) {
3091 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3092 obj
->map_and_fenceable
= false;
3093 } else if (vma
->ggtt_view
.pages
) {
3094 sg_free_table(vma
->ggtt_view
.pages
);
3095 kfree(vma
->ggtt_view
.pages
);
3096 vma
->ggtt_view
.pages
= NULL
;
3100 drm_mm_remove_node(&vma
->node
);
3101 i915_gem_vma_destroy(vma
);
3103 /* Since the unbound list is global, only move to that list if
3104 * no more VMAs exist. */
3105 if (list_empty(&obj
->vma_list
)) {
3106 /* Throw away the active reference before
3107 * moving to the unbound list. */
3108 i915_gem_object_retire(obj
);
3110 i915_gem_gtt_finish_object(obj
);
3111 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3114 /* And finally now the object is completely decoupled from this vma,
3115 * we can drop its hold on the backing storage and allow it to be
3116 * reaped by the shrinker.
3118 i915_gem_object_unpin_pages(obj
);
3123 int i915_gpu_idle(struct drm_device
*dev
)
3125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3126 struct intel_engine_cs
*ring
;
3129 /* Flush everything onto the inactive list. */
3130 for_each_ring(ring
, dev_priv
, i
) {
3131 if (!i915
.enable_execlists
) {
3132 ret
= i915_switch_context(ring
, ring
->default_context
);
3137 ret
= intel_ring_idle(ring
);
3145 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3146 struct drm_i915_gem_object
*obj
)
3148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3150 int fence_pitch_shift
;
3152 if (INTEL_INFO(dev
)->gen
>= 6) {
3153 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3154 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3156 fence_reg
= FENCE_REG_965_0
;
3157 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3160 fence_reg
+= reg
* 8;
3162 /* To w/a incoherency with non-atomic 64-bit register updates,
3163 * we split the 64-bit update into two 32-bit writes. In order
3164 * for a partial fence not to be evaluated between writes, we
3165 * precede the update with write to turn off the fence register,
3166 * and only enable the fence as the last step.
3168 * For extra levels of paranoia, we make sure each step lands
3169 * before applying the next step.
3171 I915_WRITE(fence_reg
, 0);
3172 POSTING_READ(fence_reg
);
3175 u32 size
= i915_gem_obj_ggtt_size(obj
);
3178 /* Adjust fence size to match tiled area */
3179 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3180 uint32_t row_size
= obj
->stride
*
3181 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3182 size
= (size
/ row_size
) * row_size
;
3185 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3187 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3188 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3189 if (obj
->tiling_mode
== I915_TILING_Y
)
3190 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3191 val
|= I965_FENCE_REG_VALID
;
3193 I915_WRITE(fence_reg
+ 4, val
>> 32);
3194 POSTING_READ(fence_reg
+ 4);
3196 I915_WRITE(fence_reg
+ 0, val
);
3197 POSTING_READ(fence_reg
);
3199 I915_WRITE(fence_reg
+ 4, 0);
3200 POSTING_READ(fence_reg
+ 4);
3204 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3205 struct drm_i915_gem_object
*obj
)
3207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3211 u32 size
= i915_gem_obj_ggtt_size(obj
);
3215 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3216 (size
& -size
) != size
||
3217 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3218 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3219 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3221 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3226 /* Note: pitch better be a power of two tile widths */
3227 pitch_val
= obj
->stride
/ tile_width
;
3228 pitch_val
= ffs(pitch_val
) - 1;
3230 val
= i915_gem_obj_ggtt_offset(obj
);
3231 if (obj
->tiling_mode
== I915_TILING_Y
)
3232 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3233 val
|= I915_FENCE_SIZE_BITS(size
);
3234 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3235 val
|= I830_FENCE_REG_VALID
;
3240 reg
= FENCE_REG_830_0
+ reg
* 4;
3242 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3244 I915_WRITE(reg
, val
);
3248 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3249 struct drm_i915_gem_object
*obj
)
3251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3255 u32 size
= i915_gem_obj_ggtt_size(obj
);
3258 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3259 (size
& -size
) != size
||
3260 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3261 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3262 i915_gem_obj_ggtt_offset(obj
), size
);
3264 pitch_val
= obj
->stride
/ 128;
3265 pitch_val
= ffs(pitch_val
) - 1;
3267 val
= i915_gem_obj_ggtt_offset(obj
);
3268 if (obj
->tiling_mode
== I915_TILING_Y
)
3269 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3270 val
|= I830_FENCE_SIZE_BITS(size
);
3271 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3272 val
|= I830_FENCE_REG_VALID
;
3276 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3277 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3280 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3282 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3285 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3286 struct drm_i915_gem_object
*obj
)
3288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3290 /* Ensure that all CPU reads are completed before installing a fence
3291 * and all writes before removing the fence.
3293 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3296 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3297 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3298 obj
->stride
, obj
->tiling_mode
);
3301 i830_write_fence_reg(dev
, reg
, obj
);
3302 else if (IS_GEN3(dev
))
3303 i915_write_fence_reg(dev
, reg
, obj
);
3304 else if (INTEL_INFO(dev
)->gen
>= 4)
3305 i965_write_fence_reg(dev
, reg
, obj
);
3307 /* And similarly be paranoid that no direct access to this region
3308 * is reordered to before the fence is installed.
3310 if (i915_gem_object_needs_mb(obj
))
3314 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3315 struct drm_i915_fence_reg
*fence
)
3317 return fence
- dev_priv
->fence_regs
;
3320 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3321 struct drm_i915_fence_reg
*fence
,
3324 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3325 int reg
= fence_number(dev_priv
, fence
);
3327 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3330 obj
->fence_reg
= reg
;
3332 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3334 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3336 list_del_init(&fence
->lru_list
);
3338 obj
->fence_dirty
= false;
3342 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3344 if (obj
->last_fenced_req
) {
3345 int ret
= i915_wait_request(obj
->last_fenced_req
);
3349 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3356 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3358 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3359 struct drm_i915_fence_reg
*fence
;
3362 ret
= i915_gem_object_wait_fence(obj
);
3366 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3369 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3371 if (WARN_ON(fence
->pin_count
))
3374 i915_gem_object_fence_lost(obj
);
3375 i915_gem_object_update_fence(obj
, fence
, false);
3380 static struct drm_i915_fence_reg
*
3381 i915_find_fence_reg(struct drm_device
*dev
)
3383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3384 struct drm_i915_fence_reg
*reg
, *avail
;
3387 /* First try to find a free reg */
3389 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3390 reg
= &dev_priv
->fence_regs
[i
];
3394 if (!reg
->pin_count
)
3401 /* None available, try to steal one or wait for a user to finish */
3402 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3410 /* Wait for completion of pending flips which consume fences */
3411 if (intel_has_pending_fb_unpin(dev
))
3412 return ERR_PTR(-EAGAIN
);
3414 return ERR_PTR(-EDEADLK
);
3418 * i915_gem_object_get_fence - set up fencing for an object
3419 * @obj: object to map through a fence reg
3421 * When mapping objects through the GTT, userspace wants to be able to write
3422 * to them without having to worry about swizzling if the object is tiled.
3423 * This function walks the fence regs looking for a free one for @obj,
3424 * stealing one if it can't find any.
3426 * It then sets up the reg based on the object's properties: address, pitch
3427 * and tiling format.
3429 * For an untiled surface, this removes any existing fence.
3432 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3434 struct drm_device
*dev
= obj
->base
.dev
;
3435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3436 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3437 struct drm_i915_fence_reg
*reg
;
3440 /* Have we updated the tiling parameters upon the object and so
3441 * will need to serialise the write to the associated fence register?
3443 if (obj
->fence_dirty
) {
3444 ret
= i915_gem_object_wait_fence(obj
);
3449 /* Just update our place in the LRU if our fence is getting reused. */
3450 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3451 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3452 if (!obj
->fence_dirty
) {
3453 list_move_tail(®
->lru_list
,
3454 &dev_priv
->mm
.fence_list
);
3457 } else if (enable
) {
3458 if (WARN_ON(!obj
->map_and_fenceable
))
3461 reg
= i915_find_fence_reg(dev
);
3463 return PTR_ERR(reg
);
3466 struct drm_i915_gem_object
*old
= reg
->obj
;
3468 ret
= i915_gem_object_wait_fence(old
);
3472 i915_gem_object_fence_lost(old
);
3477 i915_gem_object_update_fence(obj
, reg
, enable
);
3482 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3483 unsigned long cache_level
)
3485 struct drm_mm_node
*gtt_space
= &vma
->node
;
3486 struct drm_mm_node
*other
;
3489 * On some machines we have to be careful when putting differing types
3490 * of snoopable memory together to avoid the prefetcher crossing memory
3491 * domains and dying. During vm initialisation, we decide whether or not
3492 * these constraints apply and set the drm_mm.color_adjust
3495 if (vma
->vm
->mm
.color_adjust
== NULL
)
3498 if (!drm_mm_node_allocated(gtt_space
))
3501 if (list_empty(>t_space
->node_list
))
3504 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3505 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3508 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3509 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3516 * Finds free space in the GTT aperture and binds the object there.
3518 static struct i915_vma
*
3519 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3520 struct i915_address_space
*vm
,
3521 const struct i915_ggtt_view
*ggtt_view
,
3525 struct drm_device
*dev
= obj
->base
.dev
;
3526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3527 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3528 unsigned long start
=
3529 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3531 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3532 struct i915_vma
*vma
;
3535 if(WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3536 return ERR_PTR(-EINVAL
);
3538 fence_size
= i915_gem_get_gtt_size(dev
,
3541 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3543 obj
->tiling_mode
, true);
3544 unfenced_alignment
=
3545 i915_gem_get_gtt_alignment(dev
,
3547 obj
->tiling_mode
, false);
3550 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3552 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3553 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3554 return ERR_PTR(-EINVAL
);
3557 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3559 /* If the object is bigger than the entire aperture, reject it early
3560 * before evicting everything in a vain attempt to find space.
3562 if (obj
->base
.size
> end
) {
3563 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3565 flags
& PIN_MAPPABLE
? "mappable" : "total",
3567 return ERR_PTR(-E2BIG
);
3570 ret
= i915_gem_object_get_pages(obj
);
3572 return ERR_PTR(ret
);
3574 i915_gem_object_pin_pages(obj
);
3576 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3577 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3583 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3587 DRM_MM_SEARCH_DEFAULT
,
3588 DRM_MM_CREATE_DEFAULT
);
3590 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3599 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3601 goto err_remove_node
;
3604 ret
= i915_gem_gtt_prepare_object(obj
);
3606 goto err_remove_node
;
3608 trace_i915_vma_bind(vma
, flags
);
3609 ret
= i915_vma_bind(vma
, obj
->cache_level
,
3610 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3612 goto err_finish_gtt
;
3614 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3615 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3620 i915_gem_gtt_finish_object(obj
);
3622 drm_mm_remove_node(&vma
->node
);
3624 i915_gem_vma_destroy(vma
);
3627 i915_gem_object_unpin_pages(obj
);
3632 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3635 /* If we don't have a page list set up, then we're not pinned
3636 * to GPU, and we can ignore the cache flush because it'll happen
3637 * again at bind time.
3639 if (obj
->pages
== NULL
)
3643 * Stolen memory is always coherent with the GPU as it is explicitly
3644 * marked as wc by the system, or the system is cache-coherent.
3646 if (obj
->stolen
|| obj
->phys_handle
)
3649 /* If the GPU is snooping the contents of the CPU cache,
3650 * we do not need to manually clear the CPU cache lines. However,
3651 * the caches are only snooped when the render cache is
3652 * flushed/invalidated. As we always have to emit invalidations
3653 * and flushes when moving into and out of the RENDER domain, correct
3654 * snooping behaviour occurs naturally as the result of our domain
3657 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3658 obj
->cache_dirty
= true;
3662 trace_i915_gem_object_clflush(obj
);
3663 drm_clflush_sg(obj
->pages
);
3664 obj
->cache_dirty
= false;
3669 /** Flushes the GTT write domain for the object if it's dirty. */
3671 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3673 uint32_t old_write_domain
;
3675 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3678 /* No actual flushing is required for the GTT write domain. Writes
3679 * to it immediately go to main memory as far as we know, so there's
3680 * no chipset flush. It also doesn't land in render cache.
3682 * However, we do have to enforce the order so that all writes through
3683 * the GTT land before any writes to the device, such as updates to
3688 old_write_domain
= obj
->base
.write_domain
;
3689 obj
->base
.write_domain
= 0;
3691 intel_fb_obj_flush(obj
, false);
3693 trace_i915_gem_object_change_domain(obj
,
3694 obj
->base
.read_domains
,
3698 /** Flushes the CPU write domain for the object if it's dirty. */
3700 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3702 uint32_t old_write_domain
;
3704 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3707 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3708 i915_gem_chipset_flush(obj
->base
.dev
);
3710 old_write_domain
= obj
->base
.write_domain
;
3711 obj
->base
.write_domain
= 0;
3713 intel_fb_obj_flush(obj
, false);
3715 trace_i915_gem_object_change_domain(obj
,
3716 obj
->base
.read_domains
,
3721 * Moves a single object to the GTT read, and possibly write domain.
3723 * This function returns when the move is complete, including waiting on
3727 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3729 uint32_t old_write_domain
, old_read_domains
;
3730 struct i915_vma
*vma
;
3733 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3736 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3740 i915_gem_object_retire(obj
);
3742 /* Flush and acquire obj->pages so that we are coherent through
3743 * direct access in memory with previous cached writes through
3744 * shmemfs and that our cache domain tracking remains valid.
3745 * For example, if the obj->filp was moved to swap without us
3746 * being notified and releasing the pages, we would mistakenly
3747 * continue to assume that the obj remained out of the CPU cached
3750 ret
= i915_gem_object_get_pages(obj
);
3754 i915_gem_object_flush_cpu_write_domain(obj
);
3756 /* Serialise direct access to this object with the barriers for
3757 * coherent writes from the GPU, by effectively invalidating the
3758 * GTT domain upon first access.
3760 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3763 old_write_domain
= obj
->base
.write_domain
;
3764 old_read_domains
= obj
->base
.read_domains
;
3766 /* It should now be out of any other write domains, and we can update
3767 * the domain values for our changes.
3769 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3770 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3772 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3773 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3778 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
3780 trace_i915_gem_object_change_domain(obj
,
3784 /* And bump the LRU for this access */
3785 vma
= i915_gem_obj_to_ggtt(obj
);
3786 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3787 list_move_tail(&vma
->mm_list
,
3788 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3793 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3794 enum i915_cache_level cache_level
)
3796 struct drm_device
*dev
= obj
->base
.dev
;
3797 struct i915_vma
*vma
, *next
;
3800 if (obj
->cache_level
== cache_level
)
3803 if (i915_gem_obj_is_pinned(obj
)) {
3804 DRM_DEBUG("can not change the cache level of pinned objects\n");
3808 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3809 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3810 ret
= i915_vma_unbind(vma
);
3816 if (i915_gem_obj_bound_any(obj
)) {
3817 ret
= i915_gem_object_finish_gpu(obj
);
3821 i915_gem_object_finish_gtt(obj
);
3823 /* Before SandyBridge, you could not use tiling or fence
3824 * registers with snooped memory, so relinquish any fences
3825 * currently pointing to our region in the aperture.
3827 if (INTEL_INFO(dev
)->gen
< 6) {
3828 ret
= i915_gem_object_put_fence(obj
);
3833 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3834 if (drm_mm_node_allocated(&vma
->node
)) {
3835 ret
= i915_vma_bind(vma
, cache_level
,
3836 vma
->bound
& GLOBAL_BIND
);
3842 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3843 vma
->node
.color
= cache_level
;
3844 obj
->cache_level
= cache_level
;
3846 if (obj
->cache_dirty
&&
3847 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3848 cpu_write_needs_clflush(obj
)) {
3849 if (i915_gem_clflush_object(obj
, true))
3850 i915_gem_chipset_flush(obj
->base
.dev
);
3856 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3857 struct drm_file
*file
)
3859 struct drm_i915_gem_caching
*args
= data
;
3860 struct drm_i915_gem_object
*obj
;
3863 ret
= i915_mutex_lock_interruptible(dev
);
3867 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3868 if (&obj
->base
== NULL
) {
3873 switch (obj
->cache_level
) {
3874 case I915_CACHE_LLC
:
3875 case I915_CACHE_L3_LLC
:
3876 args
->caching
= I915_CACHING_CACHED
;
3880 args
->caching
= I915_CACHING_DISPLAY
;
3884 args
->caching
= I915_CACHING_NONE
;
3888 drm_gem_object_unreference(&obj
->base
);
3890 mutex_unlock(&dev
->struct_mutex
);
3894 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3895 struct drm_file
*file
)
3897 struct drm_i915_gem_caching
*args
= data
;
3898 struct drm_i915_gem_object
*obj
;
3899 enum i915_cache_level level
;
3902 switch (args
->caching
) {
3903 case I915_CACHING_NONE
:
3904 level
= I915_CACHE_NONE
;
3906 case I915_CACHING_CACHED
:
3907 level
= I915_CACHE_LLC
;
3909 case I915_CACHING_DISPLAY
:
3910 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3916 ret
= i915_mutex_lock_interruptible(dev
);
3920 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3921 if (&obj
->base
== NULL
) {
3926 ret
= i915_gem_object_set_cache_level(obj
, level
);
3928 drm_gem_object_unreference(&obj
->base
);
3930 mutex_unlock(&dev
->struct_mutex
);
3934 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3936 struct i915_vma
*vma
;
3938 vma
= i915_gem_obj_to_ggtt(obj
);
3942 /* There are 2 sources that pin objects:
3943 * 1. The display engine (scanouts, sprites, cursors);
3944 * 2. Reservations for execbuffer;
3946 * We can ignore reservations as we hold the struct_mutex and
3947 * are only called outside of the reservation path.
3949 return vma
->pin_count
;
3953 * Prepare buffer for display plane (scanout, cursors, etc).
3954 * Can be called from an uninterruptible phase (modesetting) and allows
3955 * any flushes to be pipelined (for pageflips).
3958 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3960 struct intel_engine_cs
*pipelined
)
3962 u32 old_read_domains
, old_write_domain
;
3963 bool was_pin_display
;
3966 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3967 ret
= i915_gem_object_sync(obj
, pipelined
);
3972 /* Mark the pin_display early so that we account for the
3973 * display coherency whilst setting up the cache domains.
3975 was_pin_display
= obj
->pin_display
;
3976 obj
->pin_display
= true;
3978 /* The display engine is not coherent with the LLC cache on gen6. As
3979 * a result, we make sure that the pinning that is about to occur is
3980 * done with uncached PTEs. This is lowest common denominator for all
3983 * However for gen6+, we could do better by using the GFDT bit instead
3984 * of uncaching, which would allow us to flush all the LLC-cached data
3985 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3987 ret
= i915_gem_object_set_cache_level(obj
,
3988 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3990 goto err_unpin_display
;
3992 /* As the user may map the buffer once pinned in the display plane
3993 * (e.g. libkms for the bootup splash), we have to ensure that we
3994 * always use map_and_fenceable for all scanout buffers.
3996 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3998 goto err_unpin_display
;
4000 i915_gem_object_flush_cpu_write_domain(obj
);
4002 old_write_domain
= obj
->base
.write_domain
;
4003 old_read_domains
= obj
->base
.read_domains
;
4005 /* It should now be out of any other write domains, and we can update
4006 * the domain values for our changes.
4008 obj
->base
.write_domain
= 0;
4009 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4011 trace_i915_gem_object_change_domain(obj
,
4018 WARN_ON(was_pin_display
!= is_pin_display(obj
));
4019 obj
->pin_display
= was_pin_display
;
4024 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
4026 i915_gem_object_ggtt_unpin(obj
);
4027 obj
->pin_display
= is_pin_display(obj
);
4031 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4035 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4038 ret
= i915_gem_object_wait_rendering(obj
, false);
4042 /* Ensure that we invalidate the GPU's caches and TLBs. */
4043 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4048 * Moves a single object to the CPU read, and possibly write domain.
4050 * This function returns when the move is complete, including waiting on
4054 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4056 uint32_t old_write_domain
, old_read_domains
;
4059 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4062 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4066 i915_gem_object_retire(obj
);
4067 i915_gem_object_flush_gtt_write_domain(obj
);
4069 old_write_domain
= obj
->base
.write_domain
;
4070 old_read_domains
= obj
->base
.read_domains
;
4072 /* Flush the CPU cache if it's still invalid. */
4073 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4074 i915_gem_clflush_object(obj
, false);
4076 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4079 /* It should now be out of any other write domains, and we can update
4080 * the domain values for our changes.
4082 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4084 /* If we're writing through the CPU, then the GPU read domains will
4085 * need to be invalidated at next use.
4088 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4089 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4093 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4095 trace_i915_gem_object_change_domain(obj
,
4102 /* Throttle our rendering by waiting until the ring has completed our requests
4103 * emitted over 20 msec ago.
4105 * Note that if we were to use the current jiffies each time around the loop,
4106 * we wouldn't escape the function with any frames outstanding if the time to
4107 * render a frame was over 20ms.
4109 * This should get us reasonable parallelism between CPU and GPU but also
4110 * relatively low latency when blocking on a particular request to finish.
4113 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4116 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4117 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4118 struct drm_i915_gem_request
*request
, *target
= NULL
;
4119 unsigned reset_counter
;
4122 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4126 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4130 spin_lock(&file_priv
->mm
.lock
);
4131 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4132 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4137 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4139 i915_gem_request_reference(target
);
4140 spin_unlock(&file_priv
->mm
.lock
);
4145 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4147 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4149 mutex_lock(&dev
->struct_mutex
);
4150 i915_gem_request_unreference(target
);
4151 mutex_unlock(&dev
->struct_mutex
);
4157 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4159 struct drm_i915_gem_object
*obj
= vma
->obj
;
4162 vma
->node
.start
& (alignment
- 1))
4165 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4168 if (flags
& PIN_OFFSET_BIAS
&&
4169 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4176 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4177 struct i915_address_space
*vm
,
4178 const struct i915_ggtt_view
*ggtt_view
,
4182 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4183 struct i915_vma
*vma
;
4187 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4190 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4193 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4196 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4199 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4200 i915_gem_obj_to_vma(obj
, vm
);
4203 return PTR_ERR(vma
);
4206 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4209 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4210 unsigned long offset
;
4211 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
->type
) :
4212 i915_gem_obj_offset(obj
, vm
);
4213 WARN(vma
->pin_count
,
4214 "bo is already pinned in %s with incorrect alignment:"
4215 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4216 " obj->map_and_fenceable=%d\n",
4217 ggtt_view
? "ggtt" : "ppgtt",
4220 !!(flags
& PIN_MAPPABLE
),
4221 obj
->map_and_fenceable
);
4222 ret
= i915_vma_unbind(vma
);
4230 bound
= vma
? vma
->bound
: 0;
4231 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4232 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4235 return PTR_ERR(vma
);
4238 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
)) {
4239 ret
= i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
);
4244 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4245 bool mappable
, fenceable
;
4246 u32 fence_size
, fence_alignment
;
4248 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4251 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4256 fenceable
= (vma
->node
.size
== fence_size
&&
4257 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4259 mappable
= (vma
->node
.start
+ fence_size
<=
4260 dev_priv
->gtt
.mappable_end
);
4262 obj
->map_and_fenceable
= mappable
&& fenceable
;
4265 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4268 if (flags
& PIN_MAPPABLE
)
4269 obj
->pin_mappable
|= true;
4275 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4276 struct i915_address_space
*vm
,
4280 return i915_gem_object_do_pin(obj
, vm
,
4281 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4286 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4287 const struct i915_ggtt_view
*view
,
4291 if (WARN_ONCE(!view
, "no view specified"))
4294 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4299 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4301 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4304 BUG_ON(vma
->pin_count
== 0);
4305 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4307 if (--vma
->pin_count
== 0)
4308 obj
->pin_mappable
= false;
4312 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4314 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4315 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4316 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4318 WARN_ON(!ggtt_vma
||
4319 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4320 ggtt_vma
->pin_count
);
4321 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4328 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4330 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4331 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4332 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4333 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4338 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4339 struct drm_file
*file
)
4341 struct drm_i915_gem_busy
*args
= data
;
4342 struct drm_i915_gem_object
*obj
;
4345 ret
= i915_mutex_lock_interruptible(dev
);
4349 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4350 if (&obj
->base
== NULL
) {
4355 /* Count all active objects as busy, even if they are currently not used
4356 * by the gpu. Users of this interface expect objects to eventually
4357 * become non-busy without any further actions, therefore emit any
4358 * necessary flushes here.
4360 ret
= i915_gem_object_flush_active(obj
);
4362 args
->busy
= obj
->active
;
4363 if (obj
->last_read_req
) {
4364 struct intel_engine_cs
*ring
;
4365 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4366 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4367 args
->busy
|= intel_ring_flag(ring
) << 16;
4370 drm_gem_object_unreference(&obj
->base
);
4372 mutex_unlock(&dev
->struct_mutex
);
4377 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4378 struct drm_file
*file_priv
)
4380 return i915_gem_ring_throttle(dev
, file_priv
);
4384 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4385 struct drm_file
*file_priv
)
4387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4388 struct drm_i915_gem_madvise
*args
= data
;
4389 struct drm_i915_gem_object
*obj
;
4392 switch (args
->madv
) {
4393 case I915_MADV_DONTNEED
:
4394 case I915_MADV_WILLNEED
:
4400 ret
= i915_mutex_lock_interruptible(dev
);
4404 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4405 if (&obj
->base
== NULL
) {
4410 if (i915_gem_obj_is_pinned(obj
)) {
4416 obj
->tiling_mode
!= I915_TILING_NONE
&&
4417 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4418 if (obj
->madv
== I915_MADV_WILLNEED
)
4419 i915_gem_object_unpin_pages(obj
);
4420 if (args
->madv
== I915_MADV_WILLNEED
)
4421 i915_gem_object_pin_pages(obj
);
4424 if (obj
->madv
!= __I915_MADV_PURGED
)
4425 obj
->madv
= args
->madv
;
4427 /* if the object is no longer attached, discard its backing storage */
4428 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4429 i915_gem_object_truncate(obj
);
4431 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4434 drm_gem_object_unreference(&obj
->base
);
4436 mutex_unlock(&dev
->struct_mutex
);
4440 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4441 const struct drm_i915_gem_object_ops
*ops
)
4443 INIT_LIST_HEAD(&obj
->global_list
);
4444 INIT_LIST_HEAD(&obj
->ring_list
);
4445 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4446 INIT_LIST_HEAD(&obj
->vma_list
);
4447 INIT_LIST_HEAD(&obj
->batch_pool_list
);
4451 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4452 obj
->madv
= I915_MADV_WILLNEED
;
4454 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4457 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4458 .get_pages
= i915_gem_object_get_pages_gtt
,
4459 .put_pages
= i915_gem_object_put_pages_gtt
,
4462 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4465 struct drm_i915_gem_object
*obj
;
4466 struct address_space
*mapping
;
4469 obj
= i915_gem_object_alloc(dev
);
4473 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4474 i915_gem_object_free(obj
);
4478 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4479 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4480 /* 965gm cannot relocate objects above 4GiB. */
4481 mask
&= ~__GFP_HIGHMEM
;
4482 mask
|= __GFP_DMA32
;
4485 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4486 mapping_set_gfp_mask(mapping
, mask
);
4488 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4490 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4491 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4494 /* On some devices, we can have the GPU use the LLC (the CPU
4495 * cache) for about a 10% performance improvement
4496 * compared to uncached. Graphics requests other than
4497 * display scanout are coherent with the CPU in
4498 * accessing this cache. This means in this mode we
4499 * don't need to clflush on the CPU side, and on the
4500 * GPU side we only need to flush internal caches to
4501 * get data visible to the CPU.
4503 * However, we maintain the display planes as UC, and so
4504 * need to rebind when first used as such.
4506 obj
->cache_level
= I915_CACHE_LLC
;
4508 obj
->cache_level
= I915_CACHE_NONE
;
4510 trace_i915_gem_object_create(obj
);
4515 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4517 /* If we are the last user of the backing storage (be it shmemfs
4518 * pages or stolen etc), we know that the pages are going to be
4519 * immediately released. In this case, we can then skip copying
4520 * back the contents from the GPU.
4523 if (obj
->madv
!= I915_MADV_WILLNEED
)
4526 if (obj
->base
.filp
== NULL
)
4529 /* At first glance, this looks racy, but then again so would be
4530 * userspace racing mmap against close. However, the first external
4531 * reference to the filp can only be obtained through the
4532 * i915_gem_mmap_ioctl() which safeguards us against the user
4533 * acquiring such a reference whilst we are in the middle of
4534 * freeing the object.
4536 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4539 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4541 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4542 struct drm_device
*dev
= obj
->base
.dev
;
4543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4544 struct i915_vma
*vma
, *next
;
4546 intel_runtime_pm_get(dev_priv
);
4548 trace_i915_gem_object_destroy(obj
);
4550 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4554 ret
= i915_vma_unbind(vma
);
4555 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4556 bool was_interruptible
;
4558 was_interruptible
= dev_priv
->mm
.interruptible
;
4559 dev_priv
->mm
.interruptible
= false;
4561 WARN_ON(i915_vma_unbind(vma
));
4563 dev_priv
->mm
.interruptible
= was_interruptible
;
4567 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4568 * before progressing. */
4570 i915_gem_object_unpin_pages(obj
);
4572 WARN_ON(obj
->frontbuffer_bits
);
4574 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4575 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4576 obj
->tiling_mode
!= I915_TILING_NONE
)
4577 i915_gem_object_unpin_pages(obj
);
4579 if (WARN_ON(obj
->pages_pin_count
))
4580 obj
->pages_pin_count
= 0;
4581 if (discard_backing_storage(obj
))
4582 obj
->madv
= I915_MADV_DONTNEED
;
4583 i915_gem_object_put_pages(obj
);
4584 i915_gem_object_free_mmap_offset(obj
);
4588 if (obj
->base
.import_attach
)
4589 drm_prime_gem_destroy(&obj
->base
, NULL
);
4591 if (obj
->ops
->release
)
4592 obj
->ops
->release(obj
);
4594 drm_gem_object_release(&obj
->base
);
4595 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4598 i915_gem_object_free(obj
);
4600 intel_runtime_pm_put(dev_priv
);
4603 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4604 struct i915_address_space
*vm
)
4606 struct i915_vma
*vma
;
4607 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4608 if (i915_is_ggtt(vma
->vm
) &&
4609 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4617 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4618 const struct i915_ggtt_view
*view
)
4620 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4621 struct i915_vma
*vma
;
4623 if (WARN_ONCE(!view
, "no view specified"))
4624 return ERR_PTR(-EINVAL
);
4626 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4627 if (vma
->vm
== ggtt
&& vma
->ggtt_view
.type
== view
->type
)
4632 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4634 struct i915_address_space
*vm
= NULL
;
4635 WARN_ON(vma
->node
.allocated
);
4637 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4638 if (!list_empty(&vma
->exec_list
))
4643 if (!i915_is_ggtt(vm
))
4644 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4646 list_del(&vma
->vma_link
);
4652 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4655 struct intel_engine_cs
*ring
;
4658 for_each_ring(ring
, dev_priv
, i
)
4659 dev_priv
->gt
.stop_ring(ring
);
4663 i915_gem_suspend(struct drm_device
*dev
)
4665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4668 mutex_lock(&dev
->struct_mutex
);
4669 ret
= i915_gpu_idle(dev
);
4673 i915_gem_retire_requests(dev
);
4675 i915_gem_stop_ringbuffers(dev
);
4676 mutex_unlock(&dev
->struct_mutex
);
4678 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4679 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4680 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4682 /* Assert that we sucessfully flushed all the work and
4683 * reset the GPU back to its idle, low power state.
4685 WARN_ON(dev_priv
->mm
.busy
);
4690 mutex_unlock(&dev
->struct_mutex
);
4694 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4696 struct drm_device
*dev
= ring
->dev
;
4697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4698 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4699 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4702 if (!HAS_L3_DPF(dev
) || !remap_info
)
4705 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4710 * Note: We do not worry about the concurrent register cacheline hang
4711 * here because no other code should access these registers other than
4712 * at initialization time.
4714 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4715 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4716 intel_ring_emit(ring
, reg_base
+ i
);
4717 intel_ring_emit(ring
, remap_info
[i
/4]);
4720 intel_ring_advance(ring
);
4725 void i915_gem_init_swizzling(struct drm_device
*dev
)
4727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4729 if (INTEL_INFO(dev
)->gen
< 5 ||
4730 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4733 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4734 DISP_TILE_SURFACE_SWIZZLING
);
4739 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4741 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4742 else if (IS_GEN7(dev
))
4743 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4744 else if (IS_GEN8(dev
))
4745 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4751 intel_enable_blt(struct drm_device
*dev
)
4756 /* The blitter was dysfunctional on early prototypes */
4757 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4758 DRM_INFO("BLT not supported on this pre-production hardware;"
4759 " graphics performance will be degraded.\n");
4766 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4770 I915_WRITE(RING_CTL(base
), 0);
4771 I915_WRITE(RING_HEAD(base
), 0);
4772 I915_WRITE(RING_TAIL(base
), 0);
4773 I915_WRITE(RING_START(base
), 0);
4776 static void init_unused_rings(struct drm_device
*dev
)
4779 init_unused_ring(dev
, PRB1_BASE
);
4780 init_unused_ring(dev
, SRB0_BASE
);
4781 init_unused_ring(dev
, SRB1_BASE
);
4782 init_unused_ring(dev
, SRB2_BASE
);
4783 init_unused_ring(dev
, SRB3_BASE
);
4784 } else if (IS_GEN2(dev
)) {
4785 init_unused_ring(dev
, SRB0_BASE
);
4786 init_unused_ring(dev
, SRB1_BASE
);
4787 } else if (IS_GEN3(dev
)) {
4788 init_unused_ring(dev
, PRB1_BASE
);
4789 init_unused_ring(dev
, PRB2_BASE
);
4793 int i915_gem_init_rings(struct drm_device
*dev
)
4795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4798 ret
= intel_init_render_ring_buffer(dev
);
4803 ret
= intel_init_bsd_ring_buffer(dev
);
4805 goto cleanup_render_ring
;
4808 if (intel_enable_blt(dev
)) {
4809 ret
= intel_init_blt_ring_buffer(dev
);
4811 goto cleanup_bsd_ring
;
4814 if (HAS_VEBOX(dev
)) {
4815 ret
= intel_init_vebox_ring_buffer(dev
);
4817 goto cleanup_blt_ring
;
4820 if (HAS_BSD2(dev
)) {
4821 ret
= intel_init_bsd2_ring_buffer(dev
);
4823 goto cleanup_vebox_ring
;
4826 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4828 goto cleanup_bsd2_ring
;
4833 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4835 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4837 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4839 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4840 cleanup_render_ring
:
4841 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4847 i915_gem_init_hw(struct drm_device
*dev
)
4849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4850 struct intel_engine_cs
*ring
;
4853 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4856 /* Double layer security blanket, see i915_gem_init() */
4857 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4859 if (dev_priv
->ellc_size
)
4860 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4862 if (IS_HASWELL(dev
))
4863 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4864 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4866 if (HAS_PCH_NOP(dev
)) {
4867 if (IS_IVYBRIDGE(dev
)) {
4868 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4869 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4870 I915_WRITE(GEN7_MSG_CTL
, temp
);
4871 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4872 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4873 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4874 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4878 i915_gem_init_swizzling(dev
);
4881 * At least 830 can leave some of the unused rings
4882 * "active" (ie. head != tail) after resume which
4883 * will prevent c3 entry. Makes sure all unused rings
4886 init_unused_rings(dev
);
4888 for_each_ring(ring
, dev_priv
, i
) {
4889 ret
= ring
->init_hw(ring
);
4894 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4895 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4897 ret
= i915_ppgtt_init_hw(dev
);
4898 if (ret
&& ret
!= -EIO
) {
4899 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4900 i915_gem_cleanup_ringbuffer(dev
);
4903 ret
= i915_gem_context_enable(dev_priv
);
4904 if (ret
&& ret
!= -EIO
) {
4905 DRM_ERROR("Context enable failed %d\n", ret
);
4906 i915_gem_cleanup_ringbuffer(dev
);
4912 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4916 int i915_gem_init(struct drm_device
*dev
)
4918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4921 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4922 i915
.enable_execlists
);
4924 mutex_lock(&dev
->struct_mutex
);
4926 if (IS_VALLEYVIEW(dev
)) {
4927 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4928 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4929 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4930 VLV_GTLC_ALLOWWAKEACK
), 10))
4931 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4934 if (!i915
.enable_execlists
) {
4935 dev_priv
->gt
.do_execbuf
= i915_gem_ringbuffer_submission
;
4936 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4937 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4938 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4940 dev_priv
->gt
.do_execbuf
= intel_execlists_submission
;
4941 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4942 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4943 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4946 /* This is just a security blanket to placate dragons.
4947 * On some systems, we very sporadically observe that the first TLBs
4948 * used by the CS may be stale, despite us poking the TLB reset. If
4949 * we hold the forcewake during initialisation these problems
4950 * just magically go away.
4952 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4954 ret
= i915_gem_init_userptr(dev
);
4958 i915_gem_init_global_gtt(dev
);
4960 ret
= i915_gem_context_init(dev
);
4964 ret
= dev_priv
->gt
.init_rings(dev
);
4968 ret
= i915_gem_init_hw(dev
);
4970 /* Allow ring initialisation to fail by marking the GPU as
4971 * wedged. But we only want to do this where the GPU is angry,
4972 * for all other failure, such as an allocation failure, bail.
4974 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4975 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4980 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4981 mutex_unlock(&dev
->struct_mutex
);
4987 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 struct intel_engine_cs
*ring
;
4993 for_each_ring(ring
, dev_priv
, i
)
4994 dev_priv
->gt
.cleanup_ring(ring
);
4998 init_ring_lists(struct intel_engine_cs
*ring
)
5000 INIT_LIST_HEAD(&ring
->active_list
);
5001 INIT_LIST_HEAD(&ring
->request_list
);
5004 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5005 struct i915_address_space
*vm
)
5007 if (!i915_is_ggtt(vm
))
5008 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5009 vm
->dev
= dev_priv
->dev
;
5010 INIT_LIST_HEAD(&vm
->active_list
);
5011 INIT_LIST_HEAD(&vm
->inactive_list
);
5012 INIT_LIST_HEAD(&vm
->global_link
);
5013 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5017 i915_gem_load(struct drm_device
*dev
)
5019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5023 kmem_cache_create("i915_gem_object",
5024 sizeof(struct drm_i915_gem_object
), 0,
5028 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5029 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5031 INIT_LIST_HEAD(&dev_priv
->context_list
);
5032 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5033 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5034 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5035 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5036 init_ring_lists(&dev_priv
->ring
[i
]);
5037 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5038 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5039 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5040 i915_gem_retire_work_handler
);
5041 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5042 i915_gem_idle_work_handler
);
5043 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5045 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5047 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5048 dev_priv
->num_fence_regs
= 32;
5049 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5050 dev_priv
->num_fence_regs
= 16;
5052 dev_priv
->num_fence_regs
= 8;
5054 if (intel_vgpu_active(dev
))
5055 dev_priv
->num_fence_regs
=
5056 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5058 /* Initialize fence registers to zero */
5059 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5060 i915_gem_restore_fences(dev
);
5062 i915_gem_detect_bit_6_swizzle(dev
);
5063 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5065 dev_priv
->mm
.interruptible
= true;
5067 dev_priv
->mm
.shrinker
.scan_objects
= i915_gem_shrinker_scan
;
5068 dev_priv
->mm
.shrinker
.count_objects
= i915_gem_shrinker_count
;
5069 dev_priv
->mm
.shrinker
.seeks
= DEFAULT_SEEKS
;
5070 register_shrinker(&dev_priv
->mm
.shrinker
);
5072 dev_priv
->mm
.oom_notifier
.notifier_call
= i915_gem_shrinker_oom
;
5073 register_oom_notifier(&dev_priv
->mm
.oom_notifier
);
5075 i915_gem_batch_pool_init(dev
, &dev_priv
->mm
.batch_pool
);
5077 mutex_init(&dev_priv
->fb_tracking
.lock
);
5080 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5082 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5084 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
5086 /* Clean up our request list when the client is going away, so that
5087 * later retire_requests won't dereference our soon-to-be-gone
5090 spin_lock(&file_priv
->mm
.lock
);
5091 while (!list_empty(&file_priv
->mm
.request_list
)) {
5092 struct drm_i915_gem_request
*request
;
5094 request
= list_first_entry(&file_priv
->mm
.request_list
,
5095 struct drm_i915_gem_request
,
5097 list_del(&request
->client_list
);
5098 request
->file_priv
= NULL
;
5100 spin_unlock(&file_priv
->mm
.lock
);
5104 i915_gem_file_idle_work_handler(struct work_struct
*work
)
5106 struct drm_i915_file_private
*file_priv
=
5107 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
5109 atomic_set(&file_priv
->rps_wait_boost
, false);
5112 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5114 struct drm_i915_file_private
*file_priv
;
5117 DRM_DEBUG_DRIVER("\n");
5119 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5123 file
->driver_priv
= file_priv
;
5124 file_priv
->dev_priv
= dev
->dev_private
;
5125 file_priv
->file
= file
;
5127 spin_lock_init(&file_priv
->mm
.lock
);
5128 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5129 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
5130 i915_gem_file_idle_work_handler
);
5132 ret
= i915_gem_context_open(dev
, file
);
5140 * i915_gem_track_fb - update frontbuffer tracking
5141 * old: current GEM buffer for the frontbuffer slots
5142 * new: new GEM buffer for the frontbuffer slots
5143 * frontbuffer_bits: bitmask of frontbuffer slots
5145 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5146 * from @old and setting them in @new. Both @old and @new can be NULL.
5148 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5149 struct drm_i915_gem_object
*new,
5150 unsigned frontbuffer_bits
)
5153 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5154 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5155 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5159 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5160 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5161 new->frontbuffer_bits
|= frontbuffer_bits
;
5165 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
5167 if (!mutex_is_locked(mutex
))
5170 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5171 return mutex
->owner
== task
;
5173 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5178 static bool i915_gem_shrinker_lock(struct drm_device
*dev
, bool *unlock
)
5180 if (!mutex_trylock(&dev
->struct_mutex
)) {
5181 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5184 if (to_i915(dev
)->mm
.shrinker_no_lock_stealing
)
5194 static int num_vma_bound(struct drm_i915_gem_object
*obj
)
5196 struct i915_vma
*vma
;
5199 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5200 if (drm_mm_node_allocated(&vma
->node
))
5206 static unsigned long
5207 i915_gem_shrinker_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5209 struct drm_i915_private
*dev_priv
=
5210 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5211 struct drm_device
*dev
= dev_priv
->dev
;
5212 struct drm_i915_gem_object
*obj
;
5213 unsigned long count
;
5216 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5220 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
5221 if (obj
->pages_pin_count
== 0)
5222 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5224 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5225 if (!i915_gem_obj_is_pinned(obj
) &&
5226 obj
->pages_pin_count
== num_vma_bound(obj
))
5227 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5231 mutex_unlock(&dev
->struct_mutex
);
5236 /* All the new VM stuff */
5238 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5239 struct i915_address_space
*vm
)
5241 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5242 struct i915_vma
*vma
;
5244 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5246 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5247 if (i915_is_ggtt(vma
->vm
) &&
5248 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5251 return vma
->node
.start
;
5254 WARN(1, "%s vma for this object not found.\n",
5255 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5260 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5261 enum i915_ggtt_view_type view
)
5263 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5264 struct i915_vma
*vma
;
5266 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5267 if (vma
->vm
== ggtt
&& vma
->ggtt_view
.type
== view
)
5268 return vma
->node
.start
;
5270 WARN(1, "global vma for this object not found.\n");
5274 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5275 struct i915_address_space
*vm
)
5277 struct i915_vma
*vma
;
5279 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5280 if (i915_is_ggtt(vma
->vm
) &&
5281 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5283 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5290 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5291 enum i915_ggtt_view_type view
)
5293 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5294 struct i915_vma
*vma
;
5296 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5297 if (vma
->vm
== ggtt
&&
5298 vma
->ggtt_view
.type
== view
&&
5299 drm_mm_node_allocated(&vma
->node
))
5305 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5307 struct i915_vma
*vma
;
5309 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5310 if (drm_mm_node_allocated(&vma
->node
))
5316 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5317 struct i915_address_space
*vm
)
5319 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5320 struct i915_vma
*vma
;
5322 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5324 BUG_ON(list_empty(&o
->vma_list
));
5326 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5327 if (i915_is_ggtt(vma
->vm
) &&
5328 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5331 return vma
->node
.size
;
5336 static unsigned long
5337 i915_gem_shrinker_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5339 struct drm_i915_private
*dev_priv
=
5340 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5341 struct drm_device
*dev
= dev_priv
->dev
;
5342 unsigned long freed
;
5345 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5348 freed
= i915_gem_shrink(dev_priv
,
5351 I915_SHRINK_UNBOUND
|
5352 I915_SHRINK_PURGEABLE
);
5353 if (freed
< sc
->nr_to_scan
)
5354 freed
+= i915_gem_shrink(dev_priv
,
5355 sc
->nr_to_scan
- freed
,
5357 I915_SHRINK_UNBOUND
);
5359 mutex_unlock(&dev
->struct_mutex
);
5365 i915_gem_shrinker_oom(struct notifier_block
*nb
, unsigned long event
, void *ptr
)
5367 struct drm_i915_private
*dev_priv
=
5368 container_of(nb
, struct drm_i915_private
, mm
.oom_notifier
);
5369 struct drm_device
*dev
= dev_priv
->dev
;
5370 struct drm_i915_gem_object
*obj
;
5371 unsigned long timeout
= msecs_to_jiffies(5000) + 1;
5372 unsigned long pinned
, bound
, unbound
, freed_pages
;
5373 bool was_interruptible
;
5376 while (!i915_gem_shrinker_lock(dev
, &unlock
) && --timeout
) {
5377 schedule_timeout_killable(1);
5378 if (fatal_signal_pending(current
))
5382 pr_err("Unable to purge GPU memory due lock contention.\n");
5386 was_interruptible
= dev_priv
->mm
.interruptible
;
5387 dev_priv
->mm
.interruptible
= false;
5389 freed_pages
= i915_gem_shrink_all(dev_priv
);
5391 dev_priv
->mm
.interruptible
= was_interruptible
;
5393 /* Because we may be allocating inside our own driver, we cannot
5394 * assert that there are no objects with pinned pages that are not
5395 * being pointed to by hardware.
5397 unbound
= bound
= pinned
= 0;
5398 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5399 if (!obj
->base
.filp
) /* not backed by a freeable object */
5402 if (obj
->pages_pin_count
)
5403 pinned
+= obj
->base
.size
;
5405 unbound
+= obj
->base
.size
;
5407 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5408 if (!obj
->base
.filp
)
5411 if (obj
->pages_pin_count
)
5412 pinned
+= obj
->base
.size
;
5414 bound
+= obj
->base
.size
;
5418 mutex_unlock(&dev
->struct_mutex
);
5420 if (freed_pages
|| unbound
|| bound
)
5421 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5422 freed_pages
<< PAGE_SHIFT
, pinned
);
5423 if (unbound
|| bound
)
5424 pr_err("%lu and %lu bytes still available in the "
5425 "bound and unbound GPU page lists.\n",
5428 *(unsigned long *)ptr
+= freed_pages
;
5432 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5434 struct i915_vma
*vma
;
5435 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
5436 if (i915_is_ggtt(vma
->vm
) &&
5437 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5439 if (vma
->pin_count
> 0)