2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret
< 0) {
118 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
123 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
127 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
131 WARN_ON(i915_verify_lists(dev
));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
138 return i915_gem_obj_ggtt_bound(obj
) && !obj
->active
;
142 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
143 struct drm_file
*file
)
145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 struct drm_i915_gem_init
*args
= data
;
148 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
151 if (args
->gtt_start
>= args
->gtt_end
||
152 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev
)->gen
>= 5)
159 mutex_lock(&dev
->struct_mutex
);
160 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
162 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
163 mutex_unlock(&dev
->struct_mutex
);
169 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
170 struct drm_file
*file
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct drm_i915_gem_get_aperture
*args
= data
;
174 struct drm_i915_gem_object
*obj
;
178 mutex_lock(&dev
->struct_mutex
);
179 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
181 pinned
+= i915_gem_obj_ggtt_size(obj
);
182 mutex_unlock(&dev
->struct_mutex
);
184 args
->aper_size
= dev_priv
->gtt
.total
;
185 args
->aper_available_size
= args
->aper_size
- pinned
;
190 void *i915_gem_object_alloc(struct drm_device
*dev
)
192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
193 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
196 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
198 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
199 kmem_cache_free(dev_priv
->slab
, obj
);
203 i915_gem_create(struct drm_file
*file
,
204 struct drm_device
*dev
,
208 struct drm_i915_gem_object
*obj
;
212 size
= roundup(size
, PAGE_SIZE
);
216 /* Allocate the new object */
217 obj
= i915_gem_alloc_object(dev
, size
);
221 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
223 drm_gem_object_release(&obj
->base
);
224 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
225 i915_gem_object_free(obj
);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj
->base
);
231 trace_i915_gem_object_create(obj
);
238 i915_gem_dumb_create(struct drm_file
*file
,
239 struct drm_device
*dev
,
240 struct drm_mode_create_dumb
*args
)
242 /* have to work out size/pitch and return them */
243 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
244 args
->size
= args
->pitch
* args
->height
;
245 return i915_gem_create(file
, dev
,
246 args
->size
, &args
->handle
);
249 int i915_gem_dumb_destroy(struct drm_file
*file
,
250 struct drm_device
*dev
,
253 return drm_gem_handle_delete(file
, handle
);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
261 struct drm_file
*file
)
263 struct drm_i915_gem_create
*args
= data
;
265 return i915_gem_create(file
, dev
,
266 args
->size
, &args
->handle
);
270 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
271 const char *gpu_vaddr
, int gpu_offset
,
274 int ret
, cpu_offset
= 0;
277 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
278 int this_length
= min(cacheline_end
- gpu_offset
, length
);
279 int swizzled_gpu_offset
= gpu_offset
^ 64;
281 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
282 gpu_vaddr
+ swizzled_gpu_offset
,
287 cpu_offset
+= this_length
;
288 gpu_offset
+= this_length
;
289 length
-= this_length
;
296 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
297 const char __user
*cpu_vaddr
,
300 int ret
, cpu_offset
= 0;
303 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
304 int this_length
= min(cacheline_end
- gpu_offset
, length
);
305 int swizzled_gpu_offset
= gpu_offset
^ 64;
307 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
308 cpu_vaddr
+ cpu_offset
,
313 cpu_offset
+= this_length
;
314 gpu_offset
+= this_length
;
315 length
-= this_length
;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
326 char __user
*user_data
,
327 bool page_do_bit17_swizzling
, bool needs_clflush
)
332 if (unlikely(page_do_bit17_swizzling
))
335 vaddr
= kmap_atomic(page
);
337 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
339 ret
= __copy_to_user_inatomic(user_data
,
340 vaddr
+ shmem_page_offset
,
342 kunmap_atomic(vaddr
);
344 return ret
? -EFAULT
: 0;
348 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
351 if (unlikely(swizzled
)) {
352 unsigned long start
= (unsigned long) addr
;
353 unsigned long end
= (unsigned long) addr
+ length
;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start
= round_down(start
, 128);
360 end
= round_up(end
, 128);
362 drm_clflush_virt_range((void *)start
, end
- start
);
364 drm_clflush_virt_range(addr
, length
);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
373 char __user
*user_data
,
374 bool page_do_bit17_swizzling
, bool needs_clflush
)
381 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
383 page_do_bit17_swizzling
);
385 if (page_do_bit17_swizzling
)
386 ret
= __copy_to_user_swizzled(user_data
,
387 vaddr
, shmem_page_offset
,
390 ret
= __copy_to_user(user_data
,
391 vaddr
+ shmem_page_offset
,
395 return ret
? - EFAULT
: 0;
399 i915_gem_shmem_pread(struct drm_device
*dev
,
400 struct drm_i915_gem_object
*obj
,
401 struct drm_i915_gem_pread
*args
,
402 struct drm_file
*file
)
404 char __user
*user_data
;
407 int shmem_page_offset
, page_length
, ret
= 0;
408 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
410 int needs_clflush
= 0;
411 struct sg_page_iter sg_iter
;
413 user_data
= to_user_ptr(args
->data_ptr
);
416 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
418 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj
->cache_level
== I915_CACHE_NONE
)
425 if (i915_gem_obj_ggtt_bound(obj
)) {
426 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
432 ret
= i915_gem_object_get_pages(obj
);
436 i915_gem_object_pin_pages(obj
);
438 offset
= args
->offset
;
440 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
441 offset
>> PAGE_SHIFT
) {
442 struct page
*page
= sg_page_iter_page(&sg_iter
);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset
= offset_in_page(offset
);
453 page_length
= remain
;
454 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
455 page_length
= PAGE_SIZE
- shmem_page_offset
;
457 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
458 (page_to_phys(page
) & (1 << 17)) != 0;
460 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
461 user_data
, page_do_bit17_swizzling
,
466 mutex_unlock(&dev
->struct_mutex
);
469 ret
= fault_in_multipages_writeable(user_data
, remain
);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
479 user_data
, page_do_bit17_swizzling
,
482 mutex_lock(&dev
->struct_mutex
);
485 mark_page_accessed(page
);
490 remain
-= page_length
;
491 user_data
+= page_length
;
492 offset
+= page_length
;
496 i915_gem_object_unpin_pages(obj
);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
508 struct drm_file
*file
)
510 struct drm_i915_gem_pread
*args
= data
;
511 struct drm_i915_gem_object
*obj
;
517 if (!access_ok(VERIFY_WRITE
,
518 to_user_ptr(args
->data_ptr
),
522 ret
= i915_mutex_lock_interruptible(dev
);
526 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
527 if (&obj
->base
== NULL
) {
532 /* Bounds check source. */
533 if (args
->offset
> obj
->base
.size
||
534 args
->size
> obj
->base
.size
- args
->offset
) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj
->base
.filp
) {
547 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
549 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
552 drm_gem_object_unreference(&obj
->base
);
554 mutex_unlock(&dev
->struct_mutex
);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping
*mapping
,
564 loff_t page_base
, int page_offset
,
565 char __user
*user_data
,
568 void __iomem
*vaddr_atomic
;
570 unsigned long unwritten
;
572 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
575 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
577 io_mapping_unmap_atomic(vaddr_atomic
);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
587 struct drm_i915_gem_object
*obj
,
588 struct drm_i915_gem_pwrite
*args
,
589 struct drm_file
*file
)
591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
593 loff_t offset
, page_base
;
594 char __user
*user_data
;
595 int page_offset
, page_length
, ret
;
597 ret
= i915_gem_object_pin(obj
, 0, true, true);
601 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
605 ret
= i915_gem_object_put_fence(obj
);
609 user_data
= to_user_ptr(args
->data_ptr
);
612 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base
= offset
& PAGE_MASK
;
622 page_offset
= offset_in_page(offset
);
623 page_length
= remain
;
624 if ((page_offset
+ remain
) > PAGE_SIZE
)
625 page_length
= PAGE_SIZE
- page_offset
;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
632 page_offset
, user_data
, page_length
)) {
637 remain
-= page_length
;
638 user_data
+= page_length
;
639 offset
+= page_length
;
643 i915_gem_object_unpin(obj
);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
654 char __user
*user_data
,
655 bool page_do_bit17_swizzling
,
656 bool needs_clflush_before
,
657 bool needs_clflush_after
)
662 if (unlikely(page_do_bit17_swizzling
))
665 vaddr
= kmap_atomic(page
);
666 if (needs_clflush_before
)
667 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
669 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
672 if (needs_clflush_after
)
673 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
675 kunmap_atomic(vaddr
);
677 return ret
? -EFAULT
: 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
684 char __user
*user_data
,
685 bool page_do_bit17_swizzling
,
686 bool needs_clflush_before
,
687 bool needs_clflush_after
)
693 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
694 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
696 page_do_bit17_swizzling
);
697 if (page_do_bit17_swizzling
)
698 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
702 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
705 if (needs_clflush_after
)
706 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
708 page_do_bit17_swizzling
);
711 return ret
? -EFAULT
: 0;
715 i915_gem_shmem_pwrite(struct drm_device
*dev
,
716 struct drm_i915_gem_object
*obj
,
717 struct drm_i915_gem_pwrite
*args
,
718 struct drm_file
*file
)
722 char __user
*user_data
;
723 int shmem_page_offset
, page_length
, ret
= 0;
724 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
725 int hit_slowpath
= 0;
726 int needs_clflush_after
= 0;
727 int needs_clflush_before
= 0;
728 struct sg_page_iter sg_iter
;
730 user_data
= to_user_ptr(args
->data_ptr
);
733 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
735 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj
->cache_level
== I915_CACHE_NONE
)
741 needs_clflush_after
= 1;
742 if (i915_gem_obj_ggtt_bound(obj
)) {
743 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
751 && obj
->cache_level
== I915_CACHE_NONE
)
752 needs_clflush_before
= 1;
754 ret
= i915_gem_object_get_pages(obj
);
758 i915_gem_object_pin_pages(obj
);
760 offset
= args
->offset
;
763 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
764 offset
>> PAGE_SHIFT
) {
765 struct page
*page
= sg_page_iter_page(&sg_iter
);
766 int partial_cacheline_write
;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset
= offset_in_page(offset
);
778 page_length
= remain
;
779 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
780 page_length
= PAGE_SIZE
- shmem_page_offset
;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write
= needs_clflush_before
&&
786 ((shmem_page_offset
| page_length
)
787 & (boot_cpu_data
.x86_clflush_size
- 1));
789 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
790 (page_to_phys(page
) & (1 << 17)) != 0;
792 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
793 user_data
, page_do_bit17_swizzling
,
794 partial_cacheline_write
,
795 needs_clflush_after
);
800 mutex_unlock(&dev
->struct_mutex
);
801 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
802 user_data
, page_do_bit17_swizzling
,
803 partial_cacheline_write
,
804 needs_clflush_after
);
806 mutex_lock(&dev
->struct_mutex
);
809 set_page_dirty(page
);
810 mark_page_accessed(page
);
815 remain
-= page_length
;
816 user_data
+= page_length
;
817 offset
+= page_length
;
821 i915_gem_object_unpin_pages(obj
);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after
&&
830 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
831 i915_gem_clflush_object(obj
);
832 i915_gem_chipset_flush(dev
);
836 if (needs_clflush_after
)
837 i915_gem_chipset_flush(dev
);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
849 struct drm_file
*file
)
851 struct drm_i915_gem_pwrite
*args
= data
;
852 struct drm_i915_gem_object
*obj
;
858 if (!access_ok(VERIFY_READ
,
859 to_user_ptr(args
->data_ptr
),
863 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
868 ret
= i915_mutex_lock_interruptible(dev
);
872 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
873 if (&obj
->base
== NULL
) {
878 /* Bounds check destination. */
879 if (args
->offset
> obj
->base
.size
||
880 args
->size
> obj
->base
.size
- args
->offset
) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj
->base
.filp
) {
893 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
907 if (obj
->cache_level
== I915_CACHE_NONE
&&
908 obj
->tiling_mode
== I915_TILING_NONE
&&
909 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
910 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
917 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
920 drm_gem_object_unreference(&obj
->base
);
922 mutex_unlock(&dev
->struct_mutex
);
927 i915_gem_check_wedge(struct i915_gpu_error
*error
,
930 if (i915_reset_in_progress(error
)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error
))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
955 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
958 if (seqno
== ring
->outstanding_lazy_request
)
959 ret
= i915_add_request(ring
, NULL
);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
983 unsigned reset_counter
,
984 bool interruptible
, struct timespec
*timeout
)
986 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
987 struct timespec before
, now
, wait_time
={1,0};
988 unsigned long timeout_jiffies
;
990 bool wait_forever
= true;
993 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
996 trace_i915_gem_request_wait_begin(ring
, seqno
);
998 if (timeout
!= NULL
) {
999 wait_time
= *timeout
;
1000 wait_forever
= false;
1003 timeout_jiffies
= timespec_to_jiffies_timeout(&wait_time
);
1005 if (WARN_ON(!ring
->irq_get(ring
)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before
);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1021 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1034 } while (end
== 0 && wait_forever
);
1036 getrawmonotonic(&now
);
1038 ring
->irq_put(ring
);
1039 trace_i915_gem_request_wait_end(ring
, seqno
);
1043 struct timespec sleep_time
= timespec_sub(now
, before
);
1044 *timeout
= timespec_sub(*timeout
, sleep_time
);
1045 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout
, 0, 0);
1051 case -EAGAIN
: /* Wedged */
1052 case -ERESTARTSYS
: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end
< 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1069 struct drm_device
*dev
= ring
->dev
;
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 bool interruptible
= dev_priv
->mm
.interruptible
;
1074 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1077 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1081 ret
= i915_gem_check_olr(ring
, seqno
);
1085 return __wait_seqno(ring
, seqno
,
1086 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1087 interruptible
, NULL
);
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1092 struct intel_ring_buffer
*ring
)
1094 i915_gem_retire_requests_ring(ring
);
1096 /* Manually manage the write flush as we may have not yet
1097 * retired the buffer.
1099 * Note that the last_write_seqno is always the earlier of
1100 * the two (read/write) seqno, so if we haved successfully waited,
1101 * we know we have passed the last write.
1103 obj
->last_write_seqno
= 0;
1104 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1110 * Ensures that all rendering to the object has completed and the object is
1111 * safe to unbind from the GTT or access from the CPU.
1113 static __must_check
int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1117 struct intel_ring_buffer
*ring
= obj
->ring
;
1121 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1125 ret
= i915_wait_seqno(ring
, seqno
);
1129 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133 * as the object state may change during this call.
1135 static __must_check
int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1139 struct drm_device
*dev
= obj
->base
.dev
;
1140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1141 struct intel_ring_buffer
*ring
= obj
->ring
;
1142 unsigned reset_counter
;
1146 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1147 BUG_ON(!dev_priv
->mm
.interruptible
);
1149 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1153 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1157 ret
= i915_gem_check_olr(ring
, seqno
);
1161 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1162 mutex_unlock(&dev
->struct_mutex
);
1163 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1164 mutex_lock(&dev
->struct_mutex
);
1168 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1172 * Called when user space prepares to use an object with the CPU, either
1173 * through the mmap ioctl's mapping or a GTT mapping.
1176 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1177 struct drm_file
*file
)
1179 struct drm_i915_gem_set_domain
*args
= data
;
1180 struct drm_i915_gem_object
*obj
;
1181 uint32_t read_domains
= args
->read_domains
;
1182 uint32_t write_domain
= args
->write_domain
;
1185 /* Only handle setting domains to types used by the CPU. */
1186 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1189 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1192 /* Having something in the write domain implies it's in the read
1193 * domain, and only that read domain. Enforce that in the request.
1195 if (write_domain
!= 0 && read_domains
!= write_domain
)
1198 ret
= i915_mutex_lock_interruptible(dev
);
1202 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1203 if (&obj
->base
== NULL
) {
1208 /* Try to flush the object off the GPU without holding the lock.
1209 * We will repeat the flush holding the lock in the normal manner
1210 * to catch cases where we are gazumped.
1212 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1216 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1217 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1219 /* Silently promote "you're not bound, there was nothing to do"
1220 * to success, since the client was just asking us to
1221 * make sure everything was done.
1226 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1230 drm_gem_object_unreference(&obj
->base
);
1232 mutex_unlock(&dev
->struct_mutex
);
1237 * Called when user space has done writes to this buffer
1240 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1241 struct drm_file
*file
)
1243 struct drm_i915_gem_sw_finish
*args
= data
;
1244 struct drm_i915_gem_object
*obj
;
1247 ret
= i915_mutex_lock_interruptible(dev
);
1251 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1252 if (&obj
->base
== NULL
) {
1257 /* Pinned buffers may be scanout, so flush the cache */
1259 i915_gem_object_flush_cpu_write_domain(obj
);
1261 drm_gem_object_unreference(&obj
->base
);
1263 mutex_unlock(&dev
->struct_mutex
);
1268 * Maps the contents of an object, returning the address it is mapped
1271 * While the mapping holds a reference on the contents of the object, it doesn't
1272 * imply a ref on the object itself.
1275 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1276 struct drm_file
*file
)
1278 struct drm_i915_gem_mmap
*args
= data
;
1279 struct drm_gem_object
*obj
;
1282 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1286 /* prime objects have no backing filp to GEM mmap
1290 drm_gem_object_unreference_unlocked(obj
);
1294 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1295 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1297 drm_gem_object_unreference_unlocked(obj
);
1298 if (IS_ERR((void *)addr
))
1301 args
->addr_ptr
= (uint64_t) addr
;
1307 * i915_gem_fault - fault a page into the GTT
1308 * vma: VMA in question
1311 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312 * from userspace. The fault handler takes care of binding the object to
1313 * the GTT (if needed), allocating and programming a fence register (again,
1314 * only if needed based on whether the old reg is still valid or the object
1315 * is tiled) and inserting a new PTE into the faulting process.
1317 * Note that the faulting process may involve evicting existing objects
1318 * from the GTT and/or fence registers to make room. So performance may
1319 * suffer if the GTT working set is large or there are few fence registers
1322 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1324 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1325 struct drm_device
*dev
= obj
->base
.dev
;
1326 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1327 pgoff_t page_offset
;
1330 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1332 /* We don't use vmf->pgoff since that has the fake offset */
1333 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1336 ret
= i915_mutex_lock_interruptible(dev
);
1340 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1342 /* Access to snoopable pages through the GTT is incoherent. */
1343 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1348 /* Now bind it into the GTT if needed */
1349 ret
= i915_gem_object_pin(obj
, 0, true, false);
1353 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1357 ret
= i915_gem_object_get_fence(obj
);
1361 obj
->fault_mappable
= true;
1363 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1367 /* Finally, remap it using the new GTT offset */
1368 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1370 i915_gem_object_unpin(obj
);
1372 mutex_unlock(&dev
->struct_mutex
);
1376 /* If this -EIO is due to a gpu hang, give the reset code a
1377 * chance to clean up the mess. Otherwise return the proper
1379 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1380 return VM_FAULT_SIGBUS
;
1382 /* Give the error handler a chance to run and move the
1383 * objects off the GPU active list. Next time we service the
1384 * fault, we should be able to transition the page into the
1385 * GTT without touching the GPU (and so avoid further
1386 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1387 * with coherency, just lost writes.
1395 * EBUSY is ok: this just means that another thread
1396 * already did the job.
1398 return VM_FAULT_NOPAGE
;
1400 return VM_FAULT_OOM
;
1402 return VM_FAULT_SIGBUS
;
1404 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1405 return VM_FAULT_SIGBUS
;
1410 * i915_gem_release_mmap - remove physical page mappings
1411 * @obj: obj in question
1413 * Preserve the reservation of the mmapping with the DRM core code, but
1414 * relinquish ownership of the pages back to the system.
1416 * It is vital that we remove the page mapping if we have mapped a tiled
1417 * object through the GTT and then lose the fence register due to
1418 * resource pressure. Similarly if the object has been moved out of the
1419 * aperture, than pages mapped into userspace must be revoked. Removing the
1420 * mapping will then trigger a page fault on the next user access, allowing
1421 * fixup by i915_gem_fault().
1424 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1426 if (!obj
->fault_mappable
)
1429 if (obj
->base
.dev
->dev_mapping
)
1430 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1431 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1434 obj
->fault_mappable
= false;
1438 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1442 if (INTEL_INFO(dev
)->gen
>= 4 ||
1443 tiling_mode
== I915_TILING_NONE
)
1446 /* Previous chips need a power-of-two fence region when tiling */
1447 if (INTEL_INFO(dev
)->gen
== 3)
1448 gtt_size
= 1024*1024;
1450 gtt_size
= 512*1024;
1452 while (gtt_size
< size
)
1459 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1460 * @obj: object to check
1462 * Return the required GTT alignment for an object, taking into account
1463 * potential fence register mapping.
1466 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1467 int tiling_mode
, bool fenced
)
1470 * Minimum alignment is 4k (GTT page size), but might be greater
1471 * if a fence register is needed for the object.
1473 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1474 tiling_mode
== I915_TILING_NONE
)
1478 * Previous chips need to be aligned to the size of the smallest
1479 * fence register that can contain the object.
1481 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1484 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1486 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1489 if (obj
->base
.map_list
.map
)
1492 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1494 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1498 /* Badly fragmented mmap space? The only way we can recover
1499 * space is by destroying unwanted objects. We can't randomly release
1500 * mmap_offsets as userspace expects them to be persistent for the
1501 * lifetime of the objects. The closest we can is to release the
1502 * offsets on purgeable objects by truncating it and marking it purged,
1503 * which prevents userspace from ever using that object again.
1505 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1506 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1510 i915_gem_shrink_all(dev_priv
);
1511 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1513 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1518 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1520 if (!obj
->base
.map_list
.map
)
1523 drm_gem_free_mmap_offset(&obj
->base
);
1527 i915_gem_mmap_gtt(struct drm_file
*file
,
1528 struct drm_device
*dev
,
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 struct drm_i915_gem_object
*obj
;
1536 ret
= i915_mutex_lock_interruptible(dev
);
1540 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1541 if (&obj
->base
== NULL
) {
1546 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1551 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1552 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1557 ret
= i915_gem_object_create_mmap_offset(obj
);
1561 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1564 drm_gem_object_unreference(&obj
->base
);
1566 mutex_unlock(&dev
->struct_mutex
);
1571 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1573 * @data: GTT mapping ioctl data
1574 * @file: GEM object info
1576 * Simply returns the fake offset to userspace so it can mmap it.
1577 * The mmap call will end up in drm_gem_mmap(), which will set things
1578 * up so we can get faults in the handler above.
1580 * The fault handler will take care of binding the object into the GTT
1581 * (since it may have been evicted to make room for something), allocating
1582 * a fence register, and mapping the appropriate aperture address into
1586 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1587 struct drm_file
*file
)
1589 struct drm_i915_gem_mmap_gtt
*args
= data
;
1591 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1594 /* Immediately discard the backing storage */
1596 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1598 struct inode
*inode
;
1600 i915_gem_object_free_mmap_offset(obj
);
1602 if (obj
->base
.filp
== NULL
)
1605 /* Our goal here is to return as much of the memory as
1606 * is possible back to the system as we are called from OOM.
1607 * To do this we must instruct the shmfs to drop all of its
1608 * backing pages, *now*.
1610 inode
= file_inode(obj
->base
.filp
);
1611 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1613 obj
->madv
= __I915_MADV_PURGED
;
1617 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1619 return obj
->madv
== I915_MADV_DONTNEED
;
1623 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1625 struct sg_page_iter sg_iter
;
1628 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1630 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1632 /* In the event of a disaster, abandon all caches and
1633 * hope for the best.
1635 WARN_ON(ret
!= -EIO
);
1636 i915_gem_clflush_object(obj
);
1637 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1640 if (i915_gem_object_needs_bit17_swizzle(obj
))
1641 i915_gem_object_save_bit_17_swizzle(obj
);
1643 if (obj
->madv
== I915_MADV_DONTNEED
)
1646 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1647 struct page
*page
= sg_page_iter_page(&sg_iter
);
1650 set_page_dirty(page
);
1652 if (obj
->madv
== I915_MADV_WILLNEED
)
1653 mark_page_accessed(page
);
1655 page_cache_release(page
);
1659 sg_free_table(obj
->pages
);
1664 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1666 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1668 if (obj
->pages
== NULL
)
1671 BUG_ON(i915_gem_obj_ggtt_bound(obj
));
1673 if (obj
->pages_pin_count
)
1676 /* ->put_pages might need to allocate memory for the bit17 swizzle
1677 * array, hence protect them from being reaped by removing them from gtt
1679 list_del(&obj
->global_list
);
1681 ops
->put_pages(obj
);
1684 if (i915_gem_object_is_purgeable(obj
))
1685 i915_gem_object_truncate(obj
);
1691 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1692 bool purgeable_only
)
1694 struct drm_i915_gem_object
*obj
, *next
;
1697 list_for_each_entry_safe(obj
, next
,
1698 &dev_priv
->mm
.unbound_list
,
1700 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1701 i915_gem_object_put_pages(obj
) == 0) {
1702 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1703 if (count
>= target
)
1708 list_for_each_entry_safe(obj
, next
,
1709 &dev_priv
->mm
.inactive_list
,
1711 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1712 i915_gem_object_unbind(obj
) == 0 &&
1713 i915_gem_object_put_pages(obj
) == 0) {
1714 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1715 if (count
>= target
)
1724 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1726 return __i915_gem_shrink(dev_priv
, target
, true);
1730 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1732 struct drm_i915_gem_object
*obj
, *next
;
1734 i915_gem_evict_everything(dev_priv
->dev
);
1736 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1738 i915_gem_object_put_pages(obj
);
1742 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1744 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1746 struct address_space
*mapping
;
1747 struct sg_table
*st
;
1748 struct scatterlist
*sg
;
1749 struct sg_page_iter sg_iter
;
1751 unsigned long last_pfn
= 0; /* suppress gcc warning */
1754 /* Assert that the object is not currently in any GPU domain. As it
1755 * wasn't in the GTT, there shouldn't be any way it could have been in
1758 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1759 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1761 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1765 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1766 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1772 /* Get the list of pages out of our struct file. They'll be pinned
1773 * at this point until we release them.
1775 * Fail silently without starting the shrinker
1777 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1778 gfp
= mapping_gfp_mask(mapping
);
1779 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1780 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1783 for (i
= 0; i
< page_count
; i
++) {
1784 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1786 i915_gem_purge(dev_priv
, page_count
);
1787 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1790 /* We've tried hard to allocate the memory by reaping
1791 * our own buffer, now let the real VM do its job and
1792 * go down in flames if truly OOM.
1794 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1795 gfp
|= __GFP_IO
| __GFP_WAIT
;
1797 i915_gem_shrink_all(dev_priv
);
1798 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1802 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1803 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1805 #ifdef CONFIG_SWIOTLB
1806 if (swiotlb_nr_tbl()) {
1808 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1813 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1817 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1819 sg
->length
+= PAGE_SIZE
;
1821 last_pfn
= page_to_pfn(page
);
1823 #ifdef CONFIG_SWIOTLB
1824 if (!swiotlb_nr_tbl())
1829 if (i915_gem_object_needs_bit17_swizzle(obj
))
1830 i915_gem_object_do_bit_17_swizzle(obj
);
1836 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1837 page_cache_release(sg_page_iter_page(&sg_iter
));
1840 return PTR_ERR(page
);
1843 /* Ensure that the associated pages are gathered from the backing storage
1844 * and pinned into our object. i915_gem_object_get_pages() may be called
1845 * multiple times before they are released by a single call to
1846 * i915_gem_object_put_pages() - once the pages are no longer referenced
1847 * either as a result of memory pressure (reaping pages under the shrinker)
1848 * or as the object is itself released.
1851 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1853 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1854 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1860 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1861 DRM_ERROR("Attempting to obtain a purgeable object\n");
1865 BUG_ON(obj
->pages_pin_count
);
1867 ret
= ops
->get_pages(obj
);
1871 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
1876 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1877 struct intel_ring_buffer
*ring
)
1879 struct drm_device
*dev
= obj
->base
.dev
;
1880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1881 u32 seqno
= intel_ring_get_seqno(ring
);
1883 BUG_ON(ring
== NULL
);
1886 /* Add a reference if we're newly entering the active list. */
1888 drm_gem_object_reference(&obj
->base
);
1892 /* Move from whatever list we were on to the tail of execution. */
1893 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1894 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1896 obj
->last_read_seqno
= seqno
;
1898 if (obj
->fenced_gpu_access
) {
1899 obj
->last_fenced_seqno
= seqno
;
1901 /* Bump MRU to take account of the delayed flush */
1902 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1903 struct drm_i915_fence_reg
*reg
;
1905 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1906 list_move_tail(®
->lru_list
,
1907 &dev_priv
->mm
.fence_list
);
1913 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1915 struct drm_device
*dev
= obj
->base
.dev
;
1916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1918 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1919 BUG_ON(!obj
->active
);
1921 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1923 list_del_init(&obj
->ring_list
);
1926 obj
->last_read_seqno
= 0;
1927 obj
->last_write_seqno
= 0;
1928 obj
->base
.write_domain
= 0;
1930 obj
->last_fenced_seqno
= 0;
1931 obj
->fenced_gpu_access
= false;
1934 drm_gem_object_unreference(&obj
->base
);
1936 WARN_ON(i915_verify_lists(dev
));
1940 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 struct intel_ring_buffer
*ring
;
1946 /* Carefully retire all requests without writing to the rings */
1947 for_each_ring(ring
, dev_priv
, i
) {
1948 ret
= intel_ring_idle(ring
);
1952 i915_gem_retire_requests(dev
);
1954 /* Finally reset hw state */
1955 for_each_ring(ring
, dev_priv
, i
) {
1956 intel_ring_init_seqno(ring
, seqno
);
1958 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1959 ring
->sync_seqno
[j
] = 0;
1965 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1973 /* HWS page needs to be set less than what we
1974 * will inject to ring
1976 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1980 /* Carefully set the last_seqno value so that wrap
1981 * detection still works
1983 dev_priv
->next_seqno
= seqno
;
1984 dev_priv
->last_seqno
= seqno
- 1;
1985 if (dev_priv
->last_seqno
== 0)
1986 dev_priv
->last_seqno
--;
1992 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1996 /* reserve 0 for non-seqno */
1997 if (dev_priv
->next_seqno
== 0) {
1998 int ret
= i915_gem_init_seqno(dev
, 0);
2002 dev_priv
->next_seqno
= 1;
2005 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2009 int __i915_add_request(struct intel_ring_buffer
*ring
,
2010 struct drm_file
*file
,
2011 struct drm_i915_gem_object
*obj
,
2014 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2015 struct drm_i915_gem_request
*request
;
2016 u32 request_ring_position
, request_start
;
2020 request_start
= intel_ring_get_tail(ring
);
2022 * Emit any outstanding flushes - execbuf can fail to emit the flush
2023 * after having emitted the batchbuffer command. Hence we need to fix
2024 * things up similar to emitting the lazy request. The difference here
2025 * is that the flush _must_ happen before the next request, no matter
2028 ret
= intel_ring_flush_all_caches(ring
);
2032 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2033 if (request
== NULL
)
2037 /* Record the position of the start of the request so that
2038 * should we detect the updated seqno part-way through the
2039 * GPU processing the request, we never over-estimate the
2040 * position of the head.
2042 request_ring_position
= intel_ring_get_tail(ring
);
2044 ret
= ring
->add_request(ring
);
2050 request
->seqno
= intel_ring_get_seqno(ring
);
2051 request
->ring
= ring
;
2052 request
->head
= request_start
;
2053 request
->tail
= request_ring_position
;
2054 request
->ctx
= ring
->last_context
;
2055 request
->batch_obj
= obj
;
2057 /* Whilst this request exists, batch_obj will be on the
2058 * active_list, and so will hold the active reference. Only when this
2059 * request is retired will the the batch_obj be moved onto the
2060 * inactive_list and lose its active reference. Hence we do not need
2061 * to explicitly hold another reference here.
2065 i915_gem_context_reference(request
->ctx
);
2067 request
->emitted_jiffies
= jiffies
;
2068 was_empty
= list_empty(&ring
->request_list
);
2069 list_add_tail(&request
->list
, &ring
->request_list
);
2070 request
->file_priv
= NULL
;
2073 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2075 spin_lock(&file_priv
->mm
.lock
);
2076 request
->file_priv
= file_priv
;
2077 list_add_tail(&request
->client_list
,
2078 &file_priv
->mm
.request_list
);
2079 spin_unlock(&file_priv
->mm
.lock
);
2082 trace_i915_gem_request_add(ring
, request
->seqno
);
2083 ring
->outstanding_lazy_request
= 0;
2085 if (!dev_priv
->mm
.suspended
) {
2086 if (i915_enable_hangcheck
) {
2087 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2088 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2091 queue_delayed_work(dev_priv
->wq
,
2092 &dev_priv
->mm
.retire_work
,
2093 round_jiffies_up_relative(HZ
));
2094 intel_mark_busy(dev_priv
->dev
);
2099 *out_seqno
= request
->seqno
;
2104 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2106 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2111 spin_lock(&file_priv
->mm
.lock
);
2112 if (request
->file_priv
) {
2113 list_del(&request
->client_list
);
2114 request
->file_priv
= NULL
;
2116 spin_unlock(&file_priv
->mm
.lock
);
2119 static bool i915_head_inside_object(u32 acthd
, struct drm_i915_gem_object
*obj
)
2121 if (acthd
>= i915_gem_obj_ggtt_offset(obj
) &&
2122 acthd
< i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
)
2128 static bool i915_head_inside_request(const u32 acthd_unmasked
,
2129 const u32 request_start
,
2130 const u32 request_end
)
2132 const u32 acthd
= acthd_unmasked
& HEAD_ADDR
;
2134 if (request_start
< request_end
) {
2135 if (acthd
>= request_start
&& acthd
< request_end
)
2137 } else if (request_start
> request_end
) {
2138 if (acthd
>= request_start
|| acthd
< request_end
)
2145 static bool i915_request_guilty(struct drm_i915_gem_request
*request
,
2146 const u32 acthd
, bool *inside
)
2148 /* There is a possibility that unmasked head address
2149 * pointing inside the ring, matches the batch_obj address range.
2150 * However this is extremely unlikely.
2153 if (request
->batch_obj
) {
2154 if (i915_head_inside_object(acthd
, request
->batch_obj
)) {
2160 if (i915_head_inside_request(acthd
, request
->head
, request
->tail
)) {
2168 static void i915_set_reset_status(struct intel_ring_buffer
*ring
,
2169 struct drm_i915_gem_request
*request
,
2172 struct i915_ctx_hang_stats
*hs
= NULL
;
2173 bool inside
, guilty
;
2175 /* Innocent until proven guilty */
2178 if (ring
->hangcheck
.action
!= wait
&&
2179 i915_request_guilty(request
, acthd
, &inside
)) {
2180 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2182 inside
? "inside" : "flushing",
2183 request
->batch_obj
?
2184 i915_gem_obj_ggtt_offset(request
->batch_obj
) : 0,
2185 request
->ctx
? request
->ctx
->id
: 0,
2191 /* If contexts are disabled or this is the default context, use
2192 * file_priv->reset_state
2194 if (request
->ctx
&& request
->ctx
->id
!= DEFAULT_CONTEXT_ID
)
2195 hs
= &request
->ctx
->hang_stats
;
2196 else if (request
->file_priv
)
2197 hs
= &request
->file_priv
->hang_stats
;
2203 hs
->batch_pending
++;
2207 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2209 list_del(&request
->list
);
2210 i915_gem_request_remove_from_client(request
);
2213 i915_gem_context_unreference(request
->ctx
);
2218 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2219 struct intel_ring_buffer
*ring
)
2221 u32 completed_seqno
;
2224 acthd
= intel_ring_get_active_head(ring
);
2225 completed_seqno
= ring
->get_seqno(ring
, false);
2227 while (!list_empty(&ring
->request_list
)) {
2228 struct drm_i915_gem_request
*request
;
2230 request
= list_first_entry(&ring
->request_list
,
2231 struct drm_i915_gem_request
,
2234 if (request
->seqno
> completed_seqno
)
2235 i915_set_reset_status(ring
, request
, acthd
);
2237 i915_gem_free_request(request
);
2240 while (!list_empty(&ring
->active_list
)) {
2241 struct drm_i915_gem_object
*obj
;
2243 obj
= list_first_entry(&ring
->active_list
,
2244 struct drm_i915_gem_object
,
2247 i915_gem_object_move_to_inactive(obj
);
2251 static void i915_gem_reset_fences(struct drm_device
*dev
)
2253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2256 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2257 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2260 i915_gem_object_fence_lost(reg
->obj
);
2262 i915_gem_write_fence(dev
, i
, NULL
);
2266 INIT_LIST_HEAD(®
->lru_list
);
2269 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2272 void i915_gem_reset(struct drm_device
*dev
)
2274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 struct drm_i915_gem_object
*obj
;
2276 struct intel_ring_buffer
*ring
;
2279 for_each_ring(ring
, dev_priv
, i
)
2280 i915_gem_reset_ring_lists(dev_priv
, ring
);
2282 /* Move everything out of the GPU domains to ensure we do any
2283 * necessary invalidation upon reuse.
2285 list_for_each_entry(obj
,
2286 &dev_priv
->mm
.inactive_list
,
2289 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2292 /* The fence registers are invalidated so clear them out */
2293 i915_gem_reset_fences(dev
);
2297 * This function clears the request list as sequence numbers are passed.
2300 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2304 if (list_empty(&ring
->request_list
))
2307 WARN_ON(i915_verify_lists(ring
->dev
));
2309 seqno
= ring
->get_seqno(ring
, true);
2311 while (!list_empty(&ring
->request_list
)) {
2312 struct drm_i915_gem_request
*request
;
2314 request
= list_first_entry(&ring
->request_list
,
2315 struct drm_i915_gem_request
,
2318 if (!i915_seqno_passed(seqno
, request
->seqno
))
2321 trace_i915_gem_request_retire(ring
, request
->seqno
);
2322 /* We know the GPU must have read the request to have
2323 * sent us the seqno + interrupt, so use the position
2324 * of tail of the request to update the last known position
2327 ring
->last_retired_head
= request
->tail
;
2329 i915_gem_free_request(request
);
2332 /* Move any buffers on the active list that are no longer referenced
2333 * by the ringbuffer to the flushing/inactive lists as appropriate.
2335 while (!list_empty(&ring
->active_list
)) {
2336 struct drm_i915_gem_object
*obj
;
2338 obj
= list_first_entry(&ring
->active_list
,
2339 struct drm_i915_gem_object
,
2342 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2345 i915_gem_object_move_to_inactive(obj
);
2348 if (unlikely(ring
->trace_irq_seqno
&&
2349 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2350 ring
->irq_put(ring
);
2351 ring
->trace_irq_seqno
= 0;
2354 WARN_ON(i915_verify_lists(ring
->dev
));
2358 i915_gem_retire_requests(struct drm_device
*dev
)
2360 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2361 struct intel_ring_buffer
*ring
;
2364 for_each_ring(ring
, dev_priv
, i
)
2365 i915_gem_retire_requests_ring(ring
);
2369 i915_gem_retire_work_handler(struct work_struct
*work
)
2371 drm_i915_private_t
*dev_priv
;
2372 struct drm_device
*dev
;
2373 struct intel_ring_buffer
*ring
;
2377 dev_priv
= container_of(work
, drm_i915_private_t
,
2378 mm
.retire_work
.work
);
2379 dev
= dev_priv
->dev
;
2381 /* Come back later if the device is busy... */
2382 if (!mutex_trylock(&dev
->struct_mutex
)) {
2383 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2384 round_jiffies_up_relative(HZ
));
2388 i915_gem_retire_requests(dev
);
2390 /* Send a periodic flush down the ring so we don't hold onto GEM
2391 * objects indefinitely.
2394 for_each_ring(ring
, dev_priv
, i
) {
2395 if (ring
->gpu_caches_dirty
)
2396 i915_add_request(ring
, NULL
);
2398 idle
&= list_empty(&ring
->request_list
);
2401 if (!dev_priv
->mm
.suspended
&& !idle
)
2402 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2403 round_jiffies_up_relative(HZ
));
2405 intel_mark_idle(dev
);
2407 mutex_unlock(&dev
->struct_mutex
);
2411 * Ensures that an object will eventually get non-busy by flushing any required
2412 * write domains, emitting any outstanding lazy request and retiring and
2413 * completed requests.
2416 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2421 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2425 i915_gem_retire_requests_ring(obj
->ring
);
2432 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2433 * @DRM_IOCTL_ARGS: standard ioctl arguments
2435 * Returns 0 if successful, else an error is returned with the remaining time in
2436 * the timeout parameter.
2437 * -ETIME: object is still busy after timeout
2438 * -ERESTARTSYS: signal interrupted the wait
2439 * -ENONENT: object doesn't exist
2440 * Also possible, but rare:
2441 * -EAGAIN: GPU wedged
2443 * -ENODEV: Internal IRQ fail
2444 * -E?: The add request failed
2446 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2447 * non-zero timeout parameter the wait ioctl will wait for the given number of
2448 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2449 * without holding struct_mutex the object may become re-busied before this
2450 * function completes. A similar but shorter * race condition exists in the busy
2454 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2456 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2457 struct drm_i915_gem_wait
*args
= data
;
2458 struct drm_i915_gem_object
*obj
;
2459 struct intel_ring_buffer
*ring
= NULL
;
2460 struct timespec timeout_stack
, *timeout
= NULL
;
2461 unsigned reset_counter
;
2465 if (args
->timeout_ns
>= 0) {
2466 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2467 timeout
= &timeout_stack
;
2470 ret
= i915_mutex_lock_interruptible(dev
);
2474 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2475 if (&obj
->base
== NULL
) {
2476 mutex_unlock(&dev
->struct_mutex
);
2480 /* Need to make sure the object gets inactive eventually. */
2481 ret
= i915_gem_object_flush_active(obj
);
2486 seqno
= obj
->last_read_seqno
;
2493 /* Do this after OLR check to make sure we make forward progress polling
2494 * on this IOCTL with a 0 timeout (like busy ioctl)
2496 if (!args
->timeout_ns
) {
2501 drm_gem_object_unreference(&obj
->base
);
2502 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2503 mutex_unlock(&dev
->struct_mutex
);
2505 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2507 args
->timeout_ns
= timespec_to_ns(timeout
);
2511 drm_gem_object_unreference(&obj
->base
);
2512 mutex_unlock(&dev
->struct_mutex
);
2517 * i915_gem_object_sync - sync an object to a ring.
2519 * @obj: object which may be in use on another ring.
2520 * @to: ring we wish to use the object on. May be NULL.
2522 * This code is meant to abstract object synchronization with the GPU.
2523 * Calling with NULL implies synchronizing the object with the CPU
2524 * rather than a particular GPU ring.
2526 * Returns 0 if successful, else propagates up the lower layer error.
2529 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2530 struct intel_ring_buffer
*to
)
2532 struct intel_ring_buffer
*from
= obj
->ring
;
2536 if (from
== NULL
|| to
== from
)
2539 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2540 return i915_gem_object_wait_rendering(obj
, false);
2542 idx
= intel_ring_sync_index(from
, to
);
2544 seqno
= obj
->last_read_seqno
;
2545 if (seqno
<= from
->sync_seqno
[idx
])
2548 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2552 ret
= to
->sync_to(to
, from
, seqno
);
2554 /* We use last_read_seqno because sync_to()
2555 * might have just caused seqno wrap under
2558 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2563 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2565 u32 old_write_domain
, old_read_domains
;
2567 /* Force a pagefault for domain tracking on next user access */
2568 i915_gem_release_mmap(obj
);
2570 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2573 /* Wait for any direct GTT access to complete */
2576 old_read_domains
= obj
->base
.read_domains
;
2577 old_write_domain
= obj
->base
.write_domain
;
2579 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2580 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2582 trace_i915_gem_object_change_domain(obj
,
2588 * Unbinds an object from the GTT aperture.
2591 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2593 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2596 if (!i915_gem_obj_ggtt_bound(obj
))
2602 BUG_ON(obj
->pages
== NULL
);
2604 ret
= i915_gem_object_finish_gpu(obj
);
2607 /* Continue on if we fail due to EIO, the GPU is hung so we
2608 * should be safe and we need to cleanup or else we might
2609 * cause memory corruption through use-after-free.
2612 i915_gem_object_finish_gtt(obj
);
2614 /* release the fence reg _after_ flushing */
2615 ret
= i915_gem_object_put_fence(obj
);
2619 trace_i915_gem_object_unbind(obj
);
2621 if (obj
->has_global_gtt_mapping
)
2622 i915_gem_gtt_unbind_object(obj
);
2623 if (obj
->has_aliasing_ppgtt_mapping
) {
2624 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2625 obj
->has_aliasing_ppgtt_mapping
= 0;
2627 i915_gem_gtt_finish_object(obj
);
2628 i915_gem_object_unpin_pages(obj
);
2630 list_del(&obj
->mm_list
);
2631 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2632 /* Avoid an unnecessary call to unbind on rebind. */
2633 obj
->map_and_fenceable
= true;
2635 drm_mm_put_block(obj
->gtt_space
);
2636 obj
->gtt_space
= NULL
;
2637 obj
->gtt_offset
= 0;
2642 int i915_gpu_idle(struct drm_device
*dev
)
2644 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2645 struct intel_ring_buffer
*ring
;
2648 /* Flush everything onto the inactive list. */
2649 for_each_ring(ring
, dev_priv
, i
) {
2650 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2654 ret
= intel_ring_idle(ring
);
2662 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2663 struct drm_i915_gem_object
*obj
)
2665 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2667 int fence_pitch_shift
;
2670 if (INTEL_INFO(dev
)->gen
>= 6) {
2671 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2672 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2674 fence_reg
= FENCE_REG_965_0
;
2675 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2679 u32 size
= i915_gem_obj_ggtt_size(obj
);
2681 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2683 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2684 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2685 if (obj
->tiling_mode
== I915_TILING_Y
)
2686 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2687 val
|= I965_FENCE_REG_VALID
;
2691 fence_reg
+= reg
* 8;
2692 I915_WRITE64(fence_reg
, val
);
2693 POSTING_READ(fence_reg
);
2696 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2697 struct drm_i915_gem_object
*obj
)
2699 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2703 u32 size
= i915_gem_obj_ggtt_size(obj
);
2707 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2708 (size
& -size
) != size
||
2709 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2710 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2711 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2713 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2718 /* Note: pitch better be a power of two tile widths */
2719 pitch_val
= obj
->stride
/ tile_width
;
2720 pitch_val
= ffs(pitch_val
) - 1;
2722 val
= i915_gem_obj_ggtt_offset(obj
);
2723 if (obj
->tiling_mode
== I915_TILING_Y
)
2724 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2725 val
|= I915_FENCE_SIZE_BITS(size
);
2726 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2727 val
|= I830_FENCE_REG_VALID
;
2732 reg
= FENCE_REG_830_0
+ reg
* 4;
2734 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2736 I915_WRITE(reg
, val
);
2740 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2741 struct drm_i915_gem_object
*obj
)
2743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2747 u32 size
= i915_gem_obj_ggtt_size(obj
);
2750 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2751 (size
& -size
) != size
||
2752 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2753 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2754 i915_gem_obj_ggtt_offset(obj
), size
);
2756 pitch_val
= obj
->stride
/ 128;
2757 pitch_val
= ffs(pitch_val
) - 1;
2759 val
= i915_gem_obj_ggtt_offset(obj
);
2760 if (obj
->tiling_mode
== I915_TILING_Y
)
2761 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2762 val
|= I830_FENCE_SIZE_BITS(size
);
2763 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2764 val
|= I830_FENCE_REG_VALID
;
2768 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2769 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2772 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2774 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2777 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2778 struct drm_i915_gem_object
*obj
)
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2782 /* Ensure that all CPU reads are completed before installing a fence
2783 * and all writes before removing the fence.
2785 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2788 switch (INTEL_INFO(dev
)->gen
) {
2792 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2793 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2794 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2798 /* And similarly be paranoid that no direct access to this region
2799 * is reordered to before the fence is installed.
2801 if (i915_gem_object_needs_mb(obj
))
2805 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2806 struct drm_i915_fence_reg
*fence
)
2808 return fence
- dev_priv
->fence_regs
;
2811 struct write_fence
{
2812 struct drm_device
*dev
;
2813 struct drm_i915_gem_object
*obj
;
2817 static void i915_gem_write_fence__ipi(void *data
)
2819 struct write_fence
*args
= data
;
2821 /* Required for SNB+ with LLC */
2824 /* Required for VLV */
2825 i915_gem_write_fence(args
->dev
, args
->fence
, args
->obj
);
2828 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2829 struct drm_i915_fence_reg
*fence
,
2832 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2833 struct write_fence args
= {
2834 .dev
= obj
->base
.dev
,
2835 .fence
= fence_number(dev_priv
, fence
),
2836 .obj
= enable
? obj
: NULL
,
2839 /* In order to fully serialize access to the fenced region and
2840 * the update to the fence register we need to take extreme
2841 * measures on SNB+. In theory, the write to the fence register
2842 * flushes all memory transactions before, and coupled with the
2843 * mb() placed around the register write we serialise all memory
2844 * operations with respect to the changes in the tiler. Yet, on
2845 * SNB+ we need to take a step further and emit an explicit wbinvd()
2846 * on each processor in order to manually flush all memory
2847 * transactions before updating the fence register.
2849 * However, Valleyview complicates matter. There the wbinvd is
2850 * insufficient and unlike SNB/IVB requires the serialising
2851 * register write. (Note that that register write by itself is
2852 * conversely not sufficient for SNB+.) To compromise, we do both.
2854 if (INTEL_INFO(args
.dev
)->gen
>= 6)
2855 on_each_cpu(i915_gem_write_fence__ipi
, &args
, 1);
2857 i915_gem_write_fence(args
.dev
, args
.fence
, args
.obj
);
2860 obj
->fence_reg
= args
.fence
;
2862 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2864 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2866 list_del_init(&fence
->lru_list
);
2871 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2873 if (obj
->last_fenced_seqno
) {
2874 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2878 obj
->last_fenced_seqno
= 0;
2881 obj
->fenced_gpu_access
= false;
2886 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2888 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2889 struct drm_i915_fence_reg
*fence
;
2892 ret
= i915_gem_object_wait_fence(obj
);
2896 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2899 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2901 i915_gem_object_fence_lost(obj
);
2902 i915_gem_object_update_fence(obj
, fence
, false);
2907 static struct drm_i915_fence_reg
*
2908 i915_find_fence_reg(struct drm_device
*dev
)
2910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2911 struct drm_i915_fence_reg
*reg
, *avail
;
2914 /* First try to find a free reg */
2916 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2917 reg
= &dev_priv
->fence_regs
[i
];
2921 if (!reg
->pin_count
)
2928 /* None available, try to steal one or wait for a user to finish */
2929 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2940 * i915_gem_object_get_fence - set up fencing for an object
2941 * @obj: object to map through a fence reg
2943 * When mapping objects through the GTT, userspace wants to be able to write
2944 * to them without having to worry about swizzling if the object is tiled.
2945 * This function walks the fence regs looking for a free one for @obj,
2946 * stealing one if it can't find any.
2948 * It then sets up the reg based on the object's properties: address, pitch
2949 * and tiling format.
2951 * For an untiled surface, this removes any existing fence.
2954 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2956 struct drm_device
*dev
= obj
->base
.dev
;
2957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2958 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2959 struct drm_i915_fence_reg
*reg
;
2962 /* Have we updated the tiling parameters upon the object and so
2963 * will need to serialise the write to the associated fence register?
2965 if (obj
->fence_dirty
) {
2966 ret
= i915_gem_object_wait_fence(obj
);
2971 /* Just update our place in the LRU if our fence is getting reused. */
2972 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2973 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2974 if (!obj
->fence_dirty
) {
2975 list_move_tail(®
->lru_list
,
2976 &dev_priv
->mm
.fence_list
);
2979 } else if (enable
) {
2980 reg
= i915_find_fence_reg(dev
);
2985 struct drm_i915_gem_object
*old
= reg
->obj
;
2987 ret
= i915_gem_object_wait_fence(old
);
2991 i915_gem_object_fence_lost(old
);
2996 i915_gem_object_update_fence(obj
, reg
, enable
);
2997 obj
->fence_dirty
= false;
3002 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3003 struct drm_mm_node
*gtt_space
,
3004 unsigned long cache_level
)
3006 struct drm_mm_node
*other
;
3008 /* On non-LLC machines we have to be careful when putting differing
3009 * types of snoopable memory together to avoid the prefetcher
3010 * crossing memory domains and dying.
3015 if (gtt_space
== NULL
)
3018 if (list_empty(>t_space
->node_list
))
3021 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3022 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3025 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3026 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3032 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3036 struct drm_i915_gem_object
*obj
;
3039 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3040 if (obj
->gtt_space
== NULL
) {
3041 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3046 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3047 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3048 i915_gem_obj_ggtt_offset(obj
),
3049 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3051 obj
->gtt_space
->color
);
3056 if (!i915_gem_valid_gtt_space(dev
,
3058 obj
->cache_level
)) {
3059 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3060 i915_gem_obj_ggtt_offset(obj
),
3061 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3073 * Finds free space in the GTT aperture and binds the object there.
3076 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
3078 bool map_and_fenceable
,
3081 struct drm_device
*dev
= obj
->base
.dev
;
3082 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3083 struct drm_mm_node
*node
;
3084 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3085 bool mappable
, fenceable
;
3086 size_t gtt_max
= map_and_fenceable
?
3087 dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
;
3090 fence_size
= i915_gem_get_gtt_size(dev
,
3093 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3095 obj
->tiling_mode
, true);
3096 unfenced_alignment
=
3097 i915_gem_get_gtt_alignment(dev
,
3099 obj
->tiling_mode
, false);
3102 alignment
= map_and_fenceable
? fence_alignment
:
3104 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
3105 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
3109 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
3111 /* If the object is bigger than the entire aperture, reject it early
3112 * before evicting everything in a vain attempt to find space.
3114 if (obj
->base
.size
> gtt_max
) {
3115 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3117 map_and_fenceable
? "mappable" : "total",
3122 ret
= i915_gem_object_get_pages(obj
);
3126 i915_gem_object_pin_pages(obj
);
3128 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
3130 i915_gem_object_unpin_pages(obj
);
3135 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
3137 obj
->cache_level
, 0, gtt_max
);
3139 ret
= i915_gem_evict_something(dev
, size
, alignment
,
3146 i915_gem_object_unpin_pages(obj
);
3150 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
3151 i915_gem_object_unpin_pages(obj
);
3152 drm_mm_put_block(node
);
3156 ret
= i915_gem_gtt_prepare_object(obj
);
3158 i915_gem_object_unpin_pages(obj
);
3159 drm_mm_put_block(node
);
3163 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3164 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3166 obj
->gtt_space
= node
;
3167 obj
->gtt_offset
= node
->start
;
3170 node
->size
== fence_size
&&
3171 (node
->start
& (fence_alignment
- 1)) == 0;
3173 mappable
= i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
<=
3174 dev_priv
->gtt
.mappable_end
;
3176 obj
->map_and_fenceable
= mappable
&& fenceable
;
3178 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3179 i915_gem_verify_gtt(dev
);
3184 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3186 /* If we don't have a page list set up, then we're not pinned
3187 * to GPU, and we can ignore the cache flush because it'll happen
3188 * again at bind time.
3190 if (obj
->pages
== NULL
)
3194 * Stolen memory is always coherent with the GPU as it is explicitly
3195 * marked as wc by the system, or the system is cache-coherent.
3200 /* If the GPU is snooping the contents of the CPU cache,
3201 * we do not need to manually clear the CPU cache lines. However,
3202 * the caches are only snooped when the render cache is
3203 * flushed/invalidated. As we always have to emit invalidations
3204 * and flushes when moving into and out of the RENDER domain, correct
3205 * snooping behaviour occurs naturally as the result of our domain
3208 if (obj
->cache_level
!= I915_CACHE_NONE
)
3211 trace_i915_gem_object_clflush(obj
);
3213 drm_clflush_sg(obj
->pages
);
3216 /** Flushes the GTT write domain for the object if it's dirty. */
3218 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3220 uint32_t old_write_domain
;
3222 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3225 /* No actual flushing is required for the GTT write domain. Writes
3226 * to it immediately go to main memory as far as we know, so there's
3227 * no chipset flush. It also doesn't land in render cache.
3229 * However, we do have to enforce the order so that all writes through
3230 * the GTT land before any writes to the device, such as updates to
3235 old_write_domain
= obj
->base
.write_domain
;
3236 obj
->base
.write_domain
= 0;
3238 trace_i915_gem_object_change_domain(obj
,
3239 obj
->base
.read_domains
,
3243 /** Flushes the CPU write domain for the object if it's dirty. */
3245 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3247 uint32_t old_write_domain
;
3249 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3252 i915_gem_clflush_object(obj
);
3253 i915_gem_chipset_flush(obj
->base
.dev
);
3254 old_write_domain
= obj
->base
.write_domain
;
3255 obj
->base
.write_domain
= 0;
3257 trace_i915_gem_object_change_domain(obj
,
3258 obj
->base
.read_domains
,
3263 * Moves a single object to the GTT read, and possibly write domain.
3265 * This function returns when the move is complete, including waiting on
3269 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3271 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3272 uint32_t old_write_domain
, old_read_domains
;
3275 /* Not valid to be called on unbound objects. */
3276 if (!i915_gem_obj_ggtt_bound(obj
))
3279 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3282 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3286 i915_gem_object_flush_cpu_write_domain(obj
);
3288 /* Serialise direct access to this object with the barriers for
3289 * coherent writes from the GPU, by effectively invalidating the
3290 * GTT domain upon first access.
3292 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3295 old_write_domain
= obj
->base
.write_domain
;
3296 old_read_domains
= obj
->base
.read_domains
;
3298 /* It should now be out of any other write domains, and we can update
3299 * the domain values for our changes.
3301 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3302 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3304 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3305 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3309 trace_i915_gem_object_change_domain(obj
,
3313 /* And bump the LRU for this access */
3314 if (i915_gem_object_is_inactive(obj
))
3315 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3320 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3321 enum i915_cache_level cache_level
)
3323 struct drm_device
*dev
= obj
->base
.dev
;
3324 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3327 if (obj
->cache_level
== cache_level
)
3330 if (obj
->pin_count
) {
3331 DRM_DEBUG("can not change the cache level of pinned objects\n");
3335 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3336 ret
= i915_gem_object_unbind(obj
);
3341 if (i915_gem_obj_ggtt_bound(obj
)) {
3342 ret
= i915_gem_object_finish_gpu(obj
);
3346 i915_gem_object_finish_gtt(obj
);
3348 /* Before SandyBridge, you could not use tiling or fence
3349 * registers with snooped memory, so relinquish any fences
3350 * currently pointing to our region in the aperture.
3352 if (INTEL_INFO(dev
)->gen
< 6) {
3353 ret
= i915_gem_object_put_fence(obj
);
3358 if (obj
->has_global_gtt_mapping
)
3359 i915_gem_gtt_bind_object(obj
, cache_level
);
3360 if (obj
->has_aliasing_ppgtt_mapping
)
3361 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3364 i915_gem_obj_ggtt_set_color(obj
, cache_level
);
3367 if (cache_level
== I915_CACHE_NONE
) {
3368 u32 old_read_domains
, old_write_domain
;
3370 /* If we're coming from LLC cached, then we haven't
3371 * actually been tracking whether the data is in the
3372 * CPU cache or not, since we only allow one bit set
3373 * in obj->write_domain and have been skipping the clflushes.
3374 * Just set it to the CPU cache for now.
3376 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3377 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3379 old_read_domains
= obj
->base
.read_domains
;
3380 old_write_domain
= obj
->base
.write_domain
;
3382 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3383 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3385 trace_i915_gem_object_change_domain(obj
,
3390 obj
->cache_level
= cache_level
;
3391 i915_gem_verify_gtt(dev
);
3395 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3396 struct drm_file
*file
)
3398 struct drm_i915_gem_caching
*args
= data
;
3399 struct drm_i915_gem_object
*obj
;
3402 ret
= i915_mutex_lock_interruptible(dev
);
3406 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3407 if (&obj
->base
== NULL
) {
3412 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3414 drm_gem_object_unreference(&obj
->base
);
3416 mutex_unlock(&dev
->struct_mutex
);
3420 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3421 struct drm_file
*file
)
3423 struct drm_i915_gem_caching
*args
= data
;
3424 struct drm_i915_gem_object
*obj
;
3425 enum i915_cache_level level
;
3428 switch (args
->caching
) {
3429 case I915_CACHING_NONE
:
3430 level
= I915_CACHE_NONE
;
3432 case I915_CACHING_CACHED
:
3433 level
= I915_CACHE_LLC
;
3439 ret
= i915_mutex_lock_interruptible(dev
);
3443 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3444 if (&obj
->base
== NULL
) {
3449 ret
= i915_gem_object_set_cache_level(obj
, level
);
3451 drm_gem_object_unreference(&obj
->base
);
3453 mutex_unlock(&dev
->struct_mutex
);
3458 * Prepare buffer for display plane (scanout, cursors, etc).
3459 * Can be called from an uninterruptible phase (modesetting) and allows
3460 * any flushes to be pipelined (for pageflips).
3463 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3465 struct intel_ring_buffer
*pipelined
)
3467 u32 old_read_domains
, old_write_domain
;
3470 if (pipelined
!= obj
->ring
) {
3471 ret
= i915_gem_object_sync(obj
, pipelined
);
3476 /* The display engine is not coherent with the LLC cache on gen6. As
3477 * a result, we make sure that the pinning that is about to occur is
3478 * done with uncached PTEs. This is lowest common denominator for all
3481 * However for gen6+, we could do better by using the GFDT bit instead
3482 * of uncaching, which would allow us to flush all the LLC-cached data
3483 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3485 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3489 /* As the user may map the buffer once pinned in the display plane
3490 * (e.g. libkms for the bootup splash), we have to ensure that we
3491 * always use map_and_fenceable for all scanout buffers.
3493 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3497 i915_gem_object_flush_cpu_write_domain(obj
);
3499 old_write_domain
= obj
->base
.write_domain
;
3500 old_read_domains
= obj
->base
.read_domains
;
3502 /* It should now be out of any other write domains, and we can update
3503 * the domain values for our changes.
3505 obj
->base
.write_domain
= 0;
3506 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3508 trace_i915_gem_object_change_domain(obj
,
3516 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3520 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3523 ret
= i915_gem_object_wait_rendering(obj
, false);
3527 /* Ensure that we invalidate the GPU's caches and TLBs. */
3528 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3533 * Moves a single object to the CPU read, and possibly write domain.
3535 * This function returns when the move is complete, including waiting on
3539 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3541 uint32_t old_write_domain
, old_read_domains
;
3544 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3547 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3551 i915_gem_object_flush_gtt_write_domain(obj
);
3553 old_write_domain
= obj
->base
.write_domain
;
3554 old_read_domains
= obj
->base
.read_domains
;
3556 /* Flush the CPU cache if it's still invalid. */
3557 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3558 i915_gem_clflush_object(obj
);
3560 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3563 /* It should now be out of any other write domains, and we can update
3564 * the domain values for our changes.
3566 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3568 /* If we're writing through the CPU, then the GPU read domains will
3569 * need to be invalidated at next use.
3572 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3573 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3576 trace_i915_gem_object_change_domain(obj
,
3583 /* Throttle our rendering by waiting until the ring has completed our requests
3584 * emitted over 20 msec ago.
3586 * Note that if we were to use the current jiffies each time around the loop,
3587 * we wouldn't escape the function with any frames outstanding if the time to
3588 * render a frame was over 20ms.
3590 * This should get us reasonable parallelism between CPU and GPU but also
3591 * relatively low latency when blocking on a particular request to finish.
3594 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3597 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3598 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3599 struct drm_i915_gem_request
*request
;
3600 struct intel_ring_buffer
*ring
= NULL
;
3601 unsigned reset_counter
;
3605 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3609 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3613 spin_lock(&file_priv
->mm
.lock
);
3614 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3615 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3618 ring
= request
->ring
;
3619 seqno
= request
->seqno
;
3621 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3622 spin_unlock(&file_priv
->mm
.lock
);
3627 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3629 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3635 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3637 bool map_and_fenceable
,
3642 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3645 if (i915_gem_obj_ggtt_bound(obj
)) {
3646 if ((alignment
&& i915_gem_obj_ggtt_offset(obj
) & (alignment
- 1)) ||
3647 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3648 WARN(obj
->pin_count
,
3649 "bo is already pinned with incorrect alignment:"
3650 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3651 " obj->map_and_fenceable=%d\n",
3652 i915_gem_obj_ggtt_offset(obj
), alignment
,
3654 obj
->map_and_fenceable
);
3655 ret
= i915_gem_object_unbind(obj
);
3661 if (!i915_gem_obj_ggtt_bound(obj
)) {
3662 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3664 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3670 if (!dev_priv
->mm
.aliasing_ppgtt
)
3671 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3674 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3675 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3678 obj
->pin_mappable
|= map_and_fenceable
;
3684 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3686 BUG_ON(obj
->pin_count
== 0);
3687 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
3689 if (--obj
->pin_count
== 0)
3690 obj
->pin_mappable
= false;
3694 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3695 struct drm_file
*file
)
3697 struct drm_i915_gem_pin
*args
= data
;
3698 struct drm_i915_gem_object
*obj
;
3701 ret
= i915_mutex_lock_interruptible(dev
);
3705 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3706 if (&obj
->base
== NULL
) {
3711 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3712 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3717 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3718 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3724 if (obj
->user_pin_count
== 0) {
3725 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3730 obj
->user_pin_count
++;
3731 obj
->pin_filp
= file
;
3733 /* XXX - flush the CPU caches for pinned objects
3734 * as the X server doesn't manage domains yet
3736 i915_gem_object_flush_cpu_write_domain(obj
);
3737 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3739 drm_gem_object_unreference(&obj
->base
);
3741 mutex_unlock(&dev
->struct_mutex
);
3746 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3747 struct drm_file
*file
)
3749 struct drm_i915_gem_pin
*args
= data
;
3750 struct drm_i915_gem_object
*obj
;
3753 ret
= i915_mutex_lock_interruptible(dev
);
3757 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3758 if (&obj
->base
== NULL
) {
3763 if (obj
->pin_filp
!= file
) {
3764 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3769 obj
->user_pin_count
--;
3770 if (obj
->user_pin_count
== 0) {
3771 obj
->pin_filp
= NULL
;
3772 i915_gem_object_unpin(obj
);
3776 drm_gem_object_unreference(&obj
->base
);
3778 mutex_unlock(&dev
->struct_mutex
);
3783 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3784 struct drm_file
*file
)
3786 struct drm_i915_gem_busy
*args
= data
;
3787 struct drm_i915_gem_object
*obj
;
3790 ret
= i915_mutex_lock_interruptible(dev
);
3794 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3795 if (&obj
->base
== NULL
) {
3800 /* Count all active objects as busy, even if they are currently not used
3801 * by the gpu. Users of this interface expect objects to eventually
3802 * become non-busy without any further actions, therefore emit any
3803 * necessary flushes here.
3805 ret
= i915_gem_object_flush_active(obj
);
3807 args
->busy
= obj
->active
;
3809 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3810 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3813 drm_gem_object_unreference(&obj
->base
);
3815 mutex_unlock(&dev
->struct_mutex
);
3820 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3821 struct drm_file
*file_priv
)
3823 return i915_gem_ring_throttle(dev
, file_priv
);
3827 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3828 struct drm_file
*file_priv
)
3830 struct drm_i915_gem_madvise
*args
= data
;
3831 struct drm_i915_gem_object
*obj
;
3834 switch (args
->madv
) {
3835 case I915_MADV_DONTNEED
:
3836 case I915_MADV_WILLNEED
:
3842 ret
= i915_mutex_lock_interruptible(dev
);
3846 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3847 if (&obj
->base
== NULL
) {
3852 if (obj
->pin_count
) {
3857 if (obj
->madv
!= __I915_MADV_PURGED
)
3858 obj
->madv
= args
->madv
;
3860 /* if the object is no longer attached, discard its backing storage */
3861 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3862 i915_gem_object_truncate(obj
);
3864 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3867 drm_gem_object_unreference(&obj
->base
);
3869 mutex_unlock(&dev
->struct_mutex
);
3873 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3874 const struct drm_i915_gem_object_ops
*ops
)
3876 INIT_LIST_HEAD(&obj
->mm_list
);
3877 INIT_LIST_HEAD(&obj
->global_list
);
3878 INIT_LIST_HEAD(&obj
->ring_list
);
3879 INIT_LIST_HEAD(&obj
->exec_list
);
3883 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3884 obj
->madv
= I915_MADV_WILLNEED
;
3885 /* Avoid an unnecessary call to unbind on the first bind. */
3886 obj
->map_and_fenceable
= true;
3888 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3891 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3892 .get_pages
= i915_gem_object_get_pages_gtt
,
3893 .put_pages
= i915_gem_object_put_pages_gtt
,
3896 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3899 struct drm_i915_gem_object
*obj
;
3900 struct address_space
*mapping
;
3903 obj
= i915_gem_object_alloc(dev
);
3907 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3908 i915_gem_object_free(obj
);
3912 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3913 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3914 /* 965gm cannot relocate objects above 4GiB. */
3915 mask
&= ~__GFP_HIGHMEM
;
3916 mask
|= __GFP_DMA32
;
3919 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
3920 mapping_set_gfp_mask(mapping
, mask
);
3922 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3924 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3925 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3928 /* On some devices, we can have the GPU use the LLC (the CPU
3929 * cache) for about a 10% performance improvement
3930 * compared to uncached. Graphics requests other than
3931 * display scanout are coherent with the CPU in
3932 * accessing this cache. This means in this mode we
3933 * don't need to clflush on the CPU side, and on the
3934 * GPU side we only need to flush internal caches to
3935 * get data visible to the CPU.
3937 * However, we maintain the display planes as UC, and so
3938 * need to rebind when first used as such.
3940 obj
->cache_level
= I915_CACHE_LLC
;
3942 obj
->cache_level
= I915_CACHE_NONE
;
3947 int i915_gem_init_object(struct drm_gem_object
*obj
)
3954 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3956 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3957 struct drm_device
*dev
= obj
->base
.dev
;
3958 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3960 trace_i915_gem_object_destroy(obj
);
3963 i915_gem_detach_phys_object(dev
, obj
);
3966 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3967 bool was_interruptible
;
3969 was_interruptible
= dev_priv
->mm
.interruptible
;
3970 dev_priv
->mm
.interruptible
= false;
3972 WARN_ON(i915_gem_object_unbind(obj
));
3974 dev_priv
->mm
.interruptible
= was_interruptible
;
3977 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3978 * before progressing. */
3980 i915_gem_object_unpin_pages(obj
);
3982 if (WARN_ON(obj
->pages_pin_count
))
3983 obj
->pages_pin_count
= 0;
3984 i915_gem_object_put_pages(obj
);
3985 i915_gem_object_free_mmap_offset(obj
);
3986 i915_gem_object_release_stolen(obj
);
3990 if (obj
->base
.import_attach
)
3991 drm_prime_gem_destroy(&obj
->base
, NULL
);
3993 drm_gem_object_release(&obj
->base
);
3994 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3997 i915_gem_object_free(obj
);
4001 i915_gem_idle(struct drm_device
*dev
)
4003 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4006 mutex_lock(&dev
->struct_mutex
);
4008 if (dev_priv
->mm
.suspended
) {
4009 mutex_unlock(&dev
->struct_mutex
);
4013 ret
= i915_gpu_idle(dev
);
4015 mutex_unlock(&dev
->struct_mutex
);
4018 i915_gem_retire_requests(dev
);
4020 /* Under UMS, be paranoid and evict. */
4021 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4022 i915_gem_evict_everything(dev
);
4024 i915_gem_reset_fences(dev
);
4026 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4027 * We need to replace this with a semaphore, or something.
4028 * And not confound mm.suspended!
4030 dev_priv
->mm
.suspended
= 1;
4031 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4033 i915_kernel_lost_context(dev
);
4034 i915_gem_cleanup_ringbuffer(dev
);
4036 mutex_unlock(&dev
->struct_mutex
);
4038 /* Cancel the retire work handler, which should be idle now. */
4039 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4044 void i915_gem_l3_remap(struct drm_device
*dev
)
4046 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4050 if (!HAS_L3_GPU_CACHE(dev
))
4053 if (!dev_priv
->l3_parity
.remap_info
)
4056 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
4057 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
4058 POSTING_READ(GEN7_MISCCPCTL
);
4060 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4061 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
4062 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
4063 DRM_DEBUG("0x%x was already programmed to %x\n",
4064 GEN7_L3LOG_BASE
+ i
, remap
);
4065 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
4066 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4067 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
4070 /* Make sure all the writes land before disabling dop clock gating */
4071 POSTING_READ(GEN7_L3LOG_BASE
);
4073 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
4076 void i915_gem_init_swizzling(struct drm_device
*dev
)
4078 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4080 if (INTEL_INFO(dev
)->gen
< 5 ||
4081 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4084 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4085 DISP_TILE_SURFACE_SWIZZLING
);
4090 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4092 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4093 else if (IS_GEN7(dev
))
4094 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4100 intel_enable_blt(struct drm_device
*dev
)
4105 /* The blitter was dysfunctional on early prototypes */
4106 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4107 DRM_INFO("BLT not supported on this pre-production hardware;"
4108 " graphics performance will be degraded.\n");
4115 static int i915_gem_init_rings(struct drm_device
*dev
)
4117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4120 ret
= intel_init_render_ring_buffer(dev
);
4125 ret
= intel_init_bsd_ring_buffer(dev
);
4127 goto cleanup_render_ring
;
4130 if (intel_enable_blt(dev
)) {
4131 ret
= intel_init_blt_ring_buffer(dev
);
4133 goto cleanup_bsd_ring
;
4136 if (HAS_VEBOX(dev
)) {
4137 ret
= intel_init_vebox_ring_buffer(dev
);
4139 goto cleanup_blt_ring
;
4143 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4145 goto cleanup_vebox_ring
;
4150 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4152 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4154 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4155 cleanup_render_ring
:
4156 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4162 i915_gem_init_hw(struct drm_device
*dev
)
4164 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4167 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4170 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
4171 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4173 if (HAS_PCH_NOP(dev
)) {
4174 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4175 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4176 I915_WRITE(GEN7_MSG_CTL
, temp
);
4179 i915_gem_l3_remap(dev
);
4181 i915_gem_init_swizzling(dev
);
4183 ret
= i915_gem_init_rings(dev
);
4188 * XXX: There was some w/a described somewhere suggesting loading
4189 * contexts before PPGTT.
4191 i915_gem_context_init(dev
);
4192 if (dev_priv
->mm
.aliasing_ppgtt
) {
4193 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4195 i915_gem_cleanup_aliasing_ppgtt(dev
);
4196 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4203 int i915_gem_init(struct drm_device
*dev
)
4205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 mutex_lock(&dev
->struct_mutex
);
4210 if (IS_VALLEYVIEW(dev
)) {
4211 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4212 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4213 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4214 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4217 i915_gem_init_global_gtt(dev
);
4219 ret
= i915_gem_init_hw(dev
);
4220 mutex_unlock(&dev
->struct_mutex
);
4222 i915_gem_cleanup_aliasing_ppgtt(dev
);
4226 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4227 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4228 dev_priv
->dri1
.allow_batchbuffer
= 1;
4233 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4235 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4236 struct intel_ring_buffer
*ring
;
4239 for_each_ring(ring
, dev_priv
, i
)
4240 intel_cleanup_ring_buffer(ring
);
4244 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4245 struct drm_file
*file_priv
)
4247 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4250 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4253 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4254 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4255 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4258 mutex_lock(&dev
->struct_mutex
);
4259 dev_priv
->mm
.suspended
= 0;
4261 ret
= i915_gem_init_hw(dev
);
4263 mutex_unlock(&dev
->struct_mutex
);
4267 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4268 mutex_unlock(&dev
->struct_mutex
);
4270 ret
= drm_irq_install(dev
);
4272 goto cleanup_ringbuffer
;
4277 mutex_lock(&dev
->struct_mutex
);
4278 i915_gem_cleanup_ringbuffer(dev
);
4279 dev_priv
->mm
.suspended
= 1;
4280 mutex_unlock(&dev
->struct_mutex
);
4286 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4287 struct drm_file
*file_priv
)
4289 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4292 drm_irq_uninstall(dev
);
4293 return i915_gem_idle(dev
);
4297 i915_gem_lastclose(struct drm_device
*dev
)
4301 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4304 ret
= i915_gem_idle(dev
);
4306 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4310 init_ring_lists(struct intel_ring_buffer
*ring
)
4312 INIT_LIST_HEAD(&ring
->active_list
);
4313 INIT_LIST_HEAD(&ring
->request_list
);
4317 i915_gem_load(struct drm_device
*dev
)
4319 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4323 kmem_cache_create("i915_gem_object",
4324 sizeof(struct drm_i915_gem_object
), 0,
4328 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4329 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4330 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4331 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4332 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4333 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4334 init_ring_lists(&dev_priv
->ring
[i
]);
4335 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4336 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4337 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4338 i915_gem_retire_work_handler
);
4339 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4341 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4343 I915_WRITE(MI_ARB_STATE
,
4344 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4347 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4349 /* Old X drivers will take 0-2 for front, back, depth buffers */
4350 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4351 dev_priv
->fence_reg_start
= 3;
4353 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4354 dev_priv
->num_fence_regs
= 32;
4355 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4356 dev_priv
->num_fence_regs
= 16;
4358 dev_priv
->num_fence_regs
= 8;
4360 /* Initialize fence registers to zero */
4361 i915_gem_reset_fences(dev
);
4363 i915_gem_detect_bit_6_swizzle(dev
);
4364 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4366 dev_priv
->mm
.interruptible
= true;
4368 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4369 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4370 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4374 * Create a physically contiguous memory object for this object
4375 * e.g. for cursor + overlay regs
4377 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4378 int id
, int size
, int align
)
4380 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4381 struct drm_i915_gem_phys_object
*phys_obj
;
4384 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4387 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4393 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4394 if (!phys_obj
->handle
) {
4399 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4402 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4410 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4412 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4413 struct drm_i915_gem_phys_object
*phys_obj
;
4415 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4418 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4419 if (phys_obj
->cur_obj
) {
4420 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4424 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4426 drm_pci_free(dev
, phys_obj
->handle
);
4428 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4431 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4435 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4436 i915_gem_free_phys_object(dev
, i
);
4439 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4440 struct drm_i915_gem_object
*obj
)
4442 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4449 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4451 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4452 for (i
= 0; i
< page_count
; i
++) {
4453 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4454 if (!IS_ERR(page
)) {
4455 char *dst
= kmap_atomic(page
);
4456 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4459 drm_clflush_pages(&page
, 1);
4461 set_page_dirty(page
);
4462 mark_page_accessed(page
);
4463 page_cache_release(page
);
4466 i915_gem_chipset_flush(dev
);
4468 obj
->phys_obj
->cur_obj
= NULL
;
4469 obj
->phys_obj
= NULL
;
4473 i915_gem_attach_phys_object(struct drm_device
*dev
,
4474 struct drm_i915_gem_object
*obj
,
4478 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4479 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4484 if (id
> I915_MAX_PHYS_OBJECT
)
4487 if (obj
->phys_obj
) {
4488 if (obj
->phys_obj
->id
== id
)
4490 i915_gem_detach_phys_object(dev
, obj
);
4493 /* create a new object */
4494 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4495 ret
= i915_gem_init_phys_object(dev
, id
,
4496 obj
->base
.size
, align
);
4498 DRM_ERROR("failed to init phys object %d size: %zu\n",
4499 id
, obj
->base
.size
);
4504 /* bind to the object */
4505 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4506 obj
->phys_obj
->cur_obj
= obj
;
4508 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4510 for (i
= 0; i
< page_count
; i
++) {
4514 page
= shmem_read_mapping_page(mapping
, i
);
4516 return PTR_ERR(page
);
4518 src
= kmap_atomic(page
);
4519 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4520 memcpy(dst
, src
, PAGE_SIZE
);
4523 mark_page_accessed(page
);
4524 page_cache_release(page
);
4531 i915_gem_phys_pwrite(struct drm_device
*dev
,
4532 struct drm_i915_gem_object
*obj
,
4533 struct drm_i915_gem_pwrite
*args
,
4534 struct drm_file
*file_priv
)
4536 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4537 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4539 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4540 unsigned long unwritten
;
4542 /* The physical object once assigned is fixed for the lifetime
4543 * of the obj, so we can safely drop the lock and continue
4546 mutex_unlock(&dev
->struct_mutex
);
4547 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4548 mutex_lock(&dev
->struct_mutex
);
4553 i915_gem_chipset_flush(dev
);
4557 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4559 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4561 /* Clean up our request list when the client is going away, so that
4562 * later retire_requests won't dereference our soon-to-be-gone
4565 spin_lock(&file_priv
->mm
.lock
);
4566 while (!list_empty(&file_priv
->mm
.request_list
)) {
4567 struct drm_i915_gem_request
*request
;
4569 request
= list_first_entry(&file_priv
->mm
.request_list
,
4570 struct drm_i915_gem_request
,
4572 list_del(&request
->client_list
);
4573 request
->file_priv
= NULL
;
4575 spin_unlock(&file_priv
->mm
.lock
);
4578 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4580 if (!mutex_is_locked(mutex
))
4583 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4584 return mutex
->owner
== task
;
4586 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4592 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4594 struct drm_i915_private
*dev_priv
=
4595 container_of(shrinker
,
4596 struct drm_i915_private
,
4597 mm
.inactive_shrinker
);
4598 struct drm_device
*dev
= dev_priv
->dev
;
4599 struct drm_i915_gem_object
*obj
;
4600 int nr_to_scan
= sc
->nr_to_scan
;
4604 if (!mutex_trylock(&dev
->struct_mutex
)) {
4605 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4608 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4615 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4617 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4620 i915_gem_shrink_all(dev_priv
);
4624 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4625 if (obj
->pages_pin_count
== 0)
4626 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4627 list_for_each_entry(obj
, &dev_priv
->mm
.inactive_list
, global_list
)
4628 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4629 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4632 mutex_unlock(&dev
->struct_mutex
);