2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define GEN6_CONTEXT_ALIGN (64<<10)
98 #define GEN7_CONTEXT_ALIGN 4096
100 static size_t get_context_alignment(struct drm_device
*dev
)
103 return GEN6_CONTEXT_ALIGN
;
105 return GEN7_CONTEXT_ALIGN
;
108 static int get_context_size(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 switch (INTEL_INFO(dev
)->gen
) {
116 reg
= I915_READ(CXT_SIZE
);
117 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
120 reg
= I915_READ(GEN7_CXT_SIZE
);
122 ret
= HSW_CXT_TOTAL_SIZE
;
124 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
127 ret
= GEN8_CXT_TOTAL_SIZE
;
136 void i915_gem_context_free(struct kref
*ctx_ref
)
138 struct intel_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
140 trace_i915_context_free(ctx
);
142 if (i915
.enable_execlists
)
143 intel_lr_context_free(ctx
);
145 i915_ppgtt_put(ctx
->ppgtt
);
147 if (ctx
->legacy_hw_ctx
.rcs_state
)
148 drm_gem_object_unreference(&ctx
->legacy_hw_ctx
.rcs_state
->base
);
149 list_del(&ctx
->link
);
153 struct drm_i915_gem_object
*
154 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
156 struct drm_i915_gem_object
*obj
;
159 obj
= i915_gem_alloc_object(dev
, size
);
161 return ERR_PTR(-ENOMEM
);
164 * Try to make the context utilize L3 as well as LLC.
166 * On VLV we don't have L3 controls in the PTEs so we
167 * shouldn't touch the cache level, especially as that
168 * would make the object snooped which might have a
169 * negative performance impact.
171 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
)) {
172 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
173 /* Failure shouldn't ever happen this early */
175 drm_gem_object_unreference(&obj
->base
);
183 static struct intel_context
*
184 __create_hw_context(struct drm_device
*dev
,
185 struct drm_i915_file_private
*file_priv
)
187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
188 struct intel_context
*ctx
;
191 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
193 return ERR_PTR(-ENOMEM
);
195 kref_init(&ctx
->ref
);
196 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
197 ctx
->i915
= dev_priv
;
199 if (dev_priv
->hw_context_size
) {
200 struct drm_i915_gem_object
*obj
=
201 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
206 ctx
->legacy_hw_ctx
.rcs_state
= obj
;
209 /* Default context will never have a file_priv */
210 if (file_priv
!= NULL
) {
211 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
212 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
216 ret
= DEFAULT_CONTEXT_HANDLE
;
218 ctx
->file_priv
= file_priv
;
219 ctx
->user_handle
= ret
;
220 /* NB: Mark all slices as needing a remap so that when the context first
221 * loads it will restore whatever remap state already exists. If there
222 * is no remap info, it will be a NOP. */
223 ctx
->remap_slice
= (1 << NUM_L3_SLICES(dev
)) - 1;
225 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
230 i915_gem_context_unreference(ctx
);
235 * The default context needs to exist per ring that uses contexts. It stores the
236 * context state of the GPU for applications that don't utilize HW contexts, as
237 * well as an idle case.
239 static struct intel_context
*
240 i915_gem_create_context(struct drm_device
*dev
,
241 struct drm_i915_file_private
*file_priv
)
243 const bool is_global_default_ctx
= file_priv
== NULL
;
244 struct intel_context
*ctx
;
247 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
249 ctx
= __create_hw_context(dev
, file_priv
);
253 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
) {
254 /* We may need to do things with the shrinker which
255 * require us to immediately switch back to the default
256 * context. This can cause a problem as pinning the
257 * default context also requires GTT space which may not
258 * be available. To avoid this we always pin the default
261 ret
= i915_gem_obj_ggtt_pin(ctx
->legacy_hw_ctx
.rcs_state
,
262 get_context_alignment(dev
), 0);
264 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret
);
269 if (USES_FULL_PPGTT(dev
)) {
270 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
272 if (IS_ERR_OR_NULL(ppgtt
)) {
273 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
275 ret
= PTR_ERR(ppgtt
);
282 trace_i915_context_create(ctx
);
287 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
)
288 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
290 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
291 i915_gem_context_unreference(ctx
);
295 void i915_gem_context_reset(struct drm_device
*dev
)
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 if (i915
.enable_execlists
) {
301 struct intel_context
*ctx
;
303 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
304 intel_lr_context_reset(dev
, ctx
);
310 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
311 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
312 struct intel_context
*lctx
= ring
->last_context
;
315 if (lctx
->legacy_hw_ctx
.rcs_state
&& i
== RCS
)
316 i915_gem_object_ggtt_unpin(lctx
->legacy_hw_ctx
.rcs_state
);
318 i915_gem_context_unreference(lctx
);
319 ring
->last_context
= NULL
;
324 int i915_gem_context_init(struct drm_device
*dev
)
326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 struct intel_context
*ctx
;
330 /* Init should only be called once per module load. Eventually the
331 * restriction on the context_disabled check can be loosened. */
332 if (WARN_ON(dev_priv
->ring
[RCS
].default_context
))
335 if (intel_vgpu_active(dev
) && HAS_LOGICAL_RING_CONTEXTS(dev
)) {
336 if (!i915
.enable_execlists
) {
337 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
342 if (i915
.enable_execlists
) {
343 /* NB: intentionally left blank. We will allocate our own
344 * backing objects as we need them, thank you very much */
345 dev_priv
->hw_context_size
= 0;
346 } else if (HAS_HW_CONTEXTS(dev
)) {
347 dev_priv
->hw_context_size
= round_up(get_context_size(dev
), 4096);
348 if (dev_priv
->hw_context_size
> (1<<20)) {
349 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
350 dev_priv
->hw_context_size
);
351 dev_priv
->hw_context_size
= 0;
355 ctx
= i915_gem_create_context(dev
, NULL
);
357 DRM_ERROR("Failed to create default global context (error %ld)\n",
362 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
363 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
365 /* NB: RCS will hold a ref for all rings */
366 ring
->default_context
= ctx
;
369 DRM_DEBUG_DRIVER("%s context support initialized\n",
370 i915
.enable_execlists
? "LR" :
371 dev_priv
->hw_context_size
? "HW" : "fake");
375 void i915_gem_context_fini(struct drm_device
*dev
)
377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 struct intel_context
*dctx
= dev_priv
->ring
[RCS
].default_context
;
381 if (dctx
->legacy_hw_ctx
.rcs_state
) {
382 /* The only known way to stop the gpu from accessing the hw context is
383 * to reset it. Do this as the very last operation to avoid confusing
384 * other code, leading to spurious errors. */
385 intel_gpu_reset(dev
);
387 /* When default context is created and switched to, base object refcount
388 * will be 2 (+1 from object creation and +1 from do_switch()).
389 * i915_gem_context_fini() will be called after gpu_idle() has switched
390 * to default context. So we need to unreference the base object once
391 * to offset the do_switch part, so that i915_gem_context_unreference()
392 * can then free the base object correctly. */
393 WARN_ON(!dev_priv
->ring
[RCS
].last_context
);
394 if (dev_priv
->ring
[RCS
].last_context
== dctx
) {
395 /* Fake switch to NULL context */
396 WARN_ON(dctx
->legacy_hw_ctx
.rcs_state
->active
);
397 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
398 i915_gem_context_unreference(dctx
);
399 dev_priv
->ring
[RCS
].last_context
= NULL
;
402 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
405 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
406 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
408 if (ring
->last_context
)
409 i915_gem_context_unreference(ring
->last_context
);
411 ring
->default_context
= NULL
;
412 ring
->last_context
= NULL
;
415 i915_gem_context_unreference(dctx
);
418 int i915_gem_context_enable(struct drm_i915_gem_request
*req
)
420 struct intel_engine_cs
*ring
= req
->ring
;
423 if (i915
.enable_execlists
) {
424 if (ring
->init_context
== NULL
)
427 ret
= ring
->init_context(req
);
429 ret
= i915_switch_context(req
);
432 DRM_ERROR("ring init context: %d\n", ret
);
439 static int context_idr_cleanup(int id
, void *p
, void *data
)
441 struct intel_context
*ctx
= p
;
443 i915_gem_context_unreference(ctx
);
447 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
449 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
450 struct intel_context
*ctx
;
452 idr_init(&file_priv
->context_idr
);
454 mutex_lock(&dev
->struct_mutex
);
455 ctx
= i915_gem_create_context(dev
, file_priv
);
456 mutex_unlock(&dev
->struct_mutex
);
459 idr_destroy(&file_priv
->context_idr
);
466 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
468 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
470 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
471 idr_destroy(&file_priv
->context_idr
);
474 struct intel_context
*
475 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
)
477 struct intel_context
*ctx
;
479 ctx
= (struct intel_context
*)idr_find(&file_priv
->context_idr
, id
);
481 return ERR_PTR(-ENOENT
);
487 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
489 struct intel_engine_cs
*ring
= req
->ring
;
490 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
491 const int num_rings
=
492 /* Use an extended w/a on ivb+ if signalling from other rings */
493 i915_semaphore_is_enabled(ring
->dev
) ?
494 hweight32(INTEL_INFO(ring
->dev
)->ring_mask
) - 1 :
498 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
499 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
500 * explicitly, so we rely on the value at ring init, stored in
501 * itlb_before_ctx_switch.
503 if (IS_GEN6(ring
->dev
)) {
504 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, 0);
509 /* These flags are for resource streamer on HSW+ */
510 if (IS_HASWELL(ring
->dev
) || INTEL_INFO(ring
->dev
)->gen
>= 8)
511 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
512 else if (INTEL_INFO(ring
->dev
)->gen
< 8)
513 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
517 if (INTEL_INFO(ring
->dev
)->gen
>= 7)
518 len
+= 2 + (num_rings
? 4*num_rings
+ 2 : 0);
520 ret
= intel_ring_begin(req
, len
);
524 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
525 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
526 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
528 struct intel_engine_cs
*signaller
;
530 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
531 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
532 if (signaller
== ring
)
535 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
536 intel_ring_emit(ring
, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
541 intel_ring_emit(ring
, MI_NOOP
);
542 intel_ring_emit(ring
, MI_SET_CONTEXT
);
543 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(req
->ctx
->legacy_hw_ctx
.rcs_state
) |
546 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
547 * WaMiSetContext_Hang:snb,ivb,vlv
549 intel_ring_emit(ring
, MI_NOOP
);
551 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
553 struct intel_engine_cs
*signaller
;
555 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
556 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
557 if (signaller
== ring
)
560 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
561 intel_ring_emit(ring
, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
564 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
567 intel_ring_advance(ring
);
572 static inline bool should_skip_switch(struct intel_engine_cs
*ring
,
573 struct intel_context
*from
,
574 struct intel_context
*to
)
579 if (to
->ppgtt
&& from
== to
&&
580 !(intel_ring_flag(ring
) & to
->ppgtt
->pd_dirty_rings
))
587 needs_pd_load_pre(struct intel_engine_cs
*ring
, struct intel_context
*to
)
589 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
594 if (INTEL_INFO(ring
->dev
)->gen
< 8)
597 if (ring
!= &dev_priv
->ring
[RCS
])
604 needs_pd_load_post(struct intel_engine_cs
*ring
, struct intel_context
*to
,
607 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
612 if (!IS_GEN8(ring
->dev
))
615 if (ring
!= &dev_priv
->ring
[RCS
])
618 if (hw_flags
& MI_RESTORE_INHIBIT
)
624 static int do_switch(struct drm_i915_gem_request
*req
)
626 struct intel_context
*to
= req
->ctx
;
627 struct intel_engine_cs
*ring
= req
->ring
;
628 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
629 struct intel_context
*from
= ring
->last_context
;
631 bool uninitialized
= false;
634 if (from
!= NULL
&& ring
== &dev_priv
->ring
[RCS
]) {
635 BUG_ON(from
->legacy_hw_ctx
.rcs_state
== NULL
);
636 BUG_ON(!i915_gem_obj_is_pinned(from
->legacy_hw_ctx
.rcs_state
));
639 if (should_skip_switch(ring
, from
, to
))
642 /* Trying to pin first makes error handling easier. */
643 if (ring
== &dev_priv
->ring
[RCS
]) {
644 ret
= i915_gem_obj_ggtt_pin(to
->legacy_hw_ctx
.rcs_state
,
645 get_context_alignment(ring
->dev
), 0);
651 * Pin can switch back to the default context if we end up calling into
652 * evict_everything - as a last ditch gtt defrag effort that also
653 * switches to the default context. Hence we need to reload from here.
655 from
= ring
->last_context
;
657 if (needs_pd_load_pre(ring
, to
)) {
658 /* Older GENs and non render rings still want the load first,
659 * "PP_DCLV followed by PP_DIR_BASE register through Load
660 * Register Immediate commands in Ring Buffer before submitting
662 trace_switch_mm(ring
, to
);
663 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, req
);
667 /* Doing a PD load always reloads the page dirs */
668 to
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(ring
);
671 if (ring
!= &dev_priv
->ring
[RCS
]) {
673 i915_gem_context_unreference(from
);
678 * Clear this page out of any CPU caches for coherent swap-in/out. Note
679 * that thanks to write = false in this call and us not setting any gpu
680 * write domains when putting a context object onto the active list
681 * (when switching away from it), this won't block.
683 * XXX: We need a real interface to do this instead of trickery.
685 ret
= i915_gem_object_set_to_gtt_domain(to
->legacy_hw_ctx
.rcs_state
, false);
689 if (!to
->legacy_hw_ctx
.initialized
) {
690 hw_flags
|= MI_RESTORE_INHIBIT
;
691 /* NB: If we inhibit the restore, the context is not allowed to
692 * die because future work may end up depending on valid address
693 * space. This means we must enforce that a page table load
694 * occur when this occurs. */
695 } else if (to
->ppgtt
&&
696 (intel_ring_flag(ring
) & to
->ppgtt
->pd_dirty_rings
)) {
697 hw_flags
|= MI_FORCE_RESTORE
;
698 to
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(ring
);
701 /* We should never emit switch_mm more than once */
702 WARN_ON(needs_pd_load_pre(ring
, to
) &&
703 needs_pd_load_post(ring
, to
, hw_flags
));
705 ret
= mi_set_context(req
, hw_flags
);
709 /* GEN8 does *not* require an explicit reload if the PDPs have been
710 * setup, and we do not wish to move them.
712 if (needs_pd_load_post(ring
, to
, hw_flags
)) {
713 trace_switch_mm(ring
, to
);
714 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, req
);
715 /* The hardware context switch is emitted, but we haven't
716 * actually changed the state - so it's probably safe to bail
717 * here. Still, let the user know something dangerous has
721 DRM_ERROR("Failed to change address space on context switch\n");
726 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
727 if (!(to
->remap_slice
& (1<<i
)))
730 ret
= i915_gem_l3_remap(req
, i
);
731 /* If it failed, try again next round */
733 DRM_DEBUG_DRIVER("L3 remapping failed\n");
735 to
->remap_slice
&= ~(1<<i
);
738 /* The backing object for the context is done after switching to the
739 * *next* context. Therefore we cannot retire the previous context until
740 * the next context has already started running. In fact, the below code
741 * is a bit suboptimal because the retiring can occur simply after the
742 * MI_SET_CONTEXT instead of when the next seqno has completed.
745 from
->legacy_hw_ctx
.rcs_state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
746 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->legacy_hw_ctx
.rcs_state
), req
);
747 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
748 * whole damn pipeline, we don't need to explicitly mark the
749 * object dirty. The only exception is that the context must be
750 * correct in case the object gets swapped out. Ideally we'd be
751 * able to defer doing this until we know the object would be
752 * swapped, but there is no way to do that yet.
754 from
->legacy_hw_ctx
.rcs_state
->dirty
= 1;
756 /* obj is kept alive until the next request by its active ref */
757 i915_gem_object_ggtt_unpin(from
->legacy_hw_ctx
.rcs_state
);
758 i915_gem_context_unreference(from
);
761 uninitialized
= !to
->legacy_hw_ctx
.initialized
;
762 to
->legacy_hw_ctx
.initialized
= true;
765 i915_gem_context_reference(to
);
766 ring
->last_context
= to
;
769 if (ring
->init_context
) {
770 ret
= ring
->init_context(req
);
772 DRM_ERROR("ring init context: %d\n", ret
);
780 i915_gem_object_ggtt_unpin(to
->legacy_hw_ctx
.rcs_state
);
785 * i915_switch_context() - perform a GPU context switch.
786 * @req: request for which we'll execute the context switch
788 * The context life cycle is simple. The context refcount is incremented and
789 * decremented by 1 and create and destroy. If the context is in use by the GPU,
790 * it will have a refcount > 1. This allows us to destroy the context abstract
791 * object while letting the normal object tracking destroy the backing BO.
793 * This function should not be used in execlists mode. Instead the context is
794 * switched by writing to the ELSP and requests keep a reference to their
797 int i915_switch_context(struct drm_i915_gem_request
*req
)
799 struct intel_engine_cs
*ring
= req
->ring
;
800 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
802 WARN_ON(i915
.enable_execlists
);
803 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
805 if (req
->ctx
->legacy_hw_ctx
.rcs_state
== NULL
) { /* We have the fake context */
806 if (req
->ctx
!= ring
->last_context
) {
807 i915_gem_context_reference(req
->ctx
);
808 if (ring
->last_context
)
809 i915_gem_context_unreference(ring
->last_context
);
810 ring
->last_context
= req
->ctx
;
815 return do_switch(req
);
818 static bool contexts_enabled(struct drm_device
*dev
)
820 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
823 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
824 struct drm_file
*file
)
826 struct drm_i915_gem_context_create
*args
= data
;
827 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
828 struct intel_context
*ctx
;
831 if (!contexts_enabled(dev
))
834 ret
= i915_mutex_lock_interruptible(dev
);
838 ctx
= i915_gem_create_context(dev
, file_priv
);
839 mutex_unlock(&dev
->struct_mutex
);
843 args
->ctx_id
= ctx
->user_handle
;
844 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
849 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
850 struct drm_file
*file
)
852 struct drm_i915_gem_context_destroy
*args
= data
;
853 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
854 struct intel_context
*ctx
;
857 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
860 ret
= i915_mutex_lock_interruptible(dev
);
864 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
866 mutex_unlock(&dev
->struct_mutex
);
870 idr_remove(&ctx
->file_priv
->context_idr
, ctx
->user_handle
);
871 i915_gem_context_unreference(ctx
);
872 mutex_unlock(&dev
->struct_mutex
);
874 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
878 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
879 struct drm_file
*file
)
881 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
882 struct drm_i915_gem_context_param
*args
= data
;
883 struct intel_context
*ctx
;
886 ret
= i915_mutex_lock_interruptible(dev
);
890 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
892 mutex_unlock(&dev
->struct_mutex
);
897 switch (args
->param
) {
898 case I915_CONTEXT_PARAM_BAN_PERIOD
:
899 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
901 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
902 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
908 mutex_unlock(&dev
->struct_mutex
);
913 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
914 struct drm_file
*file
)
916 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
917 struct drm_i915_gem_context_param
*args
= data
;
918 struct intel_context
*ctx
;
921 ret
= i915_mutex_lock_interruptible(dev
);
925 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
927 mutex_unlock(&dev
->struct_mutex
);
931 switch (args
->param
) {
932 case I915_CONTEXT_PARAM_BAN_PERIOD
:
935 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
936 !capable(CAP_SYS_ADMIN
))
939 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
941 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
945 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
946 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
953 mutex_unlock(&dev
->struct_mutex
);