2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define GEN6_CONTEXT_ALIGN (64<<10)
98 #define GEN7_CONTEXT_ALIGN 4096
100 static size_t get_context_alignment(struct drm_device
*dev
)
103 return GEN6_CONTEXT_ALIGN
;
105 return GEN7_CONTEXT_ALIGN
;
108 static int get_context_size(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 switch (INTEL_INFO(dev
)->gen
) {
116 reg
= I915_READ(CXT_SIZE
);
117 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
120 reg
= I915_READ(GEN7_CXT_SIZE
);
122 ret
= HSW_CXT_TOTAL_SIZE
;
124 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
127 ret
= GEN8_CXT_TOTAL_SIZE
;
136 void i915_gem_context_free(struct kref
*ctx_ref
)
138 struct intel_context
*ctx
= container_of(ctx_ref
,
141 trace_i915_context_free(ctx
);
143 if (i915
.enable_execlists
)
144 intel_lr_context_free(ctx
);
146 i915_ppgtt_put(ctx
->ppgtt
);
148 if (ctx
->legacy_hw_ctx
.rcs_state
)
149 drm_gem_object_unreference(&ctx
->legacy_hw_ctx
.rcs_state
->base
);
150 list_del(&ctx
->link
);
154 struct drm_i915_gem_object
*
155 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
157 struct drm_i915_gem_object
*obj
;
160 obj
= i915_gem_alloc_object(dev
, size
);
162 return ERR_PTR(-ENOMEM
);
165 * Try to make the context utilize L3 as well as LLC.
167 * On VLV we don't have L3 controls in the PTEs so we
168 * shouldn't touch the cache level, especially as that
169 * would make the object snooped which might have a
170 * negative performance impact.
172 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
)) {
173 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
174 /* Failure shouldn't ever happen this early */
176 drm_gem_object_unreference(&obj
->base
);
184 static struct intel_context
*
185 __create_hw_context(struct drm_device
*dev
,
186 struct drm_i915_file_private
*file_priv
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 struct intel_context
*ctx
;
192 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
194 return ERR_PTR(-ENOMEM
);
196 kref_init(&ctx
->ref
);
197 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
199 if (dev_priv
->hw_context_size
) {
200 struct drm_i915_gem_object
*obj
=
201 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
206 ctx
->legacy_hw_ctx
.rcs_state
= obj
;
209 /* Default context will never have a file_priv */
210 if (file_priv
!= NULL
) {
211 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
212 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
216 ret
= DEFAULT_CONTEXT_HANDLE
;
218 ctx
->file_priv
= file_priv
;
219 ctx
->user_handle
= ret
;
220 /* NB: Mark all slices as needing a remap so that when the context first
221 * loads it will restore whatever remap state already exists. If there
222 * is no remap info, it will be a NOP. */
223 ctx
->remap_slice
= (1 << NUM_L3_SLICES(dev
)) - 1;
225 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
230 i915_gem_context_unreference(ctx
);
235 * The default context needs to exist per ring that uses contexts. It stores the
236 * context state of the GPU for applications that don't utilize HW contexts, as
237 * well as an idle case.
239 static struct intel_context
*
240 i915_gem_create_context(struct drm_device
*dev
,
241 struct drm_i915_file_private
*file_priv
)
243 const bool is_global_default_ctx
= file_priv
== NULL
;
244 struct intel_context
*ctx
;
247 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
249 ctx
= __create_hw_context(dev
, file_priv
);
253 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
) {
254 /* We may need to do things with the shrinker which
255 * require us to immediately switch back to the default
256 * context. This can cause a problem as pinning the
257 * default context also requires GTT space which may not
258 * be available. To avoid this we always pin the default
261 ret
= i915_gem_obj_ggtt_pin(ctx
->legacy_hw_ctx
.rcs_state
,
262 get_context_alignment(dev
), 0);
264 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret
);
269 if (USES_FULL_PPGTT(dev
)) {
270 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
272 if (IS_ERR_OR_NULL(ppgtt
)) {
273 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
275 ret
= PTR_ERR(ppgtt
);
282 trace_i915_context_create(ctx
);
287 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
)
288 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
290 i915_gem_context_unreference(ctx
);
294 void i915_gem_context_reset(struct drm_device
*dev
)
296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 /* In execlists mode we will unreference the context when the execlist
300 * queue is cleared and the requests destroyed.
302 if (i915
.enable_execlists
)
305 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
306 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
307 struct intel_context
*lctx
= ring
->last_context
;
310 if (lctx
->legacy_hw_ctx
.rcs_state
&& i
== RCS
)
311 i915_gem_object_ggtt_unpin(lctx
->legacy_hw_ctx
.rcs_state
);
313 i915_gem_context_unreference(lctx
);
314 ring
->last_context
= NULL
;
319 int i915_gem_context_init(struct drm_device
*dev
)
321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
322 struct intel_context
*ctx
;
325 /* Init should only be called once per module load. Eventually the
326 * restriction on the context_disabled check can be loosened. */
327 if (WARN_ON(dev_priv
->ring
[RCS
].default_context
))
330 if (i915
.enable_execlists
) {
331 /* NB: intentionally left blank. We will allocate our own
332 * backing objects as we need them, thank you very much */
333 dev_priv
->hw_context_size
= 0;
334 } else if (HAS_HW_CONTEXTS(dev
)) {
335 dev_priv
->hw_context_size
= round_up(get_context_size(dev
), 4096);
336 if (dev_priv
->hw_context_size
> (1<<20)) {
337 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
338 dev_priv
->hw_context_size
);
339 dev_priv
->hw_context_size
= 0;
343 ctx
= i915_gem_create_context(dev
, NULL
);
345 DRM_ERROR("Failed to create default global context (error %ld)\n",
350 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
351 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
353 /* NB: RCS will hold a ref for all rings */
354 ring
->default_context
= ctx
;
357 DRM_DEBUG_DRIVER("%s context support initialized\n",
358 i915
.enable_execlists
? "LR" :
359 dev_priv
->hw_context_size
? "HW" : "fake");
363 void i915_gem_context_fini(struct drm_device
*dev
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct intel_context
*dctx
= dev_priv
->ring
[RCS
].default_context
;
369 if (dctx
->legacy_hw_ctx
.rcs_state
) {
370 /* The only known way to stop the gpu from accessing the hw context is
371 * to reset it. Do this as the very last operation to avoid confusing
372 * other code, leading to spurious errors. */
373 intel_gpu_reset(dev
);
375 /* When default context is created and switched to, base object refcount
376 * will be 2 (+1 from object creation and +1 from do_switch()).
377 * i915_gem_context_fini() will be called after gpu_idle() has switched
378 * to default context. So we need to unreference the base object once
379 * to offset the do_switch part, so that i915_gem_context_unreference()
380 * can then free the base object correctly. */
381 WARN_ON(!dev_priv
->ring
[RCS
].last_context
);
382 if (dev_priv
->ring
[RCS
].last_context
== dctx
) {
383 /* Fake switch to NULL context */
384 WARN_ON(dctx
->legacy_hw_ctx
.rcs_state
->active
);
385 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
386 i915_gem_context_unreference(dctx
);
387 dev_priv
->ring
[RCS
].last_context
= NULL
;
390 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
393 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
394 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
396 if (ring
->last_context
)
397 i915_gem_context_unreference(ring
->last_context
);
399 ring
->default_context
= NULL
;
400 ring
->last_context
= NULL
;
403 i915_gem_context_unreference(dctx
);
406 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
)
408 struct intel_engine_cs
*ring
;
411 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
413 if (i915
.enable_execlists
) {
414 for_each_ring(ring
, dev_priv
, i
) {
415 if (ring
->init_context
) {
416 ret
= ring
->init_context(ring
,
417 ring
->default_context
);
419 DRM_ERROR("ring init context: %d\n",
427 for_each_ring(ring
, dev_priv
, i
) {
428 ret
= i915_switch_context(ring
, ring
->default_context
);
436 static int context_idr_cleanup(int id
, void *p
, void *data
)
438 struct intel_context
*ctx
= p
;
440 i915_gem_context_unreference(ctx
);
444 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
446 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
447 struct intel_context
*ctx
;
449 idr_init(&file_priv
->context_idr
);
451 mutex_lock(&dev
->struct_mutex
);
452 ctx
= i915_gem_create_context(dev
, file_priv
);
453 mutex_unlock(&dev
->struct_mutex
);
456 idr_destroy(&file_priv
->context_idr
);
463 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
465 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
467 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
468 idr_destroy(&file_priv
->context_idr
);
471 struct intel_context
*
472 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
)
474 struct intel_context
*ctx
;
476 ctx
= (struct intel_context
*)idr_find(&file_priv
->context_idr
, id
);
478 return ERR_PTR(-ENOENT
);
484 mi_set_context(struct intel_engine_cs
*ring
,
485 struct intel_context
*new_context
,
488 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
489 const int num_rings
=
490 /* Use an extended w/a on ivb+ if signalling from other rings */
491 i915_semaphore_is_enabled(ring
->dev
) ?
492 hweight32(INTEL_INFO(ring
->dev
)->ring_mask
) - 1 :
496 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
497 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
498 * explicitly, so we rely on the value at ring init, stored in
499 * itlb_before_ctx_switch.
501 if (IS_GEN6(ring
->dev
)) {
502 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, 0);
507 /* These flags are for resource streamer on HSW+ */
508 if (!IS_HASWELL(ring
->dev
) && INTEL_INFO(ring
->dev
)->gen
< 8)
509 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
513 if (INTEL_INFO(ring
->dev
)->gen
>= 7)
514 len
+= 2 + (num_rings
? 4*num_rings
+ 2 : 0);
516 ret
= intel_ring_begin(ring
, len
);
520 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
521 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
522 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
524 struct intel_engine_cs
*signaller
;
526 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
527 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
528 if (signaller
== ring
)
531 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
532 intel_ring_emit(ring
, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
537 intel_ring_emit(ring
, MI_NOOP
);
538 intel_ring_emit(ring
, MI_SET_CONTEXT
);
539 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(new_context
->legacy_hw_ctx
.rcs_state
) |
542 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
543 * WaMiSetContext_Hang:snb,ivb,vlv
545 intel_ring_emit(ring
, MI_NOOP
);
547 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
549 struct intel_engine_cs
*signaller
;
551 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
552 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
553 if (signaller
== ring
)
556 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
557 intel_ring_emit(ring
, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
560 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
563 intel_ring_advance(ring
);
568 static int do_switch(struct intel_engine_cs
*ring
,
569 struct intel_context
*to
)
571 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
572 struct intel_context
*from
= ring
->last_context
;
574 bool uninitialized
= false;
575 struct i915_vma
*vma
;
578 if (from
!= NULL
&& ring
== &dev_priv
->ring
[RCS
]) {
579 BUG_ON(from
->legacy_hw_ctx
.rcs_state
== NULL
);
580 BUG_ON(!i915_gem_obj_is_pinned(from
->legacy_hw_ctx
.rcs_state
));
583 if (from
== to
&& !to
->remap_slice
)
586 /* Trying to pin first makes error handling easier. */
587 if (ring
== &dev_priv
->ring
[RCS
]) {
588 ret
= i915_gem_obj_ggtt_pin(to
->legacy_hw_ctx
.rcs_state
,
589 get_context_alignment(ring
->dev
), 0);
595 * Pin can switch back to the default context if we end up calling into
596 * evict_everything - as a last ditch gtt defrag effort that also
597 * switches to the default context. Hence we need to reload from here.
599 from
= ring
->last_context
;
602 trace_switch_mm(ring
, to
);
603 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, ring
);
608 if (ring
!= &dev_priv
->ring
[RCS
]) {
610 i915_gem_context_unreference(from
);
615 * Clear this page out of any CPU caches for coherent swap-in/out. Note
616 * that thanks to write = false in this call and us not setting any gpu
617 * write domains when putting a context object onto the active list
618 * (when switching away from it), this won't block.
620 * XXX: We need a real interface to do this instead of trickery.
622 ret
= i915_gem_object_set_to_gtt_domain(to
->legacy_hw_ctx
.rcs_state
, false);
626 vma
= i915_gem_obj_to_ggtt(to
->legacy_hw_ctx
.rcs_state
);
627 if (!(vma
->bound
& GLOBAL_BIND
)) {
628 ret
= i915_vma_bind(vma
,
629 to
->legacy_hw_ctx
.rcs_state
->cache_level
,
631 /* This shouldn't ever fail. */
632 if (WARN_ONCE(ret
, "GGTT context bind failed!"))
636 if (!to
->legacy_hw_ctx
.initialized
|| i915_gem_context_is_default(to
))
637 hw_flags
|= MI_RESTORE_INHIBIT
;
639 ret
= mi_set_context(ring
, to
, hw_flags
);
643 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
644 if (!(to
->remap_slice
& (1<<i
)))
647 ret
= i915_gem_l3_remap(ring
, i
);
648 /* If it failed, try again next round */
650 DRM_DEBUG_DRIVER("L3 remapping failed\n");
652 to
->remap_slice
&= ~(1<<i
);
655 /* The backing object for the context is done after switching to the
656 * *next* context. Therefore we cannot retire the previous context until
657 * the next context has already started running. In fact, the below code
658 * is a bit suboptimal because the retiring can occur simply after the
659 * MI_SET_CONTEXT instead of when the next seqno has completed.
662 from
->legacy_hw_ctx
.rcs_state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
663 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->legacy_hw_ctx
.rcs_state
), ring
);
664 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
665 * whole damn pipeline, we don't need to explicitly mark the
666 * object dirty. The only exception is that the context must be
667 * correct in case the object gets swapped out. Ideally we'd be
668 * able to defer doing this until we know the object would be
669 * swapped, but there is no way to do that yet.
671 from
->legacy_hw_ctx
.rcs_state
->dirty
= 1;
672 BUG_ON(i915_gem_request_get_ring(
673 from
->legacy_hw_ctx
.rcs_state
->last_read_req
) != ring
);
675 /* obj is kept alive until the next request by its active ref */
676 i915_gem_object_ggtt_unpin(from
->legacy_hw_ctx
.rcs_state
);
677 i915_gem_context_unreference(from
);
680 uninitialized
= !to
->legacy_hw_ctx
.initialized
&& from
== NULL
;
681 to
->legacy_hw_ctx
.initialized
= true;
684 i915_gem_context_reference(to
);
685 ring
->last_context
= to
;
688 if (ring
->init_context
) {
689 ret
= ring
->init_context(ring
, to
);
691 DRM_ERROR("ring init context: %d\n", ret
);
699 i915_gem_object_ggtt_unpin(to
->legacy_hw_ctx
.rcs_state
);
704 * i915_switch_context() - perform a GPU context switch.
705 * @ring: ring for which we'll execute the context switch
706 * @to: the context to switch to
708 * The context life cycle is simple. The context refcount is incremented and
709 * decremented by 1 and create and destroy. If the context is in use by the GPU,
710 * it will have a refcount > 1. This allows us to destroy the context abstract
711 * object while letting the normal object tracking destroy the backing BO.
713 * This function should not be used in execlists mode. Instead the context is
714 * switched by writing to the ELSP and requests keep a reference to their
717 int i915_switch_context(struct intel_engine_cs
*ring
,
718 struct intel_context
*to
)
720 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
722 WARN_ON(i915
.enable_execlists
);
723 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
725 if (to
->legacy_hw_ctx
.rcs_state
== NULL
) { /* We have the fake context */
726 if (to
!= ring
->last_context
) {
727 i915_gem_context_reference(to
);
728 if (ring
->last_context
)
729 i915_gem_context_unreference(ring
->last_context
);
730 ring
->last_context
= to
;
735 return do_switch(ring
, to
);
738 static bool contexts_enabled(struct drm_device
*dev
)
740 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
743 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
744 struct drm_file
*file
)
746 struct drm_i915_gem_context_create
*args
= data
;
747 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
748 struct intel_context
*ctx
;
751 if (!contexts_enabled(dev
))
754 ret
= i915_mutex_lock_interruptible(dev
);
758 ctx
= i915_gem_create_context(dev
, file_priv
);
759 mutex_unlock(&dev
->struct_mutex
);
763 args
->ctx_id
= ctx
->user_handle
;
764 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
769 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
770 struct drm_file
*file
)
772 struct drm_i915_gem_context_destroy
*args
= data
;
773 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
774 struct intel_context
*ctx
;
777 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
780 ret
= i915_mutex_lock_interruptible(dev
);
784 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
786 mutex_unlock(&dev
->struct_mutex
);
790 idr_remove(&ctx
->file_priv
->context_idr
, ctx
->user_handle
);
791 i915_gem_context_unreference(ctx
);
792 mutex_unlock(&dev
->struct_mutex
);
794 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
798 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
799 struct drm_file
*file
)
801 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
802 struct drm_i915_gem_context_param
*args
= data
;
803 struct intel_context
*ctx
;
806 ret
= i915_mutex_lock_interruptible(dev
);
810 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
812 mutex_unlock(&dev
->struct_mutex
);
817 switch (args
->param
) {
818 case I915_CONTEXT_PARAM_BAN_PERIOD
:
819 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
825 mutex_unlock(&dev
->struct_mutex
);
830 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
831 struct drm_file
*file
)
833 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
834 struct drm_i915_gem_context_param
*args
= data
;
835 struct intel_context
*ctx
;
838 ret
= i915_mutex_lock_interruptible(dev
);
842 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
844 mutex_unlock(&dev
->struct_mutex
);
848 switch (args
->param
) {
849 case I915_CONTEXT_PARAM_BAN_PERIOD
:
852 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
853 !capable(CAP_SYS_ADMIN
))
856 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
862 mutex_unlock(&dev
->struct_mutex
);