2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private
*dev_priv
)
104 if (IS_GEN6(dev_priv
))
105 return GEN6_CONTEXT_ALIGN
;
107 return GEN7_CONTEXT_ALIGN
;
110 static int get_context_size(struct drm_i915_private
*dev_priv
)
115 switch (INTEL_GEN(dev_priv
)) {
117 reg
= I915_READ(CXT_SIZE
);
118 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
121 reg
= I915_READ(GEN7_CXT_SIZE
);
122 if (IS_HASWELL(dev_priv
))
123 ret
= HSW_CXT_TOTAL_SIZE
;
125 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
128 ret
= GEN8_CXT_TOTAL_SIZE
;
137 static void i915_gem_context_clean(struct intel_context
*ctx
)
139 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
140 struct i915_vma
*vma
, *next
;
145 list_for_each_entry_safe(vma
, next
, &ppgtt
->base
.inactive_list
,
147 if (WARN_ON(__i915_vma_unbind_no_wait(vma
)))
152 void i915_gem_context_free(struct kref
*ctx_ref
)
154 struct intel_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
156 trace_i915_context_free(ctx
);
158 if (i915
.enable_execlists
)
159 intel_lr_context_free(ctx
);
162 * This context is going away and we need to remove all VMAs still
163 * around. This is to handle imported shared objects for which
164 * destructor did not run when their handles were closed.
166 i915_gem_context_clean(ctx
);
168 i915_ppgtt_put(ctx
->ppgtt
);
170 if (ctx
->legacy_hw_ctx
.rcs_state
)
171 drm_gem_object_unreference(&ctx
->legacy_hw_ctx
.rcs_state
->base
);
172 list_del(&ctx
->link
);
174 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
178 struct drm_i915_gem_object
*
179 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
181 struct drm_i915_gem_object
*obj
;
184 obj
= i915_gem_object_create(dev
, size
);
189 * Try to make the context utilize L3 as well as LLC.
191 * On VLV we don't have L3 controls in the PTEs so we
192 * shouldn't touch the cache level, especially as that
193 * would make the object snooped which might have a
194 * negative performance impact.
196 * Snooping is required on non-llc platforms in execlist
197 * mode, but since all GGTT accesses use PAT entry 0 we
198 * get snooping anyway regardless of cache_level.
200 * This is only applicable for Ivy Bridge devices since
201 * later platforms don't have L3 control bits in the PTE.
203 if (IS_IVYBRIDGE(dev
)) {
204 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
205 /* Failure shouldn't ever happen this early */
207 drm_gem_object_unreference(&obj
->base
);
215 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
219 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
220 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
222 /* Contexts are only released when no longer active.
223 * Flush any pending retires to hopefully release some
224 * stale contexts and try again.
226 i915_gem_retire_requests(dev_priv
);
227 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
228 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
237 static struct intel_context
*
238 __create_hw_context(struct drm_device
*dev
,
239 struct drm_i915_file_private
*file_priv
)
241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
242 struct intel_context
*ctx
;
245 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
247 return ERR_PTR(-ENOMEM
);
249 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
255 kref_init(&ctx
->ref
);
256 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
257 ctx
->i915
= dev_priv
;
259 if (dev_priv
->hw_context_size
) {
260 struct drm_i915_gem_object
*obj
=
261 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
266 ctx
->legacy_hw_ctx
.rcs_state
= obj
;
269 /* Default context will never have a file_priv */
270 if (file_priv
!= NULL
) {
271 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
272 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
276 ret
= DEFAULT_CONTEXT_HANDLE
;
278 ctx
->file_priv
= file_priv
;
279 ctx
->user_handle
= ret
;
280 /* NB: Mark all slices as needing a remap so that when the context first
281 * loads it will restore whatever remap state already exists. If there
282 * is no remap info, it will be a NOP. */
283 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
285 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
290 i915_gem_context_unreference(ctx
);
295 * The default context needs to exist per ring that uses contexts. It stores the
296 * context state of the GPU for applications that don't utilize HW contexts, as
297 * well as an idle case.
299 static struct intel_context
*
300 i915_gem_create_context(struct drm_device
*dev
,
301 struct drm_i915_file_private
*file_priv
)
303 const bool is_global_default_ctx
= file_priv
== NULL
;
304 struct intel_context
*ctx
;
307 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
309 ctx
= __create_hw_context(dev
, file_priv
);
313 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
) {
314 /* We may need to do things with the shrinker which
315 * require us to immediately switch back to the default
316 * context. This can cause a problem as pinning the
317 * default context also requires GTT space which may not
318 * be available. To avoid this we always pin the default
321 ret
= i915_gem_obj_ggtt_pin(ctx
->legacy_hw_ctx
.rcs_state
,
322 get_context_alignment(to_i915(dev
)), 0);
324 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret
);
329 if (USES_FULL_PPGTT(dev
)) {
330 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
332 if (IS_ERR_OR_NULL(ppgtt
)) {
333 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
335 ret
= PTR_ERR(ppgtt
);
342 trace_i915_context_create(ctx
);
347 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
)
348 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
350 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
351 i915_gem_context_unreference(ctx
);
355 static void i915_gem_context_unpin(struct intel_context
*ctx
,
356 struct intel_engine_cs
*engine
)
358 if (i915
.enable_execlists
) {
359 intel_lr_context_unpin(ctx
, engine
);
361 if (engine
->id
== RCS
&& ctx
->legacy_hw_ctx
.rcs_state
)
362 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
363 i915_gem_context_unreference(ctx
);
367 void i915_gem_context_reset(struct drm_device
*dev
)
369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
371 if (i915
.enable_execlists
) {
372 struct intel_context
*ctx
;
374 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
375 intel_lr_context_reset(dev_priv
, ctx
);
378 i915_gem_context_lost(dev_priv
);
381 int i915_gem_context_init(struct drm_device
*dev
)
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 struct intel_context
*ctx
;
386 /* Init should only be called once per module load. Eventually the
387 * restriction on the context_disabled check can be loosened. */
388 if (WARN_ON(dev_priv
->kernel_context
))
391 if (intel_vgpu_active(dev_priv
) &&
392 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
393 if (!i915
.enable_execlists
) {
394 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
399 /* Using the simple ida interface, the max is limited by sizeof(int) */
400 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
401 ida_init(&dev_priv
->context_hw_ida
);
403 if (i915
.enable_execlists
) {
404 /* NB: intentionally left blank. We will allocate our own
405 * backing objects as we need them, thank you very much */
406 dev_priv
->hw_context_size
= 0;
407 } else if (HAS_HW_CONTEXTS(dev_priv
)) {
408 dev_priv
->hw_context_size
=
409 round_up(get_context_size(dev_priv
), 4096);
410 if (dev_priv
->hw_context_size
> (1<<20)) {
411 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
412 dev_priv
->hw_context_size
);
413 dev_priv
->hw_context_size
= 0;
417 ctx
= i915_gem_create_context(dev
, NULL
);
419 DRM_ERROR("Failed to create default global context (error %ld)\n",
424 dev_priv
->kernel_context
= ctx
;
426 DRM_DEBUG_DRIVER("%s context support initialized\n",
427 i915
.enable_execlists
? "LR" :
428 dev_priv
->hw_context_size
? "HW" : "fake");
432 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
434 struct intel_engine_cs
*engine
;
436 for_each_engine(engine
, dev_priv
) {
437 if (engine
->last_context
== NULL
)
440 i915_gem_context_unpin(engine
->last_context
, engine
);
441 engine
->last_context
= NULL
;
444 /* Force the GPU state to be reinitialised on enabling */
445 dev_priv
->kernel_context
->legacy_hw_ctx
.initialized
= false;
446 dev_priv
->kernel_context
->remap_slice
= ALL_L3_SLICES(dev_priv
);
449 void i915_gem_context_fini(struct drm_device
*dev
)
451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
452 struct intel_context
*dctx
= dev_priv
->kernel_context
;
454 if (dctx
->legacy_hw_ctx
.rcs_state
)
455 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
457 i915_gem_context_unreference(dctx
);
458 dev_priv
->kernel_context
= NULL
;
460 ida_destroy(&dev_priv
->context_hw_ida
);
463 static int context_idr_cleanup(int id
, void *p
, void *data
)
465 struct intel_context
*ctx
= p
;
467 i915_gem_context_unreference(ctx
);
471 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
473 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
474 struct intel_context
*ctx
;
476 idr_init(&file_priv
->context_idr
);
478 mutex_lock(&dev
->struct_mutex
);
479 ctx
= i915_gem_create_context(dev
, file_priv
);
480 mutex_unlock(&dev
->struct_mutex
);
483 idr_destroy(&file_priv
->context_idr
);
490 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
492 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
494 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
495 idr_destroy(&file_priv
->context_idr
);
498 struct intel_context
*
499 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
)
501 struct intel_context
*ctx
;
503 ctx
= (struct intel_context
*)idr_find(&file_priv
->context_idr
, id
);
505 return ERR_PTR(-ENOENT
);
511 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
513 struct drm_i915_private
*dev_priv
= req
->i915
;
514 struct intel_engine_cs
*engine
= req
->engine
;
515 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
516 const int num_rings
=
517 /* Use an extended w/a on ivb+ if signalling from other rings */
518 i915_semaphore_is_enabled(dev_priv
) ?
519 hweight32(INTEL_INFO(dev_priv
)->ring_mask
) - 1 :
523 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
524 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
525 * explicitly, so we rely on the value at ring init, stored in
526 * itlb_before_ctx_switch.
528 if (IS_GEN6(dev_priv
)) {
529 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, 0);
534 /* These flags are for resource streamer on HSW+ */
535 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
536 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
537 else if (INTEL_GEN(dev_priv
) < 8)
538 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
542 if (INTEL_GEN(dev_priv
) >= 7)
543 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
545 ret
= intel_ring_begin(req
, len
);
549 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
550 if (INTEL_GEN(dev_priv
) >= 7) {
551 intel_ring_emit(engine
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
553 struct intel_engine_cs
*signaller
;
555 intel_ring_emit(engine
,
556 MI_LOAD_REGISTER_IMM(num_rings
));
557 for_each_engine(signaller
, dev_priv
) {
558 if (signaller
== engine
)
561 intel_ring_emit_reg(engine
,
562 RING_PSMI_CTL(signaller
->mmio_base
));
563 intel_ring_emit(engine
,
564 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
569 intel_ring_emit(engine
, MI_NOOP
);
570 intel_ring_emit(engine
, MI_SET_CONTEXT
);
571 intel_ring_emit(engine
,
572 i915_gem_obj_ggtt_offset(req
->ctx
->legacy_hw_ctx
.rcs_state
) |
575 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
576 * WaMiSetContext_Hang:snb,ivb,vlv
578 intel_ring_emit(engine
, MI_NOOP
);
580 if (INTEL_GEN(dev_priv
) >= 7) {
582 struct intel_engine_cs
*signaller
;
583 i915_reg_t last_reg
= {}; /* keep gcc quiet */
585 intel_ring_emit(engine
,
586 MI_LOAD_REGISTER_IMM(num_rings
));
587 for_each_engine(signaller
, dev_priv
) {
588 if (signaller
== engine
)
591 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
592 intel_ring_emit_reg(engine
, last_reg
);
593 intel_ring_emit(engine
,
594 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
597 /* Insert a delay before the next switch! */
598 intel_ring_emit(engine
,
599 MI_STORE_REGISTER_MEM
|
600 MI_SRM_LRM_GLOBAL_GTT
);
601 intel_ring_emit_reg(engine
, last_reg
);
602 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
);
603 intel_ring_emit(engine
, MI_NOOP
);
605 intel_ring_emit(engine
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
608 intel_ring_advance(engine
);
613 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
615 u32
*remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
616 struct intel_engine_cs
*engine
= req
->engine
;
622 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
627 * Note: We do not worry about the concurrent register cacheline hang
628 * here because no other code should access these registers other than
629 * at initialization time.
631 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4));
632 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
633 intel_ring_emit_reg(engine
, GEN7_L3LOG(slice
, i
));
634 intel_ring_emit(engine
, remap_info
[i
]);
636 intel_ring_emit(engine
, MI_NOOP
);
637 intel_ring_advance(engine
);
642 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
643 struct intel_engine_cs
*engine
,
644 struct intel_context
*to
)
649 if (!to
->legacy_hw_ctx
.initialized
)
652 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
655 return to
== engine
->last_context
;
659 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
,
660 struct intel_engine_cs
*engine
,
661 struct intel_context
*to
)
666 /* Always load the ppgtt on first use */
667 if (!engine
->last_context
)
670 /* Same context without new entries, skip */
671 if (engine
->last_context
== to
&&
672 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
675 if (engine
->id
!= RCS
)
678 if (INTEL_GEN(engine
->i915
) < 8)
685 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
686 struct intel_context
*to
,
692 if (!IS_GEN8(to
->i915
))
695 if (hw_flags
& MI_RESTORE_INHIBIT
)
701 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
703 struct intel_context
*to
= req
->ctx
;
704 struct intel_engine_cs
*engine
= req
->engine
;
705 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
706 struct intel_context
*from
;
710 if (skip_rcs_switch(ppgtt
, engine
, to
))
713 /* Trying to pin first makes error handling easier. */
714 ret
= i915_gem_obj_ggtt_pin(to
->legacy_hw_ctx
.rcs_state
,
715 get_context_alignment(engine
->i915
),
721 * Pin can switch back to the default context if we end up calling into
722 * evict_everything - as a last ditch gtt defrag effort that also
723 * switches to the default context. Hence we need to reload from here.
725 * XXX: Doing so is painfully broken!
727 from
= engine
->last_context
;
730 * Clear this page out of any CPU caches for coherent swap-in/out. Note
731 * that thanks to write = false in this call and us not setting any gpu
732 * write domains when putting a context object onto the active list
733 * (when switching away from it), this won't block.
735 * XXX: We need a real interface to do this instead of trickery.
737 ret
= i915_gem_object_set_to_gtt_domain(to
->legacy_hw_ctx
.rcs_state
, false);
741 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
742 /* Older GENs and non render rings still want the load first,
743 * "PP_DCLV followed by PP_DIR_BASE register through Load
744 * Register Immediate commands in Ring Buffer before submitting
746 trace_switch_mm(engine
, to
);
747 ret
= ppgtt
->switch_mm(ppgtt
, req
);
752 if (!to
->legacy_hw_ctx
.initialized
|| i915_gem_context_is_default(to
))
753 /* NB: If we inhibit the restore, the context is not allowed to
754 * die because future work may end up depending on valid address
755 * space. This means we must enforce that a page table load
756 * occur when this occurs. */
757 hw_flags
= MI_RESTORE_INHIBIT
;
758 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
759 hw_flags
= MI_FORCE_RESTORE
;
763 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
764 ret
= mi_set_context(req
, hw_flags
);
769 /* The backing object for the context is done after switching to the
770 * *next* context. Therefore we cannot retire the previous context until
771 * the next context has already started running. In fact, the below code
772 * is a bit suboptimal because the retiring can occur simply after the
773 * MI_SET_CONTEXT instead of when the next seqno has completed.
776 from
->legacy_hw_ctx
.rcs_state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
777 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->legacy_hw_ctx
.rcs_state
), req
);
778 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
779 * whole damn pipeline, we don't need to explicitly mark the
780 * object dirty. The only exception is that the context must be
781 * correct in case the object gets swapped out. Ideally we'd be
782 * able to defer doing this until we know the object would be
783 * swapped, but there is no way to do that yet.
785 from
->legacy_hw_ctx
.rcs_state
->dirty
= 1;
787 /* obj is kept alive until the next request by its active ref */
788 i915_gem_object_ggtt_unpin(from
->legacy_hw_ctx
.rcs_state
);
789 i915_gem_context_unreference(from
);
791 i915_gem_context_reference(to
);
792 engine
->last_context
= to
;
794 /* GEN8 does *not* require an explicit reload if the PDPs have been
795 * setup, and we do not wish to move them.
797 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
798 trace_switch_mm(engine
, to
);
799 ret
= ppgtt
->switch_mm(ppgtt
, req
);
800 /* The hardware context switch is emitted, but we haven't
801 * actually changed the state - so it's probably safe to bail
802 * here. Still, let the user know something dangerous has
810 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
812 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
813 if (!(to
->remap_slice
& (1<<i
)))
816 ret
= remap_l3(req
, i
);
820 to
->remap_slice
&= ~(1<<i
);
823 if (!to
->legacy_hw_ctx
.initialized
) {
824 if (engine
->init_context
) {
825 ret
= engine
->init_context(req
);
829 to
->legacy_hw_ctx
.initialized
= true;
835 i915_gem_object_ggtt_unpin(to
->legacy_hw_ctx
.rcs_state
);
840 * i915_switch_context() - perform a GPU context switch.
841 * @req: request for which we'll execute the context switch
843 * The context life cycle is simple. The context refcount is incremented and
844 * decremented by 1 and create and destroy. If the context is in use by the GPU,
845 * it will have a refcount > 1. This allows us to destroy the context abstract
846 * object while letting the normal object tracking destroy the backing BO.
848 * This function should not be used in execlists mode. Instead the context is
849 * switched by writing to the ELSP and requests keep a reference to their
852 int i915_switch_context(struct drm_i915_gem_request
*req
)
854 struct intel_engine_cs
*engine
= req
->engine
;
855 struct drm_i915_private
*dev_priv
= req
->i915
;
857 WARN_ON(i915
.enable_execlists
);
858 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
860 if (engine
->id
!= RCS
||
861 req
->ctx
->legacy_hw_ctx
.rcs_state
== NULL
) {
862 struct intel_context
*to
= req
->ctx
;
863 struct i915_hw_ppgtt
*ppgtt
=
864 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
866 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
869 trace_switch_mm(engine
, to
);
870 ret
= ppgtt
->switch_mm(ppgtt
, req
);
874 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
877 if (to
!= engine
->last_context
) {
878 i915_gem_context_reference(to
);
879 if (engine
->last_context
)
880 i915_gem_context_unreference(engine
->last_context
);
881 engine
->last_context
= to
;
887 return do_rcs_switch(req
);
890 static bool contexts_enabled(struct drm_device
*dev
)
892 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
895 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
896 struct drm_file
*file
)
898 struct drm_i915_gem_context_create
*args
= data
;
899 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
900 struct intel_context
*ctx
;
903 if (!contexts_enabled(dev
))
909 ret
= i915_mutex_lock_interruptible(dev
);
913 ctx
= i915_gem_create_context(dev
, file_priv
);
914 mutex_unlock(&dev
->struct_mutex
);
918 args
->ctx_id
= ctx
->user_handle
;
919 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
924 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
925 struct drm_file
*file
)
927 struct drm_i915_gem_context_destroy
*args
= data
;
928 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
929 struct intel_context
*ctx
;
935 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
938 ret
= i915_mutex_lock_interruptible(dev
);
942 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
944 mutex_unlock(&dev
->struct_mutex
);
948 idr_remove(&ctx
->file_priv
->context_idr
, ctx
->user_handle
);
949 i915_gem_context_unreference(ctx
);
950 mutex_unlock(&dev
->struct_mutex
);
952 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
956 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
957 struct drm_file
*file
)
959 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
960 struct drm_i915_gem_context_param
*args
= data
;
961 struct intel_context
*ctx
;
964 ret
= i915_mutex_lock_interruptible(dev
);
968 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
970 mutex_unlock(&dev
->struct_mutex
);
975 switch (args
->param
) {
976 case I915_CONTEXT_PARAM_BAN_PERIOD
:
977 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
979 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
980 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
982 case I915_CONTEXT_PARAM_GTT_SIZE
:
984 args
->value
= ctx
->ppgtt
->base
.total
;
985 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
986 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
988 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
994 mutex_unlock(&dev
->struct_mutex
);
999 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1000 struct drm_file
*file
)
1002 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1003 struct drm_i915_gem_context_param
*args
= data
;
1004 struct intel_context
*ctx
;
1007 ret
= i915_mutex_lock_interruptible(dev
);
1011 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
1013 mutex_unlock(&dev
->struct_mutex
);
1014 return PTR_ERR(ctx
);
1017 switch (args
->param
) {
1018 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1021 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
1022 !capable(CAP_SYS_ADMIN
))
1025 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
1027 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1031 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1032 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1039 mutex_unlock(&dev
->struct_mutex
);