2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private
*dev_priv
)
104 if (IS_GEN6(dev_priv
))
105 return GEN6_CONTEXT_ALIGN
;
107 return GEN7_CONTEXT_ALIGN
;
110 static int get_context_size(struct drm_i915_private
*dev_priv
)
115 switch (INTEL_GEN(dev_priv
)) {
117 reg
= I915_READ(CXT_SIZE
);
118 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
121 reg
= I915_READ(GEN7_CXT_SIZE
);
122 if (IS_HASWELL(dev_priv
))
123 ret
= HSW_CXT_TOTAL_SIZE
;
125 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
128 ret
= GEN8_CXT_TOTAL_SIZE
;
137 static void i915_gem_context_clean(struct i915_gem_context
*ctx
)
139 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
140 struct i915_vma
*vma
, *next
;
145 list_for_each_entry_safe(vma
, next
, &ppgtt
->base
.inactive_list
,
147 if (WARN_ON(__i915_vma_unbind_no_wait(vma
)))
152 void i915_gem_context_free(struct kref
*ctx_ref
)
154 struct i915_gem_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
157 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
158 trace_i915_context_free(ctx
);
159 GEM_BUG_ON(!ctx
->closed
);
162 * This context is going away and we need to remove all VMAs still
163 * around. This is to handle imported shared objects for which
164 * destructor did not run when their handles were closed.
166 i915_gem_context_clean(ctx
);
168 i915_ppgtt_put(ctx
->ppgtt
);
170 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
171 struct intel_context
*ce
= &ctx
->engine
[i
];
176 WARN_ON(ce
->pin_count
);
178 intel_ring_free(ce
->ring
);
180 i915_gem_object_put(ce
->state
);
183 list_del(&ctx
->link
);
185 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
189 struct drm_i915_gem_object
*
190 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
192 struct drm_i915_gem_object
*obj
;
195 lockdep_assert_held(&dev
->struct_mutex
);
197 obj
= i915_gem_object_create(dev
, size
);
202 * Try to make the context utilize L3 as well as LLC.
204 * On VLV we don't have L3 controls in the PTEs so we
205 * shouldn't touch the cache level, especially as that
206 * would make the object snooped which might have a
207 * negative performance impact.
209 * Snooping is required on non-llc platforms in execlist
210 * mode, but since all GGTT accesses use PAT entry 0 we
211 * get snooping anyway regardless of cache_level.
213 * This is only applicable for Ivy Bridge devices since
214 * later platforms don't have L3 control bits in the PTE.
216 if (IS_IVYBRIDGE(dev
)) {
217 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
218 /* Failure shouldn't ever happen this early */
220 i915_gem_object_put(obj
);
228 static void i915_ppgtt_close(struct i915_address_space
*vm
)
230 struct list_head
*phases
[] = {
237 GEM_BUG_ON(vm
->closed
);
240 for (phase
= phases
; *phase
; phase
++) {
241 struct i915_vma
*vma
, *vn
;
243 list_for_each_entry_safe(vma
, vn
, *phase
, vm_link
)
249 static void context_close(struct i915_gem_context
*ctx
)
251 GEM_BUG_ON(ctx
->closed
);
254 i915_ppgtt_close(&ctx
->ppgtt
->base
);
255 ctx
->file_priv
= ERR_PTR(-EBADF
);
256 i915_gem_context_put(ctx
);
259 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
263 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
264 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
266 /* Contexts are only released when no longer active.
267 * Flush any pending retires to hopefully release some
268 * stale contexts and try again.
270 i915_gem_retire_requests(dev_priv
);
271 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
272 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
281 static struct i915_gem_context
*
282 __create_hw_context(struct drm_device
*dev
,
283 struct drm_i915_file_private
*file_priv
)
285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
286 struct i915_gem_context
*ctx
;
289 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
291 return ERR_PTR(-ENOMEM
);
293 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
299 kref_init(&ctx
->ref
);
300 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
301 ctx
->i915
= dev_priv
;
303 ctx
->ggtt_alignment
= get_context_alignment(dev_priv
);
305 if (dev_priv
->hw_context_size
) {
306 struct drm_i915_gem_object
*obj
=
307 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
312 ctx
->engine
[RCS
].state
= obj
;
315 /* Default context will never have a file_priv */
316 if (file_priv
!= NULL
) {
317 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
318 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
322 ret
= DEFAULT_CONTEXT_HANDLE
;
324 ctx
->file_priv
= file_priv
;
325 ctx
->user_handle
= ret
;
326 /* NB: Mark all slices as needing a remap so that when the context first
327 * loads it will restore whatever remap state already exists. If there
328 * is no remap info, it will be a NOP. */
329 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
331 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
332 ctx
->ring_size
= 4 * PAGE_SIZE
;
333 ctx
->desc_template
= GEN8_CTX_ADDRESSING_MODE(dev_priv
) <<
334 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
335 ATOMIC_INIT_NOTIFIER_HEAD(&ctx
->status_notifier
);
345 * The default context needs to exist per ring that uses contexts. It stores the
346 * context state of the GPU for applications that don't utilize HW contexts, as
347 * well as an idle case.
349 static struct i915_gem_context
*
350 i915_gem_create_context(struct drm_device
*dev
,
351 struct drm_i915_file_private
*file_priv
)
353 struct i915_gem_context
*ctx
;
355 lockdep_assert_held(&dev
->struct_mutex
);
357 ctx
= __create_hw_context(dev
, file_priv
);
361 if (USES_FULL_PPGTT(dev
)) {
362 struct i915_hw_ppgtt
*ppgtt
=
363 i915_ppgtt_create(to_i915(dev
), file_priv
);
366 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
368 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
370 return ERR_CAST(ppgtt
);
376 trace_i915_context_create(ctx
);
382 * i915_gem_context_create_gvt - create a GVT GEM context
385 * This function is used to create a GVT specific GEM context.
388 * pointer to i915_gem_context on success, error pointer if failed
391 struct i915_gem_context
*
392 i915_gem_context_create_gvt(struct drm_device
*dev
)
394 struct i915_gem_context
*ctx
;
397 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
398 return ERR_PTR(-ENODEV
);
400 ret
= i915_mutex_lock_interruptible(dev
);
404 ctx
= i915_gem_create_context(dev
, NULL
);
408 ctx
->execlists_force_single_submission
= true;
409 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
411 mutex_unlock(&dev
->struct_mutex
);
415 static void i915_gem_context_unpin(struct i915_gem_context
*ctx
,
416 struct intel_engine_cs
*engine
)
418 if (i915
.enable_execlists
) {
419 intel_lr_context_unpin(ctx
, engine
);
421 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
424 i915_gem_object_ggtt_unpin(ce
->state
);
426 i915_gem_context_put(ctx
);
430 void i915_gem_context_reset(struct drm_device
*dev
)
432 struct drm_i915_private
*dev_priv
= to_i915(dev
);
434 lockdep_assert_held(&dev
->struct_mutex
);
436 if (i915
.enable_execlists
) {
437 struct i915_gem_context
*ctx
;
439 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
440 intel_lr_context_reset(dev_priv
, ctx
);
443 i915_gem_context_lost(dev_priv
);
446 int i915_gem_context_init(struct drm_device
*dev
)
448 struct drm_i915_private
*dev_priv
= to_i915(dev
);
449 struct i915_gem_context
*ctx
;
451 /* Init should only be called once per module load. Eventually the
452 * restriction on the context_disabled check can be loosened. */
453 if (WARN_ON(dev_priv
->kernel_context
))
456 if (intel_vgpu_active(dev_priv
) &&
457 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
458 if (!i915
.enable_execlists
) {
459 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
464 /* Using the simple ida interface, the max is limited by sizeof(int) */
465 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
466 ida_init(&dev_priv
->context_hw_ida
);
468 if (i915
.enable_execlists
) {
469 /* NB: intentionally left blank. We will allocate our own
470 * backing objects as we need them, thank you very much */
471 dev_priv
->hw_context_size
= 0;
472 } else if (HAS_HW_CONTEXTS(dev_priv
)) {
473 dev_priv
->hw_context_size
=
474 round_up(get_context_size(dev_priv
), 4096);
475 if (dev_priv
->hw_context_size
> (1<<20)) {
476 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
477 dev_priv
->hw_context_size
);
478 dev_priv
->hw_context_size
= 0;
482 ctx
= i915_gem_create_context(dev
, NULL
);
484 DRM_ERROR("Failed to create default global context (error %ld)\n",
489 dev_priv
->kernel_context
= ctx
;
491 DRM_DEBUG_DRIVER("%s context support initialized\n",
492 i915
.enable_execlists
? "LR" :
493 dev_priv
->hw_context_size
? "HW" : "fake");
497 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
499 struct intel_engine_cs
*engine
;
501 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
503 for_each_engine(engine
, dev_priv
) {
504 if (engine
->last_context
) {
505 i915_gem_context_unpin(engine
->last_context
, engine
);
506 engine
->last_context
= NULL
;
510 /* Force the GPU state to be restored on enabling */
511 if (!i915
.enable_execlists
) {
512 struct i915_gem_context
*ctx
;
514 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
515 if (!i915_gem_context_is_default(ctx
))
518 for_each_engine(engine
, dev_priv
)
519 ctx
->engine
[engine
->id
].initialised
= false;
521 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
524 for_each_engine(engine
, dev_priv
) {
525 struct intel_context
*kce
=
526 &dev_priv
->kernel_context
->engine
[engine
->id
];
528 kce
->initialised
= true;
533 void i915_gem_context_fini(struct drm_device
*dev
)
535 struct drm_i915_private
*dev_priv
= to_i915(dev
);
536 struct i915_gem_context
*dctx
= dev_priv
->kernel_context
;
538 lockdep_assert_held(&dev
->struct_mutex
);
541 dev_priv
->kernel_context
= NULL
;
543 ida_destroy(&dev_priv
->context_hw_ida
);
546 static int context_idr_cleanup(int id
, void *p
, void *data
)
548 struct i915_gem_context
*ctx
= p
;
554 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
556 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
557 struct i915_gem_context
*ctx
;
559 idr_init(&file_priv
->context_idr
);
561 mutex_lock(&dev
->struct_mutex
);
562 ctx
= i915_gem_create_context(dev
, file_priv
);
563 mutex_unlock(&dev
->struct_mutex
);
566 idr_destroy(&file_priv
->context_idr
);
573 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
575 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
577 lockdep_assert_held(&dev
->struct_mutex
);
579 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
580 idr_destroy(&file_priv
->context_idr
);
584 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
586 struct drm_i915_private
*dev_priv
= req
->i915
;
587 struct intel_ring
*ring
= req
->ring
;
588 struct intel_engine_cs
*engine
= req
->engine
;
589 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
590 const int num_rings
=
591 /* Use an extended w/a on ivb+ if signalling from other rings */
593 hweight32(INTEL_INFO(dev_priv
)->ring_mask
) - 1 :
597 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
598 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
599 * explicitly, so we rely on the value at ring init, stored in
600 * itlb_before_ctx_switch.
602 if (IS_GEN6(dev_priv
)) {
603 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
);
608 /* These flags are for resource streamer on HSW+ */
609 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
610 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
611 else if (INTEL_GEN(dev_priv
) < 8)
612 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
616 if (INTEL_GEN(dev_priv
) >= 7)
617 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
619 ret
= intel_ring_begin(req
, len
);
623 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
624 if (INTEL_GEN(dev_priv
) >= 7) {
625 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
627 struct intel_engine_cs
*signaller
;
629 intel_ring_emit(ring
,
630 MI_LOAD_REGISTER_IMM(num_rings
));
631 for_each_engine(signaller
, dev_priv
) {
632 if (signaller
== engine
)
635 intel_ring_emit_reg(ring
,
636 RING_PSMI_CTL(signaller
->mmio_base
));
637 intel_ring_emit(ring
,
638 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
643 intel_ring_emit(ring
, MI_NOOP
);
644 intel_ring_emit(ring
, MI_SET_CONTEXT
);
645 intel_ring_emit(ring
,
646 i915_gem_obj_ggtt_offset(req
->ctx
->engine
[RCS
].state
) |
649 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
650 * WaMiSetContext_Hang:snb,ivb,vlv
652 intel_ring_emit(ring
, MI_NOOP
);
654 if (INTEL_GEN(dev_priv
) >= 7) {
656 struct intel_engine_cs
*signaller
;
657 i915_reg_t last_reg
= {}; /* keep gcc quiet */
659 intel_ring_emit(ring
,
660 MI_LOAD_REGISTER_IMM(num_rings
));
661 for_each_engine(signaller
, dev_priv
) {
662 if (signaller
== engine
)
665 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
666 intel_ring_emit_reg(ring
, last_reg
);
667 intel_ring_emit(ring
,
668 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
671 /* Insert a delay before the next switch! */
672 intel_ring_emit(ring
,
673 MI_STORE_REGISTER_MEM
|
674 MI_SRM_LRM_GLOBAL_GTT
);
675 intel_ring_emit_reg(ring
, last_reg
);
676 intel_ring_emit(ring
, engine
->scratch
.gtt_offset
);
677 intel_ring_emit(ring
, MI_NOOP
);
679 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
682 intel_ring_advance(ring
);
687 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
689 u32
*remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
690 struct intel_ring
*ring
= req
->ring
;
696 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
701 * Note: We do not worry about the concurrent register cacheline hang
702 * here because no other code should access these registers other than
703 * at initialization time.
705 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4));
706 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
707 intel_ring_emit_reg(ring
, GEN7_L3LOG(slice
, i
));
708 intel_ring_emit(ring
, remap_info
[i
]);
710 intel_ring_emit(ring
, MI_NOOP
);
711 intel_ring_advance(ring
);
716 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
717 struct intel_engine_cs
*engine
,
718 struct i915_gem_context
*to
)
723 if (!to
->engine
[RCS
].initialised
)
726 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
729 return to
== engine
->last_context
;
733 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
,
734 struct intel_engine_cs
*engine
,
735 struct i915_gem_context
*to
)
740 /* Always load the ppgtt on first use */
741 if (!engine
->last_context
)
744 /* Same context without new entries, skip */
745 if (engine
->last_context
== to
&&
746 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
749 if (engine
->id
!= RCS
)
752 if (INTEL_GEN(engine
->i915
) < 8)
759 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
760 struct i915_gem_context
*to
,
766 if (!IS_GEN8(to
->i915
))
769 if (hw_flags
& MI_RESTORE_INHIBIT
)
775 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
777 struct i915_gem_context
*to
= req
->ctx
;
778 struct intel_engine_cs
*engine
= req
->engine
;
779 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
780 struct i915_gem_context
*from
;
784 if (skip_rcs_switch(ppgtt
, engine
, to
))
787 /* Trying to pin first makes error handling easier. */
788 ret
= i915_gem_obj_ggtt_pin(to
->engine
[RCS
].state
,
795 * Pin can switch back to the default context if we end up calling into
796 * evict_everything - as a last ditch gtt defrag effort that also
797 * switches to the default context. Hence we need to reload from here.
799 * XXX: Doing so is painfully broken!
801 from
= engine
->last_context
;
804 * Clear this page out of any CPU caches for coherent swap-in/out. Note
805 * that thanks to write = false in this call and us not setting any gpu
806 * write domains when putting a context object onto the active list
807 * (when switching away from it), this won't block.
809 * XXX: We need a real interface to do this instead of trickery.
811 ret
= i915_gem_object_set_to_gtt_domain(to
->engine
[RCS
].state
, false);
815 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
816 /* Older GENs and non render rings still want the load first,
817 * "PP_DCLV followed by PP_DIR_BASE register through Load
818 * Register Immediate commands in Ring Buffer before submitting
820 trace_switch_mm(engine
, to
);
821 ret
= ppgtt
->switch_mm(ppgtt
, req
);
826 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
827 /* NB: If we inhibit the restore, the context is not allowed to
828 * die because future work may end up depending on valid address
829 * space. This means we must enforce that a page table load
830 * occur when this occurs. */
831 hw_flags
= MI_RESTORE_INHIBIT
;
832 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
833 hw_flags
= MI_FORCE_RESTORE
;
837 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
838 ret
= mi_set_context(req
, hw_flags
);
843 /* The backing object for the context is done after switching to the
844 * *next* context. Therefore we cannot retire the previous context until
845 * the next context has already started running. In fact, the below code
846 * is a bit suboptimal because the retiring can occur simply after the
847 * MI_SET_CONTEXT instead of when the next seqno has completed.
850 struct drm_i915_gem_object
*obj
= from
->engine
[RCS
].state
;
852 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
853 * whole damn pipeline, we don't need to explicitly mark the
854 * object dirty. The only exception is that the context must be
855 * correct in case the object gets swapped out. Ideally we'd be
856 * able to defer doing this until we know the object would be
857 * swapped, but there is no way to do that yet.
859 obj
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
860 i915_vma_move_to_active(i915_gem_obj_to_ggtt(obj
), req
, 0);
862 /* obj is kept alive until the next request by its active ref */
863 i915_gem_object_ggtt_unpin(obj
);
864 i915_gem_context_put(from
);
866 engine
->last_context
= i915_gem_context_get(to
);
868 /* GEN8 does *not* require an explicit reload if the PDPs have been
869 * setup, and we do not wish to move them.
871 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
872 trace_switch_mm(engine
, to
);
873 ret
= ppgtt
->switch_mm(ppgtt
, req
);
874 /* The hardware context switch is emitted, but we haven't
875 * actually changed the state - so it's probably safe to bail
876 * here. Still, let the user know something dangerous has
884 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
886 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
887 if (!(to
->remap_slice
& (1<<i
)))
890 ret
= remap_l3(req
, i
);
894 to
->remap_slice
&= ~(1<<i
);
897 if (!to
->engine
[RCS
].initialised
) {
898 if (engine
->init_context
) {
899 ret
= engine
->init_context(req
);
903 to
->engine
[RCS
].initialised
= true;
909 i915_gem_object_ggtt_unpin(to
->engine
[RCS
].state
);
914 * i915_switch_context() - perform a GPU context switch.
915 * @req: request for which we'll execute the context switch
917 * The context life cycle is simple. The context refcount is incremented and
918 * decremented by 1 and create and destroy. If the context is in use by the GPU,
919 * it will have a refcount > 1. This allows us to destroy the context abstract
920 * object while letting the normal object tracking destroy the backing BO.
922 * This function should not be used in execlists mode. Instead the context is
923 * switched by writing to the ELSP and requests keep a reference to their
926 int i915_switch_context(struct drm_i915_gem_request
*req
)
928 struct intel_engine_cs
*engine
= req
->engine
;
930 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
931 if (i915
.enable_execlists
)
934 if (!req
->ctx
->engine
[engine
->id
].state
) {
935 struct i915_gem_context
*to
= req
->ctx
;
936 struct i915_hw_ppgtt
*ppgtt
=
937 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
939 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
942 trace_switch_mm(engine
, to
);
943 ret
= ppgtt
->switch_mm(ppgtt
, req
);
947 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
950 if (to
!= engine
->last_context
) {
951 if (engine
->last_context
)
952 i915_gem_context_put(engine
->last_context
);
953 engine
->last_context
= i915_gem_context_get(to
);
959 return do_rcs_switch(req
);
962 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
964 struct intel_engine_cs
*engine
;
966 for_each_engine(engine
, dev_priv
) {
967 struct drm_i915_gem_request
*req
;
970 if (engine
->last_context
== NULL
)
973 if (engine
->last_context
== dev_priv
->kernel_context
)
976 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
980 ret
= i915_switch_context(req
);
981 i915_add_request_no_flush(req
);
989 static bool contexts_enabled(struct drm_device
*dev
)
991 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
994 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
995 struct drm_file
*file
)
997 struct drm_i915_gem_context_create
*args
= data
;
998 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
999 struct i915_gem_context
*ctx
;
1002 if (!contexts_enabled(dev
))
1008 ret
= i915_mutex_lock_interruptible(dev
);
1012 ctx
= i915_gem_create_context(dev
, file_priv
);
1013 mutex_unlock(&dev
->struct_mutex
);
1015 return PTR_ERR(ctx
);
1017 args
->ctx_id
= ctx
->user_handle
;
1018 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
1023 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1024 struct drm_file
*file
)
1026 struct drm_i915_gem_context_destroy
*args
= data
;
1027 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1028 struct i915_gem_context
*ctx
;
1034 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
1037 ret
= i915_mutex_lock_interruptible(dev
);
1041 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1043 mutex_unlock(&dev
->struct_mutex
);
1044 return PTR_ERR(ctx
);
1047 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
1049 mutex_unlock(&dev
->struct_mutex
);
1051 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
1055 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1056 struct drm_file
*file
)
1058 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1059 struct drm_i915_gem_context_param
*args
= data
;
1060 struct i915_gem_context
*ctx
;
1063 ret
= i915_mutex_lock_interruptible(dev
);
1067 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1069 mutex_unlock(&dev
->struct_mutex
);
1070 return PTR_ERR(ctx
);
1074 switch (args
->param
) {
1075 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1076 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
1078 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1079 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1081 case I915_CONTEXT_PARAM_GTT_SIZE
:
1083 args
->value
= ctx
->ppgtt
->base
.total
;
1084 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1085 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1087 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1089 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1090 args
->value
= !!(ctx
->flags
& CONTEXT_NO_ERROR_CAPTURE
);
1096 mutex_unlock(&dev
->struct_mutex
);
1101 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1102 struct drm_file
*file
)
1104 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1105 struct drm_i915_gem_context_param
*args
= data
;
1106 struct i915_gem_context
*ctx
;
1109 ret
= i915_mutex_lock_interruptible(dev
);
1113 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1115 mutex_unlock(&dev
->struct_mutex
);
1116 return PTR_ERR(ctx
);
1119 switch (args
->param
) {
1120 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1123 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
1124 !capable(CAP_SYS_ADMIN
))
1127 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
1129 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1133 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1134 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1137 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1142 ctx
->flags
|= CONTEXT_NO_ERROR_CAPTURE
;
1144 ctx
->flags
&= ~CONTEXT_NO_ERROR_CAPTURE
;
1151 mutex_unlock(&dev
->struct_mutex
);
1156 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1157 void *data
, struct drm_file
*file
)
1159 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1160 struct drm_i915_reset_stats
*args
= data
;
1161 struct i915_ctx_hang_stats
*hs
;
1162 struct i915_gem_context
*ctx
;
1165 if (args
->flags
|| args
->pad
)
1168 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1171 ret
= i915_mutex_lock_interruptible(dev
);
1175 ctx
= i915_gem_context_lookup(file
->driver_priv
, args
->ctx_id
);
1177 mutex_unlock(&dev
->struct_mutex
);
1178 return PTR_ERR(ctx
);
1180 hs
= &ctx
->hang_stats
;
1182 if (capable(CAP_SYS_ADMIN
))
1183 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1185 args
->reset_count
= 0;
1187 args
->batch_active
= hs
->batch_active
;
1188 args
->batch_pending
= hs
->batch_pending
;
1190 mutex_unlock(&dev
->struct_mutex
);