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drm/i915: Replace last_[rwf]_seqno with last_[rwf]_req
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
40
41 #define BATCH_OFFSET_BIAS (256*1024)
42
43 struct eb_vmas {
44 struct list_head vmas;
45 int and;
46 union {
47 struct i915_vma *lut[0];
48 struct hlist_head buckets[0];
49 };
50 };
51
52 static struct eb_vmas *
53 eb_create(struct drm_i915_gem_execbuffer2 *args)
54 {
55 struct eb_vmas *eb = NULL;
56
57 if (args->flags & I915_EXEC_HANDLE_LUT) {
58 unsigned size = args->buffer_count;
59 size *= sizeof(struct i915_vma *);
60 size += sizeof(struct eb_vmas);
61 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
62 }
63
64 if (eb == NULL) {
65 unsigned size = args->buffer_count;
66 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
67 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
68 while (count > 2*size)
69 count >>= 1;
70 eb = kzalloc(count*sizeof(struct hlist_head) +
71 sizeof(struct eb_vmas),
72 GFP_TEMPORARY);
73 if (eb == NULL)
74 return eb;
75
76 eb->and = count - 1;
77 } else
78 eb->and = -args->buffer_count;
79
80 INIT_LIST_HEAD(&eb->vmas);
81 return eb;
82 }
83
84 static void
85 eb_reset(struct eb_vmas *eb)
86 {
87 if (eb->and >= 0)
88 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
89 }
90
91 static int
92 eb_lookup_vmas(struct eb_vmas *eb,
93 struct drm_i915_gem_exec_object2 *exec,
94 const struct drm_i915_gem_execbuffer2 *args,
95 struct i915_address_space *vm,
96 struct drm_file *file)
97 {
98 struct drm_i915_gem_object *obj;
99 struct list_head objects;
100 int i, ret;
101
102 INIT_LIST_HEAD(&objects);
103 spin_lock(&file->table_lock);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i = 0; i < args->buffer_count; i++) {
107 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
108 if (obj == NULL) {
109 spin_unlock(&file->table_lock);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
111 exec[i].handle, i);
112 ret = -ENOENT;
113 goto err;
114 }
115
116 if (!list_empty(&obj->obj_exec_link)) {
117 spin_unlock(&file->table_lock);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj, exec[i].handle, i);
120 ret = -EINVAL;
121 goto err;
122 }
123
124 WARN_ONCE(obj->base.dumb,
125 "GPU use of dumb buffer is illegal.\n");
126
127 drm_gem_object_reference(&obj->base);
128 list_add_tail(&obj->obj_exec_link, &objects);
129 }
130 spin_unlock(&file->table_lock);
131
132 i = 0;
133 while (!list_empty(&objects)) {
134 struct i915_vma *vma;
135
136 obj = list_first_entry(&objects,
137 struct drm_i915_gem_object,
138 obj_exec_link);
139
140 /*
141 * NOTE: We can leak any vmas created here when something fails
142 * later on. But that's no issue since vma_unbind can deal with
143 * vmas which are not actually bound. And since only
144 * lookup_or_create exists as an interface to get at the vma
145 * from the (obj, vm) we don't run the risk of creating
146 * duplicated vmas for the same vm.
147 */
148 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
149 if (IS_ERR(vma)) {
150 DRM_DEBUG("Failed to lookup VMA\n");
151 ret = PTR_ERR(vma);
152 goto err;
153 }
154
155 /* Transfer ownership from the objects list to the vmas list. */
156 list_add_tail(&vma->exec_list, &eb->vmas);
157 list_del_init(&obj->obj_exec_link);
158
159 vma->exec_entry = &exec[i];
160 if (eb->and < 0) {
161 eb->lut[i] = vma;
162 } else {
163 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
164 vma->exec_handle = handle;
165 hlist_add_head(&vma->exec_node,
166 &eb->buckets[handle & eb->and]);
167 }
168 ++i;
169 }
170
171 return 0;
172
173
174 err:
175 while (!list_empty(&objects)) {
176 obj = list_first_entry(&objects,
177 struct drm_i915_gem_object,
178 obj_exec_link);
179 list_del_init(&obj->obj_exec_link);
180 drm_gem_object_unreference(&obj->base);
181 }
182 /*
183 * Objects already transfered to the vmas list will be unreferenced by
184 * eb_destroy.
185 */
186
187 return ret;
188 }
189
190 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
191 {
192 if (eb->and < 0) {
193 if (handle >= -eb->and)
194 return NULL;
195 return eb->lut[handle];
196 } else {
197 struct hlist_head *head;
198 struct hlist_node *node;
199
200 head = &eb->buckets[handle & eb->and];
201 hlist_for_each(node, head) {
202 struct i915_vma *vma;
203
204 vma = hlist_entry(node, struct i915_vma, exec_node);
205 if (vma->exec_handle == handle)
206 return vma;
207 }
208 return NULL;
209 }
210 }
211
212 static void
213 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
214 {
215 struct drm_i915_gem_exec_object2 *entry;
216 struct drm_i915_gem_object *obj = vma->obj;
217
218 if (!drm_mm_node_allocated(&vma->node))
219 return;
220
221 entry = vma->exec_entry;
222
223 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
224 i915_gem_object_unpin_fence(obj);
225
226 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
227 vma->pin_count--;
228
229 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
230 }
231
232 static void eb_destroy(struct eb_vmas *eb)
233 {
234 while (!list_empty(&eb->vmas)) {
235 struct i915_vma *vma;
236
237 vma = list_first_entry(&eb->vmas,
238 struct i915_vma,
239 exec_list);
240 list_del_init(&vma->exec_list);
241 i915_gem_execbuffer_unreserve_vma(vma);
242 drm_gem_object_unreference(&vma->obj->base);
243 }
244 kfree(eb);
245 }
246
247 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
248 {
249 return (HAS_LLC(obj->base.dev) ||
250 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
251 !obj->map_and_fenceable ||
252 obj->cache_level != I915_CACHE_NONE);
253 }
254
255 static int
256 relocate_entry_cpu(struct drm_i915_gem_object *obj,
257 struct drm_i915_gem_relocation_entry *reloc,
258 uint64_t target_offset)
259 {
260 struct drm_device *dev = obj->base.dev;
261 uint32_t page_offset = offset_in_page(reloc->offset);
262 uint64_t delta = reloc->delta + target_offset;
263 char *vaddr;
264 int ret;
265
266 ret = i915_gem_object_set_to_cpu_domain(obj, true);
267 if (ret)
268 return ret;
269
270 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
271 reloc->offset >> PAGE_SHIFT));
272 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
273
274 if (INTEL_INFO(dev)->gen >= 8) {
275 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
276
277 if (page_offset == 0) {
278 kunmap_atomic(vaddr);
279 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
280 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
281 }
282
283 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
284 }
285
286 kunmap_atomic(vaddr);
287
288 return 0;
289 }
290
291 static int
292 relocate_entry_gtt(struct drm_i915_gem_object *obj,
293 struct drm_i915_gem_relocation_entry *reloc,
294 uint64_t target_offset)
295 {
296 struct drm_device *dev = obj->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 uint64_t delta = reloc->delta + target_offset;
299 uint64_t offset;
300 void __iomem *reloc_page;
301 int ret;
302
303 ret = i915_gem_object_set_to_gtt_domain(obj, true);
304 if (ret)
305 return ret;
306
307 ret = i915_gem_object_put_fence(obj);
308 if (ret)
309 return ret;
310
311 /* Map the page containing the relocation we're going to perform. */
312 offset = i915_gem_obj_ggtt_offset(obj);
313 offset += reloc->offset;
314 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
315 offset & PAGE_MASK);
316 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
317
318 if (INTEL_INFO(dev)->gen >= 8) {
319 offset += sizeof(uint32_t);
320
321 if (offset_in_page(offset) == 0) {
322 io_mapping_unmap_atomic(reloc_page);
323 reloc_page =
324 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
325 offset);
326 }
327
328 iowrite32(upper_32_bits(delta),
329 reloc_page + offset_in_page(offset));
330 }
331
332 io_mapping_unmap_atomic(reloc_page);
333
334 return 0;
335 }
336
337 static int
338 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
339 struct eb_vmas *eb,
340 struct drm_i915_gem_relocation_entry *reloc)
341 {
342 struct drm_device *dev = obj->base.dev;
343 struct drm_gem_object *target_obj;
344 struct drm_i915_gem_object *target_i915_obj;
345 struct i915_vma *target_vma;
346 uint64_t target_offset;
347 int ret;
348
349 /* we've already hold a reference to all valid objects */
350 target_vma = eb_get_vma(eb, reloc->target_handle);
351 if (unlikely(target_vma == NULL))
352 return -ENOENT;
353 target_i915_obj = target_vma->obj;
354 target_obj = &target_vma->obj->base;
355
356 target_offset = target_vma->node.start;
357
358 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
359 * pipe_control writes because the gpu doesn't properly redirect them
360 * through the ppgtt for non_secure batchbuffers. */
361 if (unlikely(IS_GEN6(dev) &&
362 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
363 !(target_vma->bound & GLOBAL_BIND)))
364 target_vma->bind_vma(target_vma, target_i915_obj->cache_level,
365 GLOBAL_BIND);
366
367 /* Validate that the target is in a valid r/w GPU domain */
368 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
369 DRM_DEBUG("reloc with multiple write domains: "
370 "obj %p target %d offset %d "
371 "read %08x write %08x",
372 obj, reloc->target_handle,
373 (int) reloc->offset,
374 reloc->read_domains,
375 reloc->write_domain);
376 return -EINVAL;
377 }
378 if (unlikely((reloc->write_domain | reloc->read_domains)
379 & ~I915_GEM_GPU_DOMAINS)) {
380 DRM_DEBUG("reloc with read/write non-GPU domains: "
381 "obj %p target %d offset %d "
382 "read %08x write %08x",
383 obj, reloc->target_handle,
384 (int) reloc->offset,
385 reloc->read_domains,
386 reloc->write_domain);
387 return -EINVAL;
388 }
389
390 target_obj->pending_read_domains |= reloc->read_domains;
391 target_obj->pending_write_domain |= reloc->write_domain;
392
393 /* If the relocation already has the right value in it, no
394 * more work needs to be done.
395 */
396 if (target_offset == reloc->presumed_offset)
397 return 0;
398
399 /* Check that the relocation address is valid... */
400 if (unlikely(reloc->offset >
401 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
402 DRM_DEBUG("Relocation beyond object bounds: "
403 "obj %p target %d offset %d size %d.\n",
404 obj, reloc->target_handle,
405 (int) reloc->offset,
406 (int) obj->base.size);
407 return -EINVAL;
408 }
409 if (unlikely(reloc->offset & 3)) {
410 DRM_DEBUG("Relocation not 4-byte aligned: "
411 "obj %p target %d offset %d.\n",
412 obj, reloc->target_handle,
413 (int) reloc->offset);
414 return -EINVAL;
415 }
416
417 /* We can't wait for rendering with pagefaults disabled */
418 if (obj->active && in_atomic())
419 return -EFAULT;
420
421 if (use_cpu_reloc(obj))
422 ret = relocate_entry_cpu(obj, reloc, target_offset);
423 else
424 ret = relocate_entry_gtt(obj, reloc, target_offset);
425
426 if (ret)
427 return ret;
428
429 /* and update the user's relocation entry */
430 reloc->presumed_offset = target_offset;
431
432 return 0;
433 }
434
435 static int
436 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
437 struct eb_vmas *eb)
438 {
439 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
440 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
441 struct drm_i915_gem_relocation_entry __user *user_relocs;
442 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
443 int remain, ret;
444
445 user_relocs = to_user_ptr(entry->relocs_ptr);
446
447 remain = entry->relocation_count;
448 while (remain) {
449 struct drm_i915_gem_relocation_entry *r = stack_reloc;
450 int count = remain;
451 if (count > ARRAY_SIZE(stack_reloc))
452 count = ARRAY_SIZE(stack_reloc);
453 remain -= count;
454
455 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
456 return -EFAULT;
457
458 do {
459 u64 offset = r->presumed_offset;
460
461 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
462 if (ret)
463 return ret;
464
465 if (r->presumed_offset != offset &&
466 __copy_to_user_inatomic(&user_relocs->presumed_offset,
467 &r->presumed_offset,
468 sizeof(r->presumed_offset))) {
469 return -EFAULT;
470 }
471
472 user_relocs++;
473 r++;
474 } while (--count);
475 }
476
477 return 0;
478 #undef N_RELOC
479 }
480
481 static int
482 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
483 struct eb_vmas *eb,
484 struct drm_i915_gem_relocation_entry *relocs)
485 {
486 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
487 int i, ret;
488
489 for (i = 0; i < entry->relocation_count; i++) {
490 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
491 if (ret)
492 return ret;
493 }
494
495 return 0;
496 }
497
498 static int
499 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
500 {
501 struct i915_vma *vma;
502 int ret = 0;
503
504 /* This is the fast path and we cannot handle a pagefault whilst
505 * holding the struct mutex lest the user pass in the relocations
506 * contained within a mmaped bo. For in such a case we, the page
507 * fault handler would call i915_gem_fault() and we would try to
508 * acquire the struct mutex again. Obviously this is bad and so
509 * lockdep complains vehemently.
510 */
511 pagefault_disable();
512 list_for_each_entry(vma, &eb->vmas, exec_list) {
513 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
514 if (ret)
515 break;
516 }
517 pagefault_enable();
518
519 return ret;
520 }
521
522 static int
523 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
524 struct intel_engine_cs *ring,
525 bool *need_reloc)
526 {
527 struct drm_i915_gem_object *obj = vma->obj;
528 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
529 uint64_t flags;
530 int ret;
531
532 flags = 0;
533 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
534 flags |= PIN_GLOBAL | PIN_MAPPABLE;
535 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
536 flags |= PIN_GLOBAL;
537 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
538 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
539
540 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
541 if (ret)
542 return ret;
543
544 entry->flags |= __EXEC_OBJECT_HAS_PIN;
545
546 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
547 ret = i915_gem_object_get_fence(obj);
548 if (ret)
549 return ret;
550
551 if (i915_gem_object_pin_fence(obj))
552 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
553 }
554
555 if (entry->offset != vma->node.start) {
556 entry->offset = vma->node.start;
557 *need_reloc = true;
558 }
559
560 if (entry->flags & EXEC_OBJECT_WRITE) {
561 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
562 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
563 }
564
565 return 0;
566 }
567
568 static bool
569 need_reloc_mappable(struct i915_vma *vma)
570 {
571 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
572
573 if (entry->relocation_count == 0)
574 return false;
575
576 if (!i915_is_ggtt(vma->vm))
577 return false;
578
579 /* See also use_cpu_reloc() */
580 if (HAS_LLC(vma->obj->base.dev))
581 return false;
582
583 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
584 return false;
585
586 return true;
587 }
588
589 static bool
590 eb_vma_misplaced(struct i915_vma *vma)
591 {
592 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
593 struct drm_i915_gem_object *obj = vma->obj;
594
595 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
596 !i915_is_ggtt(vma->vm));
597
598 if (entry->alignment &&
599 vma->node.start & (entry->alignment - 1))
600 return true;
601
602 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
603 return true;
604
605 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
606 vma->node.start < BATCH_OFFSET_BIAS)
607 return true;
608
609 return false;
610 }
611
612 static int
613 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
614 struct list_head *vmas,
615 bool *need_relocs)
616 {
617 struct drm_i915_gem_object *obj;
618 struct i915_vma *vma;
619 struct i915_address_space *vm;
620 struct list_head ordered_vmas;
621 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
622 int retry;
623
624 i915_gem_retire_requests_ring(ring);
625
626 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
627
628 INIT_LIST_HEAD(&ordered_vmas);
629 while (!list_empty(vmas)) {
630 struct drm_i915_gem_exec_object2 *entry;
631 bool need_fence, need_mappable;
632
633 vma = list_first_entry(vmas, struct i915_vma, exec_list);
634 obj = vma->obj;
635 entry = vma->exec_entry;
636
637 if (!has_fenced_gpu_access)
638 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
639 need_fence =
640 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
641 obj->tiling_mode != I915_TILING_NONE;
642 need_mappable = need_fence || need_reloc_mappable(vma);
643
644 if (need_mappable) {
645 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
646 list_move(&vma->exec_list, &ordered_vmas);
647 } else
648 list_move_tail(&vma->exec_list, &ordered_vmas);
649
650 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
651 obj->base.pending_write_domain = 0;
652 }
653 list_splice(&ordered_vmas, vmas);
654
655 /* Attempt to pin all of the buffers into the GTT.
656 * This is done in 3 phases:
657 *
658 * 1a. Unbind all objects that do not match the GTT constraints for
659 * the execbuffer (fenceable, mappable, alignment etc).
660 * 1b. Increment pin count for already bound objects.
661 * 2. Bind new objects.
662 * 3. Decrement pin count.
663 *
664 * This avoid unnecessary unbinding of later objects in order to make
665 * room for the earlier objects *unless* we need to defragment.
666 */
667 retry = 0;
668 do {
669 int ret = 0;
670
671 /* Unbind any ill-fitting objects or pin. */
672 list_for_each_entry(vma, vmas, exec_list) {
673 if (!drm_mm_node_allocated(&vma->node))
674 continue;
675
676 if (eb_vma_misplaced(vma))
677 ret = i915_vma_unbind(vma);
678 else
679 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
680 if (ret)
681 goto err;
682 }
683
684 /* Bind fresh objects */
685 list_for_each_entry(vma, vmas, exec_list) {
686 if (drm_mm_node_allocated(&vma->node))
687 continue;
688
689 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
690 if (ret)
691 goto err;
692 }
693
694 err:
695 if (ret != -ENOSPC || retry++)
696 return ret;
697
698 /* Decrement pin count for bound objects */
699 list_for_each_entry(vma, vmas, exec_list)
700 i915_gem_execbuffer_unreserve_vma(vma);
701
702 ret = i915_gem_evict_vm(vm, true);
703 if (ret)
704 return ret;
705 } while (1);
706 }
707
708 static int
709 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
710 struct drm_i915_gem_execbuffer2 *args,
711 struct drm_file *file,
712 struct intel_engine_cs *ring,
713 struct eb_vmas *eb,
714 struct drm_i915_gem_exec_object2 *exec)
715 {
716 struct drm_i915_gem_relocation_entry *reloc;
717 struct i915_address_space *vm;
718 struct i915_vma *vma;
719 bool need_relocs;
720 int *reloc_offset;
721 int i, total, ret;
722 unsigned count = args->buffer_count;
723
724 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
725
726 /* We may process another execbuffer during the unlock... */
727 while (!list_empty(&eb->vmas)) {
728 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
729 list_del_init(&vma->exec_list);
730 i915_gem_execbuffer_unreserve_vma(vma);
731 drm_gem_object_unreference(&vma->obj->base);
732 }
733
734 mutex_unlock(&dev->struct_mutex);
735
736 total = 0;
737 for (i = 0; i < count; i++)
738 total += exec[i].relocation_count;
739
740 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
741 reloc = drm_malloc_ab(total, sizeof(*reloc));
742 if (reloc == NULL || reloc_offset == NULL) {
743 drm_free_large(reloc);
744 drm_free_large(reloc_offset);
745 mutex_lock(&dev->struct_mutex);
746 return -ENOMEM;
747 }
748
749 total = 0;
750 for (i = 0; i < count; i++) {
751 struct drm_i915_gem_relocation_entry __user *user_relocs;
752 u64 invalid_offset = (u64)-1;
753 int j;
754
755 user_relocs = to_user_ptr(exec[i].relocs_ptr);
756
757 if (copy_from_user(reloc+total, user_relocs,
758 exec[i].relocation_count * sizeof(*reloc))) {
759 ret = -EFAULT;
760 mutex_lock(&dev->struct_mutex);
761 goto err;
762 }
763
764 /* As we do not update the known relocation offsets after
765 * relocating (due to the complexities in lock handling),
766 * we need to mark them as invalid now so that we force the
767 * relocation processing next time. Just in case the target
768 * object is evicted and then rebound into its old
769 * presumed_offset before the next execbuffer - if that
770 * happened we would make the mistake of assuming that the
771 * relocations were valid.
772 */
773 for (j = 0; j < exec[i].relocation_count; j++) {
774 if (__copy_to_user(&user_relocs[j].presumed_offset,
775 &invalid_offset,
776 sizeof(invalid_offset))) {
777 ret = -EFAULT;
778 mutex_lock(&dev->struct_mutex);
779 goto err;
780 }
781 }
782
783 reloc_offset[i] = total;
784 total += exec[i].relocation_count;
785 }
786
787 ret = i915_mutex_lock_interruptible(dev);
788 if (ret) {
789 mutex_lock(&dev->struct_mutex);
790 goto err;
791 }
792
793 /* reacquire the objects */
794 eb_reset(eb);
795 ret = eb_lookup_vmas(eb, exec, args, vm, file);
796 if (ret)
797 goto err;
798
799 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
800 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
801 if (ret)
802 goto err;
803
804 list_for_each_entry(vma, &eb->vmas, exec_list) {
805 int offset = vma->exec_entry - exec;
806 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
807 reloc + reloc_offset[offset]);
808 if (ret)
809 goto err;
810 }
811
812 /* Leave the user relocations as are, this is the painfully slow path,
813 * and we want to avoid the complication of dropping the lock whilst
814 * having buffers reserved in the aperture and so causing spurious
815 * ENOSPC for random operations.
816 */
817
818 err:
819 drm_free_large(reloc);
820 drm_free_large(reloc_offset);
821 return ret;
822 }
823
824 static int
825 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
826 struct list_head *vmas)
827 {
828 struct i915_vma *vma;
829 uint32_t flush_domains = 0;
830 bool flush_chipset = false;
831 int ret;
832
833 list_for_each_entry(vma, vmas, exec_list) {
834 struct drm_i915_gem_object *obj = vma->obj;
835 ret = i915_gem_object_sync(obj, ring);
836 if (ret)
837 return ret;
838
839 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
840 flush_chipset |= i915_gem_clflush_object(obj, false);
841
842 flush_domains |= obj->base.write_domain;
843 }
844
845 if (flush_chipset)
846 i915_gem_chipset_flush(ring->dev);
847
848 if (flush_domains & I915_GEM_DOMAIN_GTT)
849 wmb();
850
851 /* Unconditionally invalidate gpu caches and ensure that we do flush
852 * any residual writes from the previous batch.
853 */
854 return intel_ring_invalidate_all_caches(ring);
855 }
856
857 static bool
858 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
859 {
860 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
861 return false;
862
863 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
864 }
865
866 static int
867 validate_exec_list(struct drm_device *dev,
868 struct drm_i915_gem_exec_object2 *exec,
869 int count)
870 {
871 unsigned relocs_total = 0;
872 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
873 unsigned invalid_flags;
874 int i;
875
876 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
877 if (USES_FULL_PPGTT(dev))
878 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
879
880 for (i = 0; i < count; i++) {
881 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
882 int length; /* limited by fault_in_pages_readable() */
883
884 if (exec[i].flags & invalid_flags)
885 return -EINVAL;
886
887 /* First check for malicious input causing overflow in
888 * the worst case where we need to allocate the entire
889 * relocation tree as a single array.
890 */
891 if (exec[i].relocation_count > relocs_max - relocs_total)
892 return -EINVAL;
893 relocs_total += exec[i].relocation_count;
894
895 length = exec[i].relocation_count *
896 sizeof(struct drm_i915_gem_relocation_entry);
897 /*
898 * We must check that the entire relocation array is safe
899 * to read, but since we may need to update the presumed
900 * offsets during execution, check for full write access.
901 */
902 if (!access_ok(VERIFY_WRITE, ptr, length))
903 return -EFAULT;
904
905 if (likely(!i915.prefault_disable)) {
906 if (fault_in_multipages_readable(ptr, length))
907 return -EFAULT;
908 }
909 }
910
911 return 0;
912 }
913
914 static struct intel_context *
915 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
916 struct intel_engine_cs *ring, const u32 ctx_id)
917 {
918 struct intel_context *ctx = NULL;
919 struct i915_ctx_hang_stats *hs;
920
921 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
922 return ERR_PTR(-EINVAL);
923
924 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
925 if (IS_ERR(ctx))
926 return ctx;
927
928 hs = &ctx->hang_stats;
929 if (hs->banned) {
930 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
931 return ERR_PTR(-EIO);
932 }
933
934 if (i915.enable_execlists && !ctx->engine[ring->id].state) {
935 int ret = intel_lr_context_deferred_create(ctx, ring);
936 if (ret) {
937 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
938 return ERR_PTR(ret);
939 }
940 }
941
942 return ctx;
943 }
944
945 void
946 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
947 struct intel_engine_cs *ring)
948 {
949 struct drm_i915_gem_request *req = intel_ring_get_request(ring);
950 struct i915_vma *vma;
951
952 list_for_each_entry(vma, vmas, exec_list) {
953 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
954 struct drm_i915_gem_object *obj = vma->obj;
955 u32 old_read = obj->base.read_domains;
956 u32 old_write = obj->base.write_domain;
957
958 obj->base.write_domain = obj->base.pending_write_domain;
959 if (obj->base.write_domain == 0)
960 obj->base.pending_read_domains |= obj->base.read_domains;
961 obj->base.read_domains = obj->base.pending_read_domains;
962
963 i915_vma_move_to_active(vma, ring);
964 if (obj->base.write_domain) {
965 obj->dirty = 1;
966 i915_gem_request_assign(&obj->last_write_req, req);
967
968 intel_fb_obj_invalidate(obj, ring);
969
970 /* update for the implicit flush after a batch */
971 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
972 }
973 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
974 i915_gem_request_assign(&obj->last_fenced_req, req);
975 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
976 struct drm_i915_private *dev_priv = to_i915(ring->dev);
977 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
978 &dev_priv->mm.fence_list);
979 }
980 }
981
982 trace_i915_gem_object_change_domain(obj, old_read, old_write);
983 }
984 }
985
986 void
987 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
988 struct drm_file *file,
989 struct intel_engine_cs *ring,
990 struct drm_i915_gem_object *obj)
991 {
992 /* Unconditionally force add_request to emit a full flush. */
993 ring->gpu_caches_dirty = true;
994
995 /* Add a breadcrumb for the completion of the batch buffer */
996 (void)__i915_add_request(ring, file, obj, NULL);
997 }
998
999 static int
1000 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1001 struct intel_engine_cs *ring)
1002 {
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 int ret, i;
1005
1006 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1007 DRM_DEBUG("sol reset is gen7/rcs only\n");
1008 return -EINVAL;
1009 }
1010
1011 ret = intel_ring_begin(ring, 4 * 3);
1012 if (ret)
1013 return ret;
1014
1015 for (i = 0; i < 4; i++) {
1016 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1017 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1018 intel_ring_emit(ring, 0);
1019 }
1020
1021 intel_ring_advance(ring);
1022
1023 return 0;
1024 }
1025
1026 static int
1027 i915_emit_box(struct intel_engine_cs *ring,
1028 struct drm_clip_rect *box,
1029 int DR1, int DR4)
1030 {
1031 int ret;
1032
1033 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
1034 box->y2 <= 0 || box->x2 <= 0) {
1035 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1036 box->x1, box->y1, box->x2, box->y2);
1037 return -EINVAL;
1038 }
1039
1040 if (INTEL_INFO(ring->dev)->gen >= 4) {
1041 ret = intel_ring_begin(ring, 4);
1042 if (ret)
1043 return ret;
1044
1045 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
1046 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1047 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1048 intel_ring_emit(ring, DR4);
1049 } else {
1050 ret = intel_ring_begin(ring, 6);
1051 if (ret)
1052 return ret;
1053
1054 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
1055 intel_ring_emit(ring, DR1);
1056 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1057 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1058 intel_ring_emit(ring, DR4);
1059 intel_ring_emit(ring, 0);
1060 }
1061 intel_ring_advance(ring);
1062
1063 return 0;
1064 }
1065
1066
1067 int
1068 i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
1069 struct intel_engine_cs *ring,
1070 struct intel_context *ctx,
1071 struct drm_i915_gem_execbuffer2 *args,
1072 struct list_head *vmas,
1073 struct drm_i915_gem_object *batch_obj,
1074 u64 exec_start, u32 flags)
1075 {
1076 struct drm_clip_rect *cliprects = NULL;
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 u64 exec_len;
1079 int instp_mode;
1080 u32 instp_mask;
1081 int i, ret = 0;
1082
1083 if (args->num_cliprects != 0) {
1084 if (ring != &dev_priv->ring[RCS]) {
1085 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1086 return -EINVAL;
1087 }
1088
1089 if (INTEL_INFO(dev)->gen >= 5) {
1090 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1091 return -EINVAL;
1092 }
1093
1094 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1095 DRM_DEBUG("execbuf with %u cliprects\n",
1096 args->num_cliprects);
1097 return -EINVAL;
1098 }
1099
1100 cliprects = kcalloc(args->num_cliprects,
1101 sizeof(*cliprects),
1102 GFP_KERNEL);
1103 if (cliprects == NULL) {
1104 ret = -ENOMEM;
1105 goto error;
1106 }
1107
1108 if (copy_from_user(cliprects,
1109 to_user_ptr(args->cliprects_ptr),
1110 sizeof(*cliprects)*args->num_cliprects)) {
1111 ret = -EFAULT;
1112 goto error;
1113 }
1114 } else {
1115 if (args->DR4 == 0xffffffff) {
1116 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1117 args->DR4 = 0;
1118 }
1119
1120 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
1121 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1122 return -EINVAL;
1123 }
1124 }
1125
1126 ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
1127 if (ret)
1128 goto error;
1129
1130 ret = i915_switch_context(ring, ctx);
1131 if (ret)
1132 goto error;
1133
1134 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1135 instp_mask = I915_EXEC_CONSTANTS_MASK;
1136 switch (instp_mode) {
1137 case I915_EXEC_CONSTANTS_REL_GENERAL:
1138 case I915_EXEC_CONSTANTS_ABSOLUTE:
1139 case I915_EXEC_CONSTANTS_REL_SURFACE:
1140 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1141 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1142 ret = -EINVAL;
1143 goto error;
1144 }
1145
1146 if (instp_mode != dev_priv->relative_constants_mode) {
1147 if (INTEL_INFO(dev)->gen < 4) {
1148 DRM_DEBUG("no rel constants on pre-gen4\n");
1149 ret = -EINVAL;
1150 goto error;
1151 }
1152
1153 if (INTEL_INFO(dev)->gen > 5 &&
1154 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1155 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1156 ret = -EINVAL;
1157 goto error;
1158 }
1159
1160 /* The HW changed the meaning on this bit on gen6 */
1161 if (INTEL_INFO(dev)->gen >= 6)
1162 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1163 }
1164 break;
1165 default:
1166 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1167 ret = -EINVAL;
1168 goto error;
1169 }
1170
1171 if (ring == &dev_priv->ring[RCS] &&
1172 instp_mode != dev_priv->relative_constants_mode) {
1173 ret = intel_ring_begin(ring, 4);
1174 if (ret)
1175 goto error;
1176
1177 intel_ring_emit(ring, MI_NOOP);
1178 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1179 intel_ring_emit(ring, INSTPM);
1180 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1181 intel_ring_advance(ring);
1182
1183 dev_priv->relative_constants_mode = instp_mode;
1184 }
1185
1186 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1187 ret = i915_reset_gen7_sol_offsets(dev, ring);
1188 if (ret)
1189 goto error;
1190 }
1191
1192 exec_len = args->batch_len;
1193 if (cliprects) {
1194 for (i = 0; i < args->num_cliprects; i++) {
1195 ret = i915_emit_box(ring, &cliprects[i],
1196 args->DR1, args->DR4);
1197 if (ret)
1198 goto error;
1199
1200 ret = ring->dispatch_execbuffer(ring,
1201 exec_start, exec_len,
1202 flags);
1203 if (ret)
1204 goto error;
1205 }
1206 } else {
1207 ret = ring->dispatch_execbuffer(ring,
1208 exec_start, exec_len,
1209 flags);
1210 if (ret)
1211 return ret;
1212 }
1213
1214 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1215
1216 i915_gem_execbuffer_move_to_active(vmas, ring);
1217 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1218
1219 error:
1220 kfree(cliprects);
1221 return ret;
1222 }
1223
1224 /**
1225 * Find one BSD ring to dispatch the corresponding BSD command.
1226 * The Ring ID is returned.
1227 */
1228 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1229 struct drm_file *file)
1230 {
1231 struct drm_i915_private *dev_priv = dev->dev_private;
1232 struct drm_i915_file_private *file_priv = file->driver_priv;
1233
1234 /* Check whether the file_priv is using one ring */
1235 if (file_priv->bsd_ring)
1236 return file_priv->bsd_ring->id;
1237 else {
1238 /* If no, use the ping-pong mechanism to select one ring */
1239 int ring_id;
1240
1241 mutex_lock(&dev->struct_mutex);
1242 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1243 ring_id = VCS;
1244 dev_priv->mm.bsd_ring_dispatch_index = 1;
1245 } else {
1246 ring_id = VCS2;
1247 dev_priv->mm.bsd_ring_dispatch_index = 0;
1248 }
1249 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1250 mutex_unlock(&dev->struct_mutex);
1251 return ring_id;
1252 }
1253 }
1254
1255 static struct drm_i915_gem_object *
1256 eb_get_batch(struct eb_vmas *eb)
1257 {
1258 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1259
1260 /*
1261 * SNA is doing fancy tricks with compressing batch buffers, which leads
1262 * to negative relocation deltas. Usually that works out ok since the
1263 * relocate address is still positive, except when the batch is placed
1264 * very low in the GTT. Ensure this doesn't happen.
1265 *
1266 * Note that actual hangs have only been observed on gen7, but for
1267 * paranoia do it everywhere.
1268 */
1269 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1270
1271 return vma->obj;
1272 }
1273
1274 static int
1275 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1276 struct drm_file *file,
1277 struct drm_i915_gem_execbuffer2 *args,
1278 struct drm_i915_gem_exec_object2 *exec)
1279 {
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 struct eb_vmas *eb;
1282 struct drm_i915_gem_object *batch_obj;
1283 struct intel_engine_cs *ring;
1284 struct intel_context *ctx;
1285 struct i915_address_space *vm;
1286 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1287 u64 exec_start = args->batch_start_offset;
1288 u32 flags;
1289 int ret;
1290 bool need_relocs;
1291
1292 if (!i915_gem_check_execbuffer(args))
1293 return -EINVAL;
1294
1295 ret = validate_exec_list(dev, exec, args->buffer_count);
1296 if (ret)
1297 return ret;
1298
1299 flags = 0;
1300 if (args->flags & I915_EXEC_SECURE) {
1301 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1302 return -EPERM;
1303
1304 flags |= I915_DISPATCH_SECURE;
1305 }
1306 if (args->flags & I915_EXEC_IS_PINNED)
1307 flags |= I915_DISPATCH_PINNED;
1308
1309 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1310 DRM_DEBUG("execbuf with unknown ring: %d\n",
1311 (int)(args->flags & I915_EXEC_RING_MASK));
1312 return -EINVAL;
1313 }
1314
1315 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1316 ring = &dev_priv->ring[RCS];
1317 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1318 if (HAS_BSD2(dev)) {
1319 int ring_id;
1320 ring_id = gen8_dispatch_bsd_ring(dev, file);
1321 ring = &dev_priv->ring[ring_id];
1322 } else
1323 ring = &dev_priv->ring[VCS];
1324 } else
1325 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1326
1327 if (!intel_ring_initialized(ring)) {
1328 DRM_DEBUG("execbuf with invalid ring: %d\n",
1329 (int)(args->flags & I915_EXEC_RING_MASK));
1330 return -EINVAL;
1331 }
1332
1333 if (args->buffer_count < 1) {
1334 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1335 return -EINVAL;
1336 }
1337
1338 intel_runtime_pm_get(dev_priv);
1339
1340 ret = i915_mutex_lock_interruptible(dev);
1341 if (ret)
1342 goto pre_mutex_err;
1343
1344 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1345 if (IS_ERR(ctx)) {
1346 mutex_unlock(&dev->struct_mutex);
1347 ret = PTR_ERR(ctx);
1348 goto pre_mutex_err;
1349 }
1350
1351 i915_gem_context_reference(ctx);
1352
1353 if (ctx->ppgtt)
1354 vm = &ctx->ppgtt->base;
1355 else
1356 vm = &dev_priv->gtt.base;
1357
1358 eb = eb_create(args);
1359 if (eb == NULL) {
1360 i915_gem_context_unreference(ctx);
1361 mutex_unlock(&dev->struct_mutex);
1362 ret = -ENOMEM;
1363 goto pre_mutex_err;
1364 }
1365
1366 /* Look up object handles */
1367 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1368 if (ret)
1369 goto err;
1370
1371 /* take note of the batch buffer before we might reorder the lists */
1372 batch_obj = eb_get_batch(eb);
1373
1374 /* Move the objects en-masse into the GTT, evicting if necessary. */
1375 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1376 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
1377 if (ret)
1378 goto err;
1379
1380 /* The objects are in their final locations, apply the relocations. */
1381 if (need_relocs)
1382 ret = i915_gem_execbuffer_relocate(eb);
1383 if (ret) {
1384 if (ret == -EFAULT) {
1385 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1386 eb, exec);
1387 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1388 }
1389 if (ret)
1390 goto err;
1391 }
1392
1393 /* Set the pending read domains for the batch buffer to COMMAND */
1394 if (batch_obj->base.pending_write_domain) {
1395 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1396 ret = -EINVAL;
1397 goto err;
1398 }
1399 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1400
1401 if (i915_needs_cmd_parser(ring)) {
1402 ret = i915_parse_cmds(ring,
1403 batch_obj,
1404 args->batch_start_offset,
1405 file->is_master);
1406 if (ret) {
1407 if (ret != -EACCES)
1408 goto err;
1409 } else {
1410 /*
1411 * XXX: Actually do this when enabling batch copy...
1412 *
1413 * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
1414 * from MI_BATCH_BUFFER_START commands issued in the
1415 * dispatch_execbuffer implementations. We specifically don't
1416 * want that set when the command parser is enabled.
1417 */
1418 }
1419 }
1420
1421 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1422 * batch" bit. Hence we need to pin secure batches into the global gtt.
1423 * hsw should have this fixed, but bdw mucks it up again. */
1424 if (flags & I915_DISPATCH_SECURE) {
1425 /*
1426 * So on first glance it looks freaky that we pin the batch here
1427 * outside of the reservation loop. But:
1428 * - The batch is already pinned into the relevant ppgtt, so we
1429 * already have the backing storage fully allocated.
1430 * - No other BO uses the global gtt (well contexts, but meh),
1431 * so we don't really have issues with mutliple objects not
1432 * fitting due to fragmentation.
1433 * So this is actually safe.
1434 */
1435 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1436 if (ret)
1437 goto err;
1438
1439 exec_start += i915_gem_obj_ggtt_offset(batch_obj);
1440 } else
1441 exec_start += i915_gem_obj_offset(batch_obj, vm);
1442
1443 ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args,
1444 &eb->vmas, batch_obj, exec_start, flags);
1445
1446 /*
1447 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1448 * batch vma for correctness. For less ugly and less fragility this
1449 * needs to be adjusted to also track the ggtt batch vma properly as
1450 * active.
1451 */
1452 if (flags & I915_DISPATCH_SECURE)
1453 i915_gem_object_ggtt_unpin(batch_obj);
1454 err:
1455 /* the request owns the ref now */
1456 i915_gem_context_unreference(ctx);
1457 eb_destroy(eb);
1458
1459 mutex_unlock(&dev->struct_mutex);
1460
1461 pre_mutex_err:
1462 /* intel_gpu_busy should also get a ref, so it will free when the device
1463 * is really idle. */
1464 intel_runtime_pm_put(dev_priv);
1465 return ret;
1466 }
1467
1468 /*
1469 * Legacy execbuffer just creates an exec2 list from the original exec object
1470 * list array and passes it to the real function.
1471 */
1472 int
1473 i915_gem_execbuffer(struct drm_device *dev, void *data,
1474 struct drm_file *file)
1475 {
1476 struct drm_i915_gem_execbuffer *args = data;
1477 struct drm_i915_gem_execbuffer2 exec2;
1478 struct drm_i915_gem_exec_object *exec_list = NULL;
1479 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1480 int ret, i;
1481
1482 if (args->buffer_count < 1) {
1483 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1484 return -EINVAL;
1485 }
1486
1487 /* Copy in the exec list from userland */
1488 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1489 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1490 if (exec_list == NULL || exec2_list == NULL) {
1491 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1492 args->buffer_count);
1493 drm_free_large(exec_list);
1494 drm_free_large(exec2_list);
1495 return -ENOMEM;
1496 }
1497 ret = copy_from_user(exec_list,
1498 to_user_ptr(args->buffers_ptr),
1499 sizeof(*exec_list) * args->buffer_count);
1500 if (ret != 0) {
1501 DRM_DEBUG("copy %d exec entries failed %d\n",
1502 args->buffer_count, ret);
1503 drm_free_large(exec_list);
1504 drm_free_large(exec2_list);
1505 return -EFAULT;
1506 }
1507
1508 for (i = 0; i < args->buffer_count; i++) {
1509 exec2_list[i].handle = exec_list[i].handle;
1510 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1511 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1512 exec2_list[i].alignment = exec_list[i].alignment;
1513 exec2_list[i].offset = exec_list[i].offset;
1514 if (INTEL_INFO(dev)->gen < 4)
1515 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1516 else
1517 exec2_list[i].flags = 0;
1518 }
1519
1520 exec2.buffers_ptr = args->buffers_ptr;
1521 exec2.buffer_count = args->buffer_count;
1522 exec2.batch_start_offset = args->batch_start_offset;
1523 exec2.batch_len = args->batch_len;
1524 exec2.DR1 = args->DR1;
1525 exec2.DR4 = args->DR4;
1526 exec2.num_cliprects = args->num_cliprects;
1527 exec2.cliprects_ptr = args->cliprects_ptr;
1528 exec2.flags = I915_EXEC_RENDER;
1529 i915_execbuffer2_set_context_id(exec2, 0);
1530
1531 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1532 if (!ret) {
1533 struct drm_i915_gem_exec_object __user *user_exec_list =
1534 to_user_ptr(args->buffers_ptr);
1535
1536 /* Copy the new buffer offsets back to the user's exec list. */
1537 for (i = 0; i < args->buffer_count; i++) {
1538 ret = __copy_to_user(&user_exec_list[i].offset,
1539 &exec2_list[i].offset,
1540 sizeof(user_exec_list[i].offset));
1541 if (ret) {
1542 ret = -EFAULT;
1543 DRM_DEBUG("failed to copy %d exec entries "
1544 "back to user (%d)\n",
1545 args->buffer_count, ret);
1546 break;
1547 }
1548 }
1549 }
1550
1551 drm_free_large(exec_list);
1552 drm_free_large(exec2_list);
1553 return ret;
1554 }
1555
1556 int
1557 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1558 struct drm_file *file)
1559 {
1560 struct drm_i915_gem_execbuffer2 *args = data;
1561 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1562 int ret;
1563
1564 if (args->buffer_count < 1 ||
1565 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1566 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1567 return -EINVAL;
1568 }
1569
1570 if (args->rsvd2 != 0) {
1571 DRM_DEBUG("dirty rvsd2 field\n");
1572 return -EINVAL;
1573 }
1574
1575 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1576 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1577 if (exec2_list == NULL)
1578 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1579 args->buffer_count);
1580 if (exec2_list == NULL) {
1581 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1582 args->buffer_count);
1583 return -ENOMEM;
1584 }
1585 ret = copy_from_user(exec2_list,
1586 to_user_ptr(args->buffers_ptr),
1587 sizeof(*exec2_list) * args->buffer_count);
1588 if (ret != 0) {
1589 DRM_DEBUG("copy %d exec entries failed %d\n",
1590 args->buffer_count, ret);
1591 drm_free_large(exec2_list);
1592 return -EFAULT;
1593 }
1594
1595 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1596 if (!ret) {
1597 /* Copy the new buffer offsets back to the user's exec list. */
1598 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1599 to_user_ptr(args->buffers_ptr);
1600 int i;
1601
1602 for (i = 0; i < args->buffer_count; i++) {
1603 ret = __copy_to_user(&user_exec_list[i].offset,
1604 &exec2_list[i].offset,
1605 sizeof(user_exec_list[i].offset));
1606 if (ret) {
1607 ret = -EFAULT;
1608 DRM_DEBUG("failed to copy %d exec entries "
1609 "back to user\n",
1610 args->buffer_count);
1611 break;
1612 }
1613 }
1614 }
1615
1616 drm_free_large(exec2_list);
1617 return ret;
1618 }
Linux kernel - Deliverables
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