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drm/i915: Fix VLV DP RBR/HDMI/DAC PLL LPF coefficients
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35
36 struct eb_objects {
37 struct list_head objects;
38 int and;
39 union {
40 struct drm_i915_gem_object *lut[0];
41 struct hlist_head buckets[0];
42 };
43 };
44
45 static struct eb_objects *
46 eb_create(struct drm_i915_gem_execbuffer2 *args)
47 {
48 struct eb_objects *eb = NULL;
49
50 if (args->flags & I915_EXEC_HANDLE_LUT) {
51 int size = args->buffer_count;
52 size *= sizeof(struct drm_i915_gem_object *);
53 size += sizeof(struct eb_objects);
54 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
55 }
56
57 if (eb == NULL) {
58 int size = args->buffer_count;
59 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
60 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
61 while (count > 2*size)
62 count >>= 1;
63 eb = kzalloc(count*sizeof(struct hlist_head) +
64 sizeof(struct eb_objects),
65 GFP_TEMPORARY);
66 if (eb == NULL)
67 return eb;
68
69 eb->and = count - 1;
70 } else
71 eb->and = -args->buffer_count;
72
73 INIT_LIST_HEAD(&eb->objects);
74 return eb;
75 }
76
77 static void
78 eb_reset(struct eb_objects *eb)
79 {
80 if (eb->and >= 0)
81 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
82 }
83
84 static int
85 eb_lookup_objects(struct eb_objects *eb,
86 struct drm_i915_gem_exec_object2 *exec,
87 const struct drm_i915_gem_execbuffer2 *args,
88 struct drm_file *file)
89 {
90 int i;
91
92 spin_lock(&file->table_lock);
93 for (i = 0; i < args->buffer_count; i++) {
94 struct drm_i915_gem_object *obj;
95
96 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
97 if (obj == NULL) {
98 spin_unlock(&file->table_lock);
99 DRM_DEBUG("Invalid object handle %d at index %d\n",
100 exec[i].handle, i);
101 return -ENOENT;
102 }
103
104 if (!list_empty(&obj->exec_list)) {
105 spin_unlock(&file->table_lock);
106 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
107 obj, exec[i].handle, i);
108 return -EINVAL;
109 }
110
111 drm_gem_object_reference(&obj->base);
112 list_add_tail(&obj->exec_list, &eb->objects);
113
114 obj->exec_entry = &exec[i];
115 if (eb->and < 0) {
116 eb->lut[i] = obj;
117 } else {
118 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
119 obj->exec_handle = handle;
120 hlist_add_head(&obj->exec_node,
121 &eb->buckets[handle & eb->and]);
122 }
123 }
124 spin_unlock(&file->table_lock);
125
126 return 0;
127 }
128
129 static struct drm_i915_gem_object *
130 eb_get_object(struct eb_objects *eb, unsigned long handle)
131 {
132 if (eb->and < 0) {
133 if (handle >= -eb->and)
134 return NULL;
135 return eb->lut[handle];
136 } else {
137 struct hlist_head *head;
138 struct hlist_node *node;
139
140 head = &eb->buckets[handle & eb->and];
141 hlist_for_each(node, head) {
142 struct drm_i915_gem_object *obj;
143
144 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
145 if (obj->exec_handle == handle)
146 return obj;
147 }
148 return NULL;
149 }
150 }
151
152 static void
153 eb_destroy(struct eb_objects *eb)
154 {
155 while (!list_empty(&eb->objects)) {
156 struct drm_i915_gem_object *obj;
157
158 obj = list_first_entry(&eb->objects,
159 struct drm_i915_gem_object,
160 exec_list);
161 list_del_init(&obj->exec_list);
162 drm_gem_object_unreference(&obj->base);
163 }
164 kfree(eb);
165 }
166
167 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
168 {
169 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
170 !obj->map_and_fenceable ||
171 obj->cache_level != I915_CACHE_NONE);
172 }
173
174 static int
175 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
176 struct eb_objects *eb,
177 struct drm_i915_gem_relocation_entry *reloc)
178 {
179 struct drm_device *dev = obj->base.dev;
180 struct drm_gem_object *target_obj;
181 struct drm_i915_gem_object *target_i915_obj;
182 uint32_t target_offset;
183 int ret = -EINVAL;
184
185 /* we've already hold a reference to all valid objects */
186 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
187 if (unlikely(target_obj == NULL))
188 return -ENOENT;
189
190 target_i915_obj = to_intel_bo(target_obj);
191 target_offset = i915_gem_obj_ggtt_offset(target_i915_obj);
192
193 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
194 * pipe_control writes because the gpu doesn't properly redirect them
195 * through the ppgtt for non_secure batchbuffers. */
196 if (unlikely(IS_GEN6(dev) &&
197 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
198 !target_i915_obj->has_global_gtt_mapping)) {
199 i915_gem_gtt_bind_object(target_i915_obj,
200 target_i915_obj->cache_level);
201 }
202
203 /* Validate that the target is in a valid r/w GPU domain */
204 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
205 DRM_DEBUG("reloc with multiple write domains: "
206 "obj %p target %d offset %d "
207 "read %08x write %08x",
208 obj, reloc->target_handle,
209 (int) reloc->offset,
210 reloc->read_domains,
211 reloc->write_domain);
212 return ret;
213 }
214 if (unlikely((reloc->write_domain | reloc->read_domains)
215 & ~I915_GEM_GPU_DOMAINS)) {
216 DRM_DEBUG("reloc with read/write non-GPU domains: "
217 "obj %p target %d offset %d "
218 "read %08x write %08x",
219 obj, reloc->target_handle,
220 (int) reloc->offset,
221 reloc->read_domains,
222 reloc->write_domain);
223 return ret;
224 }
225
226 target_obj->pending_read_domains |= reloc->read_domains;
227 target_obj->pending_write_domain |= reloc->write_domain;
228
229 /* If the relocation already has the right value in it, no
230 * more work needs to be done.
231 */
232 if (target_offset == reloc->presumed_offset)
233 return 0;
234
235 /* Check that the relocation address is valid... */
236 if (unlikely(reloc->offset > obj->base.size - 4)) {
237 DRM_DEBUG("Relocation beyond object bounds: "
238 "obj %p target %d offset %d size %d.\n",
239 obj, reloc->target_handle,
240 (int) reloc->offset,
241 (int) obj->base.size);
242 return ret;
243 }
244 if (unlikely(reloc->offset & 3)) {
245 DRM_DEBUG("Relocation not 4-byte aligned: "
246 "obj %p target %d offset %d.\n",
247 obj, reloc->target_handle,
248 (int) reloc->offset);
249 return ret;
250 }
251
252 /* We can't wait for rendering with pagefaults disabled */
253 if (obj->active && in_atomic())
254 return -EFAULT;
255
256 reloc->delta += target_offset;
257 if (use_cpu_reloc(obj)) {
258 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
259 char *vaddr;
260
261 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
262 if (ret)
263 return ret;
264
265 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
266 reloc->offset >> PAGE_SHIFT));
267 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
268 kunmap_atomic(vaddr);
269 } else {
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 uint32_t __iomem *reloc_entry;
272 void __iomem *reloc_page;
273
274 ret = i915_gem_object_set_to_gtt_domain(obj, true);
275 if (ret)
276 return ret;
277
278 ret = i915_gem_object_put_fence(obj);
279 if (ret)
280 return ret;
281
282 /* Map the page containing the relocation we're going to perform. */
283 reloc->offset += i915_gem_obj_ggtt_offset(obj);
284 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
285 reloc->offset & PAGE_MASK);
286 reloc_entry = (uint32_t __iomem *)
287 (reloc_page + (reloc->offset & ~PAGE_MASK));
288 iowrite32(reloc->delta, reloc_entry);
289 io_mapping_unmap_atomic(reloc_page);
290 }
291
292 /* and update the user's relocation entry */
293 reloc->presumed_offset = target_offset;
294
295 return 0;
296 }
297
298 static int
299 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
300 struct eb_objects *eb)
301 {
302 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
303 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
304 struct drm_i915_gem_relocation_entry __user *user_relocs;
305 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
306 int remain, ret;
307
308 user_relocs = to_user_ptr(entry->relocs_ptr);
309
310 remain = entry->relocation_count;
311 while (remain) {
312 struct drm_i915_gem_relocation_entry *r = stack_reloc;
313 int count = remain;
314 if (count > ARRAY_SIZE(stack_reloc))
315 count = ARRAY_SIZE(stack_reloc);
316 remain -= count;
317
318 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
319 return -EFAULT;
320
321 do {
322 u64 offset = r->presumed_offset;
323
324 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
325 if (ret)
326 return ret;
327
328 if (r->presumed_offset != offset &&
329 __copy_to_user_inatomic(&user_relocs->presumed_offset,
330 &r->presumed_offset,
331 sizeof(r->presumed_offset))) {
332 return -EFAULT;
333 }
334
335 user_relocs++;
336 r++;
337 } while (--count);
338 }
339
340 return 0;
341 #undef N_RELOC
342 }
343
344 static int
345 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
346 struct eb_objects *eb,
347 struct drm_i915_gem_relocation_entry *relocs)
348 {
349 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
350 int i, ret;
351
352 for (i = 0; i < entry->relocation_count; i++) {
353 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
354 if (ret)
355 return ret;
356 }
357
358 return 0;
359 }
360
361 static int
362 i915_gem_execbuffer_relocate(struct eb_objects *eb)
363 {
364 struct drm_i915_gem_object *obj;
365 int ret = 0;
366
367 /* This is the fast path and we cannot handle a pagefault whilst
368 * holding the struct mutex lest the user pass in the relocations
369 * contained within a mmaped bo. For in such a case we, the page
370 * fault handler would call i915_gem_fault() and we would try to
371 * acquire the struct mutex again. Obviously this is bad and so
372 * lockdep complains vehemently.
373 */
374 pagefault_disable();
375 list_for_each_entry(obj, &eb->objects, exec_list) {
376 ret = i915_gem_execbuffer_relocate_object(obj, eb);
377 if (ret)
378 break;
379 }
380 pagefault_enable();
381
382 return ret;
383 }
384
385 #define __EXEC_OBJECT_HAS_PIN (1<<31)
386 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
387
388 static int
389 need_reloc_mappable(struct drm_i915_gem_object *obj)
390 {
391 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
392 return entry->relocation_count && !use_cpu_reloc(obj);
393 }
394
395 static int
396 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
397 struct intel_ring_buffer *ring,
398 bool *need_reloc)
399 {
400 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
401 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
402 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
403 bool need_fence, need_mappable;
404 int ret;
405
406 need_fence =
407 has_fenced_gpu_access &&
408 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
409 obj->tiling_mode != I915_TILING_NONE;
410 need_mappable = need_fence || need_reloc_mappable(obj);
411
412 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
413 if (ret)
414 return ret;
415
416 entry->flags |= __EXEC_OBJECT_HAS_PIN;
417
418 if (has_fenced_gpu_access) {
419 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
420 ret = i915_gem_object_get_fence(obj);
421 if (ret)
422 return ret;
423
424 if (i915_gem_object_pin_fence(obj))
425 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
426
427 obj->pending_fenced_gpu_access = true;
428 }
429 }
430
431 /* Ensure ppgtt mapping exists if needed */
432 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
433 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
434 obj, obj->cache_level);
435
436 obj->has_aliasing_ppgtt_mapping = 1;
437 }
438
439 if (entry->offset != i915_gem_obj_ggtt_offset(obj)) {
440 entry->offset = i915_gem_obj_ggtt_offset(obj);
441 *need_reloc = true;
442 }
443
444 if (entry->flags & EXEC_OBJECT_WRITE) {
445 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
446 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
447 }
448
449 if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
450 !obj->has_global_gtt_mapping)
451 i915_gem_gtt_bind_object(obj, obj->cache_level);
452
453 return 0;
454 }
455
456 static void
457 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
458 {
459 struct drm_i915_gem_exec_object2 *entry;
460
461 if (!i915_gem_obj_ggtt_bound(obj))
462 return;
463
464 entry = obj->exec_entry;
465
466 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
467 i915_gem_object_unpin_fence(obj);
468
469 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
470 i915_gem_object_unpin(obj);
471
472 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
473 }
474
475 static int
476 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
477 struct list_head *objects,
478 bool *need_relocs)
479 {
480 struct drm_i915_gem_object *obj;
481 struct list_head ordered_objects;
482 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
483 int retry;
484
485 INIT_LIST_HEAD(&ordered_objects);
486 while (!list_empty(objects)) {
487 struct drm_i915_gem_exec_object2 *entry;
488 bool need_fence, need_mappable;
489
490 obj = list_first_entry(objects,
491 struct drm_i915_gem_object,
492 exec_list);
493 entry = obj->exec_entry;
494
495 need_fence =
496 has_fenced_gpu_access &&
497 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
498 obj->tiling_mode != I915_TILING_NONE;
499 need_mappable = need_fence || need_reloc_mappable(obj);
500
501 if (need_mappable)
502 list_move(&obj->exec_list, &ordered_objects);
503 else
504 list_move_tail(&obj->exec_list, &ordered_objects);
505
506 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
507 obj->base.pending_write_domain = 0;
508 obj->pending_fenced_gpu_access = false;
509 }
510 list_splice(&ordered_objects, objects);
511
512 /* Attempt to pin all of the buffers into the GTT.
513 * This is done in 3 phases:
514 *
515 * 1a. Unbind all objects that do not match the GTT constraints for
516 * the execbuffer (fenceable, mappable, alignment etc).
517 * 1b. Increment pin count for already bound objects.
518 * 2. Bind new objects.
519 * 3. Decrement pin count.
520 *
521 * This avoid unnecessary unbinding of later objects in order to make
522 * room for the earlier objects *unless* we need to defragment.
523 */
524 retry = 0;
525 do {
526 int ret = 0;
527
528 /* Unbind any ill-fitting objects or pin. */
529 list_for_each_entry(obj, objects, exec_list) {
530 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
531 bool need_fence, need_mappable;
532
533 if (!i915_gem_obj_ggtt_bound(obj))
534 continue;
535
536 need_fence =
537 has_fenced_gpu_access &&
538 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
539 obj->tiling_mode != I915_TILING_NONE;
540 need_mappable = need_fence || need_reloc_mappable(obj);
541
542 if ((entry->alignment &&
543 i915_gem_obj_ggtt_offset(obj) & (entry->alignment - 1)) ||
544 (need_mappable && !obj->map_and_fenceable))
545 ret = i915_gem_object_unbind(obj);
546 else
547 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
548 if (ret)
549 goto err;
550 }
551
552 /* Bind fresh objects */
553 list_for_each_entry(obj, objects, exec_list) {
554 if (i915_gem_obj_ggtt_bound(obj))
555 continue;
556
557 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
558 if (ret)
559 goto err;
560 }
561
562 err: /* Decrement pin count for bound objects */
563 list_for_each_entry(obj, objects, exec_list)
564 i915_gem_execbuffer_unreserve_object(obj);
565
566 if (ret != -ENOSPC || retry++)
567 return ret;
568
569 ret = i915_gem_evict_everything(ring->dev);
570 if (ret)
571 return ret;
572 } while (1);
573 }
574
575 static int
576 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
577 struct drm_i915_gem_execbuffer2 *args,
578 struct drm_file *file,
579 struct intel_ring_buffer *ring,
580 struct eb_objects *eb,
581 struct drm_i915_gem_exec_object2 *exec)
582 {
583 struct drm_i915_gem_relocation_entry *reloc;
584 struct drm_i915_gem_object *obj;
585 bool need_relocs;
586 int *reloc_offset;
587 int i, total, ret;
588 int count = args->buffer_count;
589
590 /* We may process another execbuffer during the unlock... */
591 while (!list_empty(&eb->objects)) {
592 obj = list_first_entry(&eb->objects,
593 struct drm_i915_gem_object,
594 exec_list);
595 list_del_init(&obj->exec_list);
596 drm_gem_object_unreference(&obj->base);
597 }
598
599 mutex_unlock(&dev->struct_mutex);
600
601 total = 0;
602 for (i = 0; i < count; i++)
603 total += exec[i].relocation_count;
604
605 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
606 reloc = drm_malloc_ab(total, sizeof(*reloc));
607 if (reloc == NULL || reloc_offset == NULL) {
608 drm_free_large(reloc);
609 drm_free_large(reloc_offset);
610 mutex_lock(&dev->struct_mutex);
611 return -ENOMEM;
612 }
613
614 total = 0;
615 for (i = 0; i < count; i++) {
616 struct drm_i915_gem_relocation_entry __user *user_relocs;
617 u64 invalid_offset = (u64)-1;
618 int j;
619
620 user_relocs = to_user_ptr(exec[i].relocs_ptr);
621
622 if (copy_from_user(reloc+total, user_relocs,
623 exec[i].relocation_count * sizeof(*reloc))) {
624 ret = -EFAULT;
625 mutex_lock(&dev->struct_mutex);
626 goto err;
627 }
628
629 /* As we do not update the known relocation offsets after
630 * relocating (due to the complexities in lock handling),
631 * we need to mark them as invalid now so that we force the
632 * relocation processing next time. Just in case the target
633 * object is evicted and then rebound into its old
634 * presumed_offset before the next execbuffer - if that
635 * happened we would make the mistake of assuming that the
636 * relocations were valid.
637 */
638 for (j = 0; j < exec[i].relocation_count; j++) {
639 if (copy_to_user(&user_relocs[j].presumed_offset,
640 &invalid_offset,
641 sizeof(invalid_offset))) {
642 ret = -EFAULT;
643 mutex_lock(&dev->struct_mutex);
644 goto err;
645 }
646 }
647
648 reloc_offset[i] = total;
649 total += exec[i].relocation_count;
650 }
651
652 ret = i915_mutex_lock_interruptible(dev);
653 if (ret) {
654 mutex_lock(&dev->struct_mutex);
655 goto err;
656 }
657
658 /* reacquire the objects */
659 eb_reset(eb);
660 ret = eb_lookup_objects(eb, exec, args, file);
661 if (ret)
662 goto err;
663
664 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
665 ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
666 if (ret)
667 goto err;
668
669 list_for_each_entry(obj, &eb->objects, exec_list) {
670 int offset = obj->exec_entry - exec;
671 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
672 reloc + reloc_offset[offset]);
673 if (ret)
674 goto err;
675 }
676
677 /* Leave the user relocations as are, this is the painfully slow path,
678 * and we want to avoid the complication of dropping the lock whilst
679 * having buffers reserved in the aperture and so causing spurious
680 * ENOSPC for random operations.
681 */
682
683 err:
684 drm_free_large(reloc);
685 drm_free_large(reloc_offset);
686 return ret;
687 }
688
689 static int
690 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
691 struct list_head *objects)
692 {
693 struct drm_i915_gem_object *obj;
694 uint32_t flush_domains = 0;
695 int ret;
696
697 list_for_each_entry(obj, objects, exec_list) {
698 ret = i915_gem_object_sync(obj, ring);
699 if (ret)
700 return ret;
701
702 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
703 i915_gem_clflush_object(obj);
704
705 flush_domains |= obj->base.write_domain;
706 }
707
708 if (flush_domains & I915_GEM_DOMAIN_CPU)
709 i915_gem_chipset_flush(ring->dev);
710
711 if (flush_domains & I915_GEM_DOMAIN_GTT)
712 wmb();
713
714 /* Unconditionally invalidate gpu caches and ensure that we do flush
715 * any residual writes from the previous batch.
716 */
717 return intel_ring_invalidate_all_caches(ring);
718 }
719
720 static bool
721 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
722 {
723 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
724 return false;
725
726 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
727 }
728
729 static int
730 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
731 int count)
732 {
733 int i;
734 int relocs_total = 0;
735 int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
736
737 for (i = 0; i < count; i++) {
738 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
739 int length; /* limited by fault_in_pages_readable() */
740
741 if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
742 return -EINVAL;
743
744 /* First check for malicious input causing overflow in
745 * the worst case where we need to allocate the entire
746 * relocation tree as a single array.
747 */
748 if (exec[i].relocation_count > relocs_max - relocs_total)
749 return -EINVAL;
750 relocs_total += exec[i].relocation_count;
751
752 length = exec[i].relocation_count *
753 sizeof(struct drm_i915_gem_relocation_entry);
754 /*
755 * We must check that the entire relocation array is safe
756 * to read, but since we may need to update the presumed
757 * offsets during execution, check for full write access.
758 */
759 if (!access_ok(VERIFY_WRITE, ptr, length))
760 return -EFAULT;
761
762 if (fault_in_multipages_readable(ptr, length))
763 return -EFAULT;
764 }
765
766 return 0;
767 }
768
769 static void
770 i915_gem_execbuffer_move_to_active(struct list_head *objects,
771 struct intel_ring_buffer *ring)
772 {
773 struct drm_i915_gem_object *obj;
774
775 list_for_each_entry(obj, objects, exec_list) {
776 u32 old_read = obj->base.read_domains;
777 u32 old_write = obj->base.write_domain;
778
779 obj->base.write_domain = obj->base.pending_write_domain;
780 if (obj->base.write_domain == 0)
781 obj->base.pending_read_domains |= obj->base.read_domains;
782 obj->base.read_domains = obj->base.pending_read_domains;
783 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
784
785 i915_gem_object_move_to_active(obj, ring);
786 if (obj->base.write_domain) {
787 obj->dirty = 1;
788 obj->last_write_seqno = intel_ring_get_seqno(ring);
789 if (obj->pin_count) /* check for potential scanout */
790 intel_mark_fb_busy(obj, ring);
791 }
792
793 trace_i915_gem_object_change_domain(obj, old_read, old_write);
794 }
795 }
796
797 static void
798 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
799 struct drm_file *file,
800 struct intel_ring_buffer *ring,
801 struct drm_i915_gem_object *obj)
802 {
803 /* Unconditionally force add_request to emit a full flush. */
804 ring->gpu_caches_dirty = true;
805
806 /* Add a breadcrumb for the completion of the batch buffer */
807 (void)__i915_add_request(ring, file, obj, NULL);
808 }
809
810 static int
811 i915_reset_gen7_sol_offsets(struct drm_device *dev,
812 struct intel_ring_buffer *ring)
813 {
814 drm_i915_private_t *dev_priv = dev->dev_private;
815 int ret, i;
816
817 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
818 return 0;
819
820 ret = intel_ring_begin(ring, 4 * 3);
821 if (ret)
822 return ret;
823
824 for (i = 0; i < 4; i++) {
825 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
826 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
827 intel_ring_emit(ring, 0);
828 }
829
830 intel_ring_advance(ring);
831
832 return 0;
833 }
834
835 static int
836 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
837 struct drm_file *file,
838 struct drm_i915_gem_execbuffer2 *args,
839 struct drm_i915_gem_exec_object2 *exec)
840 {
841 drm_i915_private_t *dev_priv = dev->dev_private;
842 struct eb_objects *eb;
843 struct drm_i915_gem_object *batch_obj;
844 struct drm_clip_rect *cliprects = NULL;
845 struct intel_ring_buffer *ring;
846 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
847 u32 exec_start, exec_len;
848 u32 mask, flags;
849 int ret, mode, i;
850 bool need_relocs;
851
852 if (!i915_gem_check_execbuffer(args))
853 return -EINVAL;
854
855 ret = validate_exec_list(exec, args->buffer_count);
856 if (ret)
857 return ret;
858
859 flags = 0;
860 if (args->flags & I915_EXEC_SECURE) {
861 if (!file->is_master || !capable(CAP_SYS_ADMIN))
862 return -EPERM;
863
864 flags |= I915_DISPATCH_SECURE;
865 }
866 if (args->flags & I915_EXEC_IS_PINNED)
867 flags |= I915_DISPATCH_PINNED;
868
869 switch (args->flags & I915_EXEC_RING_MASK) {
870 case I915_EXEC_DEFAULT:
871 case I915_EXEC_RENDER:
872 ring = &dev_priv->ring[RCS];
873 break;
874 case I915_EXEC_BSD:
875 ring = &dev_priv->ring[VCS];
876 if (ctx_id != 0) {
877 DRM_DEBUG("Ring %s doesn't support contexts\n",
878 ring->name);
879 return -EPERM;
880 }
881 break;
882 case I915_EXEC_BLT:
883 ring = &dev_priv->ring[BCS];
884 if (ctx_id != 0) {
885 DRM_DEBUG("Ring %s doesn't support contexts\n",
886 ring->name);
887 return -EPERM;
888 }
889 break;
890 case I915_EXEC_VEBOX:
891 ring = &dev_priv->ring[VECS];
892 if (ctx_id != 0) {
893 DRM_DEBUG("Ring %s doesn't support contexts\n",
894 ring->name);
895 return -EPERM;
896 }
897 break;
898
899 default:
900 DRM_DEBUG("execbuf with unknown ring: %d\n",
901 (int)(args->flags & I915_EXEC_RING_MASK));
902 return -EINVAL;
903 }
904 if (!intel_ring_initialized(ring)) {
905 DRM_DEBUG("execbuf with invalid ring: %d\n",
906 (int)(args->flags & I915_EXEC_RING_MASK));
907 return -EINVAL;
908 }
909
910 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
911 mask = I915_EXEC_CONSTANTS_MASK;
912 switch (mode) {
913 case I915_EXEC_CONSTANTS_REL_GENERAL:
914 case I915_EXEC_CONSTANTS_ABSOLUTE:
915 case I915_EXEC_CONSTANTS_REL_SURFACE:
916 if (ring == &dev_priv->ring[RCS] &&
917 mode != dev_priv->relative_constants_mode) {
918 if (INTEL_INFO(dev)->gen < 4)
919 return -EINVAL;
920
921 if (INTEL_INFO(dev)->gen > 5 &&
922 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
923 return -EINVAL;
924
925 /* The HW changed the meaning on this bit on gen6 */
926 if (INTEL_INFO(dev)->gen >= 6)
927 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
928 }
929 break;
930 default:
931 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
932 return -EINVAL;
933 }
934
935 if (args->buffer_count < 1) {
936 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
937 return -EINVAL;
938 }
939
940 if (args->num_cliprects != 0) {
941 if (ring != &dev_priv->ring[RCS]) {
942 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
943 return -EINVAL;
944 }
945
946 if (INTEL_INFO(dev)->gen >= 5) {
947 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
948 return -EINVAL;
949 }
950
951 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
952 DRM_DEBUG("execbuf with %u cliprects\n",
953 args->num_cliprects);
954 return -EINVAL;
955 }
956
957 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
958 GFP_KERNEL);
959 if (cliprects == NULL) {
960 ret = -ENOMEM;
961 goto pre_mutex_err;
962 }
963
964 if (copy_from_user(cliprects,
965 to_user_ptr(args->cliprects_ptr),
966 sizeof(*cliprects)*args->num_cliprects)) {
967 ret = -EFAULT;
968 goto pre_mutex_err;
969 }
970 }
971
972 ret = i915_mutex_lock_interruptible(dev);
973 if (ret)
974 goto pre_mutex_err;
975
976 if (dev_priv->mm.suspended) {
977 mutex_unlock(&dev->struct_mutex);
978 ret = -EBUSY;
979 goto pre_mutex_err;
980 }
981
982 eb = eb_create(args);
983 if (eb == NULL) {
984 mutex_unlock(&dev->struct_mutex);
985 ret = -ENOMEM;
986 goto pre_mutex_err;
987 }
988
989 /* Look up object handles */
990 ret = eb_lookup_objects(eb, exec, args, file);
991 if (ret)
992 goto err;
993
994 /* take note of the batch buffer before we might reorder the lists */
995 batch_obj = list_entry(eb->objects.prev,
996 struct drm_i915_gem_object,
997 exec_list);
998
999 /* Move the objects en-masse into the GTT, evicting if necessary. */
1000 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1001 ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
1002 if (ret)
1003 goto err;
1004
1005 /* The objects are in their final locations, apply the relocations. */
1006 if (need_relocs)
1007 ret = i915_gem_execbuffer_relocate(eb);
1008 if (ret) {
1009 if (ret == -EFAULT) {
1010 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1011 eb, exec);
1012 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1013 }
1014 if (ret)
1015 goto err;
1016 }
1017
1018 /* Set the pending read domains for the batch buffer to COMMAND */
1019 if (batch_obj->base.pending_write_domain) {
1020 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1021 ret = -EINVAL;
1022 goto err;
1023 }
1024 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1025
1026 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1027 * batch" bit. Hence we need to pin secure batches into the global gtt.
1028 * hsw should have this fixed, but let's be paranoid and do it
1029 * unconditionally for now. */
1030 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
1031 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
1032
1033 ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
1034 if (ret)
1035 goto err;
1036
1037 ret = i915_switch_context(ring, file, ctx_id);
1038 if (ret)
1039 goto err;
1040
1041 if (ring == &dev_priv->ring[RCS] &&
1042 mode != dev_priv->relative_constants_mode) {
1043 ret = intel_ring_begin(ring, 4);
1044 if (ret)
1045 goto err;
1046
1047 intel_ring_emit(ring, MI_NOOP);
1048 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1049 intel_ring_emit(ring, INSTPM);
1050 intel_ring_emit(ring, mask << 16 | mode);
1051 intel_ring_advance(ring);
1052
1053 dev_priv->relative_constants_mode = mode;
1054 }
1055
1056 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1057 ret = i915_reset_gen7_sol_offsets(dev, ring);
1058 if (ret)
1059 goto err;
1060 }
1061
1062 exec_start = i915_gem_obj_ggtt_offset(batch_obj) + args->batch_start_offset;
1063 exec_len = args->batch_len;
1064 if (cliprects) {
1065 for (i = 0; i < args->num_cliprects; i++) {
1066 ret = i915_emit_box(dev, &cliprects[i],
1067 args->DR1, args->DR4);
1068 if (ret)
1069 goto err;
1070
1071 ret = ring->dispatch_execbuffer(ring,
1072 exec_start, exec_len,
1073 flags);
1074 if (ret)
1075 goto err;
1076 }
1077 } else {
1078 ret = ring->dispatch_execbuffer(ring,
1079 exec_start, exec_len,
1080 flags);
1081 if (ret)
1082 goto err;
1083 }
1084
1085 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1086
1087 i915_gem_execbuffer_move_to_active(&eb->objects, ring);
1088 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1089
1090 err:
1091 eb_destroy(eb);
1092
1093 mutex_unlock(&dev->struct_mutex);
1094
1095 pre_mutex_err:
1096 kfree(cliprects);
1097 return ret;
1098 }
1099
1100 /*
1101 * Legacy execbuffer just creates an exec2 list from the original exec object
1102 * list array and passes it to the real function.
1103 */
1104 int
1105 i915_gem_execbuffer(struct drm_device *dev, void *data,
1106 struct drm_file *file)
1107 {
1108 struct drm_i915_gem_execbuffer *args = data;
1109 struct drm_i915_gem_execbuffer2 exec2;
1110 struct drm_i915_gem_exec_object *exec_list = NULL;
1111 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1112 int ret, i;
1113
1114 if (args->buffer_count < 1) {
1115 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1116 return -EINVAL;
1117 }
1118
1119 /* Copy in the exec list from userland */
1120 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1121 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1122 if (exec_list == NULL || exec2_list == NULL) {
1123 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1124 args->buffer_count);
1125 drm_free_large(exec_list);
1126 drm_free_large(exec2_list);
1127 return -ENOMEM;
1128 }
1129 ret = copy_from_user(exec_list,
1130 to_user_ptr(args->buffers_ptr),
1131 sizeof(*exec_list) * args->buffer_count);
1132 if (ret != 0) {
1133 DRM_DEBUG("copy %d exec entries failed %d\n",
1134 args->buffer_count, ret);
1135 drm_free_large(exec_list);
1136 drm_free_large(exec2_list);
1137 return -EFAULT;
1138 }
1139
1140 for (i = 0; i < args->buffer_count; i++) {
1141 exec2_list[i].handle = exec_list[i].handle;
1142 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1143 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1144 exec2_list[i].alignment = exec_list[i].alignment;
1145 exec2_list[i].offset = exec_list[i].offset;
1146 if (INTEL_INFO(dev)->gen < 4)
1147 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1148 else
1149 exec2_list[i].flags = 0;
1150 }
1151
1152 exec2.buffers_ptr = args->buffers_ptr;
1153 exec2.buffer_count = args->buffer_count;
1154 exec2.batch_start_offset = args->batch_start_offset;
1155 exec2.batch_len = args->batch_len;
1156 exec2.DR1 = args->DR1;
1157 exec2.DR4 = args->DR4;
1158 exec2.num_cliprects = args->num_cliprects;
1159 exec2.cliprects_ptr = args->cliprects_ptr;
1160 exec2.flags = I915_EXEC_RENDER;
1161 i915_execbuffer2_set_context_id(exec2, 0);
1162
1163 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1164 if (!ret) {
1165 /* Copy the new buffer offsets back to the user's exec list. */
1166 for (i = 0; i < args->buffer_count; i++)
1167 exec_list[i].offset = exec2_list[i].offset;
1168 /* ... and back out to userspace */
1169 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1170 exec_list,
1171 sizeof(*exec_list) * args->buffer_count);
1172 if (ret) {
1173 ret = -EFAULT;
1174 DRM_DEBUG("failed to copy %d exec entries "
1175 "back to user (%d)\n",
1176 args->buffer_count, ret);
1177 }
1178 }
1179
1180 drm_free_large(exec_list);
1181 drm_free_large(exec2_list);
1182 return ret;
1183 }
1184
1185 int
1186 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1187 struct drm_file *file)
1188 {
1189 struct drm_i915_gem_execbuffer2 *args = data;
1190 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1191 int ret;
1192
1193 if (args->buffer_count < 1 ||
1194 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1195 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1196 return -EINVAL;
1197 }
1198
1199 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1200 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1201 if (exec2_list == NULL)
1202 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1203 args->buffer_count);
1204 if (exec2_list == NULL) {
1205 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1206 args->buffer_count);
1207 return -ENOMEM;
1208 }
1209 ret = copy_from_user(exec2_list,
1210 to_user_ptr(args->buffers_ptr),
1211 sizeof(*exec2_list) * args->buffer_count);
1212 if (ret != 0) {
1213 DRM_DEBUG("copy %d exec entries failed %d\n",
1214 args->buffer_count, ret);
1215 drm_free_large(exec2_list);
1216 return -EFAULT;
1217 }
1218
1219 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1220 if (!ret) {
1221 /* Copy the new buffer offsets back to the user's exec list. */
1222 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1223 exec2_list,
1224 sizeof(*exec2_list) * args->buffer_count);
1225 if (ret) {
1226 ret = -EFAULT;
1227 DRM_DEBUG("failed to copy %d exec entries "
1228 "back to user (%d)\n",
1229 args->buffer_count, ret);
1230 }
1231 }
1232
1233 drm_free_large(exec2_list);
1234 return ret;
1235 }
Linux kernel - Deliverables
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