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drm/i915/bdw: Support 64b relocations
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35
36 struct eb_vmas {
37 struct list_head vmas;
38 int and;
39 union {
40 struct i915_vma *lut[0];
41 struct hlist_head buckets[0];
42 };
43 };
44
45 static struct eb_vmas *
46 eb_create(struct drm_i915_gem_execbuffer2 *args, struct i915_address_space *vm)
47 {
48 struct eb_vmas *eb = NULL;
49
50 if (args->flags & I915_EXEC_HANDLE_LUT) {
51 unsigned size = args->buffer_count;
52 size *= sizeof(struct i915_vma *);
53 size += sizeof(struct eb_vmas);
54 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
55 }
56
57 if (eb == NULL) {
58 unsigned size = args->buffer_count;
59 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
60 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
61 while (count > 2*size)
62 count >>= 1;
63 eb = kzalloc(count*sizeof(struct hlist_head) +
64 sizeof(struct eb_vmas),
65 GFP_TEMPORARY);
66 if (eb == NULL)
67 return eb;
68
69 eb->and = count - 1;
70 } else
71 eb->and = -args->buffer_count;
72
73 INIT_LIST_HEAD(&eb->vmas);
74 return eb;
75 }
76
77 static void
78 eb_reset(struct eb_vmas *eb)
79 {
80 if (eb->and >= 0)
81 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
82 }
83
84 static int
85 eb_lookup_vmas(struct eb_vmas *eb,
86 struct drm_i915_gem_exec_object2 *exec,
87 const struct drm_i915_gem_execbuffer2 *args,
88 struct i915_address_space *vm,
89 struct drm_file *file)
90 {
91 struct drm_i915_gem_object *obj;
92 struct list_head objects;
93 int i, ret = 0;
94
95 INIT_LIST_HEAD(&objects);
96 spin_lock(&file->table_lock);
97 /* Grab a reference to the object and release the lock so we can lookup
98 * or create the VMA without using GFP_ATOMIC */
99 for (i = 0; i < args->buffer_count; i++) {
100 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
101 if (obj == NULL) {
102 spin_unlock(&file->table_lock);
103 DRM_DEBUG("Invalid object handle %d at index %d\n",
104 exec[i].handle, i);
105 ret = -ENOENT;
106 goto out;
107 }
108
109 if (!list_empty(&obj->obj_exec_link)) {
110 spin_unlock(&file->table_lock);
111 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
112 obj, exec[i].handle, i);
113 ret = -EINVAL;
114 goto out;
115 }
116
117 drm_gem_object_reference(&obj->base);
118 list_add_tail(&obj->obj_exec_link, &objects);
119 }
120 spin_unlock(&file->table_lock);
121
122 i = 0;
123 list_for_each_entry(obj, &objects, obj_exec_link) {
124 struct i915_vma *vma;
125
126 /*
127 * NOTE: We can leak any vmas created here when something fails
128 * later on. But that's no issue since vma_unbind can deal with
129 * vmas which are not actually bound. And since only
130 * lookup_or_create exists as an interface to get at the vma
131 * from the (obj, vm) we don't run the risk of creating
132 * duplicated vmas for the same vm.
133 */
134 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
135 if (IS_ERR(vma)) {
136 DRM_DEBUG("Failed to lookup VMA\n");
137 ret = PTR_ERR(vma);
138 goto out;
139 }
140
141 list_add_tail(&vma->exec_list, &eb->vmas);
142
143 vma->exec_entry = &exec[i];
144 if (eb->and < 0) {
145 eb->lut[i] = vma;
146 } else {
147 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
148 vma->exec_handle = handle;
149 hlist_add_head(&vma->exec_node,
150 &eb->buckets[handle & eb->and]);
151 }
152 ++i;
153 }
154
155
156 out:
157 while (!list_empty(&objects)) {
158 obj = list_first_entry(&objects,
159 struct drm_i915_gem_object,
160 obj_exec_link);
161 list_del_init(&obj->obj_exec_link);
162 if (ret)
163 drm_gem_object_unreference(&obj->base);
164 }
165 return ret;
166 }
167
168 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
169 {
170 if (eb->and < 0) {
171 if (handle >= -eb->and)
172 return NULL;
173 return eb->lut[handle];
174 } else {
175 struct hlist_head *head;
176 struct hlist_node *node;
177
178 head = &eb->buckets[handle & eb->and];
179 hlist_for_each(node, head) {
180 struct i915_vma *vma;
181
182 vma = hlist_entry(node, struct i915_vma, exec_node);
183 if (vma->exec_handle == handle)
184 return vma;
185 }
186 return NULL;
187 }
188 }
189
190 static void eb_destroy(struct eb_vmas *eb) {
191 while (!list_empty(&eb->vmas)) {
192 struct i915_vma *vma;
193
194 vma = list_first_entry(&eb->vmas,
195 struct i915_vma,
196 exec_list);
197 list_del_init(&vma->exec_list);
198 drm_gem_object_unreference(&vma->obj->base);
199 }
200 kfree(eb);
201 }
202
203 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
204 {
205 return (HAS_LLC(obj->base.dev) ||
206 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
207 !obj->map_and_fenceable ||
208 obj->cache_level != I915_CACHE_NONE);
209 }
210
211 static int
212 relocate_entry_cpu(struct drm_i915_gem_object *obj,
213 struct drm_i915_gem_relocation_entry *reloc)
214 {
215 struct drm_device *dev = obj->base.dev;
216 uint32_t page_offset = offset_in_page(reloc->offset);
217 char *vaddr;
218 int ret = -EINVAL;
219
220 ret = i915_gem_object_set_to_cpu_domain(obj, true);
221 if (ret)
222 return ret;
223
224 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
225 reloc->offset >> PAGE_SHIFT));
226 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
227
228 if (INTEL_INFO(dev)->gen >= 8) {
229 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
230
231 if (page_offset == 0) {
232 kunmap_atomic(vaddr);
233 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
234 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
235 }
236
237 *(uint32_t *)(vaddr + page_offset) = 0;
238 }
239
240 kunmap_atomic(vaddr);
241
242 return 0;
243 }
244
245 static int
246 relocate_entry_gtt(struct drm_i915_gem_object *obj,
247 struct drm_i915_gem_relocation_entry *reloc)
248 {
249 struct drm_device *dev = obj->base.dev;
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 uint32_t __iomem *reloc_entry;
252 void __iomem *reloc_page;
253 int ret = -EINVAL;
254
255 ret = i915_gem_object_set_to_gtt_domain(obj, true);
256 if (ret)
257 return ret;
258
259 ret = i915_gem_object_put_fence(obj);
260 if (ret)
261 return ret;
262
263 /* Map the page containing the relocation we're going to perform. */
264 reloc->offset += i915_gem_obj_ggtt_offset(obj);
265 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
266 reloc->offset & PAGE_MASK);
267 reloc_entry = (uint32_t __iomem *)
268 (reloc_page + offset_in_page(reloc->offset));
269 iowrite32(reloc->delta, reloc_entry);
270
271 if (INTEL_INFO(dev)->gen >= 8) {
272 reloc_entry += 1;
273
274 if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) {
275 io_mapping_unmap_atomic(reloc_page);
276 reloc_page = io_mapping_map_atomic_wc(
277 dev_priv->gtt.mappable,
278 reloc->offset + sizeof(uint32_t));
279 reloc_entry = reloc_page;
280 }
281
282 iowrite32(0, reloc_entry);
283 }
284
285 io_mapping_unmap_atomic(reloc_page);
286
287 return 0;
288 }
289
290 static int
291 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
292 struct eb_vmas *eb,
293 struct drm_i915_gem_relocation_entry *reloc,
294 struct i915_address_space *vm)
295 {
296 struct drm_device *dev = obj->base.dev;
297 struct drm_gem_object *target_obj;
298 struct drm_i915_gem_object *target_i915_obj;
299 struct i915_vma *target_vma;
300 uint32_t target_offset;
301 int ret = -EINVAL;
302
303 /* we've already hold a reference to all valid objects */
304 target_vma = eb_get_vma(eb, reloc->target_handle);
305 if (unlikely(target_vma == NULL))
306 return -ENOENT;
307 target_i915_obj = target_vma->obj;
308 target_obj = &target_vma->obj->base;
309
310 target_offset = i915_gem_obj_ggtt_offset(target_i915_obj);
311
312 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
313 * pipe_control writes because the gpu doesn't properly redirect them
314 * through the ppgtt for non_secure batchbuffers. */
315 if (unlikely(IS_GEN6(dev) &&
316 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
317 !target_i915_obj->has_global_gtt_mapping)) {
318 i915_gem_gtt_bind_object(target_i915_obj,
319 target_i915_obj->cache_level);
320 }
321
322 /* Validate that the target is in a valid r/w GPU domain */
323 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
324 DRM_DEBUG("reloc with multiple write domains: "
325 "obj %p target %d offset %d "
326 "read %08x write %08x",
327 obj, reloc->target_handle,
328 (int) reloc->offset,
329 reloc->read_domains,
330 reloc->write_domain);
331 return ret;
332 }
333 if (unlikely((reloc->write_domain | reloc->read_domains)
334 & ~I915_GEM_GPU_DOMAINS)) {
335 DRM_DEBUG("reloc with read/write non-GPU domains: "
336 "obj %p target %d offset %d "
337 "read %08x write %08x",
338 obj, reloc->target_handle,
339 (int) reloc->offset,
340 reloc->read_domains,
341 reloc->write_domain);
342 return ret;
343 }
344
345 target_obj->pending_read_domains |= reloc->read_domains;
346 target_obj->pending_write_domain |= reloc->write_domain;
347
348 /* If the relocation already has the right value in it, no
349 * more work needs to be done.
350 */
351 if (target_offset == reloc->presumed_offset)
352 return 0;
353
354 /* Check that the relocation address is valid... */
355 if (unlikely(reloc->offset >
356 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
357 DRM_DEBUG("Relocation beyond object bounds: "
358 "obj %p target %d offset %d size %d.\n",
359 obj, reloc->target_handle,
360 (int) reloc->offset,
361 (int) obj->base.size);
362 return ret;
363 }
364 if (unlikely(reloc->offset & 3)) {
365 DRM_DEBUG("Relocation not 4-byte aligned: "
366 "obj %p target %d offset %d.\n",
367 obj, reloc->target_handle,
368 (int) reloc->offset);
369 return ret;
370 }
371
372 /* We can't wait for rendering with pagefaults disabled */
373 if (obj->active && in_atomic())
374 return -EFAULT;
375
376 reloc->delta += target_offset;
377 if (use_cpu_reloc(obj))
378 ret = relocate_entry_cpu(obj, reloc);
379 else
380 ret = relocate_entry_gtt(obj, reloc);
381
382 if (ret)
383 return ret;
384
385 /* and update the user's relocation entry */
386 reloc->presumed_offset = target_offset;
387
388 return 0;
389 }
390
391 static int
392 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
393 struct eb_vmas *eb)
394 {
395 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
396 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
397 struct drm_i915_gem_relocation_entry __user *user_relocs;
398 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
399 int remain, ret;
400
401 user_relocs = to_user_ptr(entry->relocs_ptr);
402
403 remain = entry->relocation_count;
404 while (remain) {
405 struct drm_i915_gem_relocation_entry *r = stack_reloc;
406 int count = remain;
407 if (count > ARRAY_SIZE(stack_reloc))
408 count = ARRAY_SIZE(stack_reloc);
409 remain -= count;
410
411 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
412 return -EFAULT;
413
414 do {
415 u64 offset = r->presumed_offset;
416
417 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r,
418 vma->vm);
419 if (ret)
420 return ret;
421
422 if (r->presumed_offset != offset &&
423 __copy_to_user_inatomic(&user_relocs->presumed_offset,
424 &r->presumed_offset,
425 sizeof(r->presumed_offset))) {
426 return -EFAULT;
427 }
428
429 user_relocs++;
430 r++;
431 } while (--count);
432 }
433
434 return 0;
435 #undef N_RELOC
436 }
437
438 static int
439 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
440 struct eb_vmas *eb,
441 struct drm_i915_gem_relocation_entry *relocs)
442 {
443 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
444 int i, ret;
445
446 for (i = 0; i < entry->relocation_count; i++) {
447 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i],
448 vma->vm);
449 if (ret)
450 return ret;
451 }
452
453 return 0;
454 }
455
456 static int
457 i915_gem_execbuffer_relocate(struct eb_vmas *eb,
458 struct i915_address_space *vm)
459 {
460 struct i915_vma *vma;
461 int ret = 0;
462
463 /* This is the fast path and we cannot handle a pagefault whilst
464 * holding the struct mutex lest the user pass in the relocations
465 * contained within a mmaped bo. For in such a case we, the page
466 * fault handler would call i915_gem_fault() and we would try to
467 * acquire the struct mutex again. Obviously this is bad and so
468 * lockdep complains vehemently.
469 */
470 pagefault_disable();
471 list_for_each_entry(vma, &eb->vmas, exec_list) {
472 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
473 if (ret)
474 break;
475 }
476 pagefault_enable();
477
478 return ret;
479 }
480
481 #define __EXEC_OBJECT_HAS_PIN (1<<31)
482 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
483
484 static int
485 need_reloc_mappable(struct i915_vma *vma)
486 {
487 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
488 return entry->relocation_count && !use_cpu_reloc(vma->obj) &&
489 i915_is_ggtt(vma->vm);
490 }
491
492 static int
493 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
494 struct intel_ring_buffer *ring,
495 bool *need_reloc)
496 {
497 struct drm_i915_private *dev_priv = ring->dev->dev_private;
498 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
499 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
500 bool need_fence, need_mappable;
501 struct drm_i915_gem_object *obj = vma->obj;
502 int ret;
503
504 need_fence =
505 has_fenced_gpu_access &&
506 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
507 obj->tiling_mode != I915_TILING_NONE;
508 need_mappable = need_fence || need_reloc_mappable(vma);
509
510 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable,
511 false);
512 if (ret)
513 return ret;
514
515 entry->flags |= __EXEC_OBJECT_HAS_PIN;
516
517 if (has_fenced_gpu_access) {
518 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
519 ret = i915_gem_object_get_fence(obj);
520 if (ret)
521 return ret;
522
523 if (i915_gem_object_pin_fence(obj))
524 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
525
526 obj->pending_fenced_gpu_access = true;
527 }
528 }
529
530 /* Ensure ppgtt mapping exists if needed */
531 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
532 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
533 obj, obj->cache_level);
534
535 obj->has_aliasing_ppgtt_mapping = 1;
536 }
537
538 if (entry->offset != vma->node.start) {
539 entry->offset = vma->node.start;
540 *need_reloc = true;
541 }
542
543 if (entry->flags & EXEC_OBJECT_WRITE) {
544 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
545 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
546 }
547
548 if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
549 !obj->has_global_gtt_mapping)
550 i915_gem_gtt_bind_object(obj, obj->cache_level);
551
552 return 0;
553 }
554
555 static void
556 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
557 {
558 struct drm_i915_gem_exec_object2 *entry;
559 struct drm_i915_gem_object *obj = vma->obj;
560
561 if (!drm_mm_node_allocated(&vma->node))
562 return;
563
564 entry = vma->exec_entry;
565
566 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
567 i915_gem_object_unpin_fence(obj);
568
569 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
570 i915_gem_object_unpin(obj);
571
572 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
573 }
574
575 static int
576 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
577 struct list_head *vmas,
578 bool *need_relocs)
579 {
580 struct drm_i915_gem_object *obj;
581 struct i915_vma *vma;
582 struct i915_address_space *vm;
583 struct list_head ordered_vmas;
584 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
585 int retry;
586
587 if (list_empty(vmas))
588 return 0;
589
590 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
591
592 INIT_LIST_HEAD(&ordered_vmas);
593 while (!list_empty(vmas)) {
594 struct drm_i915_gem_exec_object2 *entry;
595 bool need_fence, need_mappable;
596
597 vma = list_first_entry(vmas, struct i915_vma, exec_list);
598 obj = vma->obj;
599 entry = vma->exec_entry;
600
601 need_fence =
602 has_fenced_gpu_access &&
603 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
604 obj->tiling_mode != I915_TILING_NONE;
605 need_mappable = need_fence || need_reloc_mappable(vma);
606
607 if (need_mappable)
608 list_move(&vma->exec_list, &ordered_vmas);
609 else
610 list_move_tail(&vma->exec_list, &ordered_vmas);
611
612 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
613 obj->base.pending_write_domain = 0;
614 obj->pending_fenced_gpu_access = false;
615 }
616 list_splice(&ordered_vmas, vmas);
617
618 /* Attempt to pin all of the buffers into the GTT.
619 * This is done in 3 phases:
620 *
621 * 1a. Unbind all objects that do not match the GTT constraints for
622 * the execbuffer (fenceable, mappable, alignment etc).
623 * 1b. Increment pin count for already bound objects.
624 * 2. Bind new objects.
625 * 3. Decrement pin count.
626 *
627 * This avoid unnecessary unbinding of later objects in order to make
628 * room for the earlier objects *unless* we need to defragment.
629 */
630 retry = 0;
631 do {
632 int ret = 0;
633
634 /* Unbind any ill-fitting objects or pin. */
635 list_for_each_entry(vma, vmas, exec_list) {
636 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
637 bool need_fence, need_mappable;
638
639 obj = vma->obj;
640
641 if (!drm_mm_node_allocated(&vma->node))
642 continue;
643
644 need_fence =
645 has_fenced_gpu_access &&
646 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
647 obj->tiling_mode != I915_TILING_NONE;
648 need_mappable = need_fence || need_reloc_mappable(vma);
649
650 WARN_ON((need_mappable || need_fence) &&
651 !i915_is_ggtt(vma->vm));
652
653 if ((entry->alignment &&
654 vma->node.start & (entry->alignment - 1)) ||
655 (need_mappable && !obj->map_and_fenceable))
656 ret = i915_vma_unbind(vma);
657 else
658 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
659 if (ret)
660 goto err;
661 }
662
663 /* Bind fresh objects */
664 list_for_each_entry(vma, vmas, exec_list) {
665 if (drm_mm_node_allocated(&vma->node))
666 continue;
667
668 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
669 if (ret)
670 goto err;
671 }
672
673 err: /* Decrement pin count for bound objects */
674 list_for_each_entry(vma, vmas, exec_list)
675 i915_gem_execbuffer_unreserve_vma(vma);
676
677 if (ret != -ENOSPC || retry++)
678 return ret;
679
680 ret = i915_gem_evict_vm(vm, true);
681 if (ret)
682 return ret;
683 } while (1);
684 }
685
686 static int
687 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
688 struct drm_i915_gem_execbuffer2 *args,
689 struct drm_file *file,
690 struct intel_ring_buffer *ring,
691 struct eb_vmas *eb,
692 struct drm_i915_gem_exec_object2 *exec)
693 {
694 struct drm_i915_gem_relocation_entry *reloc;
695 struct i915_address_space *vm;
696 struct i915_vma *vma;
697 bool need_relocs;
698 int *reloc_offset;
699 int i, total, ret;
700 unsigned count = args->buffer_count;
701
702 if (WARN_ON(list_empty(&eb->vmas)))
703 return 0;
704
705 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
706
707 /* We may process another execbuffer during the unlock... */
708 while (!list_empty(&eb->vmas)) {
709 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
710 list_del_init(&vma->exec_list);
711 drm_gem_object_unreference(&vma->obj->base);
712 }
713
714 mutex_unlock(&dev->struct_mutex);
715
716 total = 0;
717 for (i = 0; i < count; i++)
718 total += exec[i].relocation_count;
719
720 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
721 reloc = drm_malloc_ab(total, sizeof(*reloc));
722 if (reloc == NULL || reloc_offset == NULL) {
723 drm_free_large(reloc);
724 drm_free_large(reloc_offset);
725 mutex_lock(&dev->struct_mutex);
726 return -ENOMEM;
727 }
728
729 total = 0;
730 for (i = 0; i < count; i++) {
731 struct drm_i915_gem_relocation_entry __user *user_relocs;
732 u64 invalid_offset = (u64)-1;
733 int j;
734
735 user_relocs = to_user_ptr(exec[i].relocs_ptr);
736
737 if (copy_from_user(reloc+total, user_relocs,
738 exec[i].relocation_count * sizeof(*reloc))) {
739 ret = -EFAULT;
740 mutex_lock(&dev->struct_mutex);
741 goto err;
742 }
743
744 /* As we do not update the known relocation offsets after
745 * relocating (due to the complexities in lock handling),
746 * we need to mark them as invalid now so that we force the
747 * relocation processing next time. Just in case the target
748 * object is evicted and then rebound into its old
749 * presumed_offset before the next execbuffer - if that
750 * happened we would make the mistake of assuming that the
751 * relocations were valid.
752 */
753 for (j = 0; j < exec[i].relocation_count; j++) {
754 if (copy_to_user(&user_relocs[j].presumed_offset,
755 &invalid_offset,
756 sizeof(invalid_offset))) {
757 ret = -EFAULT;
758 mutex_lock(&dev->struct_mutex);
759 goto err;
760 }
761 }
762
763 reloc_offset[i] = total;
764 total += exec[i].relocation_count;
765 }
766
767 ret = i915_mutex_lock_interruptible(dev);
768 if (ret) {
769 mutex_lock(&dev->struct_mutex);
770 goto err;
771 }
772
773 /* reacquire the objects */
774 eb_reset(eb);
775 ret = eb_lookup_vmas(eb, exec, args, vm, file);
776 if (ret)
777 goto err;
778
779 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
780 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
781 if (ret)
782 goto err;
783
784 list_for_each_entry(vma, &eb->vmas, exec_list) {
785 int offset = vma->exec_entry - exec;
786 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
787 reloc + reloc_offset[offset]);
788 if (ret)
789 goto err;
790 }
791
792 /* Leave the user relocations as are, this is the painfully slow path,
793 * and we want to avoid the complication of dropping the lock whilst
794 * having buffers reserved in the aperture and so causing spurious
795 * ENOSPC for random operations.
796 */
797
798 err:
799 drm_free_large(reloc);
800 drm_free_large(reloc_offset);
801 return ret;
802 }
803
804 static int
805 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
806 struct list_head *vmas)
807 {
808 struct i915_vma *vma;
809 uint32_t flush_domains = 0;
810 bool flush_chipset = false;
811 int ret;
812
813 list_for_each_entry(vma, vmas, exec_list) {
814 struct drm_i915_gem_object *obj = vma->obj;
815 ret = i915_gem_object_sync(obj, ring);
816 if (ret)
817 return ret;
818
819 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
820 flush_chipset |= i915_gem_clflush_object(obj, false);
821
822 flush_domains |= obj->base.write_domain;
823 }
824
825 if (flush_chipset)
826 i915_gem_chipset_flush(ring->dev);
827
828 if (flush_domains & I915_GEM_DOMAIN_GTT)
829 wmb();
830
831 /* Unconditionally invalidate gpu caches and ensure that we do flush
832 * any residual writes from the previous batch.
833 */
834 return intel_ring_invalidate_all_caches(ring);
835 }
836
837 static bool
838 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
839 {
840 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
841 return false;
842
843 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
844 }
845
846 static int
847 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
848 int count)
849 {
850 int i;
851 unsigned relocs_total = 0;
852 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
853
854 for (i = 0; i < count; i++) {
855 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
856 int length; /* limited by fault_in_pages_readable() */
857
858 if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
859 return -EINVAL;
860
861 /* First check for malicious input causing overflow in
862 * the worst case where we need to allocate the entire
863 * relocation tree as a single array.
864 */
865 if (exec[i].relocation_count > relocs_max - relocs_total)
866 return -EINVAL;
867 relocs_total += exec[i].relocation_count;
868
869 length = exec[i].relocation_count *
870 sizeof(struct drm_i915_gem_relocation_entry);
871 /*
872 * We must check that the entire relocation array is safe
873 * to read, but since we may need to update the presumed
874 * offsets during execution, check for full write access.
875 */
876 if (!access_ok(VERIFY_WRITE, ptr, length))
877 return -EFAULT;
878
879 if (likely(!i915_prefault_disable)) {
880 if (fault_in_multipages_readable(ptr, length))
881 return -EFAULT;
882 }
883 }
884
885 return 0;
886 }
887
888 static void
889 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
890 struct intel_ring_buffer *ring)
891 {
892 struct i915_vma *vma;
893
894 list_for_each_entry(vma, vmas, exec_list) {
895 struct drm_i915_gem_object *obj = vma->obj;
896 u32 old_read = obj->base.read_domains;
897 u32 old_write = obj->base.write_domain;
898
899 obj->base.write_domain = obj->base.pending_write_domain;
900 if (obj->base.write_domain == 0)
901 obj->base.pending_read_domains |= obj->base.read_domains;
902 obj->base.read_domains = obj->base.pending_read_domains;
903 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
904
905 i915_vma_move_to_active(vma, ring);
906 if (obj->base.write_domain) {
907 obj->dirty = 1;
908 obj->last_write_seqno = intel_ring_get_seqno(ring);
909 if (obj->pin_count) /* check for potential scanout */
910 intel_mark_fb_busy(obj, ring);
911 }
912
913 trace_i915_gem_object_change_domain(obj, old_read, old_write);
914 }
915 }
916
917 static void
918 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
919 struct drm_file *file,
920 struct intel_ring_buffer *ring,
921 struct drm_i915_gem_object *obj)
922 {
923 /* Unconditionally force add_request to emit a full flush. */
924 ring->gpu_caches_dirty = true;
925
926 /* Add a breadcrumb for the completion of the batch buffer */
927 (void)__i915_add_request(ring, file, obj, NULL);
928 }
929
930 static int
931 i915_reset_gen7_sol_offsets(struct drm_device *dev,
932 struct intel_ring_buffer *ring)
933 {
934 drm_i915_private_t *dev_priv = dev->dev_private;
935 int ret, i;
936
937 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
938 return 0;
939
940 ret = intel_ring_begin(ring, 4 * 3);
941 if (ret)
942 return ret;
943
944 for (i = 0; i < 4; i++) {
945 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
946 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
947 intel_ring_emit(ring, 0);
948 }
949
950 intel_ring_advance(ring);
951
952 return 0;
953 }
954
955 static int
956 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
957 struct drm_file *file,
958 struct drm_i915_gem_execbuffer2 *args,
959 struct drm_i915_gem_exec_object2 *exec,
960 struct i915_address_space *vm)
961 {
962 drm_i915_private_t *dev_priv = dev->dev_private;
963 struct eb_vmas *eb;
964 struct drm_i915_gem_object *batch_obj;
965 struct drm_clip_rect *cliprects = NULL;
966 struct intel_ring_buffer *ring;
967 struct i915_ctx_hang_stats *hs;
968 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
969 u32 exec_start, exec_len;
970 u32 mask, flags;
971 int ret, mode, i;
972 bool need_relocs;
973
974 if (!i915_gem_check_execbuffer(args))
975 return -EINVAL;
976
977 ret = validate_exec_list(exec, args->buffer_count);
978 if (ret)
979 return ret;
980
981 flags = 0;
982 if (args->flags & I915_EXEC_SECURE) {
983 if (!file->is_master || !capable(CAP_SYS_ADMIN))
984 return -EPERM;
985
986 flags |= I915_DISPATCH_SECURE;
987 }
988 if (args->flags & I915_EXEC_IS_PINNED)
989 flags |= I915_DISPATCH_PINNED;
990
991 switch (args->flags & I915_EXEC_RING_MASK) {
992 case I915_EXEC_DEFAULT:
993 case I915_EXEC_RENDER:
994 ring = &dev_priv->ring[RCS];
995 break;
996 case I915_EXEC_BSD:
997 ring = &dev_priv->ring[VCS];
998 if (ctx_id != DEFAULT_CONTEXT_ID) {
999 DRM_DEBUG("Ring %s doesn't support contexts\n",
1000 ring->name);
1001 return -EPERM;
1002 }
1003 break;
1004 case I915_EXEC_BLT:
1005 ring = &dev_priv->ring[BCS];
1006 if (ctx_id != DEFAULT_CONTEXT_ID) {
1007 DRM_DEBUG("Ring %s doesn't support contexts\n",
1008 ring->name);
1009 return -EPERM;
1010 }
1011 break;
1012 case I915_EXEC_VEBOX:
1013 ring = &dev_priv->ring[VECS];
1014 if (ctx_id != DEFAULT_CONTEXT_ID) {
1015 DRM_DEBUG("Ring %s doesn't support contexts\n",
1016 ring->name);
1017 return -EPERM;
1018 }
1019 break;
1020
1021 default:
1022 DRM_DEBUG("execbuf with unknown ring: %d\n",
1023 (int)(args->flags & I915_EXEC_RING_MASK));
1024 return -EINVAL;
1025 }
1026 if (!intel_ring_initialized(ring)) {
1027 DRM_DEBUG("execbuf with invalid ring: %d\n",
1028 (int)(args->flags & I915_EXEC_RING_MASK));
1029 return -EINVAL;
1030 }
1031
1032 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1033 mask = I915_EXEC_CONSTANTS_MASK;
1034 switch (mode) {
1035 case I915_EXEC_CONSTANTS_REL_GENERAL:
1036 case I915_EXEC_CONSTANTS_ABSOLUTE:
1037 case I915_EXEC_CONSTANTS_REL_SURFACE:
1038 if (ring == &dev_priv->ring[RCS] &&
1039 mode != dev_priv->relative_constants_mode) {
1040 if (INTEL_INFO(dev)->gen < 4)
1041 return -EINVAL;
1042
1043 if (INTEL_INFO(dev)->gen > 5 &&
1044 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1045 return -EINVAL;
1046
1047 /* The HW changed the meaning on this bit on gen6 */
1048 if (INTEL_INFO(dev)->gen >= 6)
1049 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1050 }
1051 break;
1052 default:
1053 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1054 return -EINVAL;
1055 }
1056
1057 if (args->buffer_count < 1) {
1058 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1059 return -EINVAL;
1060 }
1061
1062 if (args->num_cliprects != 0) {
1063 if (ring != &dev_priv->ring[RCS]) {
1064 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1065 return -EINVAL;
1066 }
1067
1068 if (INTEL_INFO(dev)->gen >= 5) {
1069 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1070 return -EINVAL;
1071 }
1072
1073 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1074 DRM_DEBUG("execbuf with %u cliprects\n",
1075 args->num_cliprects);
1076 return -EINVAL;
1077 }
1078
1079 cliprects = kcalloc(args->num_cliprects,
1080 sizeof(*cliprects),
1081 GFP_KERNEL);
1082 if (cliprects == NULL) {
1083 ret = -ENOMEM;
1084 goto pre_mutex_err;
1085 }
1086
1087 if (copy_from_user(cliprects,
1088 to_user_ptr(args->cliprects_ptr),
1089 sizeof(*cliprects)*args->num_cliprects)) {
1090 ret = -EFAULT;
1091 goto pre_mutex_err;
1092 }
1093 }
1094
1095 ret = i915_mutex_lock_interruptible(dev);
1096 if (ret)
1097 goto pre_mutex_err;
1098
1099 if (dev_priv->ums.mm_suspended) {
1100 mutex_unlock(&dev->struct_mutex);
1101 ret = -EBUSY;
1102 goto pre_mutex_err;
1103 }
1104
1105 eb = eb_create(args, vm);
1106 if (eb == NULL) {
1107 mutex_unlock(&dev->struct_mutex);
1108 ret = -ENOMEM;
1109 goto pre_mutex_err;
1110 }
1111
1112 /* Look up object handles */
1113 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1114 if (ret)
1115 goto err;
1116
1117 /* take note of the batch buffer before we might reorder the lists */
1118 batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj;
1119
1120 /* Move the objects en-masse into the GTT, evicting if necessary. */
1121 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1122 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
1123 if (ret)
1124 goto err;
1125
1126 /* The objects are in their final locations, apply the relocations. */
1127 if (need_relocs)
1128 ret = i915_gem_execbuffer_relocate(eb, vm);
1129 if (ret) {
1130 if (ret == -EFAULT) {
1131 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1132 eb, exec);
1133 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1134 }
1135 if (ret)
1136 goto err;
1137 }
1138
1139 /* Set the pending read domains for the batch buffer to COMMAND */
1140 if (batch_obj->base.pending_write_domain) {
1141 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1142 ret = -EINVAL;
1143 goto err;
1144 }
1145 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1146
1147 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1148 * batch" bit. Hence we need to pin secure batches into the global gtt.
1149 * hsw should have this fixed, but let's be paranoid and do it
1150 * unconditionally for now. */
1151 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
1152 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
1153
1154 ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas);
1155 if (ret)
1156 goto err;
1157
1158 hs = i915_gem_context_get_hang_stats(dev, file, ctx_id);
1159 if (IS_ERR(hs)) {
1160 ret = PTR_ERR(hs);
1161 goto err;
1162 }
1163
1164 if (hs->banned) {
1165 ret = -EIO;
1166 goto err;
1167 }
1168
1169 ret = i915_switch_context(ring, file, ctx_id);
1170 if (ret)
1171 goto err;
1172
1173 if (ring == &dev_priv->ring[RCS] &&
1174 mode != dev_priv->relative_constants_mode) {
1175 ret = intel_ring_begin(ring, 4);
1176 if (ret)
1177 goto err;
1178
1179 intel_ring_emit(ring, MI_NOOP);
1180 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1181 intel_ring_emit(ring, INSTPM);
1182 intel_ring_emit(ring, mask << 16 | mode);
1183 intel_ring_advance(ring);
1184
1185 dev_priv->relative_constants_mode = mode;
1186 }
1187
1188 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1189 ret = i915_reset_gen7_sol_offsets(dev, ring);
1190 if (ret)
1191 goto err;
1192 }
1193
1194 exec_start = i915_gem_obj_offset(batch_obj, vm) +
1195 args->batch_start_offset;
1196 exec_len = args->batch_len;
1197 if (cliprects) {
1198 for (i = 0; i < args->num_cliprects; i++) {
1199 ret = i915_emit_box(dev, &cliprects[i],
1200 args->DR1, args->DR4);
1201 if (ret)
1202 goto err;
1203
1204 ret = ring->dispatch_execbuffer(ring,
1205 exec_start, exec_len,
1206 flags);
1207 if (ret)
1208 goto err;
1209 }
1210 } else {
1211 ret = ring->dispatch_execbuffer(ring,
1212 exec_start, exec_len,
1213 flags);
1214 if (ret)
1215 goto err;
1216 }
1217
1218 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1219
1220 i915_gem_execbuffer_move_to_active(&eb->vmas, ring);
1221 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1222
1223 err:
1224 eb_destroy(eb);
1225
1226 mutex_unlock(&dev->struct_mutex);
1227
1228 pre_mutex_err:
1229 kfree(cliprects);
1230 return ret;
1231 }
1232
1233 /*
1234 * Legacy execbuffer just creates an exec2 list from the original exec object
1235 * list array and passes it to the real function.
1236 */
1237 int
1238 i915_gem_execbuffer(struct drm_device *dev, void *data,
1239 struct drm_file *file)
1240 {
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 struct drm_i915_gem_execbuffer *args = data;
1243 struct drm_i915_gem_execbuffer2 exec2;
1244 struct drm_i915_gem_exec_object *exec_list = NULL;
1245 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1246 int ret, i;
1247
1248 if (args->buffer_count < 1) {
1249 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1250 return -EINVAL;
1251 }
1252
1253 /* Copy in the exec list from userland */
1254 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1255 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1256 if (exec_list == NULL || exec2_list == NULL) {
1257 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1258 args->buffer_count);
1259 drm_free_large(exec_list);
1260 drm_free_large(exec2_list);
1261 return -ENOMEM;
1262 }
1263 ret = copy_from_user(exec_list,
1264 to_user_ptr(args->buffers_ptr),
1265 sizeof(*exec_list) * args->buffer_count);
1266 if (ret != 0) {
1267 DRM_DEBUG("copy %d exec entries failed %d\n",
1268 args->buffer_count, ret);
1269 drm_free_large(exec_list);
1270 drm_free_large(exec2_list);
1271 return -EFAULT;
1272 }
1273
1274 for (i = 0; i < args->buffer_count; i++) {
1275 exec2_list[i].handle = exec_list[i].handle;
1276 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1277 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1278 exec2_list[i].alignment = exec_list[i].alignment;
1279 exec2_list[i].offset = exec_list[i].offset;
1280 if (INTEL_INFO(dev)->gen < 4)
1281 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1282 else
1283 exec2_list[i].flags = 0;
1284 }
1285
1286 exec2.buffers_ptr = args->buffers_ptr;
1287 exec2.buffer_count = args->buffer_count;
1288 exec2.batch_start_offset = args->batch_start_offset;
1289 exec2.batch_len = args->batch_len;
1290 exec2.DR1 = args->DR1;
1291 exec2.DR4 = args->DR4;
1292 exec2.num_cliprects = args->num_cliprects;
1293 exec2.cliprects_ptr = args->cliprects_ptr;
1294 exec2.flags = I915_EXEC_RENDER;
1295 i915_execbuffer2_set_context_id(exec2, 0);
1296
1297 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list,
1298 &dev_priv->gtt.base);
1299 if (!ret) {
1300 /* Copy the new buffer offsets back to the user's exec list. */
1301 for (i = 0; i < args->buffer_count; i++)
1302 exec_list[i].offset = exec2_list[i].offset;
1303 /* ... and back out to userspace */
1304 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1305 exec_list,
1306 sizeof(*exec_list) * args->buffer_count);
1307 if (ret) {
1308 ret = -EFAULT;
1309 DRM_DEBUG("failed to copy %d exec entries "
1310 "back to user (%d)\n",
1311 args->buffer_count, ret);
1312 }
1313 }
1314
1315 drm_free_large(exec_list);
1316 drm_free_large(exec2_list);
1317 return ret;
1318 }
1319
1320 int
1321 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1322 struct drm_file *file)
1323 {
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct drm_i915_gem_execbuffer2 *args = data;
1326 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1327 int ret;
1328
1329 if (args->buffer_count < 1 ||
1330 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1331 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1332 return -EINVAL;
1333 }
1334
1335 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1336 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1337 if (exec2_list == NULL)
1338 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1339 args->buffer_count);
1340 if (exec2_list == NULL) {
1341 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1342 args->buffer_count);
1343 return -ENOMEM;
1344 }
1345 ret = copy_from_user(exec2_list,
1346 to_user_ptr(args->buffers_ptr),
1347 sizeof(*exec2_list) * args->buffer_count);
1348 if (ret != 0) {
1349 DRM_DEBUG("copy %d exec entries failed %d\n",
1350 args->buffer_count, ret);
1351 drm_free_large(exec2_list);
1352 return -EFAULT;
1353 }
1354
1355 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list,
1356 &dev_priv->gtt.base);
1357 if (!ret) {
1358 /* Copy the new buffer offsets back to the user's exec list. */
1359 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1360 exec2_list,
1361 sizeof(*exec2_list) * args->buffer_count);
1362 if (ret) {
1363 ret = -EFAULT;
1364 DRM_DEBUG("failed to copy %d exec entries "
1365 "back to user (%d)\n",
1366 args->buffer_count, ret);
1367 }
1368 }
1369
1370 drm_free_large(exec2_list);
1371 return ret;
1372 }
Linux kernel - Deliverables
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