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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
40
41 #define BATCH_OFFSET_BIAS (256*1024)
42
43 struct eb_vmas {
44 struct list_head vmas;
45 int and;
46 union {
47 struct i915_vma *lut[0];
48 struct hlist_head buckets[0];
49 };
50 };
51
52 static struct eb_vmas *
53 eb_create(struct drm_i915_gem_execbuffer2 *args)
54 {
55 struct eb_vmas *eb = NULL;
56
57 if (args->flags & I915_EXEC_HANDLE_LUT) {
58 unsigned size = args->buffer_count;
59 size *= sizeof(struct i915_vma *);
60 size += sizeof(struct eb_vmas);
61 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
62 }
63
64 if (eb == NULL) {
65 unsigned size = args->buffer_count;
66 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
67 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
68 while (count > 2*size)
69 count >>= 1;
70 eb = kzalloc(count*sizeof(struct hlist_head) +
71 sizeof(struct eb_vmas),
72 GFP_TEMPORARY);
73 if (eb == NULL)
74 return eb;
75
76 eb->and = count - 1;
77 } else
78 eb->and = -args->buffer_count;
79
80 INIT_LIST_HEAD(&eb->vmas);
81 return eb;
82 }
83
84 static void
85 eb_reset(struct eb_vmas *eb)
86 {
87 if (eb->and >= 0)
88 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
89 }
90
91 static int
92 eb_lookup_vmas(struct eb_vmas *eb,
93 struct drm_i915_gem_exec_object2 *exec,
94 const struct drm_i915_gem_execbuffer2 *args,
95 struct i915_address_space *vm,
96 struct drm_file *file)
97 {
98 struct drm_i915_gem_object *obj;
99 struct list_head objects;
100 int i, ret;
101
102 INIT_LIST_HEAD(&objects);
103 spin_lock(&file->table_lock);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i = 0; i < args->buffer_count; i++) {
107 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
108 if (obj == NULL) {
109 spin_unlock(&file->table_lock);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
111 exec[i].handle, i);
112 ret = -ENOENT;
113 goto err;
114 }
115
116 if (!list_empty(&obj->obj_exec_link)) {
117 spin_unlock(&file->table_lock);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj, exec[i].handle, i);
120 ret = -EINVAL;
121 goto err;
122 }
123
124 drm_gem_object_reference(&obj->base);
125 list_add_tail(&obj->obj_exec_link, &objects);
126 }
127 spin_unlock(&file->table_lock);
128
129 i = 0;
130 while (!list_empty(&objects)) {
131 struct i915_vma *vma;
132
133 obj = list_first_entry(&objects,
134 struct drm_i915_gem_object,
135 obj_exec_link);
136
137 /*
138 * NOTE: We can leak any vmas created here when something fails
139 * later on. But that's no issue since vma_unbind can deal with
140 * vmas which are not actually bound. And since only
141 * lookup_or_create exists as an interface to get at the vma
142 * from the (obj, vm) we don't run the risk of creating
143 * duplicated vmas for the same vm.
144 */
145 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
146 if (IS_ERR(vma)) {
147 DRM_DEBUG("Failed to lookup VMA\n");
148 ret = PTR_ERR(vma);
149 goto err;
150 }
151
152 /* Transfer ownership from the objects list to the vmas list. */
153 list_add_tail(&vma->exec_list, &eb->vmas);
154 list_del_init(&obj->obj_exec_link);
155
156 vma->exec_entry = &exec[i];
157 if (eb->and < 0) {
158 eb->lut[i] = vma;
159 } else {
160 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
161 vma->exec_handle = handle;
162 hlist_add_head(&vma->exec_node,
163 &eb->buckets[handle & eb->and]);
164 }
165 ++i;
166 }
167
168 return 0;
169
170
171 err:
172 while (!list_empty(&objects)) {
173 obj = list_first_entry(&objects,
174 struct drm_i915_gem_object,
175 obj_exec_link);
176 list_del_init(&obj->obj_exec_link);
177 drm_gem_object_unreference(&obj->base);
178 }
179 /*
180 * Objects already transfered to the vmas list will be unreferenced by
181 * eb_destroy.
182 */
183
184 return ret;
185 }
186
187 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
188 {
189 if (eb->and < 0) {
190 if (handle >= -eb->and)
191 return NULL;
192 return eb->lut[handle];
193 } else {
194 struct hlist_head *head;
195 struct hlist_node *node;
196
197 head = &eb->buckets[handle & eb->and];
198 hlist_for_each(node, head) {
199 struct i915_vma *vma;
200
201 vma = hlist_entry(node, struct i915_vma, exec_node);
202 if (vma->exec_handle == handle)
203 return vma;
204 }
205 return NULL;
206 }
207 }
208
209 static void
210 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
211 {
212 struct drm_i915_gem_exec_object2 *entry;
213 struct drm_i915_gem_object *obj = vma->obj;
214
215 if (!drm_mm_node_allocated(&vma->node))
216 return;
217
218 entry = vma->exec_entry;
219
220 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
221 i915_gem_object_unpin_fence(obj);
222
223 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
224 vma->pin_count--;
225
226 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
227 }
228
229 static void eb_destroy(struct eb_vmas *eb)
230 {
231 while (!list_empty(&eb->vmas)) {
232 struct i915_vma *vma;
233
234 vma = list_first_entry(&eb->vmas,
235 struct i915_vma,
236 exec_list);
237 list_del_init(&vma->exec_list);
238 i915_gem_execbuffer_unreserve_vma(vma);
239 drm_gem_object_unreference(&vma->obj->base);
240 }
241 kfree(eb);
242 }
243
244 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
245 {
246 return (HAS_LLC(obj->base.dev) ||
247 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
248 obj->cache_level != I915_CACHE_NONE);
249 }
250
251 static int
252 relocate_entry_cpu(struct drm_i915_gem_object *obj,
253 struct drm_i915_gem_relocation_entry *reloc,
254 uint64_t target_offset)
255 {
256 struct drm_device *dev = obj->base.dev;
257 uint32_t page_offset = offset_in_page(reloc->offset);
258 uint64_t delta = reloc->delta + target_offset;
259 char *vaddr;
260 int ret;
261
262 ret = i915_gem_object_set_to_cpu_domain(obj, true);
263 if (ret)
264 return ret;
265
266 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
267 reloc->offset >> PAGE_SHIFT));
268 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
269
270 if (INTEL_INFO(dev)->gen >= 8) {
271 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
272
273 if (page_offset == 0) {
274 kunmap_atomic(vaddr);
275 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
276 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
277 }
278
279 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
280 }
281
282 kunmap_atomic(vaddr);
283
284 return 0;
285 }
286
287 static int
288 relocate_entry_gtt(struct drm_i915_gem_object *obj,
289 struct drm_i915_gem_relocation_entry *reloc,
290 uint64_t target_offset)
291 {
292 struct drm_device *dev = obj->base.dev;
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 uint64_t delta = reloc->delta + target_offset;
295 uint64_t offset;
296 void __iomem *reloc_page;
297 int ret;
298
299 ret = i915_gem_object_set_to_gtt_domain(obj, true);
300 if (ret)
301 return ret;
302
303 ret = i915_gem_object_put_fence(obj);
304 if (ret)
305 return ret;
306
307 /* Map the page containing the relocation we're going to perform. */
308 offset = i915_gem_obj_ggtt_offset(obj);
309 offset += reloc->offset;
310 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
311 offset & PAGE_MASK);
312 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
313
314 if (INTEL_INFO(dev)->gen >= 8) {
315 offset += sizeof(uint32_t);
316
317 if (offset_in_page(offset) == 0) {
318 io_mapping_unmap_atomic(reloc_page);
319 reloc_page =
320 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
321 offset);
322 }
323
324 iowrite32(upper_32_bits(delta),
325 reloc_page + offset_in_page(offset));
326 }
327
328 io_mapping_unmap_atomic(reloc_page);
329
330 return 0;
331 }
332
333 static void
334 clflush_write32(void *addr, uint32_t value)
335 {
336 /* This is not a fast path, so KISS. */
337 drm_clflush_virt_range(addr, sizeof(uint32_t));
338 *(uint32_t *)addr = value;
339 drm_clflush_virt_range(addr, sizeof(uint32_t));
340 }
341
342 static int
343 relocate_entry_clflush(struct drm_i915_gem_object *obj,
344 struct drm_i915_gem_relocation_entry *reloc,
345 uint64_t target_offset)
346 {
347 struct drm_device *dev = obj->base.dev;
348 uint32_t page_offset = offset_in_page(reloc->offset);
349 uint64_t delta = (int)reloc->delta + target_offset;
350 char *vaddr;
351 int ret;
352
353 ret = i915_gem_object_set_to_gtt_domain(obj, true);
354 if (ret)
355 return ret;
356
357 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
358 reloc->offset >> PAGE_SHIFT));
359 clflush_write32(vaddr + page_offset, lower_32_bits(delta));
360
361 if (INTEL_INFO(dev)->gen >= 8) {
362 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
363
364 if (page_offset == 0) {
365 kunmap_atomic(vaddr);
366 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
367 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
368 }
369
370 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
371 }
372
373 kunmap_atomic(vaddr);
374
375 return 0;
376 }
377
378 static int
379 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
380 struct eb_vmas *eb,
381 struct drm_i915_gem_relocation_entry *reloc)
382 {
383 struct drm_device *dev = obj->base.dev;
384 struct drm_gem_object *target_obj;
385 struct drm_i915_gem_object *target_i915_obj;
386 struct i915_vma *target_vma;
387 uint64_t target_offset;
388 int ret;
389
390 /* we've already hold a reference to all valid objects */
391 target_vma = eb_get_vma(eb, reloc->target_handle);
392 if (unlikely(target_vma == NULL))
393 return -ENOENT;
394 target_i915_obj = target_vma->obj;
395 target_obj = &target_vma->obj->base;
396
397 target_offset = target_vma->node.start;
398
399 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
400 * pipe_control writes because the gpu doesn't properly redirect them
401 * through the ppgtt for non_secure batchbuffers. */
402 if (unlikely(IS_GEN6(dev) &&
403 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
404 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
405 PIN_GLOBAL);
406 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
407 return ret;
408 }
409
410 /* Validate that the target is in a valid r/w GPU domain */
411 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
412 DRM_DEBUG("reloc with multiple write domains: "
413 "obj %p target %d offset %d "
414 "read %08x write %08x",
415 obj, reloc->target_handle,
416 (int) reloc->offset,
417 reloc->read_domains,
418 reloc->write_domain);
419 return -EINVAL;
420 }
421 if (unlikely((reloc->write_domain | reloc->read_domains)
422 & ~I915_GEM_GPU_DOMAINS)) {
423 DRM_DEBUG("reloc with read/write non-GPU domains: "
424 "obj %p target %d offset %d "
425 "read %08x write %08x",
426 obj, reloc->target_handle,
427 (int) reloc->offset,
428 reloc->read_domains,
429 reloc->write_domain);
430 return -EINVAL;
431 }
432
433 target_obj->pending_read_domains |= reloc->read_domains;
434 target_obj->pending_write_domain |= reloc->write_domain;
435
436 /* If the relocation already has the right value in it, no
437 * more work needs to be done.
438 */
439 if (target_offset == reloc->presumed_offset)
440 return 0;
441
442 /* Check that the relocation address is valid... */
443 if (unlikely(reloc->offset >
444 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
445 DRM_DEBUG("Relocation beyond object bounds: "
446 "obj %p target %d offset %d size %d.\n",
447 obj, reloc->target_handle,
448 (int) reloc->offset,
449 (int) obj->base.size);
450 return -EINVAL;
451 }
452 if (unlikely(reloc->offset & 3)) {
453 DRM_DEBUG("Relocation not 4-byte aligned: "
454 "obj %p target %d offset %d.\n",
455 obj, reloc->target_handle,
456 (int) reloc->offset);
457 return -EINVAL;
458 }
459
460 /* We can't wait for rendering with pagefaults disabled */
461 if (obj->active && in_atomic())
462 return -EFAULT;
463
464 if (use_cpu_reloc(obj))
465 ret = relocate_entry_cpu(obj, reloc, target_offset);
466 else if (obj->map_and_fenceable)
467 ret = relocate_entry_gtt(obj, reloc, target_offset);
468 else if (cpu_has_clflush)
469 ret = relocate_entry_clflush(obj, reloc, target_offset);
470 else {
471 WARN_ONCE(1, "Impossible case in relocation handling\n");
472 ret = -ENODEV;
473 }
474
475 if (ret)
476 return ret;
477
478 /* and update the user's relocation entry */
479 reloc->presumed_offset = target_offset;
480
481 return 0;
482 }
483
484 static int
485 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
486 struct eb_vmas *eb)
487 {
488 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
489 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
490 struct drm_i915_gem_relocation_entry __user *user_relocs;
491 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
492 int remain, ret;
493
494 user_relocs = to_user_ptr(entry->relocs_ptr);
495
496 remain = entry->relocation_count;
497 while (remain) {
498 struct drm_i915_gem_relocation_entry *r = stack_reloc;
499 int count = remain;
500 if (count > ARRAY_SIZE(stack_reloc))
501 count = ARRAY_SIZE(stack_reloc);
502 remain -= count;
503
504 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
505 return -EFAULT;
506
507 do {
508 u64 offset = r->presumed_offset;
509
510 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
511 if (ret)
512 return ret;
513
514 if (r->presumed_offset != offset &&
515 __copy_to_user_inatomic(&user_relocs->presumed_offset,
516 &r->presumed_offset,
517 sizeof(r->presumed_offset))) {
518 return -EFAULT;
519 }
520
521 user_relocs++;
522 r++;
523 } while (--count);
524 }
525
526 return 0;
527 #undef N_RELOC
528 }
529
530 static int
531 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
532 struct eb_vmas *eb,
533 struct drm_i915_gem_relocation_entry *relocs)
534 {
535 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
536 int i, ret;
537
538 for (i = 0; i < entry->relocation_count; i++) {
539 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
540 if (ret)
541 return ret;
542 }
543
544 return 0;
545 }
546
547 static int
548 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
549 {
550 struct i915_vma *vma;
551 int ret = 0;
552
553 /* This is the fast path and we cannot handle a pagefault whilst
554 * holding the struct mutex lest the user pass in the relocations
555 * contained within a mmaped bo. For in such a case we, the page
556 * fault handler would call i915_gem_fault() and we would try to
557 * acquire the struct mutex again. Obviously this is bad and so
558 * lockdep complains vehemently.
559 */
560 pagefault_disable();
561 list_for_each_entry(vma, &eb->vmas, exec_list) {
562 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
563 if (ret)
564 break;
565 }
566 pagefault_enable();
567
568 return ret;
569 }
570
571 static bool only_mappable_for_reloc(unsigned int flags)
572 {
573 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
574 __EXEC_OBJECT_NEEDS_MAP;
575 }
576
577 static int
578 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
579 struct intel_engine_cs *ring,
580 bool *need_reloc)
581 {
582 struct drm_i915_gem_object *obj = vma->obj;
583 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
584 uint64_t flags;
585 int ret;
586
587 flags = PIN_USER;
588 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
589 flags |= PIN_GLOBAL;
590
591 if (!drm_mm_node_allocated(&vma->node)) {
592 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
593 flags |= PIN_GLOBAL | PIN_MAPPABLE;
594 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
595 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
596 }
597
598 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
599 if ((ret == -ENOSPC || ret == -E2BIG) &&
600 only_mappable_for_reloc(entry->flags))
601 ret = i915_gem_object_pin(obj, vma->vm,
602 entry->alignment,
603 flags & ~PIN_MAPPABLE);
604 if (ret)
605 return ret;
606
607 entry->flags |= __EXEC_OBJECT_HAS_PIN;
608
609 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
610 ret = i915_gem_object_get_fence(obj);
611 if (ret)
612 return ret;
613
614 if (i915_gem_object_pin_fence(obj))
615 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
616 }
617
618 if (entry->offset != vma->node.start) {
619 entry->offset = vma->node.start;
620 *need_reloc = true;
621 }
622
623 if (entry->flags & EXEC_OBJECT_WRITE) {
624 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
625 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
626 }
627
628 return 0;
629 }
630
631 static bool
632 need_reloc_mappable(struct i915_vma *vma)
633 {
634 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
635
636 if (entry->relocation_count == 0)
637 return false;
638
639 if (!i915_is_ggtt(vma->vm))
640 return false;
641
642 /* See also use_cpu_reloc() */
643 if (HAS_LLC(vma->obj->base.dev))
644 return false;
645
646 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
647 return false;
648
649 return true;
650 }
651
652 static bool
653 eb_vma_misplaced(struct i915_vma *vma)
654 {
655 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
656 struct drm_i915_gem_object *obj = vma->obj;
657
658 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
659 !i915_is_ggtt(vma->vm));
660
661 if (entry->alignment &&
662 vma->node.start & (entry->alignment - 1))
663 return true;
664
665 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
666 vma->node.start < BATCH_OFFSET_BIAS)
667 return true;
668
669 /* avoid costly ping-pong once a batch bo ended up non-mappable */
670 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
671 return !only_mappable_for_reloc(entry->flags);
672
673 return false;
674 }
675
676 static int
677 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
678 struct list_head *vmas,
679 bool *need_relocs)
680 {
681 struct drm_i915_gem_object *obj;
682 struct i915_vma *vma;
683 struct i915_address_space *vm;
684 struct list_head ordered_vmas;
685 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
686 int retry;
687
688 i915_gem_retire_requests_ring(ring);
689
690 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
691
692 INIT_LIST_HEAD(&ordered_vmas);
693 while (!list_empty(vmas)) {
694 struct drm_i915_gem_exec_object2 *entry;
695 bool need_fence, need_mappable;
696
697 vma = list_first_entry(vmas, struct i915_vma, exec_list);
698 obj = vma->obj;
699 entry = vma->exec_entry;
700
701 if (!has_fenced_gpu_access)
702 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
703 need_fence =
704 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
705 obj->tiling_mode != I915_TILING_NONE;
706 need_mappable = need_fence || need_reloc_mappable(vma);
707
708 if (need_mappable) {
709 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
710 list_move(&vma->exec_list, &ordered_vmas);
711 } else
712 list_move_tail(&vma->exec_list, &ordered_vmas);
713
714 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
715 obj->base.pending_write_domain = 0;
716 }
717 list_splice(&ordered_vmas, vmas);
718
719 /* Attempt to pin all of the buffers into the GTT.
720 * This is done in 3 phases:
721 *
722 * 1a. Unbind all objects that do not match the GTT constraints for
723 * the execbuffer (fenceable, mappable, alignment etc).
724 * 1b. Increment pin count for already bound objects.
725 * 2. Bind new objects.
726 * 3. Decrement pin count.
727 *
728 * This avoid unnecessary unbinding of later objects in order to make
729 * room for the earlier objects *unless* we need to defragment.
730 */
731 retry = 0;
732 do {
733 int ret = 0;
734
735 /* Unbind any ill-fitting objects or pin. */
736 list_for_each_entry(vma, vmas, exec_list) {
737 if (!drm_mm_node_allocated(&vma->node))
738 continue;
739
740 if (eb_vma_misplaced(vma))
741 ret = i915_vma_unbind(vma);
742 else
743 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
744 if (ret)
745 goto err;
746 }
747
748 /* Bind fresh objects */
749 list_for_each_entry(vma, vmas, exec_list) {
750 if (drm_mm_node_allocated(&vma->node))
751 continue;
752
753 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
754 if (ret)
755 goto err;
756 }
757
758 err:
759 if (ret != -ENOSPC || retry++)
760 return ret;
761
762 /* Decrement pin count for bound objects */
763 list_for_each_entry(vma, vmas, exec_list)
764 i915_gem_execbuffer_unreserve_vma(vma);
765
766 ret = i915_gem_evict_vm(vm, true);
767 if (ret)
768 return ret;
769 } while (1);
770 }
771
772 static int
773 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
774 struct drm_i915_gem_execbuffer2 *args,
775 struct drm_file *file,
776 struct intel_engine_cs *ring,
777 struct eb_vmas *eb,
778 struct drm_i915_gem_exec_object2 *exec)
779 {
780 struct drm_i915_gem_relocation_entry *reloc;
781 struct i915_address_space *vm;
782 struct i915_vma *vma;
783 bool need_relocs;
784 int *reloc_offset;
785 int i, total, ret;
786 unsigned count = args->buffer_count;
787
788 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
789
790 /* We may process another execbuffer during the unlock... */
791 while (!list_empty(&eb->vmas)) {
792 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
793 list_del_init(&vma->exec_list);
794 i915_gem_execbuffer_unreserve_vma(vma);
795 drm_gem_object_unreference(&vma->obj->base);
796 }
797
798 mutex_unlock(&dev->struct_mutex);
799
800 total = 0;
801 for (i = 0; i < count; i++)
802 total += exec[i].relocation_count;
803
804 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
805 reloc = drm_malloc_ab(total, sizeof(*reloc));
806 if (reloc == NULL || reloc_offset == NULL) {
807 drm_free_large(reloc);
808 drm_free_large(reloc_offset);
809 mutex_lock(&dev->struct_mutex);
810 return -ENOMEM;
811 }
812
813 total = 0;
814 for (i = 0; i < count; i++) {
815 struct drm_i915_gem_relocation_entry __user *user_relocs;
816 u64 invalid_offset = (u64)-1;
817 int j;
818
819 user_relocs = to_user_ptr(exec[i].relocs_ptr);
820
821 if (copy_from_user(reloc+total, user_relocs,
822 exec[i].relocation_count * sizeof(*reloc))) {
823 ret = -EFAULT;
824 mutex_lock(&dev->struct_mutex);
825 goto err;
826 }
827
828 /* As we do not update the known relocation offsets after
829 * relocating (due to the complexities in lock handling),
830 * we need to mark them as invalid now so that we force the
831 * relocation processing next time. Just in case the target
832 * object is evicted and then rebound into its old
833 * presumed_offset before the next execbuffer - if that
834 * happened we would make the mistake of assuming that the
835 * relocations were valid.
836 */
837 for (j = 0; j < exec[i].relocation_count; j++) {
838 if (__copy_to_user(&user_relocs[j].presumed_offset,
839 &invalid_offset,
840 sizeof(invalid_offset))) {
841 ret = -EFAULT;
842 mutex_lock(&dev->struct_mutex);
843 goto err;
844 }
845 }
846
847 reloc_offset[i] = total;
848 total += exec[i].relocation_count;
849 }
850
851 ret = i915_mutex_lock_interruptible(dev);
852 if (ret) {
853 mutex_lock(&dev->struct_mutex);
854 goto err;
855 }
856
857 /* reacquire the objects */
858 eb_reset(eb);
859 ret = eb_lookup_vmas(eb, exec, args, vm, file);
860 if (ret)
861 goto err;
862
863 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
864 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
865 if (ret)
866 goto err;
867
868 list_for_each_entry(vma, &eb->vmas, exec_list) {
869 int offset = vma->exec_entry - exec;
870 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
871 reloc + reloc_offset[offset]);
872 if (ret)
873 goto err;
874 }
875
876 /* Leave the user relocations as are, this is the painfully slow path,
877 * and we want to avoid the complication of dropping the lock whilst
878 * having buffers reserved in the aperture and so causing spurious
879 * ENOSPC for random operations.
880 */
881
882 err:
883 drm_free_large(reloc);
884 drm_free_large(reloc_offset);
885 return ret;
886 }
887
888 static int
889 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
890 struct list_head *vmas)
891 {
892 const unsigned other_rings = ~intel_ring_flag(ring);
893 struct i915_vma *vma;
894 uint32_t flush_domains = 0;
895 bool flush_chipset = false;
896 int ret;
897
898 list_for_each_entry(vma, vmas, exec_list) {
899 struct drm_i915_gem_object *obj = vma->obj;
900
901 if (obj->active & other_rings) {
902 ret = i915_gem_object_sync(obj, ring);
903 if (ret)
904 return ret;
905 }
906
907 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
908 flush_chipset |= i915_gem_clflush_object(obj, false);
909
910 flush_domains |= obj->base.write_domain;
911 }
912
913 if (flush_chipset)
914 i915_gem_chipset_flush(ring->dev);
915
916 if (flush_domains & I915_GEM_DOMAIN_GTT)
917 wmb();
918
919 /* Unconditionally invalidate gpu caches and ensure that we do flush
920 * any residual writes from the previous batch.
921 */
922 return intel_ring_invalidate_all_caches(ring);
923 }
924
925 static bool
926 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
927 {
928 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
929 return false;
930
931 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
932 }
933
934 static int
935 validate_exec_list(struct drm_device *dev,
936 struct drm_i915_gem_exec_object2 *exec,
937 int count)
938 {
939 unsigned relocs_total = 0;
940 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
941 unsigned invalid_flags;
942 int i;
943
944 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
945 if (USES_FULL_PPGTT(dev))
946 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
947
948 for (i = 0; i < count; i++) {
949 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
950 int length; /* limited by fault_in_pages_readable() */
951
952 if (exec[i].flags & invalid_flags)
953 return -EINVAL;
954
955 /* First check for malicious input causing overflow in
956 * the worst case where we need to allocate the entire
957 * relocation tree as a single array.
958 */
959 if (exec[i].relocation_count > relocs_max - relocs_total)
960 return -EINVAL;
961 relocs_total += exec[i].relocation_count;
962
963 length = exec[i].relocation_count *
964 sizeof(struct drm_i915_gem_relocation_entry);
965 /*
966 * We must check that the entire relocation array is safe
967 * to read, but since we may need to update the presumed
968 * offsets during execution, check for full write access.
969 */
970 if (!access_ok(VERIFY_WRITE, ptr, length))
971 return -EFAULT;
972
973 if (likely(!i915.prefault_disable)) {
974 if (fault_in_multipages_readable(ptr, length))
975 return -EFAULT;
976 }
977 }
978
979 return 0;
980 }
981
982 static struct intel_context *
983 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
984 struct intel_engine_cs *ring, const u32 ctx_id)
985 {
986 struct intel_context *ctx = NULL;
987 struct i915_ctx_hang_stats *hs;
988
989 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
990 return ERR_PTR(-EINVAL);
991
992 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
993 if (IS_ERR(ctx))
994 return ctx;
995
996 hs = &ctx->hang_stats;
997 if (hs->banned) {
998 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
999 return ERR_PTR(-EIO);
1000 }
1001
1002 if (i915.enable_execlists && !ctx->engine[ring->id].state) {
1003 int ret = intel_lr_context_deferred_create(ctx, ring);
1004 if (ret) {
1005 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
1006 return ERR_PTR(ret);
1007 }
1008 }
1009
1010 return ctx;
1011 }
1012
1013 void
1014 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1015 struct intel_engine_cs *ring)
1016 {
1017 struct drm_i915_gem_request *req = intel_ring_get_request(ring);
1018 struct i915_vma *vma;
1019
1020 list_for_each_entry(vma, vmas, exec_list) {
1021 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1022 struct drm_i915_gem_object *obj = vma->obj;
1023 u32 old_read = obj->base.read_domains;
1024 u32 old_write = obj->base.write_domain;
1025
1026 obj->base.write_domain = obj->base.pending_write_domain;
1027 if (obj->base.write_domain == 0)
1028 obj->base.pending_read_domains |= obj->base.read_domains;
1029 obj->base.read_domains = obj->base.pending_read_domains;
1030
1031 i915_vma_move_to_active(vma, ring);
1032 if (obj->base.write_domain) {
1033 obj->dirty = 1;
1034 i915_gem_request_assign(&obj->last_write_req, req);
1035
1036 intel_fb_obj_invalidate(obj, ring, ORIGIN_CS);
1037
1038 /* update for the implicit flush after a batch */
1039 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1040 }
1041 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1042 i915_gem_request_assign(&obj->last_fenced_req, req);
1043 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1044 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1045 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1046 &dev_priv->mm.fence_list);
1047 }
1048 }
1049
1050 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1051 }
1052 }
1053
1054 void
1055 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
1056 struct drm_file *file,
1057 struct intel_engine_cs *ring,
1058 struct drm_i915_gem_object *obj)
1059 {
1060 /* Unconditionally force add_request to emit a full flush. */
1061 ring->gpu_caches_dirty = true;
1062
1063 /* Add a breadcrumb for the completion of the batch buffer */
1064 (void)__i915_add_request(ring, file, obj);
1065 }
1066
1067 static int
1068 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1069 struct intel_engine_cs *ring)
1070 {
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 int ret, i;
1073
1074 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1075 DRM_DEBUG("sol reset is gen7/rcs only\n");
1076 return -EINVAL;
1077 }
1078
1079 ret = intel_ring_begin(ring, 4 * 3);
1080 if (ret)
1081 return ret;
1082
1083 for (i = 0; i < 4; i++) {
1084 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1085 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1086 intel_ring_emit(ring, 0);
1087 }
1088
1089 intel_ring_advance(ring);
1090
1091 return 0;
1092 }
1093
1094 static int
1095 i915_emit_box(struct intel_engine_cs *ring,
1096 struct drm_clip_rect *box,
1097 int DR1, int DR4)
1098 {
1099 int ret;
1100
1101 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
1102 box->y2 <= 0 || box->x2 <= 0) {
1103 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1104 box->x1, box->y1, box->x2, box->y2);
1105 return -EINVAL;
1106 }
1107
1108 if (INTEL_INFO(ring->dev)->gen >= 4) {
1109 ret = intel_ring_begin(ring, 4);
1110 if (ret)
1111 return ret;
1112
1113 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
1114 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1115 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1116 intel_ring_emit(ring, DR4);
1117 } else {
1118 ret = intel_ring_begin(ring, 6);
1119 if (ret)
1120 return ret;
1121
1122 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
1123 intel_ring_emit(ring, DR1);
1124 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1125 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1126 intel_ring_emit(ring, DR4);
1127 intel_ring_emit(ring, 0);
1128 }
1129 intel_ring_advance(ring);
1130
1131 return 0;
1132 }
1133
1134 static struct drm_i915_gem_object*
1135 i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
1136 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1137 struct eb_vmas *eb,
1138 struct drm_i915_gem_object *batch_obj,
1139 u32 batch_start_offset,
1140 u32 batch_len,
1141 bool is_master)
1142 {
1143 struct drm_i915_gem_object *shadow_batch_obj;
1144 struct i915_vma *vma;
1145 int ret;
1146
1147 shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
1148 PAGE_ALIGN(batch_len));
1149 if (IS_ERR(shadow_batch_obj))
1150 return shadow_batch_obj;
1151
1152 ret = i915_parse_cmds(ring,
1153 batch_obj,
1154 shadow_batch_obj,
1155 batch_start_offset,
1156 batch_len,
1157 is_master);
1158 if (ret)
1159 goto err;
1160
1161 ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1162 if (ret)
1163 goto err;
1164
1165 i915_gem_object_unpin_pages(shadow_batch_obj);
1166
1167 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1168
1169 vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1170 vma->exec_entry = shadow_exec_entry;
1171 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1172 drm_gem_object_reference(&shadow_batch_obj->base);
1173 list_add_tail(&vma->exec_list, &eb->vmas);
1174
1175 shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1176
1177 return shadow_batch_obj;
1178
1179 err:
1180 i915_gem_object_unpin_pages(shadow_batch_obj);
1181 if (ret == -EACCES) /* unhandled chained batch */
1182 return batch_obj;
1183 else
1184 return ERR_PTR(ret);
1185 }
1186
1187 int
1188 i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
1189 struct intel_engine_cs *ring,
1190 struct intel_context *ctx,
1191 struct drm_i915_gem_execbuffer2 *args,
1192 struct list_head *vmas,
1193 struct drm_i915_gem_object *batch_obj,
1194 u64 exec_start, u32 dispatch_flags)
1195 {
1196 struct drm_clip_rect *cliprects = NULL;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u64 exec_len;
1199 int instp_mode;
1200 u32 instp_mask;
1201 int i, ret = 0;
1202
1203 if (args->num_cliprects != 0) {
1204 if (ring != &dev_priv->ring[RCS]) {
1205 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1206 return -EINVAL;
1207 }
1208
1209 if (INTEL_INFO(dev)->gen >= 5) {
1210 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1211 return -EINVAL;
1212 }
1213
1214 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1215 DRM_DEBUG("execbuf with %u cliprects\n",
1216 args->num_cliprects);
1217 return -EINVAL;
1218 }
1219
1220 cliprects = kcalloc(args->num_cliprects,
1221 sizeof(*cliprects),
1222 GFP_KERNEL);
1223 if (cliprects == NULL) {
1224 ret = -ENOMEM;
1225 goto error;
1226 }
1227
1228 if (copy_from_user(cliprects,
1229 to_user_ptr(args->cliprects_ptr),
1230 sizeof(*cliprects)*args->num_cliprects)) {
1231 ret = -EFAULT;
1232 goto error;
1233 }
1234 } else {
1235 if (args->DR4 == 0xffffffff) {
1236 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1237 args->DR4 = 0;
1238 }
1239
1240 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
1241 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1242 return -EINVAL;
1243 }
1244 }
1245
1246 ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
1247 if (ret)
1248 goto error;
1249
1250 ret = i915_switch_context(ring, ctx);
1251 if (ret)
1252 goto error;
1253
1254 WARN(ctx->ppgtt && ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
1255 "%s didn't clear reload\n", ring->name);
1256
1257 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1258 instp_mask = I915_EXEC_CONSTANTS_MASK;
1259 switch (instp_mode) {
1260 case I915_EXEC_CONSTANTS_REL_GENERAL:
1261 case I915_EXEC_CONSTANTS_ABSOLUTE:
1262 case I915_EXEC_CONSTANTS_REL_SURFACE:
1263 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1264 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1265 ret = -EINVAL;
1266 goto error;
1267 }
1268
1269 if (instp_mode != dev_priv->relative_constants_mode) {
1270 if (INTEL_INFO(dev)->gen < 4) {
1271 DRM_DEBUG("no rel constants on pre-gen4\n");
1272 ret = -EINVAL;
1273 goto error;
1274 }
1275
1276 if (INTEL_INFO(dev)->gen > 5 &&
1277 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1278 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1279 ret = -EINVAL;
1280 goto error;
1281 }
1282
1283 /* The HW changed the meaning on this bit on gen6 */
1284 if (INTEL_INFO(dev)->gen >= 6)
1285 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1286 }
1287 break;
1288 default:
1289 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1290 ret = -EINVAL;
1291 goto error;
1292 }
1293
1294 if (ring == &dev_priv->ring[RCS] &&
1295 instp_mode != dev_priv->relative_constants_mode) {
1296 ret = intel_ring_begin(ring, 4);
1297 if (ret)
1298 goto error;
1299
1300 intel_ring_emit(ring, MI_NOOP);
1301 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1302 intel_ring_emit(ring, INSTPM);
1303 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1304 intel_ring_advance(ring);
1305
1306 dev_priv->relative_constants_mode = instp_mode;
1307 }
1308
1309 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1310 ret = i915_reset_gen7_sol_offsets(dev, ring);
1311 if (ret)
1312 goto error;
1313 }
1314
1315 exec_len = args->batch_len;
1316 if (cliprects) {
1317 for (i = 0; i < args->num_cliprects; i++) {
1318 ret = i915_emit_box(ring, &cliprects[i],
1319 args->DR1, args->DR4);
1320 if (ret)
1321 goto error;
1322
1323 ret = ring->dispatch_execbuffer(ring,
1324 exec_start, exec_len,
1325 dispatch_flags);
1326 if (ret)
1327 goto error;
1328 }
1329 } else {
1330 ret = ring->dispatch_execbuffer(ring,
1331 exec_start, exec_len,
1332 dispatch_flags);
1333 if (ret)
1334 return ret;
1335 }
1336
1337 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
1338
1339 i915_gem_execbuffer_move_to_active(vmas, ring);
1340 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1341
1342 error:
1343 kfree(cliprects);
1344 return ret;
1345 }
1346
1347 /**
1348 * Find one BSD ring to dispatch the corresponding BSD command.
1349 * The Ring ID is returned.
1350 */
1351 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1352 struct drm_file *file)
1353 {
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 struct drm_i915_file_private *file_priv = file->driver_priv;
1356
1357 /* Check whether the file_priv is using one ring */
1358 if (file_priv->bsd_ring)
1359 return file_priv->bsd_ring->id;
1360 else {
1361 /* If no, use the ping-pong mechanism to select one ring */
1362 int ring_id;
1363
1364 mutex_lock(&dev->struct_mutex);
1365 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1366 ring_id = VCS;
1367 dev_priv->mm.bsd_ring_dispatch_index = 1;
1368 } else {
1369 ring_id = VCS2;
1370 dev_priv->mm.bsd_ring_dispatch_index = 0;
1371 }
1372 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1373 mutex_unlock(&dev->struct_mutex);
1374 return ring_id;
1375 }
1376 }
1377
1378 static struct drm_i915_gem_object *
1379 eb_get_batch(struct eb_vmas *eb)
1380 {
1381 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1382
1383 /*
1384 * SNA is doing fancy tricks with compressing batch buffers, which leads
1385 * to negative relocation deltas. Usually that works out ok since the
1386 * relocate address is still positive, except when the batch is placed
1387 * very low in the GTT. Ensure this doesn't happen.
1388 *
1389 * Note that actual hangs have only been observed on gen7, but for
1390 * paranoia do it everywhere.
1391 */
1392 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1393
1394 return vma->obj;
1395 }
1396
1397 static int
1398 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1399 struct drm_file *file,
1400 struct drm_i915_gem_execbuffer2 *args,
1401 struct drm_i915_gem_exec_object2 *exec)
1402 {
1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404 struct eb_vmas *eb;
1405 struct drm_i915_gem_object *batch_obj;
1406 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1407 struct intel_engine_cs *ring;
1408 struct intel_context *ctx;
1409 struct i915_address_space *vm;
1410 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1411 u64 exec_start = args->batch_start_offset;
1412 u32 dispatch_flags;
1413 int ret;
1414 bool need_relocs;
1415
1416 if (!i915_gem_check_execbuffer(args))
1417 return -EINVAL;
1418
1419 ret = validate_exec_list(dev, exec, args->buffer_count);
1420 if (ret)
1421 return ret;
1422
1423 dispatch_flags = 0;
1424 if (args->flags & I915_EXEC_SECURE) {
1425 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1426 return -EPERM;
1427
1428 dispatch_flags |= I915_DISPATCH_SECURE;
1429 }
1430 if (args->flags & I915_EXEC_IS_PINNED)
1431 dispatch_flags |= I915_DISPATCH_PINNED;
1432
1433 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1434 DRM_DEBUG("execbuf with unknown ring: %d\n",
1435 (int)(args->flags & I915_EXEC_RING_MASK));
1436 return -EINVAL;
1437 }
1438
1439 if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
1440 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1441 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1442 "bsd dispatch flags: %d\n", (int)(args->flags));
1443 return -EINVAL;
1444 }
1445
1446 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1447 ring = &dev_priv->ring[RCS];
1448 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1449 if (HAS_BSD2(dev)) {
1450 int ring_id;
1451
1452 switch (args->flags & I915_EXEC_BSD_MASK) {
1453 case I915_EXEC_BSD_DEFAULT:
1454 ring_id = gen8_dispatch_bsd_ring(dev, file);
1455 ring = &dev_priv->ring[ring_id];
1456 break;
1457 case I915_EXEC_BSD_RING1:
1458 ring = &dev_priv->ring[VCS];
1459 break;
1460 case I915_EXEC_BSD_RING2:
1461 ring = &dev_priv->ring[VCS2];
1462 break;
1463 default:
1464 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1465 (int)(args->flags & I915_EXEC_BSD_MASK));
1466 return -EINVAL;
1467 }
1468 } else
1469 ring = &dev_priv->ring[VCS];
1470 } else
1471 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1472
1473 if (!intel_ring_initialized(ring)) {
1474 DRM_DEBUG("execbuf with invalid ring: %d\n",
1475 (int)(args->flags & I915_EXEC_RING_MASK));
1476 return -EINVAL;
1477 }
1478
1479 if (args->buffer_count < 1) {
1480 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1481 return -EINVAL;
1482 }
1483
1484 intel_runtime_pm_get(dev_priv);
1485
1486 ret = i915_mutex_lock_interruptible(dev);
1487 if (ret)
1488 goto pre_mutex_err;
1489
1490 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1491 if (IS_ERR(ctx)) {
1492 mutex_unlock(&dev->struct_mutex);
1493 ret = PTR_ERR(ctx);
1494 goto pre_mutex_err;
1495 }
1496
1497 i915_gem_context_reference(ctx);
1498
1499 if (ctx->ppgtt)
1500 vm = &ctx->ppgtt->base;
1501 else
1502 vm = &dev_priv->gtt.base;
1503
1504 eb = eb_create(args);
1505 if (eb == NULL) {
1506 i915_gem_context_unreference(ctx);
1507 mutex_unlock(&dev->struct_mutex);
1508 ret = -ENOMEM;
1509 goto pre_mutex_err;
1510 }
1511
1512 /* Look up object handles */
1513 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1514 if (ret)
1515 goto err;
1516
1517 /* take note of the batch buffer before we might reorder the lists */
1518 batch_obj = eb_get_batch(eb);
1519
1520 /* Move the objects en-masse into the GTT, evicting if necessary. */
1521 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1522 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
1523 if (ret)
1524 goto err;
1525
1526 /* The objects are in their final locations, apply the relocations. */
1527 if (need_relocs)
1528 ret = i915_gem_execbuffer_relocate(eb);
1529 if (ret) {
1530 if (ret == -EFAULT) {
1531 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1532 eb, exec);
1533 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1534 }
1535 if (ret)
1536 goto err;
1537 }
1538
1539 /* Set the pending read domains for the batch buffer to COMMAND */
1540 if (batch_obj->base.pending_write_domain) {
1541 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1542 ret = -EINVAL;
1543 goto err;
1544 }
1545
1546 if (i915_needs_cmd_parser(ring) && args->batch_len) {
1547 struct drm_i915_gem_object *parsed_batch_obj;
1548
1549 parsed_batch_obj = i915_gem_execbuffer_parse(ring,
1550 &shadow_exec_entry,
1551 eb,
1552 batch_obj,
1553 args->batch_start_offset,
1554 args->batch_len,
1555 file->is_master);
1556 if (IS_ERR(parsed_batch_obj)) {
1557 ret = PTR_ERR(parsed_batch_obj);
1558 goto err;
1559 }
1560
1561 /*
1562 * parsed_batch_obj == batch_obj means batch not fully parsed:
1563 * Accept, but don't promote to secure.
1564 */
1565
1566 if (parsed_batch_obj != batch_obj) {
1567 /*
1568 * Batch parsed and accepted:
1569 *
1570 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1571 * bit from MI_BATCH_BUFFER_START commands issued in
1572 * the dispatch_execbuffer implementations. We
1573 * specifically don't want that set on batches the
1574 * command parser has accepted.
1575 */
1576 dispatch_flags |= I915_DISPATCH_SECURE;
1577 exec_start = 0;
1578 batch_obj = parsed_batch_obj;
1579 }
1580 }
1581
1582 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1583
1584 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1585 * batch" bit. Hence we need to pin secure batches into the global gtt.
1586 * hsw should have this fixed, but bdw mucks it up again. */
1587 if (dispatch_flags & I915_DISPATCH_SECURE) {
1588 /*
1589 * So on first glance it looks freaky that we pin the batch here
1590 * outside of the reservation loop. But:
1591 * - The batch is already pinned into the relevant ppgtt, so we
1592 * already have the backing storage fully allocated.
1593 * - No other BO uses the global gtt (well contexts, but meh),
1594 * so we don't really have issues with multiple objects not
1595 * fitting due to fragmentation.
1596 * So this is actually safe.
1597 */
1598 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1599 if (ret)
1600 goto err;
1601
1602 exec_start += i915_gem_obj_ggtt_offset(batch_obj);
1603 } else
1604 exec_start += i915_gem_obj_offset(batch_obj, vm);
1605
1606 ret = dev_priv->gt.execbuf_submit(dev, file, ring, ctx, args,
1607 &eb->vmas, batch_obj, exec_start,
1608 dispatch_flags);
1609
1610 /*
1611 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1612 * batch vma for correctness. For less ugly and less fragility this
1613 * needs to be adjusted to also track the ggtt batch vma properly as
1614 * active.
1615 */
1616 if (dispatch_flags & I915_DISPATCH_SECURE)
1617 i915_gem_object_ggtt_unpin(batch_obj);
1618 err:
1619 /* the request owns the ref now */
1620 i915_gem_context_unreference(ctx);
1621 eb_destroy(eb);
1622
1623 mutex_unlock(&dev->struct_mutex);
1624
1625 pre_mutex_err:
1626 /* intel_gpu_busy should also get a ref, so it will free when the device
1627 * is really idle. */
1628 intel_runtime_pm_put(dev_priv);
1629 return ret;
1630 }
1631
1632 /*
1633 * Legacy execbuffer just creates an exec2 list from the original exec object
1634 * list array and passes it to the real function.
1635 */
1636 int
1637 i915_gem_execbuffer(struct drm_device *dev, void *data,
1638 struct drm_file *file)
1639 {
1640 struct drm_i915_gem_execbuffer *args = data;
1641 struct drm_i915_gem_execbuffer2 exec2;
1642 struct drm_i915_gem_exec_object *exec_list = NULL;
1643 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1644 int ret, i;
1645
1646 if (args->buffer_count < 1) {
1647 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1648 return -EINVAL;
1649 }
1650
1651 /* Copy in the exec list from userland */
1652 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1653 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1654 if (exec_list == NULL || exec2_list == NULL) {
1655 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1656 args->buffer_count);
1657 drm_free_large(exec_list);
1658 drm_free_large(exec2_list);
1659 return -ENOMEM;
1660 }
1661 ret = copy_from_user(exec_list,
1662 to_user_ptr(args->buffers_ptr),
1663 sizeof(*exec_list) * args->buffer_count);
1664 if (ret != 0) {
1665 DRM_DEBUG("copy %d exec entries failed %d\n",
1666 args->buffer_count, ret);
1667 drm_free_large(exec_list);
1668 drm_free_large(exec2_list);
1669 return -EFAULT;
1670 }
1671
1672 for (i = 0; i < args->buffer_count; i++) {
1673 exec2_list[i].handle = exec_list[i].handle;
1674 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1675 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1676 exec2_list[i].alignment = exec_list[i].alignment;
1677 exec2_list[i].offset = exec_list[i].offset;
1678 if (INTEL_INFO(dev)->gen < 4)
1679 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1680 else
1681 exec2_list[i].flags = 0;
1682 }
1683
1684 exec2.buffers_ptr = args->buffers_ptr;
1685 exec2.buffer_count = args->buffer_count;
1686 exec2.batch_start_offset = args->batch_start_offset;
1687 exec2.batch_len = args->batch_len;
1688 exec2.DR1 = args->DR1;
1689 exec2.DR4 = args->DR4;
1690 exec2.num_cliprects = args->num_cliprects;
1691 exec2.cliprects_ptr = args->cliprects_ptr;
1692 exec2.flags = I915_EXEC_RENDER;
1693 i915_execbuffer2_set_context_id(exec2, 0);
1694
1695 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1696 if (!ret) {
1697 struct drm_i915_gem_exec_object __user *user_exec_list =
1698 to_user_ptr(args->buffers_ptr);
1699
1700 /* Copy the new buffer offsets back to the user's exec list. */
1701 for (i = 0; i < args->buffer_count; i++) {
1702 ret = __copy_to_user(&user_exec_list[i].offset,
1703 &exec2_list[i].offset,
1704 sizeof(user_exec_list[i].offset));
1705 if (ret) {
1706 ret = -EFAULT;
1707 DRM_DEBUG("failed to copy %d exec entries "
1708 "back to user (%d)\n",
1709 args->buffer_count, ret);
1710 break;
1711 }
1712 }
1713 }
1714
1715 drm_free_large(exec_list);
1716 drm_free_large(exec2_list);
1717 return ret;
1718 }
1719
1720 int
1721 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1722 struct drm_file *file)
1723 {
1724 struct drm_i915_gem_execbuffer2 *args = data;
1725 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1726 int ret;
1727
1728 if (args->buffer_count < 1 ||
1729 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1730 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1731 return -EINVAL;
1732 }
1733
1734 if (args->rsvd2 != 0) {
1735 DRM_DEBUG("dirty rvsd2 field\n");
1736 return -EINVAL;
1737 }
1738
1739 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1740 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1741 if (exec2_list == NULL)
1742 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1743 args->buffer_count);
1744 if (exec2_list == NULL) {
1745 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1746 args->buffer_count);
1747 return -ENOMEM;
1748 }
1749 ret = copy_from_user(exec2_list,
1750 to_user_ptr(args->buffers_ptr),
1751 sizeof(*exec2_list) * args->buffer_count);
1752 if (ret != 0) {
1753 DRM_DEBUG("copy %d exec entries failed %d\n",
1754 args->buffer_count, ret);
1755 drm_free_large(exec2_list);
1756 return -EFAULT;
1757 }
1758
1759 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1760 if (!ret) {
1761 /* Copy the new buffer offsets back to the user's exec list. */
1762 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1763 to_user_ptr(args->buffers_ptr);
1764 int i;
1765
1766 for (i = 0; i < args->buffer_count; i++) {
1767 ret = __copy_to_user(&user_exec_list[i].offset,
1768 &exec2_list[i].offset,
1769 sizeof(user_exec_list[i].offset));
1770 if (ret) {
1771 ret = -EFAULT;
1772 DRM_DEBUG("failed to copy %d exec entries "
1773 "back to user\n",
1774 args->buffer_count);
1775 break;
1776 }
1777 }
1778 }
1779
1780 drm_free_large(exec2_list);
1781 return ret;
1782 }
Linux kernel - Deliverables
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