2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
41 #define BATCH_OFFSET_BIAS (256*1024)
44 struct list_head vmas
;
47 struct i915_vma
*lut
[0];
48 struct hlist_head buckets
[0];
52 static struct eb_vmas
*
53 eb_create(struct drm_i915_gem_execbuffer2
*args
)
55 struct eb_vmas
*eb
= NULL
;
57 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
58 unsigned size
= args
->buffer_count
;
59 size
*= sizeof(struct i915_vma
*);
60 size
+= sizeof(struct eb_vmas
);
61 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
65 unsigned size
= args
->buffer_count
;
66 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
67 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
68 while (count
> 2*size
)
70 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
71 sizeof(struct eb_vmas
),
78 eb
->and = -args
->buffer_count
;
80 INIT_LIST_HEAD(&eb
->vmas
);
85 eb_reset(struct eb_vmas
*eb
)
88 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
92 eb_lookup_vmas(struct eb_vmas
*eb
,
93 struct drm_i915_gem_exec_object2
*exec
,
94 const struct drm_i915_gem_execbuffer2
*args
,
95 struct i915_address_space
*vm
,
96 struct drm_file
*file
)
98 struct drm_i915_gem_object
*obj
;
99 struct list_head objects
;
102 INIT_LIST_HEAD(&objects
);
103 spin_lock(&file
->table_lock
);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i
= 0; i
< args
->buffer_count
; i
++) {
107 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
109 spin_unlock(&file
->table_lock
);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
116 if (!list_empty(&obj
->obj_exec_link
)) {
117 spin_unlock(&file
->table_lock
);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj
, exec
[i
].handle
, i
);
124 WARN_ONCE(obj
->base
.dumb
,
125 "GPU use of dumb buffer is illegal.\n");
127 drm_gem_object_reference(&obj
->base
);
128 list_add_tail(&obj
->obj_exec_link
, &objects
);
130 spin_unlock(&file
->table_lock
);
133 while (!list_empty(&objects
)) {
134 struct i915_vma
*vma
;
136 obj
= list_first_entry(&objects
,
137 struct drm_i915_gem_object
,
141 * NOTE: We can leak any vmas created here when something fails
142 * later on. But that's no issue since vma_unbind can deal with
143 * vmas which are not actually bound. And since only
144 * lookup_or_create exists as an interface to get at the vma
145 * from the (obj, vm) we don't run the risk of creating
146 * duplicated vmas for the same vm.
148 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
150 DRM_DEBUG("Failed to lookup VMA\n");
155 /* Transfer ownership from the objects list to the vmas list. */
156 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
157 list_del_init(&obj
->obj_exec_link
);
159 vma
->exec_entry
= &exec
[i
];
163 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
164 vma
->exec_handle
= handle
;
165 hlist_add_head(&vma
->exec_node
,
166 &eb
->buckets
[handle
& eb
->and]);
175 while (!list_empty(&objects
)) {
176 obj
= list_first_entry(&objects
,
177 struct drm_i915_gem_object
,
179 list_del_init(&obj
->obj_exec_link
);
180 drm_gem_object_unreference(&obj
->base
);
183 * Objects already transfered to the vmas list will be unreferenced by
190 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
193 if (handle
>= -eb
->and)
195 return eb
->lut
[handle
];
197 struct hlist_head
*head
;
198 struct hlist_node
*node
;
200 head
= &eb
->buckets
[handle
& eb
->and];
201 hlist_for_each(node
, head
) {
202 struct i915_vma
*vma
;
204 vma
= hlist_entry(node
, struct i915_vma
, exec_node
);
205 if (vma
->exec_handle
== handle
)
213 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
215 struct drm_i915_gem_exec_object2
*entry
;
216 struct drm_i915_gem_object
*obj
= vma
->obj
;
218 if (!drm_mm_node_allocated(&vma
->node
))
221 entry
= vma
->exec_entry
;
223 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
224 i915_gem_object_unpin_fence(obj
);
226 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
229 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
232 static void eb_destroy(struct eb_vmas
*eb
)
234 while (!list_empty(&eb
->vmas
)) {
235 struct i915_vma
*vma
;
237 vma
= list_first_entry(&eb
->vmas
,
240 list_del_init(&vma
->exec_list
);
241 i915_gem_execbuffer_unreserve_vma(vma
);
242 drm_gem_object_unreference(&vma
->obj
->base
);
247 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
249 return (HAS_LLC(obj
->base
.dev
) ||
250 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
251 !obj
->map_and_fenceable
||
252 obj
->cache_level
!= I915_CACHE_NONE
);
256 relocate_entry_cpu(struct drm_i915_gem_object
*obj
,
257 struct drm_i915_gem_relocation_entry
*reloc
,
258 uint64_t target_offset
)
260 struct drm_device
*dev
= obj
->base
.dev
;
261 uint32_t page_offset
= offset_in_page(reloc
->offset
);
262 uint64_t delta
= reloc
->delta
+ target_offset
;
266 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
270 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
271 reloc
->offset
>> PAGE_SHIFT
));
272 *(uint32_t *)(vaddr
+ page_offset
) = lower_32_bits(delta
);
274 if (INTEL_INFO(dev
)->gen
>= 8) {
275 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
277 if (page_offset
== 0) {
278 kunmap_atomic(vaddr
);
279 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
280 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
283 *(uint32_t *)(vaddr
+ page_offset
) = upper_32_bits(delta
);
286 kunmap_atomic(vaddr
);
292 relocate_entry_gtt(struct drm_i915_gem_object
*obj
,
293 struct drm_i915_gem_relocation_entry
*reloc
,
294 uint64_t target_offset
)
296 struct drm_device
*dev
= obj
->base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 uint64_t delta
= reloc
->delta
+ target_offset
;
300 void __iomem
*reloc_page
;
303 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
307 ret
= i915_gem_object_put_fence(obj
);
311 /* Map the page containing the relocation we're going to perform. */
312 offset
= i915_gem_obj_ggtt_offset(obj
);
313 offset
+= reloc
->offset
;
314 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
316 iowrite32(lower_32_bits(delta
), reloc_page
+ offset_in_page(offset
));
318 if (INTEL_INFO(dev
)->gen
>= 8) {
319 offset
+= sizeof(uint32_t);
321 if (offset_in_page(offset
) == 0) {
322 io_mapping_unmap_atomic(reloc_page
);
324 io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
328 iowrite32(upper_32_bits(delta
),
329 reloc_page
+ offset_in_page(offset
));
332 io_mapping_unmap_atomic(reloc_page
);
338 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
340 struct drm_i915_gem_relocation_entry
*reloc
)
342 struct drm_device
*dev
= obj
->base
.dev
;
343 struct drm_gem_object
*target_obj
;
344 struct drm_i915_gem_object
*target_i915_obj
;
345 struct i915_vma
*target_vma
;
346 uint64_t target_offset
;
349 /* we've already hold a reference to all valid objects */
350 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
351 if (unlikely(target_vma
== NULL
))
353 target_i915_obj
= target_vma
->obj
;
354 target_obj
= &target_vma
->obj
->base
;
356 target_offset
= target_vma
->node
.start
;
358 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
359 * pipe_control writes because the gpu doesn't properly redirect them
360 * through the ppgtt for non_secure batchbuffers. */
361 if (unlikely(IS_GEN6(dev
) &&
362 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
&&
363 !(target_vma
->bound
& GLOBAL_BIND
)))
364 target_vma
->bind_vma(target_vma
, target_i915_obj
->cache_level
,
367 /* Validate that the target is in a valid r/w GPU domain */
368 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
369 DRM_DEBUG("reloc with multiple write domains: "
370 "obj %p target %d offset %d "
371 "read %08x write %08x",
372 obj
, reloc
->target_handle
,
375 reloc
->write_domain
);
378 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
379 & ~I915_GEM_GPU_DOMAINS
)) {
380 DRM_DEBUG("reloc with read/write non-GPU domains: "
381 "obj %p target %d offset %d "
382 "read %08x write %08x",
383 obj
, reloc
->target_handle
,
386 reloc
->write_domain
);
390 target_obj
->pending_read_domains
|= reloc
->read_domains
;
391 target_obj
->pending_write_domain
|= reloc
->write_domain
;
393 /* If the relocation already has the right value in it, no
394 * more work needs to be done.
396 if (target_offset
== reloc
->presumed_offset
)
399 /* Check that the relocation address is valid... */
400 if (unlikely(reloc
->offset
>
401 obj
->base
.size
- (INTEL_INFO(dev
)->gen
>= 8 ? 8 : 4))) {
402 DRM_DEBUG("Relocation beyond object bounds: "
403 "obj %p target %d offset %d size %d.\n",
404 obj
, reloc
->target_handle
,
406 (int) obj
->base
.size
);
409 if (unlikely(reloc
->offset
& 3)) {
410 DRM_DEBUG("Relocation not 4-byte aligned: "
411 "obj %p target %d offset %d.\n",
412 obj
, reloc
->target_handle
,
413 (int) reloc
->offset
);
417 /* We can't wait for rendering with pagefaults disabled */
418 if (obj
->active
&& in_atomic())
421 if (use_cpu_reloc(obj
))
422 ret
= relocate_entry_cpu(obj
, reloc
, target_offset
);
424 ret
= relocate_entry_gtt(obj
, reloc
, target_offset
);
429 /* and update the user's relocation entry */
430 reloc
->presumed_offset
= target_offset
;
436 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
439 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
440 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
441 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
442 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
445 user_relocs
= to_user_ptr(entry
->relocs_ptr
);
447 remain
= entry
->relocation_count
;
449 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
451 if (count
> ARRAY_SIZE(stack_reloc
))
452 count
= ARRAY_SIZE(stack_reloc
);
455 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
459 u64 offset
= r
->presumed_offset
;
461 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
);
465 if (r
->presumed_offset
!= offset
&&
466 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
468 sizeof(r
->presumed_offset
))) {
482 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
484 struct drm_i915_gem_relocation_entry
*relocs
)
486 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
489 for (i
= 0; i
< entry
->relocation_count
; i
++) {
490 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
]);
499 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
501 struct i915_vma
*vma
;
504 /* This is the fast path and we cannot handle a pagefault whilst
505 * holding the struct mutex lest the user pass in the relocations
506 * contained within a mmaped bo. For in such a case we, the page
507 * fault handler would call i915_gem_fault() and we would try to
508 * acquire the struct mutex again. Obviously this is bad and so
509 * lockdep complains vehemently.
512 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
513 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
523 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
524 struct intel_engine_cs
*ring
,
527 struct drm_i915_gem_object
*obj
= vma
->obj
;
528 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
533 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
534 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
535 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
537 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
538 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
540 ret
= i915_gem_object_pin(obj
, vma
->vm
, entry
->alignment
, flags
);
544 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
546 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
547 ret
= i915_gem_object_get_fence(obj
);
551 if (i915_gem_object_pin_fence(obj
))
552 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
555 if (entry
->offset
!= vma
->node
.start
) {
556 entry
->offset
= vma
->node
.start
;
560 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
561 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
562 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
569 need_reloc_mappable(struct i915_vma
*vma
)
571 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
573 if (entry
->relocation_count
== 0)
576 if (!i915_is_ggtt(vma
->vm
))
579 /* See also use_cpu_reloc() */
580 if (HAS_LLC(vma
->obj
->base
.dev
))
583 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
590 eb_vma_misplaced(struct i915_vma
*vma
)
592 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
593 struct drm_i915_gem_object
*obj
= vma
->obj
;
595 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
596 !i915_is_ggtt(vma
->vm
));
598 if (entry
->alignment
&&
599 vma
->node
.start
& (entry
->alignment
- 1))
602 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !obj
->map_and_fenceable
)
605 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
606 vma
->node
.start
< BATCH_OFFSET_BIAS
)
613 i915_gem_execbuffer_reserve(struct intel_engine_cs
*ring
,
614 struct list_head
*vmas
,
617 struct drm_i915_gem_object
*obj
;
618 struct i915_vma
*vma
;
619 struct i915_address_space
*vm
;
620 struct list_head ordered_vmas
;
621 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
624 i915_gem_retire_requests_ring(ring
);
626 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
628 INIT_LIST_HEAD(&ordered_vmas
);
629 while (!list_empty(vmas
)) {
630 struct drm_i915_gem_exec_object2
*entry
;
631 bool need_fence
, need_mappable
;
633 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
635 entry
= vma
->exec_entry
;
637 if (!has_fenced_gpu_access
)
638 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
640 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
641 obj
->tiling_mode
!= I915_TILING_NONE
;
642 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
645 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
646 list_move(&vma
->exec_list
, &ordered_vmas
);
648 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
650 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
651 obj
->base
.pending_write_domain
= 0;
653 list_splice(&ordered_vmas
, vmas
);
655 /* Attempt to pin all of the buffers into the GTT.
656 * This is done in 3 phases:
658 * 1a. Unbind all objects that do not match the GTT constraints for
659 * the execbuffer (fenceable, mappable, alignment etc).
660 * 1b. Increment pin count for already bound objects.
661 * 2. Bind new objects.
662 * 3. Decrement pin count.
664 * This avoid unnecessary unbinding of later objects in order to make
665 * room for the earlier objects *unless* we need to defragment.
671 /* Unbind any ill-fitting objects or pin. */
672 list_for_each_entry(vma
, vmas
, exec_list
) {
673 if (!drm_mm_node_allocated(&vma
->node
))
676 if (eb_vma_misplaced(vma
))
677 ret
= i915_vma_unbind(vma
);
679 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
684 /* Bind fresh objects */
685 list_for_each_entry(vma
, vmas
, exec_list
) {
686 if (drm_mm_node_allocated(&vma
->node
))
689 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
695 if (ret
!= -ENOSPC
|| retry
++)
698 /* Decrement pin count for bound objects */
699 list_for_each_entry(vma
, vmas
, exec_list
)
700 i915_gem_execbuffer_unreserve_vma(vma
);
702 ret
= i915_gem_evict_vm(vm
, true);
709 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
710 struct drm_i915_gem_execbuffer2
*args
,
711 struct drm_file
*file
,
712 struct intel_engine_cs
*ring
,
714 struct drm_i915_gem_exec_object2
*exec
)
716 struct drm_i915_gem_relocation_entry
*reloc
;
717 struct i915_address_space
*vm
;
718 struct i915_vma
*vma
;
722 unsigned count
= args
->buffer_count
;
724 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
726 /* We may process another execbuffer during the unlock... */
727 while (!list_empty(&eb
->vmas
)) {
728 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
729 list_del_init(&vma
->exec_list
);
730 i915_gem_execbuffer_unreserve_vma(vma
);
731 drm_gem_object_unreference(&vma
->obj
->base
);
734 mutex_unlock(&dev
->struct_mutex
);
737 for (i
= 0; i
< count
; i
++)
738 total
+= exec
[i
].relocation_count
;
740 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
741 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
742 if (reloc
== NULL
|| reloc_offset
== NULL
) {
743 drm_free_large(reloc
);
744 drm_free_large(reloc_offset
);
745 mutex_lock(&dev
->struct_mutex
);
750 for (i
= 0; i
< count
; i
++) {
751 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
752 u64 invalid_offset
= (u64
)-1;
755 user_relocs
= to_user_ptr(exec
[i
].relocs_ptr
);
757 if (copy_from_user(reloc
+total
, user_relocs
,
758 exec
[i
].relocation_count
* sizeof(*reloc
))) {
760 mutex_lock(&dev
->struct_mutex
);
764 /* As we do not update the known relocation offsets after
765 * relocating (due to the complexities in lock handling),
766 * we need to mark them as invalid now so that we force the
767 * relocation processing next time. Just in case the target
768 * object is evicted and then rebound into its old
769 * presumed_offset before the next execbuffer - if that
770 * happened we would make the mistake of assuming that the
771 * relocations were valid.
773 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
774 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
776 sizeof(invalid_offset
))) {
778 mutex_lock(&dev
->struct_mutex
);
783 reloc_offset
[i
] = total
;
784 total
+= exec
[i
].relocation_count
;
787 ret
= i915_mutex_lock_interruptible(dev
);
789 mutex_lock(&dev
->struct_mutex
);
793 /* reacquire the objects */
795 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
799 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
800 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, &need_relocs
);
804 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
805 int offset
= vma
->exec_entry
- exec
;
806 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
807 reloc
+ reloc_offset
[offset
]);
812 /* Leave the user relocations as are, this is the painfully slow path,
813 * and we want to avoid the complication of dropping the lock whilst
814 * having buffers reserved in the aperture and so causing spurious
815 * ENOSPC for random operations.
819 drm_free_large(reloc
);
820 drm_free_large(reloc_offset
);
825 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring
,
826 struct list_head
*vmas
)
828 struct i915_vma
*vma
;
829 uint32_t flush_domains
= 0;
830 bool flush_chipset
= false;
833 list_for_each_entry(vma
, vmas
, exec_list
) {
834 struct drm_i915_gem_object
*obj
= vma
->obj
;
835 ret
= i915_gem_object_sync(obj
, ring
);
839 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
840 flush_chipset
|= i915_gem_clflush_object(obj
, false);
842 flush_domains
|= obj
->base
.write_domain
;
846 i915_gem_chipset_flush(ring
->dev
);
848 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
851 /* Unconditionally invalidate gpu caches and ensure that we do flush
852 * any residual writes from the previous batch.
854 return intel_ring_invalidate_all_caches(ring
);
858 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
860 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
863 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
867 validate_exec_list(struct drm_device
*dev
,
868 struct drm_i915_gem_exec_object2
*exec
,
871 unsigned relocs_total
= 0;
872 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
873 unsigned invalid_flags
;
876 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
877 if (USES_FULL_PPGTT(dev
))
878 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
880 for (i
= 0; i
< count
; i
++) {
881 char __user
*ptr
= to_user_ptr(exec
[i
].relocs_ptr
);
882 int length
; /* limited by fault_in_pages_readable() */
884 if (exec
[i
].flags
& invalid_flags
)
887 /* First check for malicious input causing overflow in
888 * the worst case where we need to allocate the entire
889 * relocation tree as a single array.
891 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
893 relocs_total
+= exec
[i
].relocation_count
;
895 length
= exec
[i
].relocation_count
*
896 sizeof(struct drm_i915_gem_relocation_entry
);
898 * We must check that the entire relocation array is safe
899 * to read, but since we may need to update the presumed
900 * offsets during execution, check for full write access.
902 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
905 if (likely(!i915
.prefault_disable
)) {
906 if (fault_in_multipages_readable(ptr
, length
))
914 static struct intel_context
*
915 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
916 struct intel_engine_cs
*ring
, const u32 ctx_id
)
918 struct intel_context
*ctx
= NULL
;
919 struct i915_ctx_hang_stats
*hs
;
921 if (ring
->id
!= RCS
&& ctx_id
!= DEFAULT_CONTEXT_HANDLE
)
922 return ERR_PTR(-EINVAL
);
924 ctx
= i915_gem_context_get(file
->driver_priv
, ctx_id
);
928 hs
= &ctx
->hang_stats
;
930 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
931 return ERR_PTR(-EIO
);
934 if (i915
.enable_execlists
&& !ctx
->engine
[ring
->id
].state
) {
935 int ret
= intel_lr_context_deferred_create(ctx
, ring
);
937 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id
, ret
);
946 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
947 struct intel_engine_cs
*ring
)
949 struct drm_i915_gem_request
*req
= intel_ring_get_request(ring
);
950 struct i915_vma
*vma
;
952 list_for_each_entry(vma
, vmas
, exec_list
) {
953 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
954 struct drm_i915_gem_object
*obj
= vma
->obj
;
955 u32 old_read
= obj
->base
.read_domains
;
956 u32 old_write
= obj
->base
.write_domain
;
958 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
959 if (obj
->base
.write_domain
== 0)
960 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
961 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
963 i915_vma_move_to_active(vma
, ring
);
964 if (obj
->base
.write_domain
) {
966 i915_gem_request_assign(&obj
->last_write_req
, req
);
968 intel_fb_obj_invalidate(obj
, ring
);
970 /* update for the implicit flush after a batch */
971 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
973 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
974 i915_gem_request_assign(&obj
->last_fenced_req
, req
);
975 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
976 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
977 list_move_tail(&dev_priv
->fence_regs
[obj
->fence_reg
].lru_list
,
978 &dev_priv
->mm
.fence_list
);
982 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
987 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
988 struct drm_file
*file
,
989 struct intel_engine_cs
*ring
,
990 struct drm_i915_gem_object
*obj
)
992 /* Unconditionally force add_request to emit a full flush. */
993 ring
->gpu_caches_dirty
= true;
995 /* Add a breadcrumb for the completion of the batch buffer */
996 (void)__i915_add_request(ring
, file
, obj
);
1000 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
1001 struct intel_engine_cs
*ring
)
1003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1006 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
]) {
1007 DRM_DEBUG("sol reset is gen7/rcs only\n");
1011 ret
= intel_ring_begin(ring
, 4 * 3);
1015 for (i
= 0; i
< 4; i
++) {
1016 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1017 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
1018 intel_ring_emit(ring
, 0);
1021 intel_ring_advance(ring
);
1027 i915_emit_box(struct intel_engine_cs
*ring
,
1028 struct drm_clip_rect
*box
,
1033 if (box
->y2
<= box
->y1
|| box
->x2
<= box
->x1
||
1034 box
->y2
<= 0 || box
->x2
<= 0) {
1035 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1036 box
->x1
, box
->y1
, box
->x2
, box
->y2
);
1040 if (INTEL_INFO(ring
->dev
)->gen
>= 4) {
1041 ret
= intel_ring_begin(ring
, 4);
1045 intel_ring_emit(ring
, GFX_OP_DRAWRECT_INFO_I965
);
1046 intel_ring_emit(ring
, (box
->x1
& 0xffff) | box
->y1
<< 16);
1047 intel_ring_emit(ring
, ((box
->x2
- 1) & 0xffff) | (box
->y2
- 1) << 16);
1048 intel_ring_emit(ring
, DR4
);
1050 ret
= intel_ring_begin(ring
, 6);
1054 intel_ring_emit(ring
, GFX_OP_DRAWRECT_INFO
);
1055 intel_ring_emit(ring
, DR1
);
1056 intel_ring_emit(ring
, (box
->x1
& 0xffff) | box
->y1
<< 16);
1057 intel_ring_emit(ring
, ((box
->x2
- 1) & 0xffff) | (box
->y2
- 1) << 16);
1058 intel_ring_emit(ring
, DR4
);
1059 intel_ring_emit(ring
, 0);
1061 intel_ring_advance(ring
);
1068 i915_gem_ringbuffer_submission(struct drm_device
*dev
, struct drm_file
*file
,
1069 struct intel_engine_cs
*ring
,
1070 struct intel_context
*ctx
,
1071 struct drm_i915_gem_execbuffer2
*args
,
1072 struct list_head
*vmas
,
1073 struct drm_i915_gem_object
*batch_obj
,
1074 u64 exec_start
, u32 flags
)
1076 struct drm_clip_rect
*cliprects
= NULL
;
1077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1083 if (args
->num_cliprects
!= 0) {
1084 if (ring
!= &dev_priv
->ring
[RCS
]) {
1085 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1089 if (INTEL_INFO(dev
)->gen
>= 5) {
1090 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1094 if (args
->num_cliprects
> UINT_MAX
/ sizeof(*cliprects
)) {
1095 DRM_DEBUG("execbuf with %u cliprects\n",
1096 args
->num_cliprects
);
1100 cliprects
= kcalloc(args
->num_cliprects
,
1103 if (cliprects
== NULL
) {
1108 if (copy_from_user(cliprects
,
1109 to_user_ptr(args
->cliprects_ptr
),
1110 sizeof(*cliprects
)*args
->num_cliprects
)) {
1115 if (args
->DR4
== 0xffffffff) {
1116 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1120 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
1121 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1126 ret
= i915_gem_execbuffer_move_to_gpu(ring
, vmas
);
1130 ret
= i915_switch_context(ring
, ctx
);
1134 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1135 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1136 switch (instp_mode
) {
1137 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1138 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1139 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1140 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
1141 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1146 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1147 if (INTEL_INFO(dev
)->gen
< 4) {
1148 DRM_DEBUG("no rel constants on pre-gen4\n");
1153 if (INTEL_INFO(dev
)->gen
> 5 &&
1154 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1155 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1160 /* The HW changed the meaning on this bit on gen6 */
1161 if (INTEL_INFO(dev
)->gen
>= 6)
1162 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1166 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1171 if (ring
== &dev_priv
->ring
[RCS
] &&
1172 instp_mode
!= dev_priv
->relative_constants_mode
) {
1173 ret
= intel_ring_begin(ring
, 4);
1177 intel_ring_emit(ring
, MI_NOOP
);
1178 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1179 intel_ring_emit(ring
, INSTPM
);
1180 intel_ring_emit(ring
, instp_mask
<< 16 | instp_mode
);
1181 intel_ring_advance(ring
);
1183 dev_priv
->relative_constants_mode
= instp_mode
;
1186 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1187 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1192 exec_len
= args
->batch_len
;
1194 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1195 ret
= i915_emit_box(ring
, &cliprects
[i
],
1196 args
->DR1
, args
->DR4
);
1200 ret
= ring
->dispatch_execbuffer(ring
,
1201 exec_start
, exec_len
,
1207 ret
= ring
->dispatch_execbuffer(ring
,
1208 exec_start
, exec_len
,
1214 trace_i915_gem_ring_dispatch(ring
,
1215 i915_gem_request_get_seqno(intel_ring_get_request(ring
)),
1218 i915_gem_execbuffer_move_to_active(vmas
, ring
);
1219 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
1227 * Find one BSD ring to dispatch the corresponding BSD command.
1228 * The Ring ID is returned.
1230 static int gen8_dispatch_bsd_ring(struct drm_device
*dev
,
1231 struct drm_file
*file
)
1233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1234 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1236 /* Check whether the file_priv is using one ring */
1237 if (file_priv
->bsd_ring
)
1238 return file_priv
->bsd_ring
->id
;
1240 /* If no, use the ping-pong mechanism to select one ring */
1243 mutex_lock(&dev
->struct_mutex
);
1244 if (dev_priv
->mm
.bsd_ring_dispatch_index
== 0) {
1246 dev_priv
->mm
.bsd_ring_dispatch_index
= 1;
1249 dev_priv
->mm
.bsd_ring_dispatch_index
= 0;
1251 file_priv
->bsd_ring
= &dev_priv
->ring
[ring_id
];
1252 mutex_unlock(&dev
->struct_mutex
);
1257 static struct drm_i915_gem_object
*
1258 eb_get_batch(struct eb_vmas
*eb
)
1260 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
1263 * SNA is doing fancy tricks with compressing batch buffers, which leads
1264 * to negative relocation deltas. Usually that works out ok since the
1265 * relocate address is still positive, except when the batch is placed
1266 * very low in the GTT. Ensure this doesn't happen.
1268 * Note that actual hangs have only been observed on gen7, but for
1269 * paranoia do it everywhere.
1271 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
1277 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1278 struct drm_file
*file
,
1279 struct drm_i915_gem_execbuffer2
*args
,
1280 struct drm_i915_gem_exec_object2
*exec
)
1282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1284 struct drm_i915_gem_object
*batch_obj
;
1285 struct intel_engine_cs
*ring
;
1286 struct intel_context
*ctx
;
1287 struct i915_address_space
*vm
;
1288 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1289 u64 exec_start
= args
->batch_start_offset
;
1294 if (!i915_gem_check_execbuffer(args
))
1297 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1302 if (args
->flags
& I915_EXEC_SECURE
) {
1303 if (!file
->is_master
|| !capable(CAP_SYS_ADMIN
))
1306 flags
|= I915_DISPATCH_SECURE
;
1308 if (args
->flags
& I915_EXEC_IS_PINNED
)
1309 flags
|= I915_DISPATCH_PINNED
;
1311 if ((args
->flags
& I915_EXEC_RING_MASK
) > LAST_USER_RING
) {
1312 DRM_DEBUG("execbuf with unknown ring: %d\n",
1313 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1317 if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_DEFAULT
)
1318 ring
= &dev_priv
->ring
[RCS
];
1319 else if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_BSD
) {
1320 if (HAS_BSD2(dev
)) {
1322 ring_id
= gen8_dispatch_bsd_ring(dev
, file
);
1323 ring
= &dev_priv
->ring
[ring_id
];
1325 ring
= &dev_priv
->ring
[VCS
];
1327 ring
= &dev_priv
->ring
[(args
->flags
& I915_EXEC_RING_MASK
) - 1];
1329 if (!intel_ring_initialized(ring
)) {
1330 DRM_DEBUG("execbuf with invalid ring: %d\n",
1331 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1335 if (args
->buffer_count
< 1) {
1336 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1340 intel_runtime_pm_get(dev_priv
);
1342 ret
= i915_mutex_lock_interruptible(dev
);
1346 ctx
= i915_gem_validate_context(dev
, file
, ring
, ctx_id
);
1348 mutex_unlock(&dev
->struct_mutex
);
1353 i915_gem_context_reference(ctx
);
1356 vm
= &ctx
->ppgtt
->base
;
1358 vm
= &dev_priv
->gtt
.base
;
1360 eb
= eb_create(args
);
1362 i915_gem_context_unreference(ctx
);
1363 mutex_unlock(&dev
->struct_mutex
);
1368 /* Look up object handles */
1369 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1373 /* take note of the batch buffer before we might reorder the lists */
1374 batch_obj
= eb_get_batch(eb
);
1376 /* Move the objects en-masse into the GTT, evicting if necessary. */
1377 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1378 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, &need_relocs
);
1382 /* The objects are in their final locations, apply the relocations. */
1384 ret
= i915_gem_execbuffer_relocate(eb
);
1386 if (ret
== -EFAULT
) {
1387 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
, ring
,
1389 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1395 /* Set the pending read domains for the batch buffer to COMMAND */
1396 if (batch_obj
->base
.pending_write_domain
) {
1397 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1401 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1403 if (i915_needs_cmd_parser(ring
)) {
1404 ret
= i915_parse_cmds(ring
,
1406 args
->batch_start_offset
,
1413 * XXX: Actually do this when enabling batch copy...
1415 * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
1416 * from MI_BATCH_BUFFER_START commands issued in the
1417 * dispatch_execbuffer implementations. We specifically don't
1418 * want that set when the command parser is enabled.
1423 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1424 * batch" bit. Hence we need to pin secure batches into the global gtt.
1425 * hsw should have this fixed, but bdw mucks it up again. */
1426 if (flags
& I915_DISPATCH_SECURE
) {
1428 * So on first glance it looks freaky that we pin the batch here
1429 * outside of the reservation loop. But:
1430 * - The batch is already pinned into the relevant ppgtt, so we
1431 * already have the backing storage fully allocated.
1432 * - No other BO uses the global gtt (well contexts, but meh),
1433 * so we don't really have issues with mutliple objects not
1434 * fitting due to fragmentation.
1435 * So this is actually safe.
1437 ret
= i915_gem_obj_ggtt_pin(batch_obj
, 0, 0);
1441 exec_start
+= i915_gem_obj_ggtt_offset(batch_obj
);
1443 exec_start
+= i915_gem_obj_offset(batch_obj
, vm
);
1445 ret
= dev_priv
->gt
.do_execbuf(dev
, file
, ring
, ctx
, args
,
1446 &eb
->vmas
, batch_obj
, exec_start
, flags
);
1449 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1450 * batch vma for correctness. For less ugly and less fragility this
1451 * needs to be adjusted to also track the ggtt batch vma properly as
1454 if (flags
& I915_DISPATCH_SECURE
)
1455 i915_gem_object_ggtt_unpin(batch_obj
);
1457 /* the request owns the ref now */
1458 i915_gem_context_unreference(ctx
);
1461 mutex_unlock(&dev
->struct_mutex
);
1464 /* intel_gpu_busy should also get a ref, so it will free when the device
1465 * is really idle. */
1466 intel_runtime_pm_put(dev_priv
);
1471 * Legacy execbuffer just creates an exec2 list from the original exec object
1472 * list array and passes it to the real function.
1475 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1476 struct drm_file
*file
)
1478 struct drm_i915_gem_execbuffer
*args
= data
;
1479 struct drm_i915_gem_execbuffer2 exec2
;
1480 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1481 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1484 if (args
->buffer_count
< 1) {
1485 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1489 /* Copy in the exec list from userland */
1490 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1491 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1492 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1493 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1494 args
->buffer_count
);
1495 drm_free_large(exec_list
);
1496 drm_free_large(exec2_list
);
1499 ret
= copy_from_user(exec_list
,
1500 to_user_ptr(args
->buffers_ptr
),
1501 sizeof(*exec_list
) * args
->buffer_count
);
1503 DRM_DEBUG("copy %d exec entries failed %d\n",
1504 args
->buffer_count
, ret
);
1505 drm_free_large(exec_list
);
1506 drm_free_large(exec2_list
);
1510 for (i
= 0; i
< args
->buffer_count
; i
++) {
1511 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1512 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1513 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1514 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1515 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1516 if (INTEL_INFO(dev
)->gen
< 4)
1517 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1519 exec2_list
[i
].flags
= 0;
1522 exec2
.buffers_ptr
= args
->buffers_ptr
;
1523 exec2
.buffer_count
= args
->buffer_count
;
1524 exec2
.batch_start_offset
= args
->batch_start_offset
;
1525 exec2
.batch_len
= args
->batch_len
;
1526 exec2
.DR1
= args
->DR1
;
1527 exec2
.DR4
= args
->DR4
;
1528 exec2
.num_cliprects
= args
->num_cliprects
;
1529 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1530 exec2
.flags
= I915_EXEC_RENDER
;
1531 i915_execbuffer2_set_context_id(exec2
, 0);
1533 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1535 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1536 to_user_ptr(args
->buffers_ptr
);
1538 /* Copy the new buffer offsets back to the user's exec list. */
1539 for (i
= 0; i
< args
->buffer_count
; i
++) {
1540 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1541 &exec2_list
[i
].offset
,
1542 sizeof(user_exec_list
[i
].offset
));
1545 DRM_DEBUG("failed to copy %d exec entries "
1546 "back to user (%d)\n",
1547 args
->buffer_count
, ret
);
1553 drm_free_large(exec_list
);
1554 drm_free_large(exec2_list
);
1559 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1560 struct drm_file
*file
)
1562 struct drm_i915_gem_execbuffer2
*args
= data
;
1563 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1566 if (args
->buffer_count
< 1 ||
1567 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1568 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1572 if (args
->rsvd2
!= 0) {
1573 DRM_DEBUG("dirty rvsd2 field\n");
1577 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1578 GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
1579 if (exec2_list
== NULL
)
1580 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1581 args
->buffer_count
);
1582 if (exec2_list
== NULL
) {
1583 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1584 args
->buffer_count
);
1587 ret
= copy_from_user(exec2_list
,
1588 to_user_ptr(args
->buffers_ptr
),
1589 sizeof(*exec2_list
) * args
->buffer_count
);
1591 DRM_DEBUG("copy %d exec entries failed %d\n",
1592 args
->buffer_count
, ret
);
1593 drm_free_large(exec2_list
);
1597 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1599 /* Copy the new buffer offsets back to the user's exec list. */
1600 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1601 to_user_ptr(args
->buffers_ptr
);
1604 for (i
= 0; i
< args
->buffer_count
; i
++) {
1605 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1606 &exec2_list
[i
].offset
,
1607 sizeof(user_exec_list
[i
].offset
));
1610 DRM_DEBUG("failed to copy %d exec entries "
1612 args
->buffer_count
);
1618 drm_free_large(exec2_list
);