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drm/i915: Early alloc request in execbuff
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
40
41 #define BATCH_OFFSET_BIAS (256*1024)
42
43 struct eb_vmas {
44 struct list_head vmas;
45 int and;
46 union {
47 struct i915_vma *lut[0];
48 struct hlist_head buckets[0];
49 };
50 };
51
52 static struct eb_vmas *
53 eb_create(struct drm_i915_gem_execbuffer2 *args)
54 {
55 struct eb_vmas *eb = NULL;
56
57 if (args->flags & I915_EXEC_HANDLE_LUT) {
58 unsigned size = args->buffer_count;
59 size *= sizeof(struct i915_vma *);
60 size += sizeof(struct eb_vmas);
61 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
62 }
63
64 if (eb == NULL) {
65 unsigned size = args->buffer_count;
66 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
67 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
68 while (count > 2*size)
69 count >>= 1;
70 eb = kzalloc(count*sizeof(struct hlist_head) +
71 sizeof(struct eb_vmas),
72 GFP_TEMPORARY);
73 if (eb == NULL)
74 return eb;
75
76 eb->and = count - 1;
77 } else
78 eb->and = -args->buffer_count;
79
80 INIT_LIST_HEAD(&eb->vmas);
81 return eb;
82 }
83
84 static void
85 eb_reset(struct eb_vmas *eb)
86 {
87 if (eb->and >= 0)
88 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
89 }
90
91 static int
92 eb_lookup_vmas(struct eb_vmas *eb,
93 struct drm_i915_gem_exec_object2 *exec,
94 const struct drm_i915_gem_execbuffer2 *args,
95 struct i915_address_space *vm,
96 struct drm_file *file)
97 {
98 struct drm_i915_gem_object *obj;
99 struct list_head objects;
100 int i, ret;
101
102 INIT_LIST_HEAD(&objects);
103 spin_lock(&file->table_lock);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i = 0; i < args->buffer_count; i++) {
107 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
108 if (obj == NULL) {
109 spin_unlock(&file->table_lock);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
111 exec[i].handle, i);
112 ret = -ENOENT;
113 goto err;
114 }
115
116 if (!list_empty(&obj->obj_exec_link)) {
117 spin_unlock(&file->table_lock);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj, exec[i].handle, i);
120 ret = -EINVAL;
121 goto err;
122 }
123
124 drm_gem_object_reference(&obj->base);
125 list_add_tail(&obj->obj_exec_link, &objects);
126 }
127 spin_unlock(&file->table_lock);
128
129 i = 0;
130 while (!list_empty(&objects)) {
131 struct i915_vma *vma;
132
133 obj = list_first_entry(&objects,
134 struct drm_i915_gem_object,
135 obj_exec_link);
136
137 /*
138 * NOTE: We can leak any vmas created here when something fails
139 * later on. But that's no issue since vma_unbind can deal with
140 * vmas which are not actually bound. And since only
141 * lookup_or_create exists as an interface to get at the vma
142 * from the (obj, vm) we don't run the risk of creating
143 * duplicated vmas for the same vm.
144 */
145 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
146 if (IS_ERR(vma)) {
147 DRM_DEBUG("Failed to lookup VMA\n");
148 ret = PTR_ERR(vma);
149 goto err;
150 }
151
152 /* Transfer ownership from the objects list to the vmas list. */
153 list_add_tail(&vma->exec_list, &eb->vmas);
154 list_del_init(&obj->obj_exec_link);
155
156 vma->exec_entry = &exec[i];
157 if (eb->and < 0) {
158 eb->lut[i] = vma;
159 } else {
160 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
161 vma->exec_handle = handle;
162 hlist_add_head(&vma->exec_node,
163 &eb->buckets[handle & eb->and]);
164 }
165 ++i;
166 }
167
168 return 0;
169
170
171 err:
172 while (!list_empty(&objects)) {
173 obj = list_first_entry(&objects,
174 struct drm_i915_gem_object,
175 obj_exec_link);
176 list_del_init(&obj->obj_exec_link);
177 drm_gem_object_unreference(&obj->base);
178 }
179 /*
180 * Objects already transfered to the vmas list will be unreferenced by
181 * eb_destroy.
182 */
183
184 return ret;
185 }
186
187 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
188 {
189 if (eb->and < 0) {
190 if (handle >= -eb->and)
191 return NULL;
192 return eb->lut[handle];
193 } else {
194 struct hlist_head *head;
195 struct hlist_node *node;
196
197 head = &eb->buckets[handle & eb->and];
198 hlist_for_each(node, head) {
199 struct i915_vma *vma;
200
201 vma = hlist_entry(node, struct i915_vma, exec_node);
202 if (vma->exec_handle == handle)
203 return vma;
204 }
205 return NULL;
206 }
207 }
208
209 static void
210 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
211 {
212 struct drm_i915_gem_exec_object2 *entry;
213 struct drm_i915_gem_object *obj = vma->obj;
214
215 if (!drm_mm_node_allocated(&vma->node))
216 return;
217
218 entry = vma->exec_entry;
219
220 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
221 i915_gem_object_unpin_fence(obj);
222
223 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
224 vma->pin_count--;
225
226 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
227 }
228
229 static void eb_destroy(struct eb_vmas *eb)
230 {
231 while (!list_empty(&eb->vmas)) {
232 struct i915_vma *vma;
233
234 vma = list_first_entry(&eb->vmas,
235 struct i915_vma,
236 exec_list);
237 list_del_init(&vma->exec_list);
238 i915_gem_execbuffer_unreserve_vma(vma);
239 drm_gem_object_unreference(&vma->obj->base);
240 }
241 kfree(eb);
242 }
243
244 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
245 {
246 return (HAS_LLC(obj->base.dev) ||
247 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
248 obj->cache_level != I915_CACHE_NONE);
249 }
250
251 static int
252 relocate_entry_cpu(struct drm_i915_gem_object *obj,
253 struct drm_i915_gem_relocation_entry *reloc,
254 uint64_t target_offset)
255 {
256 struct drm_device *dev = obj->base.dev;
257 uint32_t page_offset = offset_in_page(reloc->offset);
258 uint64_t delta = reloc->delta + target_offset;
259 char *vaddr;
260 int ret;
261
262 ret = i915_gem_object_set_to_cpu_domain(obj, true);
263 if (ret)
264 return ret;
265
266 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
267 reloc->offset >> PAGE_SHIFT));
268 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
269
270 if (INTEL_INFO(dev)->gen >= 8) {
271 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
272
273 if (page_offset == 0) {
274 kunmap_atomic(vaddr);
275 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
276 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
277 }
278
279 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
280 }
281
282 kunmap_atomic(vaddr);
283
284 return 0;
285 }
286
287 static int
288 relocate_entry_gtt(struct drm_i915_gem_object *obj,
289 struct drm_i915_gem_relocation_entry *reloc,
290 uint64_t target_offset)
291 {
292 struct drm_device *dev = obj->base.dev;
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 uint64_t delta = reloc->delta + target_offset;
295 uint64_t offset;
296 void __iomem *reloc_page;
297 int ret;
298
299 ret = i915_gem_object_set_to_gtt_domain(obj, true);
300 if (ret)
301 return ret;
302
303 ret = i915_gem_object_put_fence(obj);
304 if (ret)
305 return ret;
306
307 /* Map the page containing the relocation we're going to perform. */
308 offset = i915_gem_obj_ggtt_offset(obj);
309 offset += reloc->offset;
310 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
311 offset & PAGE_MASK);
312 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
313
314 if (INTEL_INFO(dev)->gen >= 8) {
315 offset += sizeof(uint32_t);
316
317 if (offset_in_page(offset) == 0) {
318 io_mapping_unmap_atomic(reloc_page);
319 reloc_page =
320 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
321 offset);
322 }
323
324 iowrite32(upper_32_bits(delta),
325 reloc_page + offset_in_page(offset));
326 }
327
328 io_mapping_unmap_atomic(reloc_page);
329
330 return 0;
331 }
332
333 static void
334 clflush_write32(void *addr, uint32_t value)
335 {
336 /* This is not a fast path, so KISS. */
337 drm_clflush_virt_range(addr, sizeof(uint32_t));
338 *(uint32_t *)addr = value;
339 drm_clflush_virt_range(addr, sizeof(uint32_t));
340 }
341
342 static int
343 relocate_entry_clflush(struct drm_i915_gem_object *obj,
344 struct drm_i915_gem_relocation_entry *reloc,
345 uint64_t target_offset)
346 {
347 struct drm_device *dev = obj->base.dev;
348 uint32_t page_offset = offset_in_page(reloc->offset);
349 uint64_t delta = (int)reloc->delta + target_offset;
350 char *vaddr;
351 int ret;
352
353 ret = i915_gem_object_set_to_gtt_domain(obj, true);
354 if (ret)
355 return ret;
356
357 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
358 reloc->offset >> PAGE_SHIFT));
359 clflush_write32(vaddr + page_offset, lower_32_bits(delta));
360
361 if (INTEL_INFO(dev)->gen >= 8) {
362 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
363
364 if (page_offset == 0) {
365 kunmap_atomic(vaddr);
366 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
367 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
368 }
369
370 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
371 }
372
373 kunmap_atomic(vaddr);
374
375 return 0;
376 }
377
378 static int
379 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
380 struct eb_vmas *eb,
381 struct drm_i915_gem_relocation_entry *reloc)
382 {
383 struct drm_device *dev = obj->base.dev;
384 struct drm_gem_object *target_obj;
385 struct drm_i915_gem_object *target_i915_obj;
386 struct i915_vma *target_vma;
387 uint64_t target_offset;
388 int ret;
389
390 /* we've already hold a reference to all valid objects */
391 target_vma = eb_get_vma(eb, reloc->target_handle);
392 if (unlikely(target_vma == NULL))
393 return -ENOENT;
394 target_i915_obj = target_vma->obj;
395 target_obj = &target_vma->obj->base;
396
397 target_offset = target_vma->node.start;
398
399 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
400 * pipe_control writes because the gpu doesn't properly redirect them
401 * through the ppgtt for non_secure batchbuffers. */
402 if (unlikely(IS_GEN6(dev) &&
403 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
404 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
405 PIN_GLOBAL);
406 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
407 return ret;
408 }
409
410 /* Validate that the target is in a valid r/w GPU domain */
411 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
412 DRM_DEBUG("reloc with multiple write domains: "
413 "obj %p target %d offset %d "
414 "read %08x write %08x",
415 obj, reloc->target_handle,
416 (int) reloc->offset,
417 reloc->read_domains,
418 reloc->write_domain);
419 return -EINVAL;
420 }
421 if (unlikely((reloc->write_domain | reloc->read_domains)
422 & ~I915_GEM_GPU_DOMAINS)) {
423 DRM_DEBUG("reloc with read/write non-GPU domains: "
424 "obj %p target %d offset %d "
425 "read %08x write %08x",
426 obj, reloc->target_handle,
427 (int) reloc->offset,
428 reloc->read_domains,
429 reloc->write_domain);
430 return -EINVAL;
431 }
432
433 target_obj->pending_read_domains |= reloc->read_domains;
434 target_obj->pending_write_domain |= reloc->write_domain;
435
436 /* If the relocation already has the right value in it, no
437 * more work needs to be done.
438 */
439 if (target_offset == reloc->presumed_offset)
440 return 0;
441
442 /* Check that the relocation address is valid... */
443 if (unlikely(reloc->offset >
444 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
445 DRM_DEBUG("Relocation beyond object bounds: "
446 "obj %p target %d offset %d size %d.\n",
447 obj, reloc->target_handle,
448 (int) reloc->offset,
449 (int) obj->base.size);
450 return -EINVAL;
451 }
452 if (unlikely(reloc->offset & 3)) {
453 DRM_DEBUG("Relocation not 4-byte aligned: "
454 "obj %p target %d offset %d.\n",
455 obj, reloc->target_handle,
456 (int) reloc->offset);
457 return -EINVAL;
458 }
459
460 /* We can't wait for rendering with pagefaults disabled */
461 if (obj->active && in_atomic())
462 return -EFAULT;
463
464 if (use_cpu_reloc(obj))
465 ret = relocate_entry_cpu(obj, reloc, target_offset);
466 else if (obj->map_and_fenceable)
467 ret = relocate_entry_gtt(obj, reloc, target_offset);
468 else if (cpu_has_clflush)
469 ret = relocate_entry_clflush(obj, reloc, target_offset);
470 else {
471 WARN_ONCE(1, "Impossible case in relocation handling\n");
472 ret = -ENODEV;
473 }
474
475 if (ret)
476 return ret;
477
478 /* and update the user's relocation entry */
479 reloc->presumed_offset = target_offset;
480
481 return 0;
482 }
483
484 static int
485 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
486 struct eb_vmas *eb)
487 {
488 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
489 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
490 struct drm_i915_gem_relocation_entry __user *user_relocs;
491 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
492 int remain, ret;
493
494 user_relocs = to_user_ptr(entry->relocs_ptr);
495
496 remain = entry->relocation_count;
497 while (remain) {
498 struct drm_i915_gem_relocation_entry *r = stack_reloc;
499 int count = remain;
500 if (count > ARRAY_SIZE(stack_reloc))
501 count = ARRAY_SIZE(stack_reloc);
502 remain -= count;
503
504 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
505 return -EFAULT;
506
507 do {
508 u64 offset = r->presumed_offset;
509
510 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
511 if (ret)
512 return ret;
513
514 if (r->presumed_offset != offset &&
515 __copy_to_user_inatomic(&user_relocs->presumed_offset,
516 &r->presumed_offset,
517 sizeof(r->presumed_offset))) {
518 return -EFAULT;
519 }
520
521 user_relocs++;
522 r++;
523 } while (--count);
524 }
525
526 return 0;
527 #undef N_RELOC
528 }
529
530 static int
531 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
532 struct eb_vmas *eb,
533 struct drm_i915_gem_relocation_entry *relocs)
534 {
535 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
536 int i, ret;
537
538 for (i = 0; i < entry->relocation_count; i++) {
539 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
540 if (ret)
541 return ret;
542 }
543
544 return 0;
545 }
546
547 static int
548 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
549 {
550 struct i915_vma *vma;
551 int ret = 0;
552
553 /* This is the fast path and we cannot handle a pagefault whilst
554 * holding the struct mutex lest the user pass in the relocations
555 * contained within a mmaped bo. For in such a case we, the page
556 * fault handler would call i915_gem_fault() and we would try to
557 * acquire the struct mutex again. Obviously this is bad and so
558 * lockdep complains vehemently.
559 */
560 pagefault_disable();
561 list_for_each_entry(vma, &eb->vmas, exec_list) {
562 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
563 if (ret)
564 break;
565 }
566 pagefault_enable();
567
568 return ret;
569 }
570
571 static bool only_mappable_for_reloc(unsigned int flags)
572 {
573 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
574 __EXEC_OBJECT_NEEDS_MAP;
575 }
576
577 static int
578 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
579 struct intel_engine_cs *ring,
580 bool *need_reloc)
581 {
582 struct drm_i915_gem_object *obj = vma->obj;
583 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
584 uint64_t flags;
585 int ret;
586
587 flags = PIN_USER;
588 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
589 flags |= PIN_GLOBAL;
590
591 if (!drm_mm_node_allocated(&vma->node)) {
592 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
593 flags |= PIN_GLOBAL | PIN_MAPPABLE;
594 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
595 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
596 }
597
598 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
599 if ((ret == -ENOSPC || ret == -E2BIG) &&
600 only_mappable_for_reloc(entry->flags))
601 ret = i915_gem_object_pin(obj, vma->vm,
602 entry->alignment,
603 flags & ~PIN_MAPPABLE);
604 if (ret)
605 return ret;
606
607 entry->flags |= __EXEC_OBJECT_HAS_PIN;
608
609 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
610 ret = i915_gem_object_get_fence(obj);
611 if (ret)
612 return ret;
613
614 if (i915_gem_object_pin_fence(obj))
615 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
616 }
617
618 if (entry->offset != vma->node.start) {
619 entry->offset = vma->node.start;
620 *need_reloc = true;
621 }
622
623 if (entry->flags & EXEC_OBJECT_WRITE) {
624 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
625 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
626 }
627
628 return 0;
629 }
630
631 static bool
632 need_reloc_mappable(struct i915_vma *vma)
633 {
634 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
635
636 if (entry->relocation_count == 0)
637 return false;
638
639 if (!i915_is_ggtt(vma->vm))
640 return false;
641
642 /* See also use_cpu_reloc() */
643 if (HAS_LLC(vma->obj->base.dev))
644 return false;
645
646 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
647 return false;
648
649 return true;
650 }
651
652 static bool
653 eb_vma_misplaced(struct i915_vma *vma)
654 {
655 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
656 struct drm_i915_gem_object *obj = vma->obj;
657
658 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
659 !i915_is_ggtt(vma->vm));
660
661 if (entry->alignment &&
662 vma->node.start & (entry->alignment - 1))
663 return true;
664
665 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
666 vma->node.start < BATCH_OFFSET_BIAS)
667 return true;
668
669 /* avoid costly ping-pong once a batch bo ended up non-mappable */
670 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
671 return !only_mappable_for_reloc(entry->flags);
672
673 return false;
674 }
675
676 static int
677 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
678 struct list_head *vmas,
679 struct intel_context *ctx,
680 bool *need_relocs)
681 {
682 struct drm_i915_gem_object *obj;
683 struct i915_vma *vma;
684 struct i915_address_space *vm;
685 struct list_head ordered_vmas;
686 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
687 int retry;
688
689 i915_gem_retire_requests_ring(ring);
690
691 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
692
693 INIT_LIST_HEAD(&ordered_vmas);
694 while (!list_empty(vmas)) {
695 struct drm_i915_gem_exec_object2 *entry;
696 bool need_fence, need_mappable;
697
698 vma = list_first_entry(vmas, struct i915_vma, exec_list);
699 obj = vma->obj;
700 entry = vma->exec_entry;
701
702 if (ctx->flags & CONTEXT_NO_ZEROMAP)
703 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
704
705 if (!has_fenced_gpu_access)
706 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
707 need_fence =
708 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
709 obj->tiling_mode != I915_TILING_NONE;
710 need_mappable = need_fence || need_reloc_mappable(vma);
711
712 if (need_mappable) {
713 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
714 list_move(&vma->exec_list, &ordered_vmas);
715 } else
716 list_move_tail(&vma->exec_list, &ordered_vmas);
717
718 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
719 obj->base.pending_write_domain = 0;
720 }
721 list_splice(&ordered_vmas, vmas);
722
723 /* Attempt to pin all of the buffers into the GTT.
724 * This is done in 3 phases:
725 *
726 * 1a. Unbind all objects that do not match the GTT constraints for
727 * the execbuffer (fenceable, mappable, alignment etc).
728 * 1b. Increment pin count for already bound objects.
729 * 2. Bind new objects.
730 * 3. Decrement pin count.
731 *
732 * This avoid unnecessary unbinding of later objects in order to make
733 * room for the earlier objects *unless* we need to defragment.
734 */
735 retry = 0;
736 do {
737 int ret = 0;
738
739 /* Unbind any ill-fitting objects or pin. */
740 list_for_each_entry(vma, vmas, exec_list) {
741 if (!drm_mm_node_allocated(&vma->node))
742 continue;
743
744 if (eb_vma_misplaced(vma))
745 ret = i915_vma_unbind(vma);
746 else
747 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
748 if (ret)
749 goto err;
750 }
751
752 /* Bind fresh objects */
753 list_for_each_entry(vma, vmas, exec_list) {
754 if (drm_mm_node_allocated(&vma->node))
755 continue;
756
757 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
758 if (ret)
759 goto err;
760 }
761
762 err:
763 if (ret != -ENOSPC || retry++)
764 return ret;
765
766 /* Decrement pin count for bound objects */
767 list_for_each_entry(vma, vmas, exec_list)
768 i915_gem_execbuffer_unreserve_vma(vma);
769
770 ret = i915_gem_evict_vm(vm, true);
771 if (ret)
772 return ret;
773 } while (1);
774 }
775
776 static int
777 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
778 struct drm_i915_gem_execbuffer2 *args,
779 struct drm_file *file,
780 struct intel_engine_cs *ring,
781 struct eb_vmas *eb,
782 struct drm_i915_gem_exec_object2 *exec,
783 struct intel_context *ctx)
784 {
785 struct drm_i915_gem_relocation_entry *reloc;
786 struct i915_address_space *vm;
787 struct i915_vma *vma;
788 bool need_relocs;
789 int *reloc_offset;
790 int i, total, ret;
791 unsigned count = args->buffer_count;
792
793 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
794
795 /* We may process another execbuffer during the unlock... */
796 while (!list_empty(&eb->vmas)) {
797 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
798 list_del_init(&vma->exec_list);
799 i915_gem_execbuffer_unreserve_vma(vma);
800 drm_gem_object_unreference(&vma->obj->base);
801 }
802
803 mutex_unlock(&dev->struct_mutex);
804
805 total = 0;
806 for (i = 0; i < count; i++)
807 total += exec[i].relocation_count;
808
809 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
810 reloc = drm_malloc_ab(total, sizeof(*reloc));
811 if (reloc == NULL || reloc_offset == NULL) {
812 drm_free_large(reloc);
813 drm_free_large(reloc_offset);
814 mutex_lock(&dev->struct_mutex);
815 return -ENOMEM;
816 }
817
818 total = 0;
819 for (i = 0; i < count; i++) {
820 struct drm_i915_gem_relocation_entry __user *user_relocs;
821 u64 invalid_offset = (u64)-1;
822 int j;
823
824 user_relocs = to_user_ptr(exec[i].relocs_ptr);
825
826 if (copy_from_user(reloc+total, user_relocs,
827 exec[i].relocation_count * sizeof(*reloc))) {
828 ret = -EFAULT;
829 mutex_lock(&dev->struct_mutex);
830 goto err;
831 }
832
833 /* As we do not update the known relocation offsets after
834 * relocating (due to the complexities in lock handling),
835 * we need to mark them as invalid now so that we force the
836 * relocation processing next time. Just in case the target
837 * object is evicted and then rebound into its old
838 * presumed_offset before the next execbuffer - if that
839 * happened we would make the mistake of assuming that the
840 * relocations were valid.
841 */
842 for (j = 0; j < exec[i].relocation_count; j++) {
843 if (__copy_to_user(&user_relocs[j].presumed_offset,
844 &invalid_offset,
845 sizeof(invalid_offset))) {
846 ret = -EFAULT;
847 mutex_lock(&dev->struct_mutex);
848 goto err;
849 }
850 }
851
852 reloc_offset[i] = total;
853 total += exec[i].relocation_count;
854 }
855
856 ret = i915_mutex_lock_interruptible(dev);
857 if (ret) {
858 mutex_lock(&dev->struct_mutex);
859 goto err;
860 }
861
862 /* reacquire the objects */
863 eb_reset(eb);
864 ret = eb_lookup_vmas(eb, exec, args, vm, file);
865 if (ret)
866 goto err;
867
868 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
869 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
870 if (ret)
871 goto err;
872
873 list_for_each_entry(vma, &eb->vmas, exec_list) {
874 int offset = vma->exec_entry - exec;
875 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
876 reloc + reloc_offset[offset]);
877 if (ret)
878 goto err;
879 }
880
881 /* Leave the user relocations as are, this is the painfully slow path,
882 * and we want to avoid the complication of dropping the lock whilst
883 * having buffers reserved in the aperture and so causing spurious
884 * ENOSPC for random operations.
885 */
886
887 err:
888 drm_free_large(reloc);
889 drm_free_large(reloc_offset);
890 return ret;
891 }
892
893 static int
894 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
895 struct list_head *vmas)
896 {
897 const unsigned other_rings = ~intel_ring_flag(ring);
898 struct i915_vma *vma;
899 uint32_t flush_domains = 0;
900 bool flush_chipset = false;
901 int ret;
902
903 list_for_each_entry(vma, vmas, exec_list) {
904 struct drm_i915_gem_object *obj = vma->obj;
905
906 if (obj->active & other_rings) {
907 ret = i915_gem_object_sync(obj, ring);
908 if (ret)
909 return ret;
910 }
911
912 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
913 flush_chipset |= i915_gem_clflush_object(obj, false);
914
915 flush_domains |= obj->base.write_domain;
916 }
917
918 if (flush_chipset)
919 i915_gem_chipset_flush(ring->dev);
920
921 if (flush_domains & I915_GEM_DOMAIN_GTT)
922 wmb();
923
924 /* Unconditionally invalidate gpu caches and ensure that we do flush
925 * any residual writes from the previous batch.
926 */
927 return intel_ring_invalidate_all_caches(ring);
928 }
929
930 static bool
931 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
932 {
933 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
934 return false;
935
936 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
937 }
938
939 static int
940 validate_exec_list(struct drm_device *dev,
941 struct drm_i915_gem_exec_object2 *exec,
942 int count)
943 {
944 unsigned relocs_total = 0;
945 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
946 unsigned invalid_flags;
947 int i;
948
949 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
950 if (USES_FULL_PPGTT(dev))
951 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
952
953 for (i = 0; i < count; i++) {
954 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
955 int length; /* limited by fault_in_pages_readable() */
956
957 if (exec[i].flags & invalid_flags)
958 return -EINVAL;
959
960 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
961 return -EINVAL;
962
963 /* First check for malicious input causing overflow in
964 * the worst case where we need to allocate the entire
965 * relocation tree as a single array.
966 */
967 if (exec[i].relocation_count > relocs_max - relocs_total)
968 return -EINVAL;
969 relocs_total += exec[i].relocation_count;
970
971 length = exec[i].relocation_count *
972 sizeof(struct drm_i915_gem_relocation_entry);
973 /*
974 * We must check that the entire relocation array is safe
975 * to read, but since we may need to update the presumed
976 * offsets during execution, check for full write access.
977 */
978 if (!access_ok(VERIFY_WRITE, ptr, length))
979 return -EFAULT;
980
981 if (likely(!i915.prefault_disable)) {
982 if (fault_in_multipages_readable(ptr, length))
983 return -EFAULT;
984 }
985 }
986
987 return 0;
988 }
989
990 static struct intel_context *
991 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
992 struct intel_engine_cs *ring, const u32 ctx_id)
993 {
994 struct intel_context *ctx = NULL;
995 struct i915_ctx_hang_stats *hs;
996
997 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
998 return ERR_PTR(-EINVAL);
999
1000 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
1001 if (IS_ERR(ctx))
1002 return ctx;
1003
1004 hs = &ctx->hang_stats;
1005 if (hs->banned) {
1006 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1007 return ERR_PTR(-EIO);
1008 }
1009
1010 if (i915.enable_execlists && !ctx->engine[ring->id].state) {
1011 int ret = intel_lr_context_deferred_create(ctx, ring);
1012 if (ret) {
1013 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
1014 return ERR_PTR(ret);
1015 }
1016 }
1017
1018 return ctx;
1019 }
1020
1021 void
1022 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1023 struct intel_engine_cs *ring)
1024 {
1025 struct drm_i915_gem_request *req = intel_ring_get_request(ring);
1026 struct i915_vma *vma;
1027
1028 list_for_each_entry(vma, vmas, exec_list) {
1029 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1030 struct drm_i915_gem_object *obj = vma->obj;
1031 u32 old_read = obj->base.read_domains;
1032 u32 old_write = obj->base.write_domain;
1033
1034 obj->base.write_domain = obj->base.pending_write_domain;
1035 if (obj->base.write_domain == 0)
1036 obj->base.pending_read_domains |= obj->base.read_domains;
1037 obj->base.read_domains = obj->base.pending_read_domains;
1038
1039 i915_vma_move_to_active(vma, ring);
1040 if (obj->base.write_domain) {
1041 obj->dirty = 1;
1042 i915_gem_request_assign(&obj->last_write_req, req);
1043
1044 intel_fb_obj_invalidate(obj, ORIGIN_CS);
1045
1046 /* update for the implicit flush after a batch */
1047 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1048 }
1049 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1050 i915_gem_request_assign(&obj->last_fenced_req, req);
1051 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1052 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1053 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1054 &dev_priv->mm.fence_list);
1055 }
1056 }
1057
1058 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1059 }
1060 }
1061
1062 void
1063 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
1064 struct drm_file *file,
1065 struct intel_engine_cs *ring,
1066 struct drm_i915_gem_object *obj)
1067 {
1068 /* Unconditionally force add_request to emit a full flush. */
1069 ring->gpu_caches_dirty = true;
1070
1071 /* Add a breadcrumb for the completion of the batch buffer */
1072 __i915_add_request(ring, file, obj);
1073 }
1074
1075 static int
1076 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1077 struct intel_engine_cs *ring)
1078 {
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 int ret, i;
1081
1082 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1083 DRM_DEBUG("sol reset is gen7/rcs only\n");
1084 return -EINVAL;
1085 }
1086
1087 ret = intel_ring_begin(ring, 4 * 3);
1088 if (ret)
1089 return ret;
1090
1091 for (i = 0; i < 4; i++) {
1092 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1093 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1094 intel_ring_emit(ring, 0);
1095 }
1096
1097 intel_ring_advance(ring);
1098
1099 return 0;
1100 }
1101
1102 static int
1103 i915_emit_box(struct intel_engine_cs *ring,
1104 struct drm_clip_rect *box,
1105 int DR1, int DR4)
1106 {
1107 int ret;
1108
1109 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
1110 box->y2 <= 0 || box->x2 <= 0) {
1111 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1112 box->x1, box->y1, box->x2, box->y2);
1113 return -EINVAL;
1114 }
1115
1116 if (INTEL_INFO(ring->dev)->gen >= 4) {
1117 ret = intel_ring_begin(ring, 4);
1118 if (ret)
1119 return ret;
1120
1121 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
1122 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1123 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1124 intel_ring_emit(ring, DR4);
1125 } else {
1126 ret = intel_ring_begin(ring, 6);
1127 if (ret)
1128 return ret;
1129
1130 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
1131 intel_ring_emit(ring, DR1);
1132 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1133 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1134 intel_ring_emit(ring, DR4);
1135 intel_ring_emit(ring, 0);
1136 }
1137 intel_ring_advance(ring);
1138
1139 return 0;
1140 }
1141
1142 static struct drm_i915_gem_object*
1143 i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
1144 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1145 struct eb_vmas *eb,
1146 struct drm_i915_gem_object *batch_obj,
1147 u32 batch_start_offset,
1148 u32 batch_len,
1149 bool is_master)
1150 {
1151 struct drm_i915_gem_object *shadow_batch_obj;
1152 struct i915_vma *vma;
1153 int ret;
1154
1155 shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
1156 PAGE_ALIGN(batch_len));
1157 if (IS_ERR(shadow_batch_obj))
1158 return shadow_batch_obj;
1159
1160 ret = i915_parse_cmds(ring,
1161 batch_obj,
1162 shadow_batch_obj,
1163 batch_start_offset,
1164 batch_len,
1165 is_master);
1166 if (ret)
1167 goto err;
1168
1169 ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1170 if (ret)
1171 goto err;
1172
1173 i915_gem_object_unpin_pages(shadow_batch_obj);
1174
1175 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1176
1177 vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1178 vma->exec_entry = shadow_exec_entry;
1179 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1180 drm_gem_object_reference(&shadow_batch_obj->base);
1181 list_add_tail(&vma->exec_list, &eb->vmas);
1182
1183 shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1184
1185 return shadow_batch_obj;
1186
1187 err:
1188 i915_gem_object_unpin_pages(shadow_batch_obj);
1189 if (ret == -EACCES) /* unhandled chained batch */
1190 return batch_obj;
1191 else
1192 return ERR_PTR(ret);
1193 }
1194
1195 int
1196 i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
1197 struct intel_engine_cs *ring,
1198 struct intel_context *ctx,
1199 struct drm_i915_gem_execbuffer2 *args,
1200 struct list_head *vmas,
1201 struct drm_i915_gem_object *batch_obj,
1202 u64 exec_start, u32 dispatch_flags)
1203 {
1204 struct drm_clip_rect *cliprects = NULL;
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u64 exec_len;
1207 int instp_mode;
1208 u32 instp_mask;
1209 int i, ret = 0;
1210
1211 if (args->num_cliprects != 0) {
1212 if (ring != &dev_priv->ring[RCS]) {
1213 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1214 return -EINVAL;
1215 }
1216
1217 if (INTEL_INFO(dev)->gen >= 5) {
1218 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1219 return -EINVAL;
1220 }
1221
1222 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1223 DRM_DEBUG("execbuf with %u cliprects\n",
1224 args->num_cliprects);
1225 return -EINVAL;
1226 }
1227
1228 cliprects = kcalloc(args->num_cliprects,
1229 sizeof(*cliprects),
1230 GFP_KERNEL);
1231 if (cliprects == NULL) {
1232 ret = -ENOMEM;
1233 goto error;
1234 }
1235
1236 if (copy_from_user(cliprects,
1237 to_user_ptr(args->cliprects_ptr),
1238 sizeof(*cliprects)*args->num_cliprects)) {
1239 ret = -EFAULT;
1240 goto error;
1241 }
1242 } else {
1243 if (args->DR4 == 0xffffffff) {
1244 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1245 args->DR4 = 0;
1246 }
1247
1248 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
1249 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1250 return -EINVAL;
1251 }
1252 }
1253
1254 ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
1255 if (ret)
1256 goto error;
1257
1258 ret = i915_switch_context(ring, ctx);
1259 if (ret)
1260 goto error;
1261
1262 WARN(ctx->ppgtt && ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
1263 "%s didn't clear reload\n", ring->name);
1264
1265 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1266 instp_mask = I915_EXEC_CONSTANTS_MASK;
1267 switch (instp_mode) {
1268 case I915_EXEC_CONSTANTS_REL_GENERAL:
1269 case I915_EXEC_CONSTANTS_ABSOLUTE:
1270 case I915_EXEC_CONSTANTS_REL_SURFACE:
1271 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1272 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1273 ret = -EINVAL;
1274 goto error;
1275 }
1276
1277 if (instp_mode != dev_priv->relative_constants_mode) {
1278 if (INTEL_INFO(dev)->gen < 4) {
1279 DRM_DEBUG("no rel constants on pre-gen4\n");
1280 ret = -EINVAL;
1281 goto error;
1282 }
1283
1284 if (INTEL_INFO(dev)->gen > 5 &&
1285 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1286 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1287 ret = -EINVAL;
1288 goto error;
1289 }
1290
1291 /* The HW changed the meaning on this bit on gen6 */
1292 if (INTEL_INFO(dev)->gen >= 6)
1293 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1294 }
1295 break;
1296 default:
1297 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1298 ret = -EINVAL;
1299 goto error;
1300 }
1301
1302 if (ring == &dev_priv->ring[RCS] &&
1303 instp_mode != dev_priv->relative_constants_mode) {
1304 ret = intel_ring_begin(ring, 4);
1305 if (ret)
1306 goto error;
1307
1308 intel_ring_emit(ring, MI_NOOP);
1309 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1310 intel_ring_emit(ring, INSTPM);
1311 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1312 intel_ring_advance(ring);
1313
1314 dev_priv->relative_constants_mode = instp_mode;
1315 }
1316
1317 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1318 ret = i915_reset_gen7_sol_offsets(dev, ring);
1319 if (ret)
1320 goto error;
1321 }
1322
1323 exec_len = args->batch_len;
1324 if (cliprects) {
1325 for (i = 0; i < args->num_cliprects; i++) {
1326 ret = i915_emit_box(ring, &cliprects[i],
1327 args->DR1, args->DR4);
1328 if (ret)
1329 goto error;
1330
1331 ret = ring->dispatch_execbuffer(ring,
1332 exec_start, exec_len,
1333 dispatch_flags);
1334 if (ret)
1335 goto error;
1336 }
1337 } else {
1338 ret = ring->dispatch_execbuffer(ring,
1339 exec_start, exec_len,
1340 dispatch_flags);
1341 if (ret)
1342 return ret;
1343 }
1344
1345 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
1346
1347 i915_gem_execbuffer_move_to_active(vmas, ring);
1348 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1349
1350 error:
1351 kfree(cliprects);
1352 return ret;
1353 }
1354
1355 /**
1356 * Find one BSD ring to dispatch the corresponding BSD command.
1357 * The Ring ID is returned.
1358 */
1359 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1360 struct drm_file *file)
1361 {
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 struct drm_i915_file_private *file_priv = file->driver_priv;
1364
1365 /* Check whether the file_priv is using one ring */
1366 if (file_priv->bsd_ring)
1367 return file_priv->bsd_ring->id;
1368 else {
1369 /* If no, use the ping-pong mechanism to select one ring */
1370 int ring_id;
1371
1372 mutex_lock(&dev->struct_mutex);
1373 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1374 ring_id = VCS;
1375 dev_priv->mm.bsd_ring_dispatch_index = 1;
1376 } else {
1377 ring_id = VCS2;
1378 dev_priv->mm.bsd_ring_dispatch_index = 0;
1379 }
1380 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1381 mutex_unlock(&dev->struct_mutex);
1382 return ring_id;
1383 }
1384 }
1385
1386 static struct drm_i915_gem_object *
1387 eb_get_batch(struct eb_vmas *eb)
1388 {
1389 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1390
1391 /*
1392 * SNA is doing fancy tricks with compressing batch buffers, which leads
1393 * to negative relocation deltas. Usually that works out ok since the
1394 * relocate address is still positive, except when the batch is placed
1395 * very low in the GTT. Ensure this doesn't happen.
1396 *
1397 * Note that actual hangs have only been observed on gen7, but for
1398 * paranoia do it everywhere.
1399 */
1400 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1401
1402 return vma->obj;
1403 }
1404
1405 static int
1406 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1407 struct drm_file *file,
1408 struct drm_i915_gem_execbuffer2 *args,
1409 struct drm_i915_gem_exec_object2 *exec)
1410 {
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1412 struct eb_vmas *eb;
1413 struct drm_i915_gem_object *batch_obj;
1414 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1415 struct intel_engine_cs *ring;
1416 struct intel_context *ctx;
1417 struct i915_address_space *vm;
1418 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1419 u64 exec_start = args->batch_start_offset;
1420 u32 dispatch_flags;
1421 int ret;
1422 bool need_relocs;
1423
1424 if (!i915_gem_check_execbuffer(args))
1425 return -EINVAL;
1426
1427 ret = validate_exec_list(dev, exec, args->buffer_count);
1428 if (ret)
1429 return ret;
1430
1431 dispatch_flags = 0;
1432 if (args->flags & I915_EXEC_SECURE) {
1433 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1434 return -EPERM;
1435
1436 dispatch_flags |= I915_DISPATCH_SECURE;
1437 }
1438 if (args->flags & I915_EXEC_IS_PINNED)
1439 dispatch_flags |= I915_DISPATCH_PINNED;
1440
1441 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1442 DRM_DEBUG("execbuf with unknown ring: %d\n",
1443 (int)(args->flags & I915_EXEC_RING_MASK));
1444 return -EINVAL;
1445 }
1446
1447 if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
1448 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1449 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1450 "bsd dispatch flags: %d\n", (int)(args->flags));
1451 return -EINVAL;
1452 }
1453
1454 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1455 ring = &dev_priv->ring[RCS];
1456 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1457 if (HAS_BSD2(dev)) {
1458 int ring_id;
1459
1460 switch (args->flags & I915_EXEC_BSD_MASK) {
1461 case I915_EXEC_BSD_DEFAULT:
1462 ring_id = gen8_dispatch_bsd_ring(dev, file);
1463 ring = &dev_priv->ring[ring_id];
1464 break;
1465 case I915_EXEC_BSD_RING1:
1466 ring = &dev_priv->ring[VCS];
1467 break;
1468 case I915_EXEC_BSD_RING2:
1469 ring = &dev_priv->ring[VCS2];
1470 break;
1471 default:
1472 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1473 (int)(args->flags & I915_EXEC_BSD_MASK));
1474 return -EINVAL;
1475 }
1476 } else
1477 ring = &dev_priv->ring[VCS];
1478 } else
1479 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1480
1481 if (!intel_ring_initialized(ring)) {
1482 DRM_DEBUG("execbuf with invalid ring: %d\n",
1483 (int)(args->flags & I915_EXEC_RING_MASK));
1484 return -EINVAL;
1485 }
1486
1487 if (args->buffer_count < 1) {
1488 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1489 return -EINVAL;
1490 }
1491
1492 intel_runtime_pm_get(dev_priv);
1493
1494 ret = i915_mutex_lock_interruptible(dev);
1495 if (ret)
1496 goto pre_mutex_err;
1497
1498 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1499 if (IS_ERR(ctx)) {
1500 mutex_unlock(&dev->struct_mutex);
1501 ret = PTR_ERR(ctx);
1502 goto pre_mutex_err;
1503 }
1504
1505 i915_gem_context_reference(ctx);
1506
1507 if (ctx->ppgtt)
1508 vm = &ctx->ppgtt->base;
1509 else
1510 vm = &dev_priv->gtt.base;
1511
1512 eb = eb_create(args);
1513 if (eb == NULL) {
1514 i915_gem_context_unreference(ctx);
1515 mutex_unlock(&dev->struct_mutex);
1516 ret = -ENOMEM;
1517 goto pre_mutex_err;
1518 }
1519
1520 /* Look up object handles */
1521 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1522 if (ret)
1523 goto err;
1524
1525 /* take note of the batch buffer before we might reorder the lists */
1526 batch_obj = eb_get_batch(eb);
1527
1528 /* Move the objects en-masse into the GTT, evicting if necessary. */
1529 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1530 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
1531 if (ret)
1532 goto err;
1533
1534 /* The objects are in their final locations, apply the relocations. */
1535 if (need_relocs)
1536 ret = i915_gem_execbuffer_relocate(eb);
1537 if (ret) {
1538 if (ret == -EFAULT) {
1539 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1540 eb, exec, ctx);
1541 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1542 }
1543 if (ret)
1544 goto err;
1545 }
1546
1547 /* Set the pending read domains for the batch buffer to COMMAND */
1548 if (batch_obj->base.pending_write_domain) {
1549 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1550 ret = -EINVAL;
1551 goto err;
1552 }
1553
1554 if (i915_needs_cmd_parser(ring) && args->batch_len) {
1555 struct drm_i915_gem_object *parsed_batch_obj;
1556
1557 parsed_batch_obj = i915_gem_execbuffer_parse(ring,
1558 &shadow_exec_entry,
1559 eb,
1560 batch_obj,
1561 args->batch_start_offset,
1562 args->batch_len,
1563 file->is_master);
1564 if (IS_ERR(parsed_batch_obj)) {
1565 ret = PTR_ERR(parsed_batch_obj);
1566 goto err;
1567 }
1568
1569 /*
1570 * parsed_batch_obj == batch_obj means batch not fully parsed:
1571 * Accept, but don't promote to secure.
1572 */
1573
1574 if (parsed_batch_obj != batch_obj) {
1575 /*
1576 * Batch parsed and accepted:
1577 *
1578 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1579 * bit from MI_BATCH_BUFFER_START commands issued in
1580 * the dispatch_execbuffer implementations. We
1581 * specifically don't want that set on batches the
1582 * command parser has accepted.
1583 */
1584 dispatch_flags |= I915_DISPATCH_SECURE;
1585 exec_start = 0;
1586 batch_obj = parsed_batch_obj;
1587 }
1588 }
1589
1590 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1591
1592 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1593 * batch" bit. Hence we need to pin secure batches into the global gtt.
1594 * hsw should have this fixed, but bdw mucks it up again. */
1595 if (dispatch_flags & I915_DISPATCH_SECURE) {
1596 /*
1597 * So on first glance it looks freaky that we pin the batch here
1598 * outside of the reservation loop. But:
1599 * - The batch is already pinned into the relevant ppgtt, so we
1600 * already have the backing storage fully allocated.
1601 * - No other BO uses the global gtt (well contexts, but meh),
1602 * so we don't really have issues with multiple objects not
1603 * fitting due to fragmentation.
1604 * So this is actually safe.
1605 */
1606 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1607 if (ret)
1608 goto err;
1609
1610 exec_start += i915_gem_obj_ggtt_offset(batch_obj);
1611 } else
1612 exec_start += i915_gem_obj_offset(batch_obj, vm);
1613
1614 /* Allocate a request for this batch buffer nice and early. */
1615 ret = i915_gem_request_alloc(ring, ctx);
1616 if (ret)
1617 goto err_batch_unpin;
1618
1619 ret = dev_priv->gt.execbuf_submit(dev, file, ring, ctx, args,
1620 &eb->vmas, batch_obj, exec_start,
1621 dispatch_flags);
1622
1623 err_batch_unpin:
1624 /*
1625 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1626 * batch vma for correctness. For less ugly and less fragility this
1627 * needs to be adjusted to also track the ggtt batch vma properly as
1628 * active.
1629 */
1630 if (dispatch_flags & I915_DISPATCH_SECURE)
1631 i915_gem_object_ggtt_unpin(batch_obj);
1632
1633 err:
1634 /* the request owns the ref now */
1635 i915_gem_context_unreference(ctx);
1636 eb_destroy(eb);
1637
1638 mutex_unlock(&dev->struct_mutex);
1639
1640 pre_mutex_err:
1641 /* intel_gpu_busy should also get a ref, so it will free when the device
1642 * is really idle. */
1643 intel_runtime_pm_put(dev_priv);
1644 return ret;
1645 }
1646
1647 /*
1648 * Legacy execbuffer just creates an exec2 list from the original exec object
1649 * list array and passes it to the real function.
1650 */
1651 int
1652 i915_gem_execbuffer(struct drm_device *dev, void *data,
1653 struct drm_file *file)
1654 {
1655 struct drm_i915_gem_execbuffer *args = data;
1656 struct drm_i915_gem_execbuffer2 exec2;
1657 struct drm_i915_gem_exec_object *exec_list = NULL;
1658 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1659 int ret, i;
1660
1661 if (args->buffer_count < 1) {
1662 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1663 return -EINVAL;
1664 }
1665
1666 /* Copy in the exec list from userland */
1667 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1668 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1669 if (exec_list == NULL || exec2_list == NULL) {
1670 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1671 args->buffer_count);
1672 drm_free_large(exec_list);
1673 drm_free_large(exec2_list);
1674 return -ENOMEM;
1675 }
1676 ret = copy_from_user(exec_list,
1677 to_user_ptr(args->buffers_ptr),
1678 sizeof(*exec_list) * args->buffer_count);
1679 if (ret != 0) {
1680 DRM_DEBUG("copy %d exec entries failed %d\n",
1681 args->buffer_count, ret);
1682 drm_free_large(exec_list);
1683 drm_free_large(exec2_list);
1684 return -EFAULT;
1685 }
1686
1687 for (i = 0; i < args->buffer_count; i++) {
1688 exec2_list[i].handle = exec_list[i].handle;
1689 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1690 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1691 exec2_list[i].alignment = exec_list[i].alignment;
1692 exec2_list[i].offset = exec_list[i].offset;
1693 if (INTEL_INFO(dev)->gen < 4)
1694 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1695 else
1696 exec2_list[i].flags = 0;
1697 }
1698
1699 exec2.buffers_ptr = args->buffers_ptr;
1700 exec2.buffer_count = args->buffer_count;
1701 exec2.batch_start_offset = args->batch_start_offset;
1702 exec2.batch_len = args->batch_len;
1703 exec2.DR1 = args->DR1;
1704 exec2.DR4 = args->DR4;
1705 exec2.num_cliprects = args->num_cliprects;
1706 exec2.cliprects_ptr = args->cliprects_ptr;
1707 exec2.flags = I915_EXEC_RENDER;
1708 i915_execbuffer2_set_context_id(exec2, 0);
1709
1710 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1711 if (!ret) {
1712 struct drm_i915_gem_exec_object __user *user_exec_list =
1713 to_user_ptr(args->buffers_ptr);
1714
1715 /* Copy the new buffer offsets back to the user's exec list. */
1716 for (i = 0; i < args->buffer_count; i++) {
1717 ret = __copy_to_user(&user_exec_list[i].offset,
1718 &exec2_list[i].offset,
1719 sizeof(user_exec_list[i].offset));
1720 if (ret) {
1721 ret = -EFAULT;
1722 DRM_DEBUG("failed to copy %d exec entries "
1723 "back to user (%d)\n",
1724 args->buffer_count, ret);
1725 break;
1726 }
1727 }
1728 }
1729
1730 drm_free_large(exec_list);
1731 drm_free_large(exec2_list);
1732 return ret;
1733 }
1734
1735 int
1736 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1737 struct drm_file *file)
1738 {
1739 struct drm_i915_gem_execbuffer2 *args = data;
1740 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1741 int ret;
1742
1743 if (args->buffer_count < 1 ||
1744 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1745 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1746 return -EINVAL;
1747 }
1748
1749 if (args->rsvd2 != 0) {
1750 DRM_DEBUG("dirty rvsd2 field\n");
1751 return -EINVAL;
1752 }
1753
1754 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1755 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1756 if (exec2_list == NULL)
1757 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1758 args->buffer_count);
1759 if (exec2_list == NULL) {
1760 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1761 args->buffer_count);
1762 return -ENOMEM;
1763 }
1764 ret = copy_from_user(exec2_list,
1765 to_user_ptr(args->buffers_ptr),
1766 sizeof(*exec2_list) * args->buffer_count);
1767 if (ret != 0) {
1768 DRM_DEBUG("copy %d exec entries failed %d\n",
1769 args->buffer_count, ret);
1770 drm_free_large(exec2_list);
1771 return -EFAULT;
1772 }
1773
1774 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1775 if (!ret) {
1776 /* Copy the new buffer offsets back to the user's exec list. */
1777 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1778 to_user_ptr(args->buffers_ptr);
1779 int i;
1780
1781 for (i = 0; i < args->buffer_count; i++) {
1782 ret = __copy_to_user(&user_exec_list[i].offset,
1783 &exec2_list[i].offset,
1784 sizeof(user_exec_list[i].offset));
1785 if (ret) {
1786 ret = -EFAULT;
1787 DRM_DEBUG("failed to copy %d exec entries "
1788 "back to user\n",
1789 args->buffer_count);
1790 break;
1791 }
1792 }
1793 }
1794
1795 drm_free_large(exec2_list);
1796 return ret;
1797 }
Linux kernel - Deliverables
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