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drm/i915: Abort command parsing for chained batches
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
40
41 #define BATCH_OFFSET_BIAS (256*1024)
42
43 struct eb_vmas {
44 struct list_head vmas;
45 int and;
46 union {
47 struct i915_vma *lut[0];
48 struct hlist_head buckets[0];
49 };
50 };
51
52 static struct eb_vmas *
53 eb_create(struct drm_i915_gem_execbuffer2 *args)
54 {
55 struct eb_vmas *eb = NULL;
56
57 if (args->flags & I915_EXEC_HANDLE_LUT) {
58 unsigned size = args->buffer_count;
59 size *= sizeof(struct i915_vma *);
60 size += sizeof(struct eb_vmas);
61 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
62 }
63
64 if (eb == NULL) {
65 unsigned size = args->buffer_count;
66 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
67 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
68 while (count > 2*size)
69 count >>= 1;
70 eb = kzalloc(count*sizeof(struct hlist_head) +
71 sizeof(struct eb_vmas),
72 GFP_TEMPORARY);
73 if (eb == NULL)
74 return eb;
75
76 eb->and = count - 1;
77 } else
78 eb->and = -args->buffer_count;
79
80 INIT_LIST_HEAD(&eb->vmas);
81 return eb;
82 }
83
84 static void
85 eb_reset(struct eb_vmas *eb)
86 {
87 if (eb->and >= 0)
88 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
89 }
90
91 static int
92 eb_lookup_vmas(struct eb_vmas *eb,
93 struct drm_i915_gem_exec_object2 *exec,
94 const struct drm_i915_gem_execbuffer2 *args,
95 struct i915_address_space *vm,
96 struct drm_file *file)
97 {
98 struct drm_i915_gem_object *obj;
99 struct list_head objects;
100 int i, ret;
101
102 INIT_LIST_HEAD(&objects);
103 spin_lock(&file->table_lock);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i = 0; i < args->buffer_count; i++) {
107 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
108 if (obj == NULL) {
109 spin_unlock(&file->table_lock);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
111 exec[i].handle, i);
112 ret = -ENOENT;
113 goto err;
114 }
115
116 if (!list_empty(&obj->obj_exec_link)) {
117 spin_unlock(&file->table_lock);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj, exec[i].handle, i);
120 ret = -EINVAL;
121 goto err;
122 }
123
124 drm_gem_object_reference(&obj->base);
125 list_add_tail(&obj->obj_exec_link, &objects);
126 }
127 spin_unlock(&file->table_lock);
128
129 i = 0;
130 while (!list_empty(&objects)) {
131 struct i915_vma *vma;
132
133 obj = list_first_entry(&objects,
134 struct drm_i915_gem_object,
135 obj_exec_link);
136
137 /*
138 * NOTE: We can leak any vmas created here when something fails
139 * later on. But that's no issue since vma_unbind can deal with
140 * vmas which are not actually bound. And since only
141 * lookup_or_create exists as an interface to get at the vma
142 * from the (obj, vm) we don't run the risk of creating
143 * duplicated vmas for the same vm.
144 */
145 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
146 if (IS_ERR(vma)) {
147 DRM_DEBUG("Failed to lookup VMA\n");
148 ret = PTR_ERR(vma);
149 goto err;
150 }
151
152 /* Transfer ownership from the objects list to the vmas list. */
153 list_add_tail(&vma->exec_list, &eb->vmas);
154 list_del_init(&obj->obj_exec_link);
155
156 vma->exec_entry = &exec[i];
157 if (eb->and < 0) {
158 eb->lut[i] = vma;
159 } else {
160 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
161 vma->exec_handle = handle;
162 hlist_add_head(&vma->exec_node,
163 &eb->buckets[handle & eb->and]);
164 }
165 ++i;
166 }
167
168 return 0;
169
170
171 err:
172 while (!list_empty(&objects)) {
173 obj = list_first_entry(&objects,
174 struct drm_i915_gem_object,
175 obj_exec_link);
176 list_del_init(&obj->obj_exec_link);
177 drm_gem_object_unreference(&obj->base);
178 }
179 /*
180 * Objects already transfered to the vmas list will be unreferenced by
181 * eb_destroy.
182 */
183
184 return ret;
185 }
186
187 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
188 {
189 if (eb->and < 0) {
190 if (handle >= -eb->and)
191 return NULL;
192 return eb->lut[handle];
193 } else {
194 struct hlist_head *head;
195 struct hlist_node *node;
196
197 head = &eb->buckets[handle & eb->and];
198 hlist_for_each(node, head) {
199 struct i915_vma *vma;
200
201 vma = hlist_entry(node, struct i915_vma, exec_node);
202 if (vma->exec_handle == handle)
203 return vma;
204 }
205 return NULL;
206 }
207 }
208
209 static void
210 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
211 {
212 struct drm_i915_gem_exec_object2 *entry;
213 struct drm_i915_gem_object *obj = vma->obj;
214
215 if (!drm_mm_node_allocated(&vma->node))
216 return;
217
218 entry = vma->exec_entry;
219
220 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
221 i915_gem_object_unpin_fence(obj);
222
223 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
224 vma->pin_count--;
225
226 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
227 }
228
229 static void eb_destroy(struct eb_vmas *eb)
230 {
231 while (!list_empty(&eb->vmas)) {
232 struct i915_vma *vma;
233
234 vma = list_first_entry(&eb->vmas,
235 struct i915_vma,
236 exec_list);
237 list_del_init(&vma->exec_list);
238 i915_gem_execbuffer_unreserve_vma(vma);
239 drm_gem_object_unreference(&vma->obj->base);
240 }
241 kfree(eb);
242 }
243
244 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
245 {
246 return (HAS_LLC(obj->base.dev) ||
247 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
248 !obj->map_and_fenceable ||
249 obj->cache_level != I915_CACHE_NONE);
250 }
251
252 static int
253 relocate_entry_cpu(struct drm_i915_gem_object *obj,
254 struct drm_i915_gem_relocation_entry *reloc,
255 uint64_t target_offset)
256 {
257 struct drm_device *dev = obj->base.dev;
258 uint32_t page_offset = offset_in_page(reloc->offset);
259 uint64_t delta = reloc->delta + target_offset;
260 char *vaddr;
261 int ret;
262
263 ret = i915_gem_object_set_to_cpu_domain(obj, true);
264 if (ret)
265 return ret;
266
267 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
268 reloc->offset >> PAGE_SHIFT));
269 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
270
271 if (INTEL_INFO(dev)->gen >= 8) {
272 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
273
274 if (page_offset == 0) {
275 kunmap_atomic(vaddr);
276 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
277 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
278 }
279
280 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
281 }
282
283 kunmap_atomic(vaddr);
284
285 return 0;
286 }
287
288 static int
289 relocate_entry_gtt(struct drm_i915_gem_object *obj,
290 struct drm_i915_gem_relocation_entry *reloc,
291 uint64_t target_offset)
292 {
293 struct drm_device *dev = obj->base.dev;
294 struct drm_i915_private *dev_priv = dev->dev_private;
295 uint64_t delta = reloc->delta + target_offset;
296 uint64_t offset;
297 void __iomem *reloc_page;
298 int ret;
299
300 ret = i915_gem_object_set_to_gtt_domain(obj, true);
301 if (ret)
302 return ret;
303
304 ret = i915_gem_object_put_fence(obj);
305 if (ret)
306 return ret;
307
308 /* Map the page containing the relocation we're going to perform. */
309 offset = i915_gem_obj_ggtt_offset(obj);
310 offset += reloc->offset;
311 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
312 offset & PAGE_MASK);
313 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
314
315 if (INTEL_INFO(dev)->gen >= 8) {
316 offset += sizeof(uint32_t);
317
318 if (offset_in_page(offset) == 0) {
319 io_mapping_unmap_atomic(reloc_page);
320 reloc_page =
321 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
322 offset);
323 }
324
325 iowrite32(upper_32_bits(delta),
326 reloc_page + offset_in_page(offset));
327 }
328
329 io_mapping_unmap_atomic(reloc_page);
330
331 return 0;
332 }
333
334 static int
335 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
336 struct eb_vmas *eb,
337 struct drm_i915_gem_relocation_entry *reloc)
338 {
339 struct drm_device *dev = obj->base.dev;
340 struct drm_gem_object *target_obj;
341 struct drm_i915_gem_object *target_i915_obj;
342 struct i915_vma *target_vma;
343 uint64_t target_offset;
344 int ret;
345
346 /* we've already hold a reference to all valid objects */
347 target_vma = eb_get_vma(eb, reloc->target_handle);
348 if (unlikely(target_vma == NULL))
349 return -ENOENT;
350 target_i915_obj = target_vma->obj;
351 target_obj = &target_vma->obj->base;
352
353 target_offset = target_vma->node.start;
354
355 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
356 * pipe_control writes because the gpu doesn't properly redirect them
357 * through the ppgtt for non_secure batchbuffers. */
358 if (unlikely(IS_GEN6(dev) &&
359 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
360 !(target_vma->bound & GLOBAL_BIND)))
361 target_vma->bind_vma(target_vma, target_i915_obj->cache_level,
362 GLOBAL_BIND);
363
364 /* Validate that the target is in a valid r/w GPU domain */
365 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
366 DRM_DEBUG("reloc with multiple write domains: "
367 "obj %p target %d offset %d "
368 "read %08x write %08x",
369 obj, reloc->target_handle,
370 (int) reloc->offset,
371 reloc->read_domains,
372 reloc->write_domain);
373 return -EINVAL;
374 }
375 if (unlikely((reloc->write_domain | reloc->read_domains)
376 & ~I915_GEM_GPU_DOMAINS)) {
377 DRM_DEBUG("reloc with read/write non-GPU domains: "
378 "obj %p target %d offset %d "
379 "read %08x write %08x",
380 obj, reloc->target_handle,
381 (int) reloc->offset,
382 reloc->read_domains,
383 reloc->write_domain);
384 return -EINVAL;
385 }
386
387 target_obj->pending_read_domains |= reloc->read_domains;
388 target_obj->pending_write_domain |= reloc->write_domain;
389
390 /* If the relocation already has the right value in it, no
391 * more work needs to be done.
392 */
393 if (target_offset == reloc->presumed_offset)
394 return 0;
395
396 /* Check that the relocation address is valid... */
397 if (unlikely(reloc->offset >
398 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
399 DRM_DEBUG("Relocation beyond object bounds: "
400 "obj %p target %d offset %d size %d.\n",
401 obj, reloc->target_handle,
402 (int) reloc->offset,
403 (int) obj->base.size);
404 return -EINVAL;
405 }
406 if (unlikely(reloc->offset & 3)) {
407 DRM_DEBUG("Relocation not 4-byte aligned: "
408 "obj %p target %d offset %d.\n",
409 obj, reloc->target_handle,
410 (int) reloc->offset);
411 return -EINVAL;
412 }
413
414 /* We can't wait for rendering with pagefaults disabled */
415 if (obj->active && in_atomic())
416 return -EFAULT;
417
418 if (use_cpu_reloc(obj))
419 ret = relocate_entry_cpu(obj, reloc, target_offset);
420 else
421 ret = relocate_entry_gtt(obj, reloc, target_offset);
422
423 if (ret)
424 return ret;
425
426 /* and update the user's relocation entry */
427 reloc->presumed_offset = target_offset;
428
429 return 0;
430 }
431
432 static int
433 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
434 struct eb_vmas *eb)
435 {
436 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
437 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
438 struct drm_i915_gem_relocation_entry __user *user_relocs;
439 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
440 int remain, ret;
441
442 user_relocs = to_user_ptr(entry->relocs_ptr);
443
444 remain = entry->relocation_count;
445 while (remain) {
446 struct drm_i915_gem_relocation_entry *r = stack_reloc;
447 int count = remain;
448 if (count > ARRAY_SIZE(stack_reloc))
449 count = ARRAY_SIZE(stack_reloc);
450 remain -= count;
451
452 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
453 return -EFAULT;
454
455 do {
456 u64 offset = r->presumed_offset;
457
458 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
459 if (ret)
460 return ret;
461
462 if (r->presumed_offset != offset &&
463 __copy_to_user_inatomic(&user_relocs->presumed_offset,
464 &r->presumed_offset,
465 sizeof(r->presumed_offset))) {
466 return -EFAULT;
467 }
468
469 user_relocs++;
470 r++;
471 } while (--count);
472 }
473
474 return 0;
475 #undef N_RELOC
476 }
477
478 static int
479 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
480 struct eb_vmas *eb,
481 struct drm_i915_gem_relocation_entry *relocs)
482 {
483 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
484 int i, ret;
485
486 for (i = 0; i < entry->relocation_count; i++) {
487 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
488 if (ret)
489 return ret;
490 }
491
492 return 0;
493 }
494
495 static int
496 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
497 {
498 struct i915_vma *vma;
499 int ret = 0;
500
501 /* This is the fast path and we cannot handle a pagefault whilst
502 * holding the struct mutex lest the user pass in the relocations
503 * contained within a mmaped bo. For in such a case we, the page
504 * fault handler would call i915_gem_fault() and we would try to
505 * acquire the struct mutex again. Obviously this is bad and so
506 * lockdep complains vehemently.
507 */
508 pagefault_disable();
509 list_for_each_entry(vma, &eb->vmas, exec_list) {
510 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
511 if (ret)
512 break;
513 }
514 pagefault_enable();
515
516 return ret;
517 }
518
519 static int
520 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
521 struct intel_engine_cs *ring,
522 bool *need_reloc)
523 {
524 struct drm_i915_gem_object *obj = vma->obj;
525 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
526 uint64_t flags;
527 int ret;
528
529 flags = 0;
530 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
531 flags |= PIN_MAPPABLE;
532 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
533 flags |= PIN_GLOBAL;
534 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
535 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
536
537 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
538 if (ret)
539 return ret;
540
541 entry->flags |= __EXEC_OBJECT_HAS_PIN;
542
543 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
544 ret = i915_gem_object_get_fence(obj);
545 if (ret)
546 return ret;
547
548 if (i915_gem_object_pin_fence(obj))
549 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
550 }
551
552 if (entry->offset != vma->node.start) {
553 entry->offset = vma->node.start;
554 *need_reloc = true;
555 }
556
557 if (entry->flags & EXEC_OBJECT_WRITE) {
558 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
559 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
560 }
561
562 return 0;
563 }
564
565 static bool
566 need_reloc_mappable(struct i915_vma *vma)
567 {
568 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
569
570 if (entry->relocation_count == 0)
571 return false;
572
573 if (!i915_is_ggtt(vma->vm))
574 return false;
575
576 /* See also use_cpu_reloc() */
577 if (HAS_LLC(vma->obj->base.dev))
578 return false;
579
580 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
581 return false;
582
583 return true;
584 }
585
586 static bool
587 eb_vma_misplaced(struct i915_vma *vma)
588 {
589 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
590 struct drm_i915_gem_object *obj = vma->obj;
591
592 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
593 !i915_is_ggtt(vma->vm));
594
595 if (entry->alignment &&
596 vma->node.start & (entry->alignment - 1))
597 return true;
598
599 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
600 return true;
601
602 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
603 vma->node.start < BATCH_OFFSET_BIAS)
604 return true;
605
606 return false;
607 }
608
609 static int
610 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
611 struct list_head *vmas,
612 bool *need_relocs)
613 {
614 struct drm_i915_gem_object *obj;
615 struct i915_vma *vma;
616 struct i915_address_space *vm;
617 struct list_head ordered_vmas;
618 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
619 int retry;
620
621 i915_gem_retire_requests_ring(ring);
622
623 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
624
625 INIT_LIST_HEAD(&ordered_vmas);
626 while (!list_empty(vmas)) {
627 struct drm_i915_gem_exec_object2 *entry;
628 bool need_fence, need_mappable;
629
630 vma = list_first_entry(vmas, struct i915_vma, exec_list);
631 obj = vma->obj;
632 entry = vma->exec_entry;
633
634 if (!has_fenced_gpu_access)
635 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
636 need_fence =
637 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
638 obj->tiling_mode != I915_TILING_NONE;
639 need_mappable = need_fence || need_reloc_mappable(vma);
640
641 if (need_mappable) {
642 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
643 list_move(&vma->exec_list, &ordered_vmas);
644 } else
645 list_move_tail(&vma->exec_list, &ordered_vmas);
646
647 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
648 obj->base.pending_write_domain = 0;
649 }
650 list_splice(&ordered_vmas, vmas);
651
652 /* Attempt to pin all of the buffers into the GTT.
653 * This is done in 3 phases:
654 *
655 * 1a. Unbind all objects that do not match the GTT constraints for
656 * the execbuffer (fenceable, mappable, alignment etc).
657 * 1b. Increment pin count for already bound objects.
658 * 2. Bind new objects.
659 * 3. Decrement pin count.
660 *
661 * This avoid unnecessary unbinding of later objects in order to make
662 * room for the earlier objects *unless* we need to defragment.
663 */
664 retry = 0;
665 do {
666 int ret = 0;
667
668 /* Unbind any ill-fitting objects or pin. */
669 list_for_each_entry(vma, vmas, exec_list) {
670 if (!drm_mm_node_allocated(&vma->node))
671 continue;
672
673 if (eb_vma_misplaced(vma))
674 ret = i915_vma_unbind(vma);
675 else
676 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
677 if (ret)
678 goto err;
679 }
680
681 /* Bind fresh objects */
682 list_for_each_entry(vma, vmas, exec_list) {
683 if (drm_mm_node_allocated(&vma->node))
684 continue;
685
686 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
687 if (ret)
688 goto err;
689 }
690
691 err:
692 if (ret != -ENOSPC || retry++)
693 return ret;
694
695 /* Decrement pin count for bound objects */
696 list_for_each_entry(vma, vmas, exec_list)
697 i915_gem_execbuffer_unreserve_vma(vma);
698
699 ret = i915_gem_evict_vm(vm, true);
700 if (ret)
701 return ret;
702 } while (1);
703 }
704
705 static int
706 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
707 struct drm_i915_gem_execbuffer2 *args,
708 struct drm_file *file,
709 struct intel_engine_cs *ring,
710 struct eb_vmas *eb,
711 struct drm_i915_gem_exec_object2 *exec)
712 {
713 struct drm_i915_gem_relocation_entry *reloc;
714 struct i915_address_space *vm;
715 struct i915_vma *vma;
716 bool need_relocs;
717 int *reloc_offset;
718 int i, total, ret;
719 unsigned count = args->buffer_count;
720
721 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
722
723 /* We may process another execbuffer during the unlock... */
724 while (!list_empty(&eb->vmas)) {
725 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
726 list_del_init(&vma->exec_list);
727 i915_gem_execbuffer_unreserve_vma(vma);
728 drm_gem_object_unreference(&vma->obj->base);
729 }
730
731 mutex_unlock(&dev->struct_mutex);
732
733 total = 0;
734 for (i = 0; i < count; i++)
735 total += exec[i].relocation_count;
736
737 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
738 reloc = drm_malloc_ab(total, sizeof(*reloc));
739 if (reloc == NULL || reloc_offset == NULL) {
740 drm_free_large(reloc);
741 drm_free_large(reloc_offset);
742 mutex_lock(&dev->struct_mutex);
743 return -ENOMEM;
744 }
745
746 total = 0;
747 for (i = 0; i < count; i++) {
748 struct drm_i915_gem_relocation_entry __user *user_relocs;
749 u64 invalid_offset = (u64)-1;
750 int j;
751
752 user_relocs = to_user_ptr(exec[i].relocs_ptr);
753
754 if (copy_from_user(reloc+total, user_relocs,
755 exec[i].relocation_count * sizeof(*reloc))) {
756 ret = -EFAULT;
757 mutex_lock(&dev->struct_mutex);
758 goto err;
759 }
760
761 /* As we do not update the known relocation offsets after
762 * relocating (due to the complexities in lock handling),
763 * we need to mark them as invalid now so that we force the
764 * relocation processing next time. Just in case the target
765 * object is evicted and then rebound into its old
766 * presumed_offset before the next execbuffer - if that
767 * happened we would make the mistake of assuming that the
768 * relocations were valid.
769 */
770 for (j = 0; j < exec[i].relocation_count; j++) {
771 if (__copy_to_user(&user_relocs[j].presumed_offset,
772 &invalid_offset,
773 sizeof(invalid_offset))) {
774 ret = -EFAULT;
775 mutex_lock(&dev->struct_mutex);
776 goto err;
777 }
778 }
779
780 reloc_offset[i] = total;
781 total += exec[i].relocation_count;
782 }
783
784 ret = i915_mutex_lock_interruptible(dev);
785 if (ret) {
786 mutex_lock(&dev->struct_mutex);
787 goto err;
788 }
789
790 /* reacquire the objects */
791 eb_reset(eb);
792 ret = eb_lookup_vmas(eb, exec, args, vm, file);
793 if (ret)
794 goto err;
795
796 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
797 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
798 if (ret)
799 goto err;
800
801 list_for_each_entry(vma, &eb->vmas, exec_list) {
802 int offset = vma->exec_entry - exec;
803 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
804 reloc + reloc_offset[offset]);
805 if (ret)
806 goto err;
807 }
808
809 /* Leave the user relocations as are, this is the painfully slow path,
810 * and we want to avoid the complication of dropping the lock whilst
811 * having buffers reserved in the aperture and so causing spurious
812 * ENOSPC for random operations.
813 */
814
815 err:
816 drm_free_large(reloc);
817 drm_free_large(reloc_offset);
818 return ret;
819 }
820
821 static int
822 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
823 struct list_head *vmas)
824 {
825 struct i915_vma *vma;
826 uint32_t flush_domains = 0;
827 bool flush_chipset = false;
828 int ret;
829
830 list_for_each_entry(vma, vmas, exec_list) {
831 struct drm_i915_gem_object *obj = vma->obj;
832 ret = i915_gem_object_sync(obj, ring);
833 if (ret)
834 return ret;
835
836 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
837 flush_chipset |= i915_gem_clflush_object(obj, false);
838
839 flush_domains |= obj->base.write_domain;
840 }
841
842 if (flush_chipset)
843 i915_gem_chipset_flush(ring->dev);
844
845 if (flush_domains & I915_GEM_DOMAIN_GTT)
846 wmb();
847
848 /* Unconditionally invalidate gpu caches and ensure that we do flush
849 * any residual writes from the previous batch.
850 */
851 return intel_ring_invalidate_all_caches(ring);
852 }
853
854 static bool
855 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
856 {
857 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
858 return false;
859
860 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
861 }
862
863 static int
864 validate_exec_list(struct drm_device *dev,
865 struct drm_i915_gem_exec_object2 *exec,
866 int count)
867 {
868 unsigned relocs_total = 0;
869 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
870 unsigned invalid_flags;
871 int i;
872
873 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
874 if (USES_FULL_PPGTT(dev))
875 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
876
877 for (i = 0; i < count; i++) {
878 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
879 int length; /* limited by fault_in_pages_readable() */
880
881 if (exec[i].flags & invalid_flags)
882 return -EINVAL;
883
884 /* First check for malicious input causing overflow in
885 * the worst case where we need to allocate the entire
886 * relocation tree as a single array.
887 */
888 if (exec[i].relocation_count > relocs_max - relocs_total)
889 return -EINVAL;
890 relocs_total += exec[i].relocation_count;
891
892 length = exec[i].relocation_count *
893 sizeof(struct drm_i915_gem_relocation_entry);
894 /*
895 * We must check that the entire relocation array is safe
896 * to read, but since we may need to update the presumed
897 * offsets during execution, check for full write access.
898 */
899 if (!access_ok(VERIFY_WRITE, ptr, length))
900 return -EFAULT;
901
902 if (likely(!i915.prefault_disable)) {
903 if (fault_in_multipages_readable(ptr, length))
904 return -EFAULT;
905 }
906 }
907
908 return 0;
909 }
910
911 static struct intel_context *
912 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
913 struct intel_engine_cs *ring, const u32 ctx_id)
914 {
915 struct intel_context *ctx = NULL;
916 struct i915_ctx_hang_stats *hs;
917
918 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
919 return ERR_PTR(-EINVAL);
920
921 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
922 if (IS_ERR(ctx))
923 return ctx;
924
925 hs = &ctx->hang_stats;
926 if (hs->banned) {
927 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
928 return ERR_PTR(-EIO);
929 }
930
931 if (i915.enable_execlists && !ctx->engine[ring->id].state) {
932 int ret = intel_lr_context_deferred_create(ctx, ring);
933 if (ret) {
934 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
935 return ERR_PTR(ret);
936 }
937 }
938
939 return ctx;
940 }
941
942 void
943 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
944 struct intel_engine_cs *ring)
945 {
946 u32 seqno = intel_ring_get_seqno(ring);
947 struct i915_vma *vma;
948
949 list_for_each_entry(vma, vmas, exec_list) {
950 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
951 struct drm_i915_gem_object *obj = vma->obj;
952 u32 old_read = obj->base.read_domains;
953 u32 old_write = obj->base.write_domain;
954
955 obj->base.write_domain = obj->base.pending_write_domain;
956 if (obj->base.write_domain == 0)
957 obj->base.pending_read_domains |= obj->base.read_domains;
958 obj->base.read_domains = obj->base.pending_read_domains;
959
960 i915_vma_move_to_active(vma, ring);
961 if (obj->base.write_domain) {
962 obj->dirty = 1;
963 obj->last_write_seqno = seqno;
964
965 intel_fb_obj_invalidate(obj, ring);
966
967 /* update for the implicit flush after a batch */
968 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
969 }
970 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
971 obj->last_fenced_seqno = seqno;
972 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
973 struct drm_i915_private *dev_priv = to_i915(ring->dev);
974 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
975 &dev_priv->mm.fence_list);
976 }
977 }
978
979 trace_i915_gem_object_change_domain(obj, old_read, old_write);
980 }
981 }
982
983 void
984 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
985 struct drm_file *file,
986 struct intel_engine_cs *ring,
987 struct drm_i915_gem_object *obj)
988 {
989 /* Unconditionally force add_request to emit a full flush. */
990 ring->gpu_caches_dirty = true;
991
992 /* Add a breadcrumb for the completion of the batch buffer */
993 (void)__i915_add_request(ring, file, obj, NULL);
994 }
995
996 static int
997 i915_reset_gen7_sol_offsets(struct drm_device *dev,
998 struct intel_engine_cs *ring)
999 {
1000 struct drm_i915_private *dev_priv = dev->dev_private;
1001 int ret, i;
1002
1003 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1004 DRM_DEBUG("sol reset is gen7/rcs only\n");
1005 return -EINVAL;
1006 }
1007
1008 ret = intel_ring_begin(ring, 4 * 3);
1009 if (ret)
1010 return ret;
1011
1012 for (i = 0; i < 4; i++) {
1013 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1014 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1015 intel_ring_emit(ring, 0);
1016 }
1017
1018 intel_ring_advance(ring);
1019
1020 return 0;
1021 }
1022
1023 int
1024 i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
1025 struct intel_engine_cs *ring,
1026 struct intel_context *ctx,
1027 struct drm_i915_gem_execbuffer2 *args,
1028 struct list_head *vmas,
1029 struct drm_i915_gem_object *batch_obj,
1030 u64 exec_start, u32 flags)
1031 {
1032 struct drm_clip_rect *cliprects = NULL;
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u64 exec_len;
1035 int instp_mode;
1036 u32 instp_mask;
1037 int i, ret = 0;
1038
1039 if (args->num_cliprects != 0) {
1040 if (ring != &dev_priv->ring[RCS]) {
1041 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1042 return -EINVAL;
1043 }
1044
1045 if (INTEL_INFO(dev)->gen >= 5) {
1046 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1047 return -EINVAL;
1048 }
1049
1050 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1051 DRM_DEBUG("execbuf with %u cliprects\n",
1052 args->num_cliprects);
1053 return -EINVAL;
1054 }
1055
1056 cliprects = kcalloc(args->num_cliprects,
1057 sizeof(*cliprects),
1058 GFP_KERNEL);
1059 if (cliprects == NULL) {
1060 ret = -ENOMEM;
1061 goto error;
1062 }
1063
1064 if (copy_from_user(cliprects,
1065 to_user_ptr(args->cliprects_ptr),
1066 sizeof(*cliprects)*args->num_cliprects)) {
1067 ret = -EFAULT;
1068 goto error;
1069 }
1070 } else {
1071 if (args->DR4 == 0xffffffff) {
1072 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1073 args->DR4 = 0;
1074 }
1075
1076 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
1077 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1078 return -EINVAL;
1079 }
1080 }
1081
1082 ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
1083 if (ret)
1084 goto error;
1085
1086 ret = i915_switch_context(ring, ctx);
1087 if (ret)
1088 goto error;
1089
1090 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1091 instp_mask = I915_EXEC_CONSTANTS_MASK;
1092 switch (instp_mode) {
1093 case I915_EXEC_CONSTANTS_REL_GENERAL:
1094 case I915_EXEC_CONSTANTS_ABSOLUTE:
1095 case I915_EXEC_CONSTANTS_REL_SURFACE:
1096 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1097 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1098 ret = -EINVAL;
1099 goto error;
1100 }
1101
1102 if (instp_mode != dev_priv->relative_constants_mode) {
1103 if (INTEL_INFO(dev)->gen < 4) {
1104 DRM_DEBUG("no rel constants on pre-gen4\n");
1105 ret = -EINVAL;
1106 goto error;
1107 }
1108
1109 if (INTEL_INFO(dev)->gen > 5 &&
1110 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1111 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1112 ret = -EINVAL;
1113 goto error;
1114 }
1115
1116 /* The HW changed the meaning on this bit on gen6 */
1117 if (INTEL_INFO(dev)->gen >= 6)
1118 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1119 }
1120 break;
1121 default:
1122 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1123 ret = -EINVAL;
1124 goto error;
1125 }
1126
1127 if (ring == &dev_priv->ring[RCS] &&
1128 instp_mode != dev_priv->relative_constants_mode) {
1129 ret = intel_ring_begin(ring, 4);
1130 if (ret)
1131 goto error;
1132
1133 intel_ring_emit(ring, MI_NOOP);
1134 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1135 intel_ring_emit(ring, INSTPM);
1136 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1137 intel_ring_advance(ring);
1138
1139 dev_priv->relative_constants_mode = instp_mode;
1140 }
1141
1142 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1143 ret = i915_reset_gen7_sol_offsets(dev, ring);
1144 if (ret)
1145 goto error;
1146 }
1147
1148 exec_len = args->batch_len;
1149 if (cliprects) {
1150 for (i = 0; i < args->num_cliprects; i++) {
1151 ret = i915_emit_box(dev, &cliprects[i],
1152 args->DR1, args->DR4);
1153 if (ret)
1154 goto error;
1155
1156 ret = ring->dispatch_execbuffer(ring,
1157 exec_start, exec_len,
1158 flags);
1159 if (ret)
1160 goto error;
1161 }
1162 } else {
1163 ret = ring->dispatch_execbuffer(ring,
1164 exec_start, exec_len,
1165 flags);
1166 if (ret)
1167 return ret;
1168 }
1169
1170 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1171
1172 i915_gem_execbuffer_move_to_active(vmas, ring);
1173 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1174
1175 error:
1176 kfree(cliprects);
1177 return ret;
1178 }
1179
1180 /**
1181 * Find one BSD ring to dispatch the corresponding BSD command.
1182 * The Ring ID is returned.
1183 */
1184 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1185 struct drm_file *file)
1186 {
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 struct drm_i915_file_private *file_priv = file->driver_priv;
1189
1190 /* Check whether the file_priv is using one ring */
1191 if (file_priv->bsd_ring)
1192 return file_priv->bsd_ring->id;
1193 else {
1194 /* If no, use the ping-pong mechanism to select one ring */
1195 int ring_id;
1196
1197 mutex_lock(&dev->struct_mutex);
1198 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1199 ring_id = VCS;
1200 dev_priv->mm.bsd_ring_dispatch_index = 1;
1201 } else {
1202 ring_id = VCS2;
1203 dev_priv->mm.bsd_ring_dispatch_index = 0;
1204 }
1205 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1206 mutex_unlock(&dev->struct_mutex);
1207 return ring_id;
1208 }
1209 }
1210
1211 static struct drm_i915_gem_object *
1212 eb_get_batch(struct eb_vmas *eb)
1213 {
1214 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1215
1216 /*
1217 * SNA is doing fancy tricks with compressing batch buffers, which leads
1218 * to negative relocation deltas. Usually that works out ok since the
1219 * relocate address is still positive, except when the batch is placed
1220 * very low in the GTT. Ensure this doesn't happen.
1221 *
1222 * Note that actual hangs have only been observed on gen7, but for
1223 * paranoia do it everywhere.
1224 */
1225 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1226
1227 return vma->obj;
1228 }
1229
1230 static int
1231 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1232 struct drm_file *file,
1233 struct drm_i915_gem_execbuffer2 *args,
1234 struct drm_i915_gem_exec_object2 *exec)
1235 {
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 struct eb_vmas *eb;
1238 struct drm_i915_gem_object *batch_obj;
1239 struct intel_engine_cs *ring;
1240 struct intel_context *ctx;
1241 struct i915_address_space *vm;
1242 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1243 u64 exec_start = args->batch_start_offset;
1244 u32 flags;
1245 int ret;
1246 bool need_relocs;
1247
1248 if (!i915_gem_check_execbuffer(args))
1249 return -EINVAL;
1250
1251 ret = validate_exec_list(dev, exec, args->buffer_count);
1252 if (ret)
1253 return ret;
1254
1255 flags = 0;
1256 if (args->flags & I915_EXEC_SECURE) {
1257 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1258 return -EPERM;
1259
1260 flags |= I915_DISPATCH_SECURE;
1261 }
1262 if (args->flags & I915_EXEC_IS_PINNED)
1263 flags |= I915_DISPATCH_PINNED;
1264
1265 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1266 DRM_DEBUG("execbuf with unknown ring: %d\n",
1267 (int)(args->flags & I915_EXEC_RING_MASK));
1268 return -EINVAL;
1269 }
1270
1271 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1272 ring = &dev_priv->ring[RCS];
1273 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1274 if (HAS_BSD2(dev)) {
1275 int ring_id;
1276 ring_id = gen8_dispatch_bsd_ring(dev, file);
1277 ring = &dev_priv->ring[ring_id];
1278 } else
1279 ring = &dev_priv->ring[VCS];
1280 } else
1281 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1282
1283 if (!intel_ring_initialized(ring)) {
1284 DRM_DEBUG("execbuf with invalid ring: %d\n",
1285 (int)(args->flags & I915_EXEC_RING_MASK));
1286 return -EINVAL;
1287 }
1288
1289 if (args->buffer_count < 1) {
1290 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1291 return -EINVAL;
1292 }
1293
1294 intel_runtime_pm_get(dev_priv);
1295
1296 ret = i915_mutex_lock_interruptible(dev);
1297 if (ret)
1298 goto pre_mutex_err;
1299
1300 if (dev_priv->ums.mm_suspended) {
1301 mutex_unlock(&dev->struct_mutex);
1302 ret = -EBUSY;
1303 goto pre_mutex_err;
1304 }
1305
1306 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1307 if (IS_ERR(ctx)) {
1308 mutex_unlock(&dev->struct_mutex);
1309 ret = PTR_ERR(ctx);
1310 goto pre_mutex_err;
1311 }
1312
1313 i915_gem_context_reference(ctx);
1314
1315 if (ctx->ppgtt)
1316 vm = &ctx->ppgtt->base;
1317 else
1318 vm = &dev_priv->gtt.base;
1319
1320 eb = eb_create(args);
1321 if (eb == NULL) {
1322 i915_gem_context_unreference(ctx);
1323 mutex_unlock(&dev->struct_mutex);
1324 ret = -ENOMEM;
1325 goto pre_mutex_err;
1326 }
1327
1328 /* Look up object handles */
1329 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1330 if (ret)
1331 goto err;
1332
1333 /* take note of the batch buffer before we might reorder the lists */
1334 batch_obj = eb_get_batch(eb);
1335
1336 /* Move the objects en-masse into the GTT, evicting if necessary. */
1337 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1338 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
1339 if (ret)
1340 goto err;
1341
1342 /* The objects are in their final locations, apply the relocations. */
1343 if (need_relocs)
1344 ret = i915_gem_execbuffer_relocate(eb);
1345 if (ret) {
1346 if (ret == -EFAULT) {
1347 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1348 eb, exec);
1349 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1350 }
1351 if (ret)
1352 goto err;
1353 }
1354
1355 /* Set the pending read domains for the batch buffer to COMMAND */
1356 if (batch_obj->base.pending_write_domain) {
1357 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1358 ret = -EINVAL;
1359 goto err;
1360 }
1361 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1362
1363 if (i915_needs_cmd_parser(ring)) {
1364 ret = i915_parse_cmds(ring,
1365 batch_obj,
1366 args->batch_start_offset,
1367 file->is_master);
1368 if (ret) {
1369 if (ret != -EACCES)
1370 goto err;
1371 } else {
1372 /*
1373 * XXX: Actually do this when enabling batch copy...
1374 *
1375 * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
1376 * from MI_BATCH_BUFFER_START commands issued in the
1377 * dispatch_execbuffer implementations. We specifically don't
1378 * want that set when the command parser is enabled.
1379 */
1380 }
1381 }
1382
1383 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1384 * batch" bit. Hence we need to pin secure batches into the global gtt.
1385 * hsw should have this fixed, but bdw mucks it up again. */
1386 if (flags & I915_DISPATCH_SECURE) {
1387 /*
1388 * So on first glance it looks freaky that we pin the batch here
1389 * outside of the reservation loop. But:
1390 * - The batch is already pinned into the relevant ppgtt, so we
1391 * already have the backing storage fully allocated.
1392 * - No other BO uses the global gtt (well contexts, but meh),
1393 * so we don't really have issues with mutliple objects not
1394 * fitting due to fragmentation.
1395 * So this is actually safe.
1396 */
1397 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1398 if (ret)
1399 goto err;
1400
1401 exec_start += i915_gem_obj_ggtt_offset(batch_obj);
1402 } else
1403 exec_start += i915_gem_obj_offset(batch_obj, vm);
1404
1405 ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args,
1406 &eb->vmas, batch_obj, exec_start, flags);
1407
1408 /*
1409 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1410 * batch vma for correctness. For less ugly and less fragility this
1411 * needs to be adjusted to also track the ggtt batch vma properly as
1412 * active.
1413 */
1414 if (flags & I915_DISPATCH_SECURE)
1415 i915_gem_object_ggtt_unpin(batch_obj);
1416 err:
1417 /* the request owns the ref now */
1418 i915_gem_context_unreference(ctx);
1419 eb_destroy(eb);
1420
1421 mutex_unlock(&dev->struct_mutex);
1422
1423 pre_mutex_err:
1424 /* intel_gpu_busy should also get a ref, so it will free when the device
1425 * is really idle. */
1426 intel_runtime_pm_put(dev_priv);
1427 return ret;
1428 }
1429
1430 /*
1431 * Legacy execbuffer just creates an exec2 list from the original exec object
1432 * list array and passes it to the real function.
1433 */
1434 int
1435 i915_gem_execbuffer(struct drm_device *dev, void *data,
1436 struct drm_file *file)
1437 {
1438 struct drm_i915_gem_execbuffer *args = data;
1439 struct drm_i915_gem_execbuffer2 exec2;
1440 struct drm_i915_gem_exec_object *exec_list = NULL;
1441 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1442 int ret, i;
1443
1444 if (args->buffer_count < 1) {
1445 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1446 return -EINVAL;
1447 }
1448
1449 /* Copy in the exec list from userland */
1450 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1451 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1452 if (exec_list == NULL || exec2_list == NULL) {
1453 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1454 args->buffer_count);
1455 drm_free_large(exec_list);
1456 drm_free_large(exec2_list);
1457 return -ENOMEM;
1458 }
1459 ret = copy_from_user(exec_list,
1460 to_user_ptr(args->buffers_ptr),
1461 sizeof(*exec_list) * args->buffer_count);
1462 if (ret != 0) {
1463 DRM_DEBUG("copy %d exec entries failed %d\n",
1464 args->buffer_count, ret);
1465 drm_free_large(exec_list);
1466 drm_free_large(exec2_list);
1467 return -EFAULT;
1468 }
1469
1470 for (i = 0; i < args->buffer_count; i++) {
1471 exec2_list[i].handle = exec_list[i].handle;
1472 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1473 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1474 exec2_list[i].alignment = exec_list[i].alignment;
1475 exec2_list[i].offset = exec_list[i].offset;
1476 if (INTEL_INFO(dev)->gen < 4)
1477 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1478 else
1479 exec2_list[i].flags = 0;
1480 }
1481
1482 exec2.buffers_ptr = args->buffers_ptr;
1483 exec2.buffer_count = args->buffer_count;
1484 exec2.batch_start_offset = args->batch_start_offset;
1485 exec2.batch_len = args->batch_len;
1486 exec2.DR1 = args->DR1;
1487 exec2.DR4 = args->DR4;
1488 exec2.num_cliprects = args->num_cliprects;
1489 exec2.cliprects_ptr = args->cliprects_ptr;
1490 exec2.flags = I915_EXEC_RENDER;
1491 i915_execbuffer2_set_context_id(exec2, 0);
1492
1493 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1494 if (!ret) {
1495 struct drm_i915_gem_exec_object __user *user_exec_list =
1496 to_user_ptr(args->buffers_ptr);
1497
1498 /* Copy the new buffer offsets back to the user's exec list. */
1499 for (i = 0; i < args->buffer_count; i++) {
1500 ret = __copy_to_user(&user_exec_list[i].offset,
1501 &exec2_list[i].offset,
1502 sizeof(user_exec_list[i].offset));
1503 if (ret) {
1504 ret = -EFAULT;
1505 DRM_DEBUG("failed to copy %d exec entries "
1506 "back to user (%d)\n",
1507 args->buffer_count, ret);
1508 break;
1509 }
1510 }
1511 }
1512
1513 drm_free_large(exec_list);
1514 drm_free_large(exec2_list);
1515 return ret;
1516 }
1517
1518 int
1519 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1520 struct drm_file *file)
1521 {
1522 struct drm_i915_gem_execbuffer2 *args = data;
1523 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1524 int ret;
1525
1526 if (args->buffer_count < 1 ||
1527 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1528 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1529 return -EINVAL;
1530 }
1531
1532 if (args->rsvd2 != 0) {
1533 DRM_DEBUG("dirty rvsd2 field\n");
1534 return -EINVAL;
1535 }
1536
1537 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1538 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1539 if (exec2_list == NULL)
1540 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1541 args->buffer_count);
1542 if (exec2_list == NULL) {
1543 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1544 args->buffer_count);
1545 return -ENOMEM;
1546 }
1547 ret = copy_from_user(exec2_list,
1548 to_user_ptr(args->buffers_ptr),
1549 sizeof(*exec2_list) * args->buffer_count);
1550 if (ret != 0) {
1551 DRM_DEBUG("copy %d exec entries failed %d\n",
1552 args->buffer_count, ret);
1553 drm_free_large(exec2_list);
1554 return -EFAULT;
1555 }
1556
1557 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1558 if (!ret) {
1559 /* Copy the new buffer offsets back to the user's exec list. */
1560 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1561 to_user_ptr(args->buffers_ptr);
1562 int i;
1563
1564 for (i = 0; i < args->buffer_count; i++) {
1565 ret = __copy_to_user(&user_exec_list[i].offset,
1566 &exec2_list[i].offset,
1567 sizeof(user_exec_list[i].offset));
1568 if (ret) {
1569 ret = -EFAULT;
1570 DRM_DEBUG("failed to copy %d exec entries "
1571 "back to user\n",
1572 args->buffer_count);
1573 break;
1574 }
1575 }
1576 }
1577
1578 drm_free_large(exec2_list);
1579 return ret;
1580 }
Linux kernel - Deliverables
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