2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
40 #define __EXEC_OBJECT_PURGEABLE (1<<27)
42 #define BATCH_OFFSET_BIAS (256*1024)
45 struct list_head vmas
;
48 struct i915_vma
*lut
[0];
49 struct hlist_head buckets
[0];
53 static struct eb_vmas
*
54 eb_create(struct drm_i915_gem_execbuffer2
*args
)
56 struct eb_vmas
*eb
= NULL
;
58 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
59 unsigned size
= args
->buffer_count
;
60 size
*= sizeof(struct i915_vma
*);
61 size
+= sizeof(struct eb_vmas
);
62 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
66 unsigned size
= args
->buffer_count
;
67 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
68 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
69 while (count
> 2*size
)
71 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
72 sizeof(struct eb_vmas
),
79 eb
->and = -args
->buffer_count
;
81 INIT_LIST_HEAD(&eb
->vmas
);
86 eb_reset(struct eb_vmas
*eb
)
89 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
93 eb_lookup_vmas(struct eb_vmas
*eb
,
94 struct drm_i915_gem_exec_object2
*exec
,
95 const struct drm_i915_gem_execbuffer2
*args
,
96 struct i915_address_space
*vm
,
97 struct drm_file
*file
)
99 struct drm_i915_gem_object
*obj
;
100 struct list_head objects
;
103 INIT_LIST_HEAD(&objects
);
104 spin_lock(&file
->table_lock
);
105 /* Grab a reference to the object and release the lock so we can lookup
106 * or create the VMA without using GFP_ATOMIC */
107 for (i
= 0; i
< args
->buffer_count
; i
++) {
108 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
110 spin_unlock(&file
->table_lock
);
111 DRM_DEBUG("Invalid object handle %d at index %d\n",
117 if (!list_empty(&obj
->obj_exec_link
)) {
118 spin_unlock(&file
->table_lock
);
119 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
120 obj
, exec
[i
].handle
, i
);
125 drm_gem_object_reference(&obj
->base
);
126 list_add_tail(&obj
->obj_exec_link
, &objects
);
128 spin_unlock(&file
->table_lock
);
131 while (!list_empty(&objects
)) {
132 struct i915_vma
*vma
;
134 obj
= list_first_entry(&objects
,
135 struct drm_i915_gem_object
,
139 * NOTE: We can leak any vmas created here when something fails
140 * later on. But that's no issue since vma_unbind can deal with
141 * vmas which are not actually bound. And since only
142 * lookup_or_create exists as an interface to get at the vma
143 * from the (obj, vm) we don't run the risk of creating
144 * duplicated vmas for the same vm.
146 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
148 DRM_DEBUG("Failed to lookup VMA\n");
153 /* Transfer ownership from the objects list to the vmas list. */
154 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
155 list_del_init(&obj
->obj_exec_link
);
157 vma
->exec_entry
= &exec
[i
];
161 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
162 vma
->exec_handle
= handle
;
163 hlist_add_head(&vma
->exec_node
,
164 &eb
->buckets
[handle
& eb
->and]);
173 while (!list_empty(&objects
)) {
174 obj
= list_first_entry(&objects
,
175 struct drm_i915_gem_object
,
177 list_del_init(&obj
->obj_exec_link
);
178 drm_gem_object_unreference(&obj
->base
);
181 * Objects already transfered to the vmas list will be unreferenced by
188 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
191 if (handle
>= -eb
->and)
193 return eb
->lut
[handle
];
195 struct hlist_head
*head
;
196 struct hlist_node
*node
;
198 head
= &eb
->buckets
[handle
& eb
->and];
199 hlist_for_each(node
, head
) {
200 struct i915_vma
*vma
;
202 vma
= hlist_entry(node
, struct i915_vma
, exec_node
);
203 if (vma
->exec_handle
== handle
)
211 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
213 struct drm_i915_gem_exec_object2
*entry
;
214 struct drm_i915_gem_object
*obj
= vma
->obj
;
216 if (!drm_mm_node_allocated(&vma
->node
))
219 entry
= vma
->exec_entry
;
221 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
222 i915_gem_object_unpin_fence(obj
);
224 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
227 if (entry
->flags
& __EXEC_OBJECT_PURGEABLE
)
228 obj
->madv
= I915_MADV_DONTNEED
;
230 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
|
231 __EXEC_OBJECT_HAS_PIN
|
232 __EXEC_OBJECT_PURGEABLE
);
235 static void eb_destroy(struct eb_vmas
*eb
)
237 while (!list_empty(&eb
->vmas
)) {
238 struct i915_vma
*vma
;
240 vma
= list_first_entry(&eb
->vmas
,
243 list_del_init(&vma
->exec_list
);
244 i915_gem_execbuffer_unreserve_vma(vma
);
245 drm_gem_object_unreference(&vma
->obj
->base
);
250 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
252 return (HAS_LLC(obj
->base
.dev
) ||
253 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
254 !obj
->map_and_fenceable
||
255 obj
->cache_level
!= I915_CACHE_NONE
);
259 relocate_entry_cpu(struct drm_i915_gem_object
*obj
,
260 struct drm_i915_gem_relocation_entry
*reloc
,
261 uint64_t target_offset
)
263 struct drm_device
*dev
= obj
->base
.dev
;
264 uint32_t page_offset
= offset_in_page(reloc
->offset
);
265 uint64_t delta
= reloc
->delta
+ target_offset
;
269 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
273 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
274 reloc
->offset
>> PAGE_SHIFT
));
275 *(uint32_t *)(vaddr
+ page_offset
) = lower_32_bits(delta
);
277 if (INTEL_INFO(dev
)->gen
>= 8) {
278 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
280 if (page_offset
== 0) {
281 kunmap_atomic(vaddr
);
282 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
283 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
286 *(uint32_t *)(vaddr
+ page_offset
) = upper_32_bits(delta
);
289 kunmap_atomic(vaddr
);
295 relocate_entry_gtt(struct drm_i915_gem_object
*obj
,
296 struct drm_i915_gem_relocation_entry
*reloc
,
297 uint64_t target_offset
)
299 struct drm_device
*dev
= obj
->base
.dev
;
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
301 uint64_t delta
= reloc
->delta
+ target_offset
;
303 void __iomem
*reloc_page
;
306 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
310 ret
= i915_gem_object_put_fence(obj
);
314 /* Map the page containing the relocation we're going to perform. */
315 offset
= i915_gem_obj_ggtt_offset(obj
);
316 offset
+= reloc
->offset
;
317 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
319 iowrite32(lower_32_bits(delta
), reloc_page
+ offset_in_page(offset
));
321 if (INTEL_INFO(dev
)->gen
>= 8) {
322 offset
+= sizeof(uint32_t);
324 if (offset_in_page(offset
) == 0) {
325 io_mapping_unmap_atomic(reloc_page
);
327 io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
331 iowrite32(upper_32_bits(delta
),
332 reloc_page
+ offset_in_page(offset
));
335 io_mapping_unmap_atomic(reloc_page
);
341 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
343 struct drm_i915_gem_relocation_entry
*reloc
)
345 struct drm_device
*dev
= obj
->base
.dev
;
346 struct drm_gem_object
*target_obj
;
347 struct drm_i915_gem_object
*target_i915_obj
;
348 struct i915_vma
*target_vma
;
349 uint64_t target_offset
;
352 /* we've already hold a reference to all valid objects */
353 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
354 if (unlikely(target_vma
== NULL
))
356 target_i915_obj
= target_vma
->obj
;
357 target_obj
= &target_vma
->obj
->base
;
359 target_offset
= target_vma
->node
.start
;
361 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
362 * pipe_control writes because the gpu doesn't properly redirect them
363 * through the ppgtt for non_secure batchbuffers. */
364 if (unlikely(IS_GEN6(dev
) &&
365 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
&&
366 !(target_vma
->bound
& GLOBAL_BIND
))) {
367 ret
= i915_vma_bind(target_vma
, target_i915_obj
->cache_level
,
369 if (WARN_ONCE(ret
, "Unexpected failure to bind target VMA!"))
373 /* Validate that the target is in a valid r/w GPU domain */
374 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
375 DRM_DEBUG("reloc with multiple write domains: "
376 "obj %p target %d offset %d "
377 "read %08x write %08x",
378 obj
, reloc
->target_handle
,
381 reloc
->write_domain
);
384 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
385 & ~I915_GEM_GPU_DOMAINS
)) {
386 DRM_DEBUG("reloc with read/write non-GPU domains: "
387 "obj %p target %d offset %d "
388 "read %08x write %08x",
389 obj
, reloc
->target_handle
,
392 reloc
->write_domain
);
396 target_obj
->pending_read_domains
|= reloc
->read_domains
;
397 target_obj
->pending_write_domain
|= reloc
->write_domain
;
399 /* If the relocation already has the right value in it, no
400 * more work needs to be done.
402 if (target_offset
== reloc
->presumed_offset
)
405 /* Check that the relocation address is valid... */
406 if (unlikely(reloc
->offset
>
407 obj
->base
.size
- (INTEL_INFO(dev
)->gen
>= 8 ? 8 : 4))) {
408 DRM_DEBUG("Relocation beyond object bounds: "
409 "obj %p target %d offset %d size %d.\n",
410 obj
, reloc
->target_handle
,
412 (int) obj
->base
.size
);
415 if (unlikely(reloc
->offset
& 3)) {
416 DRM_DEBUG("Relocation not 4-byte aligned: "
417 "obj %p target %d offset %d.\n",
418 obj
, reloc
->target_handle
,
419 (int) reloc
->offset
);
423 /* We can't wait for rendering with pagefaults disabled */
424 if (obj
->active
&& in_atomic())
427 if (use_cpu_reloc(obj
))
428 ret
= relocate_entry_cpu(obj
, reloc
, target_offset
);
430 ret
= relocate_entry_gtt(obj
, reloc
, target_offset
);
435 /* and update the user's relocation entry */
436 reloc
->presumed_offset
= target_offset
;
442 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
445 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
446 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
447 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
448 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
451 user_relocs
= to_user_ptr(entry
->relocs_ptr
);
453 remain
= entry
->relocation_count
;
455 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
457 if (count
> ARRAY_SIZE(stack_reloc
))
458 count
= ARRAY_SIZE(stack_reloc
);
461 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
465 u64 offset
= r
->presumed_offset
;
467 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
);
471 if (r
->presumed_offset
!= offset
&&
472 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
474 sizeof(r
->presumed_offset
))) {
488 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
490 struct drm_i915_gem_relocation_entry
*relocs
)
492 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
495 for (i
= 0; i
< entry
->relocation_count
; i
++) {
496 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
]);
505 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
507 struct i915_vma
*vma
;
510 /* This is the fast path and we cannot handle a pagefault whilst
511 * holding the struct mutex lest the user pass in the relocations
512 * contained within a mmaped bo. For in such a case we, the page
513 * fault handler would call i915_gem_fault() and we would try to
514 * acquire the struct mutex again. Obviously this is bad and so
515 * lockdep complains vehemently.
518 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
519 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
529 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
530 struct intel_engine_cs
*ring
,
533 struct drm_i915_gem_object
*obj
= vma
->obj
;
534 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
539 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
540 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
541 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
543 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
544 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
546 ret
= i915_gem_object_pin(obj
, vma
->vm
, entry
->alignment
, flags
);
550 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
552 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
553 ret
= i915_gem_object_get_fence(obj
);
557 if (i915_gem_object_pin_fence(obj
))
558 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
561 if (entry
->offset
!= vma
->node
.start
) {
562 entry
->offset
= vma
->node
.start
;
566 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
567 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
568 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
575 need_reloc_mappable(struct i915_vma
*vma
)
577 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
579 if (entry
->relocation_count
== 0)
582 if (!i915_is_ggtt(vma
->vm
))
585 /* See also use_cpu_reloc() */
586 if (HAS_LLC(vma
->obj
->base
.dev
))
589 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
596 eb_vma_misplaced(struct i915_vma
*vma
)
598 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
599 struct drm_i915_gem_object
*obj
= vma
->obj
;
601 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
602 !i915_is_ggtt(vma
->vm
));
604 if (entry
->alignment
&&
605 vma
->node
.start
& (entry
->alignment
- 1))
608 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !obj
->map_and_fenceable
)
611 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
612 vma
->node
.start
< BATCH_OFFSET_BIAS
)
619 i915_gem_execbuffer_reserve(struct intel_engine_cs
*ring
,
620 struct list_head
*vmas
,
623 struct drm_i915_gem_object
*obj
;
624 struct i915_vma
*vma
;
625 struct i915_address_space
*vm
;
626 struct list_head ordered_vmas
;
627 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
630 i915_gem_retire_requests_ring(ring
);
632 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
634 INIT_LIST_HEAD(&ordered_vmas
);
635 while (!list_empty(vmas
)) {
636 struct drm_i915_gem_exec_object2
*entry
;
637 bool need_fence
, need_mappable
;
639 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
641 entry
= vma
->exec_entry
;
643 if (!has_fenced_gpu_access
)
644 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
646 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
647 obj
->tiling_mode
!= I915_TILING_NONE
;
648 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
651 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
652 list_move(&vma
->exec_list
, &ordered_vmas
);
654 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
656 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
657 obj
->base
.pending_write_domain
= 0;
659 list_splice(&ordered_vmas
, vmas
);
661 /* Attempt to pin all of the buffers into the GTT.
662 * This is done in 3 phases:
664 * 1a. Unbind all objects that do not match the GTT constraints for
665 * the execbuffer (fenceable, mappable, alignment etc).
666 * 1b. Increment pin count for already bound objects.
667 * 2. Bind new objects.
668 * 3. Decrement pin count.
670 * This avoid unnecessary unbinding of later objects in order to make
671 * room for the earlier objects *unless* we need to defragment.
677 /* Unbind any ill-fitting objects or pin. */
678 list_for_each_entry(vma
, vmas
, exec_list
) {
679 if (!drm_mm_node_allocated(&vma
->node
))
682 if (eb_vma_misplaced(vma
))
683 ret
= i915_vma_unbind(vma
);
685 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
690 /* Bind fresh objects */
691 list_for_each_entry(vma
, vmas
, exec_list
) {
692 if (drm_mm_node_allocated(&vma
->node
))
695 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
701 if (ret
!= -ENOSPC
|| retry
++)
704 /* Decrement pin count for bound objects */
705 list_for_each_entry(vma
, vmas
, exec_list
)
706 i915_gem_execbuffer_unreserve_vma(vma
);
708 ret
= i915_gem_evict_vm(vm
, true);
715 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
716 struct drm_i915_gem_execbuffer2
*args
,
717 struct drm_file
*file
,
718 struct intel_engine_cs
*ring
,
720 struct drm_i915_gem_exec_object2
*exec
)
722 struct drm_i915_gem_relocation_entry
*reloc
;
723 struct i915_address_space
*vm
;
724 struct i915_vma
*vma
;
728 unsigned count
= args
->buffer_count
;
730 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
732 /* We may process another execbuffer during the unlock... */
733 while (!list_empty(&eb
->vmas
)) {
734 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
735 list_del_init(&vma
->exec_list
);
736 i915_gem_execbuffer_unreserve_vma(vma
);
737 drm_gem_object_unreference(&vma
->obj
->base
);
740 mutex_unlock(&dev
->struct_mutex
);
743 for (i
= 0; i
< count
; i
++)
744 total
+= exec
[i
].relocation_count
;
746 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
747 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
748 if (reloc
== NULL
|| reloc_offset
== NULL
) {
749 drm_free_large(reloc
);
750 drm_free_large(reloc_offset
);
751 mutex_lock(&dev
->struct_mutex
);
756 for (i
= 0; i
< count
; i
++) {
757 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
758 u64 invalid_offset
= (u64
)-1;
761 user_relocs
= to_user_ptr(exec
[i
].relocs_ptr
);
763 if (copy_from_user(reloc
+total
, user_relocs
,
764 exec
[i
].relocation_count
* sizeof(*reloc
))) {
766 mutex_lock(&dev
->struct_mutex
);
770 /* As we do not update the known relocation offsets after
771 * relocating (due to the complexities in lock handling),
772 * we need to mark them as invalid now so that we force the
773 * relocation processing next time. Just in case the target
774 * object is evicted and then rebound into its old
775 * presumed_offset before the next execbuffer - if that
776 * happened we would make the mistake of assuming that the
777 * relocations were valid.
779 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
780 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
782 sizeof(invalid_offset
))) {
784 mutex_lock(&dev
->struct_mutex
);
789 reloc_offset
[i
] = total
;
790 total
+= exec
[i
].relocation_count
;
793 ret
= i915_mutex_lock_interruptible(dev
);
795 mutex_lock(&dev
->struct_mutex
);
799 /* reacquire the objects */
801 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
805 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
806 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, &need_relocs
);
810 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
811 int offset
= vma
->exec_entry
- exec
;
812 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
813 reloc
+ reloc_offset
[offset
]);
818 /* Leave the user relocations as are, this is the painfully slow path,
819 * and we want to avoid the complication of dropping the lock whilst
820 * having buffers reserved in the aperture and so causing spurious
821 * ENOSPC for random operations.
825 drm_free_large(reloc
);
826 drm_free_large(reloc_offset
);
831 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring
,
832 struct list_head
*vmas
)
834 struct i915_vma
*vma
;
835 uint32_t flush_domains
= 0;
836 bool flush_chipset
= false;
839 list_for_each_entry(vma
, vmas
, exec_list
) {
840 struct drm_i915_gem_object
*obj
= vma
->obj
;
841 ret
= i915_gem_object_sync(obj
, ring
);
845 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
846 flush_chipset
|= i915_gem_clflush_object(obj
, false);
848 flush_domains
|= obj
->base
.write_domain
;
852 i915_gem_chipset_flush(ring
->dev
);
854 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
857 /* Unconditionally invalidate gpu caches and ensure that we do flush
858 * any residual writes from the previous batch.
860 return intel_ring_invalidate_all_caches(ring
);
864 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
866 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
869 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
873 validate_exec_list(struct drm_device
*dev
,
874 struct drm_i915_gem_exec_object2
*exec
,
877 unsigned relocs_total
= 0;
878 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
879 unsigned invalid_flags
;
882 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
883 if (USES_FULL_PPGTT(dev
))
884 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
886 for (i
= 0; i
< count
; i
++) {
887 char __user
*ptr
= to_user_ptr(exec
[i
].relocs_ptr
);
888 int length
; /* limited by fault_in_pages_readable() */
890 if (exec
[i
].flags
& invalid_flags
)
893 /* First check for malicious input causing overflow in
894 * the worst case where we need to allocate the entire
895 * relocation tree as a single array.
897 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
899 relocs_total
+= exec
[i
].relocation_count
;
901 length
= exec
[i
].relocation_count
*
902 sizeof(struct drm_i915_gem_relocation_entry
);
904 * We must check that the entire relocation array is safe
905 * to read, but since we may need to update the presumed
906 * offsets during execution, check for full write access.
908 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
911 if (likely(!i915
.prefault_disable
)) {
912 if (fault_in_multipages_readable(ptr
, length
))
920 static struct intel_context
*
921 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
922 struct intel_engine_cs
*ring
, const u32 ctx_id
)
924 struct intel_context
*ctx
= NULL
;
925 struct i915_ctx_hang_stats
*hs
;
927 if (ring
->id
!= RCS
&& ctx_id
!= DEFAULT_CONTEXT_HANDLE
)
928 return ERR_PTR(-EINVAL
);
930 ctx
= i915_gem_context_get(file
->driver_priv
, ctx_id
);
934 hs
= &ctx
->hang_stats
;
936 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
937 return ERR_PTR(-EIO
);
940 if (i915
.enable_execlists
&& !ctx
->engine
[ring
->id
].state
) {
941 int ret
= intel_lr_context_deferred_create(ctx
, ring
);
943 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id
, ret
);
952 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
953 struct intel_engine_cs
*ring
)
955 struct drm_i915_gem_request
*req
= intel_ring_get_request(ring
);
956 struct i915_vma
*vma
;
958 list_for_each_entry(vma
, vmas
, exec_list
) {
959 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
960 struct drm_i915_gem_object
*obj
= vma
->obj
;
961 u32 old_read
= obj
->base
.read_domains
;
962 u32 old_write
= obj
->base
.write_domain
;
964 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
965 if (obj
->base
.write_domain
== 0)
966 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
967 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
969 i915_vma_move_to_active(vma
, ring
);
970 if (obj
->base
.write_domain
) {
972 i915_gem_request_assign(&obj
->last_write_req
, req
);
974 intel_fb_obj_invalidate(obj
, ring
);
976 /* update for the implicit flush after a batch */
977 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
979 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
980 i915_gem_request_assign(&obj
->last_fenced_req
, req
);
981 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
982 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
983 list_move_tail(&dev_priv
->fence_regs
[obj
->fence_reg
].lru_list
,
984 &dev_priv
->mm
.fence_list
);
988 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
993 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
994 struct drm_file
*file
,
995 struct intel_engine_cs
*ring
,
996 struct drm_i915_gem_object
*obj
)
998 /* Unconditionally force add_request to emit a full flush. */
999 ring
->gpu_caches_dirty
= true;
1001 /* Add a breadcrumb for the completion of the batch buffer */
1002 (void)__i915_add_request(ring
, file
, obj
);
1006 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
1007 struct intel_engine_cs
*ring
)
1009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1012 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
]) {
1013 DRM_DEBUG("sol reset is gen7/rcs only\n");
1017 ret
= intel_ring_begin(ring
, 4 * 3);
1021 for (i
= 0; i
< 4; i
++) {
1022 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1023 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
1024 intel_ring_emit(ring
, 0);
1027 intel_ring_advance(ring
);
1033 i915_emit_box(struct intel_engine_cs
*ring
,
1034 struct drm_clip_rect
*box
,
1039 if (box
->y2
<= box
->y1
|| box
->x2
<= box
->x1
||
1040 box
->y2
<= 0 || box
->x2
<= 0) {
1041 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1042 box
->x1
, box
->y1
, box
->x2
, box
->y2
);
1046 if (INTEL_INFO(ring
->dev
)->gen
>= 4) {
1047 ret
= intel_ring_begin(ring
, 4);
1051 intel_ring_emit(ring
, GFX_OP_DRAWRECT_INFO_I965
);
1052 intel_ring_emit(ring
, (box
->x1
& 0xffff) | box
->y1
<< 16);
1053 intel_ring_emit(ring
, ((box
->x2
- 1) & 0xffff) | (box
->y2
- 1) << 16);
1054 intel_ring_emit(ring
, DR4
);
1056 ret
= intel_ring_begin(ring
, 6);
1060 intel_ring_emit(ring
, GFX_OP_DRAWRECT_INFO
);
1061 intel_ring_emit(ring
, DR1
);
1062 intel_ring_emit(ring
, (box
->x1
& 0xffff) | box
->y1
<< 16);
1063 intel_ring_emit(ring
, ((box
->x2
- 1) & 0xffff) | (box
->y2
- 1) << 16);
1064 intel_ring_emit(ring
, DR4
);
1065 intel_ring_emit(ring
, 0);
1067 intel_ring_advance(ring
);
1072 static struct drm_i915_gem_object
*
1073 i915_gem_execbuffer_parse(struct intel_engine_cs
*ring
,
1074 struct drm_i915_gem_exec_object2
*shadow_exec_entry
,
1076 struct drm_i915_gem_object
*batch_obj
,
1077 u32 batch_start_offset
,
1082 struct drm_i915_private
*dev_priv
= to_i915(batch_obj
->base
.dev
);
1083 struct drm_i915_gem_object
*shadow_batch_obj
;
1084 bool need_reloc
= false;
1087 shadow_batch_obj
= i915_gem_batch_pool_get(&dev_priv
->mm
.batch_pool
,
1088 batch_obj
->base
.size
);
1089 if (IS_ERR(shadow_batch_obj
))
1090 return shadow_batch_obj
;
1092 ret
= i915_parse_cmds(ring
,
1102 struct i915_vma
*vma
;
1104 memset(shadow_exec_entry
, 0, sizeof(*shadow_exec_entry
));
1106 vma
= i915_gem_obj_to_ggtt(shadow_batch_obj
);
1107 vma
->exec_entry
= shadow_exec_entry
;
1108 vma
->exec_entry
->flags
= __EXEC_OBJECT_PURGEABLE
;
1109 drm_gem_object_reference(&shadow_batch_obj
->base
);
1110 i915_gem_execbuffer_reserve_vma(vma
, ring
, &need_reloc
);
1111 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
1113 shadow_batch_obj
->base
.pending_read_domains
=
1114 batch_obj
->base
.pending_read_domains
;
1117 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1118 * bit from MI_BATCH_BUFFER_START commands issued in the
1119 * dispatch_execbuffer implementations. We specifically
1120 * don't want that set when the command parser is
1123 * FIXME: with aliasing ppgtt, buffers that should only
1124 * be in ggtt still end up in the aliasing ppgtt. remove
1125 * this check when that is fixed.
1127 if (USES_FULL_PPGTT(dev
))
1128 *flags
|= I915_DISPATCH_SECURE
;
1131 return ret
? ERR_PTR(ret
) : shadow_batch_obj
;
1135 i915_gem_ringbuffer_submission(struct drm_device
*dev
, struct drm_file
*file
,
1136 struct intel_engine_cs
*ring
,
1137 struct intel_context
*ctx
,
1138 struct drm_i915_gem_execbuffer2
*args
,
1139 struct list_head
*vmas
,
1140 struct drm_i915_gem_object
*batch_obj
,
1141 u64 exec_start
, u32 flags
)
1143 struct drm_clip_rect
*cliprects
= NULL
;
1144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1150 if (args
->num_cliprects
!= 0) {
1151 if (ring
!= &dev_priv
->ring
[RCS
]) {
1152 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1156 if (INTEL_INFO(dev
)->gen
>= 5) {
1157 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1161 if (args
->num_cliprects
> UINT_MAX
/ sizeof(*cliprects
)) {
1162 DRM_DEBUG("execbuf with %u cliprects\n",
1163 args
->num_cliprects
);
1167 cliprects
= kcalloc(args
->num_cliprects
,
1170 if (cliprects
== NULL
) {
1175 if (copy_from_user(cliprects
,
1176 to_user_ptr(args
->cliprects_ptr
),
1177 sizeof(*cliprects
)*args
->num_cliprects
)) {
1182 if (args
->DR4
== 0xffffffff) {
1183 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1187 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
1188 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1193 ret
= i915_gem_execbuffer_move_to_gpu(ring
, vmas
);
1197 ret
= i915_switch_context(ring
, ctx
);
1201 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1202 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1203 switch (instp_mode
) {
1204 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1205 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1206 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1207 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
1208 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1213 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1214 if (INTEL_INFO(dev
)->gen
< 4) {
1215 DRM_DEBUG("no rel constants on pre-gen4\n");
1220 if (INTEL_INFO(dev
)->gen
> 5 &&
1221 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1222 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1227 /* The HW changed the meaning on this bit on gen6 */
1228 if (INTEL_INFO(dev
)->gen
>= 6)
1229 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1233 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1238 if (ring
== &dev_priv
->ring
[RCS
] &&
1239 instp_mode
!= dev_priv
->relative_constants_mode
) {
1240 ret
= intel_ring_begin(ring
, 4);
1244 intel_ring_emit(ring
, MI_NOOP
);
1245 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1246 intel_ring_emit(ring
, INSTPM
);
1247 intel_ring_emit(ring
, instp_mask
<< 16 | instp_mode
);
1248 intel_ring_advance(ring
);
1250 dev_priv
->relative_constants_mode
= instp_mode
;
1253 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1254 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1259 exec_len
= args
->batch_len
;
1261 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1262 ret
= i915_emit_box(ring
, &cliprects
[i
],
1263 args
->DR1
, args
->DR4
);
1267 ret
= ring
->dispatch_execbuffer(ring
,
1268 exec_start
, exec_len
,
1274 ret
= ring
->dispatch_execbuffer(ring
,
1275 exec_start
, exec_len
,
1281 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring
), flags
);
1283 i915_gem_execbuffer_move_to_active(vmas
, ring
);
1284 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
1292 * Find one BSD ring to dispatch the corresponding BSD command.
1293 * The Ring ID is returned.
1295 static int gen8_dispatch_bsd_ring(struct drm_device
*dev
,
1296 struct drm_file
*file
)
1298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1299 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1301 /* Check whether the file_priv is using one ring */
1302 if (file_priv
->bsd_ring
)
1303 return file_priv
->bsd_ring
->id
;
1305 /* If no, use the ping-pong mechanism to select one ring */
1308 mutex_lock(&dev
->struct_mutex
);
1309 if (dev_priv
->mm
.bsd_ring_dispatch_index
== 0) {
1311 dev_priv
->mm
.bsd_ring_dispatch_index
= 1;
1314 dev_priv
->mm
.bsd_ring_dispatch_index
= 0;
1316 file_priv
->bsd_ring
= &dev_priv
->ring
[ring_id
];
1317 mutex_unlock(&dev
->struct_mutex
);
1322 static struct drm_i915_gem_object
*
1323 eb_get_batch(struct eb_vmas
*eb
)
1325 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
1328 * SNA is doing fancy tricks with compressing batch buffers, which leads
1329 * to negative relocation deltas. Usually that works out ok since the
1330 * relocate address is still positive, except when the batch is placed
1331 * very low in the GTT. Ensure this doesn't happen.
1333 * Note that actual hangs have only been observed on gen7, but for
1334 * paranoia do it everywhere.
1336 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
1342 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1343 struct drm_file
*file
,
1344 struct drm_i915_gem_execbuffer2
*args
,
1345 struct drm_i915_gem_exec_object2
*exec
)
1347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1349 struct drm_i915_gem_object
*batch_obj
;
1350 struct drm_i915_gem_exec_object2 shadow_exec_entry
;
1351 struct intel_engine_cs
*ring
;
1352 struct intel_context
*ctx
;
1353 struct i915_address_space
*vm
;
1354 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1355 u64 exec_start
= args
->batch_start_offset
;
1360 if (!i915_gem_check_execbuffer(args
))
1363 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1368 if (args
->flags
& I915_EXEC_SECURE
) {
1369 if (!file
->is_master
|| !capable(CAP_SYS_ADMIN
))
1372 flags
|= I915_DISPATCH_SECURE
;
1374 if (args
->flags
& I915_EXEC_IS_PINNED
)
1375 flags
|= I915_DISPATCH_PINNED
;
1377 if ((args
->flags
& I915_EXEC_RING_MASK
) > LAST_USER_RING
) {
1378 DRM_DEBUG("execbuf with unknown ring: %d\n",
1379 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1383 if (((args
->flags
& I915_EXEC_RING_MASK
) != I915_EXEC_BSD
) &&
1384 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
1385 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1386 "bsd dispatch flags: %d\n", (int)(args
->flags
));
1390 if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_DEFAULT
)
1391 ring
= &dev_priv
->ring
[RCS
];
1392 else if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_BSD
) {
1393 if (HAS_BSD2(dev
)) {
1396 switch (args
->flags
& I915_EXEC_BSD_MASK
) {
1397 case I915_EXEC_BSD_DEFAULT
:
1398 ring_id
= gen8_dispatch_bsd_ring(dev
, file
);
1399 ring
= &dev_priv
->ring
[ring_id
];
1401 case I915_EXEC_BSD_RING1
:
1402 ring
= &dev_priv
->ring
[VCS
];
1404 case I915_EXEC_BSD_RING2
:
1405 ring
= &dev_priv
->ring
[VCS2
];
1408 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1409 (int)(args
->flags
& I915_EXEC_BSD_MASK
));
1413 ring
= &dev_priv
->ring
[VCS
];
1415 ring
= &dev_priv
->ring
[(args
->flags
& I915_EXEC_RING_MASK
) - 1];
1417 if (!intel_ring_initialized(ring
)) {
1418 DRM_DEBUG("execbuf with invalid ring: %d\n",
1419 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1423 if (args
->buffer_count
< 1) {
1424 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1428 intel_runtime_pm_get(dev_priv
);
1430 ret
= i915_mutex_lock_interruptible(dev
);
1434 ctx
= i915_gem_validate_context(dev
, file
, ring
, ctx_id
);
1436 mutex_unlock(&dev
->struct_mutex
);
1441 i915_gem_context_reference(ctx
);
1444 vm
= &ctx
->ppgtt
->base
;
1446 vm
= &dev_priv
->gtt
.base
;
1448 eb
= eb_create(args
);
1450 i915_gem_context_unreference(ctx
);
1451 mutex_unlock(&dev
->struct_mutex
);
1456 /* Look up object handles */
1457 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1461 /* take note of the batch buffer before we might reorder the lists */
1462 batch_obj
= eb_get_batch(eb
);
1464 /* Move the objects en-masse into the GTT, evicting if necessary. */
1465 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1466 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, &need_relocs
);
1470 /* The objects are in their final locations, apply the relocations. */
1472 ret
= i915_gem_execbuffer_relocate(eb
);
1474 if (ret
== -EFAULT
) {
1475 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
, ring
,
1477 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1483 /* Set the pending read domains for the batch buffer to COMMAND */
1484 if (batch_obj
->base
.pending_write_domain
) {
1485 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1490 if (i915_needs_cmd_parser(ring
) && args
->batch_len
) {
1491 batch_obj
= i915_gem_execbuffer_parse(ring
,
1495 args
->batch_start_offset
,
1499 if (IS_ERR(batch_obj
)) {
1500 ret
= PTR_ERR(batch_obj
);
1505 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1507 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1508 * batch" bit. Hence we need to pin secure batches into the global gtt.
1509 * hsw should have this fixed, but bdw mucks it up again. */
1510 if (flags
& I915_DISPATCH_SECURE
) {
1512 * So on first glance it looks freaky that we pin the batch here
1513 * outside of the reservation loop. But:
1514 * - The batch is already pinned into the relevant ppgtt, so we
1515 * already have the backing storage fully allocated.
1516 * - No other BO uses the global gtt (well contexts, but meh),
1517 * so we don't really have issues with mutliple objects not
1518 * fitting due to fragmentation.
1519 * So this is actually safe.
1521 ret
= i915_gem_obj_ggtt_pin(batch_obj
, 0, 0);
1525 exec_start
+= i915_gem_obj_ggtt_offset(batch_obj
);
1527 exec_start
+= i915_gem_obj_offset(batch_obj
, vm
);
1529 ret
= dev_priv
->gt
.do_execbuf(dev
, file
, ring
, ctx
, args
,
1530 &eb
->vmas
, batch_obj
, exec_start
, flags
);
1533 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1534 * batch vma for correctness. For less ugly and less fragility this
1535 * needs to be adjusted to also track the ggtt batch vma properly as
1538 if (flags
& I915_DISPATCH_SECURE
)
1539 i915_gem_object_ggtt_unpin(batch_obj
);
1541 /* the request owns the ref now */
1542 i915_gem_context_unreference(ctx
);
1545 mutex_unlock(&dev
->struct_mutex
);
1548 /* intel_gpu_busy should also get a ref, so it will free when the device
1549 * is really idle. */
1550 intel_runtime_pm_put(dev_priv
);
1555 * Legacy execbuffer just creates an exec2 list from the original exec object
1556 * list array and passes it to the real function.
1559 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1560 struct drm_file
*file
)
1562 struct drm_i915_gem_execbuffer
*args
= data
;
1563 struct drm_i915_gem_execbuffer2 exec2
;
1564 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1565 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1568 if (args
->buffer_count
< 1) {
1569 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1573 /* Copy in the exec list from userland */
1574 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1575 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1576 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1577 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1578 args
->buffer_count
);
1579 drm_free_large(exec_list
);
1580 drm_free_large(exec2_list
);
1583 ret
= copy_from_user(exec_list
,
1584 to_user_ptr(args
->buffers_ptr
),
1585 sizeof(*exec_list
) * args
->buffer_count
);
1587 DRM_DEBUG("copy %d exec entries failed %d\n",
1588 args
->buffer_count
, ret
);
1589 drm_free_large(exec_list
);
1590 drm_free_large(exec2_list
);
1594 for (i
= 0; i
< args
->buffer_count
; i
++) {
1595 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1596 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1597 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1598 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1599 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1600 if (INTEL_INFO(dev
)->gen
< 4)
1601 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1603 exec2_list
[i
].flags
= 0;
1606 exec2
.buffers_ptr
= args
->buffers_ptr
;
1607 exec2
.buffer_count
= args
->buffer_count
;
1608 exec2
.batch_start_offset
= args
->batch_start_offset
;
1609 exec2
.batch_len
= args
->batch_len
;
1610 exec2
.DR1
= args
->DR1
;
1611 exec2
.DR4
= args
->DR4
;
1612 exec2
.num_cliprects
= args
->num_cliprects
;
1613 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1614 exec2
.flags
= I915_EXEC_RENDER
;
1615 i915_execbuffer2_set_context_id(exec2
, 0);
1617 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1619 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1620 to_user_ptr(args
->buffers_ptr
);
1622 /* Copy the new buffer offsets back to the user's exec list. */
1623 for (i
= 0; i
< args
->buffer_count
; i
++) {
1624 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1625 &exec2_list
[i
].offset
,
1626 sizeof(user_exec_list
[i
].offset
));
1629 DRM_DEBUG("failed to copy %d exec entries "
1630 "back to user (%d)\n",
1631 args
->buffer_count
, ret
);
1637 drm_free_large(exec_list
);
1638 drm_free_large(exec2_list
);
1643 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1644 struct drm_file
*file
)
1646 struct drm_i915_gem_execbuffer2
*args
= data
;
1647 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1650 if (args
->buffer_count
< 1 ||
1651 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1652 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1656 if (args
->rsvd2
!= 0) {
1657 DRM_DEBUG("dirty rvsd2 field\n");
1661 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1662 GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
1663 if (exec2_list
== NULL
)
1664 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1665 args
->buffer_count
);
1666 if (exec2_list
== NULL
) {
1667 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1668 args
->buffer_count
);
1671 ret
= copy_from_user(exec2_list
,
1672 to_user_ptr(args
->buffers_ptr
),
1673 sizeof(*exec2_list
) * args
->buffer_count
);
1675 DRM_DEBUG("copy %d exec entries failed %d\n",
1676 args
->buffer_count
, ret
);
1677 drm_free_large(exec2_list
);
1681 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1683 /* Copy the new buffer offsets back to the user's exec list. */
1684 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1685 to_user_ptr(args
->buffers_ptr
);
1688 for (i
= 0; i
< args
->buffer_count
; i
++) {
1689 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1690 &exec2_list
[i
].offset
,
1691 sizeof(user_exec_list
[i
].offset
));
1694 DRM_DEBUG("failed to copy %d exec entries "
1696 args
->buffer_count
);
1702 drm_free_large(exec2_list
);