2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
39 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
41 #define BATCH_OFFSET_BIAS (256*1024)
44 struct list_head vmas
;
47 struct i915_vma
*lut
[0];
48 struct hlist_head buckets
[0];
52 static struct eb_vmas
*
53 eb_create(struct drm_i915_gem_execbuffer2
*args
)
55 struct eb_vmas
*eb
= NULL
;
57 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
58 unsigned size
= args
->buffer_count
;
59 size
*= sizeof(struct i915_vma
*);
60 size
+= sizeof(struct eb_vmas
);
61 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
65 unsigned size
= args
->buffer_count
;
66 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
67 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
68 while (count
> 2*size
)
70 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
71 sizeof(struct eb_vmas
),
78 eb
->and = -args
->buffer_count
;
80 INIT_LIST_HEAD(&eb
->vmas
);
85 eb_reset(struct eb_vmas
*eb
)
88 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
92 eb_lookup_vmas(struct eb_vmas
*eb
,
93 struct drm_i915_gem_exec_object2
*exec
,
94 const struct drm_i915_gem_execbuffer2
*args
,
95 struct i915_address_space
*vm
,
96 struct drm_file
*file
)
98 struct drm_i915_gem_object
*obj
;
99 struct list_head objects
;
102 INIT_LIST_HEAD(&objects
);
103 spin_lock(&file
->table_lock
);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i
= 0; i
< args
->buffer_count
; i
++) {
107 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
109 spin_unlock(&file
->table_lock
);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
116 if (!list_empty(&obj
->obj_exec_link
)) {
117 spin_unlock(&file
->table_lock
);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj
, exec
[i
].handle
, i
);
124 drm_gem_object_reference(&obj
->base
);
125 list_add_tail(&obj
->obj_exec_link
, &objects
);
127 spin_unlock(&file
->table_lock
);
130 while (!list_empty(&objects
)) {
131 struct i915_vma
*vma
;
133 obj
= list_first_entry(&objects
,
134 struct drm_i915_gem_object
,
138 * NOTE: We can leak any vmas created here when something fails
139 * later on. But that's no issue since vma_unbind can deal with
140 * vmas which are not actually bound. And since only
141 * lookup_or_create exists as an interface to get at the vma
142 * from the (obj, vm) we don't run the risk of creating
143 * duplicated vmas for the same vm.
145 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
147 DRM_DEBUG("Failed to lookup VMA\n");
152 /* Transfer ownership from the objects list to the vmas list. */
153 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
154 list_del_init(&obj
->obj_exec_link
);
156 vma
->exec_entry
= &exec
[i
];
160 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
161 vma
->exec_handle
= handle
;
162 hlist_add_head(&vma
->exec_node
,
163 &eb
->buckets
[handle
& eb
->and]);
172 while (!list_empty(&objects
)) {
173 obj
= list_first_entry(&objects
,
174 struct drm_i915_gem_object
,
176 list_del_init(&obj
->obj_exec_link
);
177 drm_gem_object_unreference(&obj
->base
);
180 * Objects already transfered to the vmas list will be unreferenced by
187 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
190 if (handle
>= -eb
->and)
192 return eb
->lut
[handle
];
194 struct hlist_head
*head
;
195 struct hlist_node
*node
;
197 head
= &eb
->buckets
[handle
& eb
->and];
198 hlist_for_each(node
, head
) {
199 struct i915_vma
*vma
;
201 vma
= hlist_entry(node
, struct i915_vma
, exec_node
);
202 if (vma
->exec_handle
== handle
)
210 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
212 struct drm_i915_gem_exec_object2
*entry
;
213 struct drm_i915_gem_object
*obj
= vma
->obj
;
215 if (!drm_mm_node_allocated(&vma
->node
))
218 entry
= vma
->exec_entry
;
220 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
221 i915_gem_object_unpin_fence(obj
);
223 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
226 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
229 static void eb_destroy(struct eb_vmas
*eb
)
231 while (!list_empty(&eb
->vmas
)) {
232 struct i915_vma
*vma
;
234 vma
= list_first_entry(&eb
->vmas
,
237 list_del_init(&vma
->exec_list
);
238 i915_gem_execbuffer_unreserve_vma(vma
);
239 drm_gem_object_unreference(&vma
->obj
->base
);
244 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
246 return (HAS_LLC(obj
->base
.dev
) ||
247 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
248 obj
->cache_level
!= I915_CACHE_NONE
);
252 relocate_entry_cpu(struct drm_i915_gem_object
*obj
,
253 struct drm_i915_gem_relocation_entry
*reloc
,
254 uint64_t target_offset
)
256 struct drm_device
*dev
= obj
->base
.dev
;
257 uint32_t page_offset
= offset_in_page(reloc
->offset
);
258 uint64_t delta
= reloc
->delta
+ target_offset
;
262 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
266 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
267 reloc
->offset
>> PAGE_SHIFT
));
268 *(uint32_t *)(vaddr
+ page_offset
) = lower_32_bits(delta
);
270 if (INTEL_INFO(dev
)->gen
>= 8) {
271 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
273 if (page_offset
== 0) {
274 kunmap_atomic(vaddr
);
275 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
276 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
279 *(uint32_t *)(vaddr
+ page_offset
) = upper_32_bits(delta
);
282 kunmap_atomic(vaddr
);
288 relocate_entry_gtt(struct drm_i915_gem_object
*obj
,
289 struct drm_i915_gem_relocation_entry
*reloc
,
290 uint64_t target_offset
)
292 struct drm_device
*dev
= obj
->base
.dev
;
293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
294 uint64_t delta
= reloc
->delta
+ target_offset
;
296 void __iomem
*reloc_page
;
299 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
303 ret
= i915_gem_object_put_fence(obj
);
307 /* Map the page containing the relocation we're going to perform. */
308 offset
= i915_gem_obj_ggtt_offset(obj
);
309 offset
+= reloc
->offset
;
310 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
312 iowrite32(lower_32_bits(delta
), reloc_page
+ offset_in_page(offset
));
314 if (INTEL_INFO(dev
)->gen
>= 8) {
315 offset
+= sizeof(uint32_t);
317 if (offset_in_page(offset
) == 0) {
318 io_mapping_unmap_atomic(reloc_page
);
320 io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
324 iowrite32(upper_32_bits(delta
),
325 reloc_page
+ offset_in_page(offset
));
328 io_mapping_unmap_atomic(reloc_page
);
334 clflush_write32(void *addr
, uint32_t value
)
336 /* This is not a fast path, so KISS. */
337 drm_clflush_virt_range(addr
, sizeof(uint32_t));
338 *(uint32_t *)addr
= value
;
339 drm_clflush_virt_range(addr
, sizeof(uint32_t));
343 relocate_entry_clflush(struct drm_i915_gem_object
*obj
,
344 struct drm_i915_gem_relocation_entry
*reloc
,
345 uint64_t target_offset
)
347 struct drm_device
*dev
= obj
->base
.dev
;
348 uint32_t page_offset
= offset_in_page(reloc
->offset
);
349 uint64_t delta
= (int)reloc
->delta
+ target_offset
;
353 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
357 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
358 reloc
->offset
>> PAGE_SHIFT
));
359 clflush_write32(vaddr
+ page_offset
, lower_32_bits(delta
));
361 if (INTEL_INFO(dev
)->gen
>= 8) {
362 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
364 if (page_offset
== 0) {
365 kunmap_atomic(vaddr
);
366 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
367 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
370 clflush_write32(vaddr
+ page_offset
, upper_32_bits(delta
));
373 kunmap_atomic(vaddr
);
379 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
381 struct drm_i915_gem_relocation_entry
*reloc
)
383 struct drm_device
*dev
= obj
->base
.dev
;
384 struct drm_gem_object
*target_obj
;
385 struct drm_i915_gem_object
*target_i915_obj
;
386 struct i915_vma
*target_vma
;
387 uint64_t target_offset
;
390 /* we've already hold a reference to all valid objects */
391 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
392 if (unlikely(target_vma
== NULL
))
394 target_i915_obj
= target_vma
->obj
;
395 target_obj
= &target_vma
->obj
->base
;
397 target_offset
= target_vma
->node
.start
;
399 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
400 * pipe_control writes because the gpu doesn't properly redirect them
401 * through the ppgtt for non_secure batchbuffers. */
402 if (unlikely(IS_GEN6(dev
) &&
403 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
)) {
404 ret
= i915_vma_bind(target_vma
, target_i915_obj
->cache_level
,
406 if (WARN_ONCE(ret
, "Unexpected failure to bind target VMA!"))
410 /* Validate that the target is in a valid r/w GPU domain */
411 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
412 DRM_DEBUG("reloc with multiple write domains: "
413 "obj %p target %d offset %d "
414 "read %08x write %08x",
415 obj
, reloc
->target_handle
,
418 reloc
->write_domain
);
421 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
422 & ~I915_GEM_GPU_DOMAINS
)) {
423 DRM_DEBUG("reloc with read/write non-GPU domains: "
424 "obj %p target %d offset %d "
425 "read %08x write %08x",
426 obj
, reloc
->target_handle
,
429 reloc
->write_domain
);
433 target_obj
->pending_read_domains
|= reloc
->read_domains
;
434 target_obj
->pending_write_domain
|= reloc
->write_domain
;
436 /* If the relocation already has the right value in it, no
437 * more work needs to be done.
439 if (target_offset
== reloc
->presumed_offset
)
442 /* Check that the relocation address is valid... */
443 if (unlikely(reloc
->offset
>
444 obj
->base
.size
- (INTEL_INFO(dev
)->gen
>= 8 ? 8 : 4))) {
445 DRM_DEBUG("Relocation beyond object bounds: "
446 "obj %p target %d offset %d size %d.\n",
447 obj
, reloc
->target_handle
,
449 (int) obj
->base
.size
);
452 if (unlikely(reloc
->offset
& 3)) {
453 DRM_DEBUG("Relocation not 4-byte aligned: "
454 "obj %p target %d offset %d.\n",
455 obj
, reloc
->target_handle
,
456 (int) reloc
->offset
);
460 /* We can't wait for rendering with pagefaults disabled */
461 if (obj
->active
&& in_atomic())
464 if (use_cpu_reloc(obj
))
465 ret
= relocate_entry_cpu(obj
, reloc
, target_offset
);
466 else if (obj
->map_and_fenceable
)
467 ret
= relocate_entry_gtt(obj
, reloc
, target_offset
);
468 else if (cpu_has_clflush
)
469 ret
= relocate_entry_clflush(obj
, reloc
, target_offset
);
471 WARN_ONCE(1, "Impossible case in relocation handling\n");
478 /* and update the user's relocation entry */
479 reloc
->presumed_offset
= target_offset
;
485 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
488 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
489 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
490 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
491 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
494 user_relocs
= to_user_ptr(entry
->relocs_ptr
);
496 remain
= entry
->relocation_count
;
498 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
500 if (count
> ARRAY_SIZE(stack_reloc
))
501 count
= ARRAY_SIZE(stack_reloc
);
504 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
508 u64 offset
= r
->presumed_offset
;
510 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
);
514 if (r
->presumed_offset
!= offset
&&
515 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
517 sizeof(r
->presumed_offset
))) {
531 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
533 struct drm_i915_gem_relocation_entry
*relocs
)
535 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
538 for (i
= 0; i
< entry
->relocation_count
; i
++) {
539 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
]);
548 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
550 struct i915_vma
*vma
;
553 /* This is the fast path and we cannot handle a pagefault whilst
554 * holding the struct mutex lest the user pass in the relocations
555 * contained within a mmaped bo. For in such a case we, the page
556 * fault handler would call i915_gem_fault() and we would try to
557 * acquire the struct mutex again. Obviously this is bad and so
558 * lockdep complains vehemently.
561 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
562 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
571 static bool only_mappable_for_reloc(unsigned int flags
)
573 return (flags
& (EXEC_OBJECT_NEEDS_FENCE
| __EXEC_OBJECT_NEEDS_MAP
)) ==
574 __EXEC_OBJECT_NEEDS_MAP
;
578 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
579 struct intel_engine_cs
*ring
,
582 struct drm_i915_gem_object
*obj
= vma
->obj
;
583 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
588 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
591 if (!drm_mm_node_allocated(&vma
->node
)) {
592 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
593 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
594 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
595 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
598 ret
= i915_gem_object_pin(obj
, vma
->vm
, entry
->alignment
, flags
);
599 if ((ret
== -ENOSPC
|| ret
== -E2BIG
) &&
600 only_mappable_for_reloc(entry
->flags
))
601 ret
= i915_gem_object_pin(obj
, vma
->vm
,
603 flags
& ~PIN_MAPPABLE
);
607 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
609 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
610 ret
= i915_gem_object_get_fence(obj
);
614 if (i915_gem_object_pin_fence(obj
))
615 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
618 if (entry
->offset
!= vma
->node
.start
) {
619 entry
->offset
= vma
->node
.start
;
623 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
624 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
625 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
632 need_reloc_mappable(struct i915_vma
*vma
)
634 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
636 if (entry
->relocation_count
== 0)
639 if (!i915_is_ggtt(vma
->vm
))
642 /* See also use_cpu_reloc() */
643 if (HAS_LLC(vma
->obj
->base
.dev
))
646 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
653 eb_vma_misplaced(struct i915_vma
*vma
)
655 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
656 struct drm_i915_gem_object
*obj
= vma
->obj
;
658 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
659 !i915_is_ggtt(vma
->vm
));
661 if (entry
->alignment
&&
662 vma
->node
.start
& (entry
->alignment
- 1))
665 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
666 vma
->node
.start
< BATCH_OFFSET_BIAS
)
669 /* avoid costly ping-pong once a batch bo ended up non-mappable */
670 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !obj
->map_and_fenceable
)
671 return !only_mappable_for_reloc(entry
->flags
);
677 i915_gem_execbuffer_reserve(struct intel_engine_cs
*ring
,
678 struct list_head
*vmas
,
679 struct intel_context
*ctx
,
682 struct drm_i915_gem_object
*obj
;
683 struct i915_vma
*vma
;
684 struct i915_address_space
*vm
;
685 struct list_head ordered_vmas
;
686 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
689 i915_gem_retire_requests_ring(ring
);
691 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
693 INIT_LIST_HEAD(&ordered_vmas
);
694 while (!list_empty(vmas
)) {
695 struct drm_i915_gem_exec_object2
*entry
;
696 bool need_fence
, need_mappable
;
698 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
700 entry
= vma
->exec_entry
;
702 if (ctx
->flags
& CONTEXT_NO_ZEROMAP
)
703 entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
705 if (!has_fenced_gpu_access
)
706 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
708 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
709 obj
->tiling_mode
!= I915_TILING_NONE
;
710 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
713 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
714 list_move(&vma
->exec_list
, &ordered_vmas
);
716 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
718 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
719 obj
->base
.pending_write_domain
= 0;
721 list_splice(&ordered_vmas
, vmas
);
723 /* Attempt to pin all of the buffers into the GTT.
724 * This is done in 3 phases:
726 * 1a. Unbind all objects that do not match the GTT constraints for
727 * the execbuffer (fenceable, mappable, alignment etc).
728 * 1b. Increment pin count for already bound objects.
729 * 2. Bind new objects.
730 * 3. Decrement pin count.
732 * This avoid unnecessary unbinding of later objects in order to make
733 * room for the earlier objects *unless* we need to defragment.
739 /* Unbind any ill-fitting objects or pin. */
740 list_for_each_entry(vma
, vmas
, exec_list
) {
741 if (!drm_mm_node_allocated(&vma
->node
))
744 if (eb_vma_misplaced(vma
))
745 ret
= i915_vma_unbind(vma
);
747 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
752 /* Bind fresh objects */
753 list_for_each_entry(vma
, vmas
, exec_list
) {
754 if (drm_mm_node_allocated(&vma
->node
))
757 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
763 if (ret
!= -ENOSPC
|| retry
++)
766 /* Decrement pin count for bound objects */
767 list_for_each_entry(vma
, vmas
, exec_list
)
768 i915_gem_execbuffer_unreserve_vma(vma
);
770 ret
= i915_gem_evict_vm(vm
, true);
777 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
778 struct drm_i915_gem_execbuffer2
*args
,
779 struct drm_file
*file
,
780 struct intel_engine_cs
*ring
,
782 struct drm_i915_gem_exec_object2
*exec
,
783 struct intel_context
*ctx
)
785 struct drm_i915_gem_relocation_entry
*reloc
;
786 struct i915_address_space
*vm
;
787 struct i915_vma
*vma
;
791 unsigned count
= args
->buffer_count
;
793 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
795 /* We may process another execbuffer during the unlock... */
796 while (!list_empty(&eb
->vmas
)) {
797 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
798 list_del_init(&vma
->exec_list
);
799 i915_gem_execbuffer_unreserve_vma(vma
);
800 drm_gem_object_unreference(&vma
->obj
->base
);
803 mutex_unlock(&dev
->struct_mutex
);
806 for (i
= 0; i
< count
; i
++)
807 total
+= exec
[i
].relocation_count
;
809 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
810 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
811 if (reloc
== NULL
|| reloc_offset
== NULL
) {
812 drm_free_large(reloc
);
813 drm_free_large(reloc_offset
);
814 mutex_lock(&dev
->struct_mutex
);
819 for (i
= 0; i
< count
; i
++) {
820 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
821 u64 invalid_offset
= (u64
)-1;
824 user_relocs
= to_user_ptr(exec
[i
].relocs_ptr
);
826 if (copy_from_user(reloc
+total
, user_relocs
,
827 exec
[i
].relocation_count
* sizeof(*reloc
))) {
829 mutex_lock(&dev
->struct_mutex
);
833 /* As we do not update the known relocation offsets after
834 * relocating (due to the complexities in lock handling),
835 * we need to mark them as invalid now so that we force the
836 * relocation processing next time. Just in case the target
837 * object is evicted and then rebound into its old
838 * presumed_offset before the next execbuffer - if that
839 * happened we would make the mistake of assuming that the
840 * relocations were valid.
842 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
843 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
845 sizeof(invalid_offset
))) {
847 mutex_lock(&dev
->struct_mutex
);
852 reloc_offset
[i
] = total
;
853 total
+= exec
[i
].relocation_count
;
856 ret
= i915_mutex_lock_interruptible(dev
);
858 mutex_lock(&dev
->struct_mutex
);
862 /* reacquire the objects */
864 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
868 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
869 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, ctx
, &need_relocs
);
873 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
874 int offset
= vma
->exec_entry
- exec
;
875 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
876 reloc
+ reloc_offset
[offset
]);
881 /* Leave the user relocations as are, this is the painfully slow path,
882 * and we want to avoid the complication of dropping the lock whilst
883 * having buffers reserved in the aperture and so causing spurious
884 * ENOSPC for random operations.
888 drm_free_large(reloc
);
889 drm_free_large(reloc_offset
);
894 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req
,
895 struct list_head
*vmas
)
897 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
898 struct i915_vma
*vma
;
899 uint32_t flush_domains
= 0;
900 bool flush_chipset
= false;
903 list_for_each_entry(vma
, vmas
, exec_list
) {
904 struct drm_i915_gem_object
*obj
= vma
->obj
;
906 if (obj
->active
& other_rings
) {
907 ret
= i915_gem_object_sync(obj
, req
->ring
);
912 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
913 flush_chipset
|= i915_gem_clflush_object(obj
, false);
915 flush_domains
|= obj
->base
.write_domain
;
919 i915_gem_chipset_flush(req
->ring
->dev
);
921 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
924 /* Unconditionally invalidate gpu caches and ensure that we do flush
925 * any residual writes from the previous batch.
927 return intel_ring_invalidate_all_caches(req
->ring
);
931 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
933 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
936 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
940 validate_exec_list(struct drm_device
*dev
,
941 struct drm_i915_gem_exec_object2
*exec
,
944 unsigned relocs_total
= 0;
945 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
946 unsigned invalid_flags
;
949 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
950 if (USES_FULL_PPGTT(dev
))
951 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
953 for (i
= 0; i
< count
; i
++) {
954 char __user
*ptr
= to_user_ptr(exec
[i
].relocs_ptr
);
955 int length
; /* limited by fault_in_pages_readable() */
957 if (exec
[i
].flags
& invalid_flags
)
960 if (exec
[i
].alignment
&& !is_power_of_2(exec
[i
].alignment
))
963 /* First check for malicious input causing overflow in
964 * the worst case where we need to allocate the entire
965 * relocation tree as a single array.
967 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
969 relocs_total
+= exec
[i
].relocation_count
;
971 length
= exec
[i
].relocation_count
*
972 sizeof(struct drm_i915_gem_relocation_entry
);
974 * We must check that the entire relocation array is safe
975 * to read, but since we may need to update the presumed
976 * offsets during execution, check for full write access.
978 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
981 if (likely(!i915
.prefault_disable
)) {
982 if (fault_in_multipages_readable(ptr
, length
))
990 static struct intel_context
*
991 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
992 struct intel_engine_cs
*ring
, const u32 ctx_id
)
994 struct intel_context
*ctx
= NULL
;
995 struct i915_ctx_hang_stats
*hs
;
997 if (ring
->id
!= RCS
&& ctx_id
!= DEFAULT_CONTEXT_HANDLE
)
998 return ERR_PTR(-EINVAL
);
1000 ctx
= i915_gem_context_get(file
->driver_priv
, ctx_id
);
1004 hs
= &ctx
->hang_stats
;
1006 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
1007 return ERR_PTR(-EIO
);
1010 if (i915
.enable_execlists
&& !ctx
->engine
[ring
->id
].state
) {
1011 int ret
= intel_lr_context_deferred_create(ctx
, ring
);
1013 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id
, ret
);
1014 return ERR_PTR(ret
);
1022 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
1023 struct intel_engine_cs
*ring
)
1025 struct drm_i915_gem_request
*req
= intel_ring_get_request(ring
);
1026 struct i915_vma
*vma
;
1028 list_for_each_entry(vma
, vmas
, exec_list
) {
1029 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
1030 struct drm_i915_gem_object
*obj
= vma
->obj
;
1031 u32 old_read
= obj
->base
.read_domains
;
1032 u32 old_write
= obj
->base
.write_domain
;
1034 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
1035 if (obj
->base
.write_domain
== 0)
1036 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
1037 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
1039 i915_vma_move_to_active(vma
, ring
);
1040 if (obj
->base
.write_domain
) {
1042 i915_gem_request_assign(&obj
->last_write_req
, req
);
1044 intel_fb_obj_invalidate(obj
, ORIGIN_CS
);
1046 /* update for the implicit flush after a batch */
1047 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1049 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
1050 i915_gem_request_assign(&obj
->last_fenced_req
, req
);
1051 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
1052 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
1053 list_move_tail(&dev_priv
->fence_regs
[obj
->fence_reg
].lru_list
,
1054 &dev_priv
->mm
.fence_list
);
1058 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
1063 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
)
1065 /* Unconditionally force add_request to emit a full flush. */
1066 params
->ring
->gpu_caches_dirty
= true;
1068 /* Add a breadcrumb for the completion of the batch buffer */
1069 __i915_add_request(params
->ring
, params
->file
, params
->batch_obj
);
1073 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
1074 struct intel_engine_cs
*ring
)
1076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1079 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
]) {
1080 DRM_DEBUG("sol reset is gen7/rcs only\n");
1084 ret
= intel_ring_begin(ring
, 4 * 3);
1088 for (i
= 0; i
< 4; i
++) {
1089 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1090 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
1091 intel_ring_emit(ring
, 0);
1094 intel_ring_advance(ring
);
1100 i915_emit_box(struct intel_engine_cs
*ring
,
1101 struct drm_clip_rect
*box
,
1106 if (box
->y2
<= box
->y1
|| box
->x2
<= box
->x1
||
1107 box
->y2
<= 0 || box
->x2
<= 0) {
1108 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1109 box
->x1
, box
->y1
, box
->x2
, box
->y2
);
1113 if (INTEL_INFO(ring
->dev
)->gen
>= 4) {
1114 ret
= intel_ring_begin(ring
, 4);
1118 intel_ring_emit(ring
, GFX_OP_DRAWRECT_INFO_I965
);
1119 intel_ring_emit(ring
, (box
->x1
& 0xffff) | box
->y1
<< 16);
1120 intel_ring_emit(ring
, ((box
->x2
- 1) & 0xffff) | (box
->y2
- 1) << 16);
1121 intel_ring_emit(ring
, DR4
);
1123 ret
= intel_ring_begin(ring
, 6);
1127 intel_ring_emit(ring
, GFX_OP_DRAWRECT_INFO
);
1128 intel_ring_emit(ring
, DR1
);
1129 intel_ring_emit(ring
, (box
->x1
& 0xffff) | box
->y1
<< 16);
1130 intel_ring_emit(ring
, ((box
->x2
- 1) & 0xffff) | (box
->y2
- 1) << 16);
1131 intel_ring_emit(ring
, DR4
);
1132 intel_ring_emit(ring
, 0);
1134 intel_ring_advance(ring
);
1139 static struct drm_i915_gem_object
*
1140 i915_gem_execbuffer_parse(struct intel_engine_cs
*ring
,
1141 struct drm_i915_gem_exec_object2
*shadow_exec_entry
,
1143 struct drm_i915_gem_object
*batch_obj
,
1144 u32 batch_start_offset
,
1148 struct drm_i915_gem_object
*shadow_batch_obj
;
1149 struct i915_vma
*vma
;
1152 shadow_batch_obj
= i915_gem_batch_pool_get(&ring
->batch_pool
,
1153 PAGE_ALIGN(batch_len
));
1154 if (IS_ERR(shadow_batch_obj
))
1155 return shadow_batch_obj
;
1157 ret
= i915_parse_cmds(ring
,
1166 ret
= i915_gem_obj_ggtt_pin(shadow_batch_obj
, 0, 0);
1170 i915_gem_object_unpin_pages(shadow_batch_obj
);
1172 memset(shadow_exec_entry
, 0, sizeof(*shadow_exec_entry
));
1174 vma
= i915_gem_obj_to_ggtt(shadow_batch_obj
);
1175 vma
->exec_entry
= shadow_exec_entry
;
1176 vma
->exec_entry
->flags
= __EXEC_OBJECT_HAS_PIN
;
1177 drm_gem_object_reference(&shadow_batch_obj
->base
);
1178 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
1180 shadow_batch_obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_COMMAND
;
1182 return shadow_batch_obj
;
1185 i915_gem_object_unpin_pages(shadow_batch_obj
);
1186 if (ret
== -EACCES
) /* unhandled chained batch */
1189 return ERR_PTR(ret
);
1193 i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
1194 struct drm_i915_gem_execbuffer2
*args
,
1195 struct list_head
*vmas
)
1197 struct drm_clip_rect
*cliprects
= NULL
;
1198 struct drm_device
*dev
= params
->dev
;
1199 struct intel_engine_cs
*ring
= params
->ring
;
1200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1201 u64 exec_start
, exec_len
;
1206 if (args
->num_cliprects
!= 0) {
1207 if (ring
!= &dev_priv
->ring
[RCS
]) {
1208 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1212 if (INTEL_INFO(dev
)->gen
>= 5) {
1213 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1217 if (args
->num_cliprects
> UINT_MAX
/ sizeof(*cliprects
)) {
1218 DRM_DEBUG("execbuf with %u cliprects\n",
1219 args
->num_cliprects
);
1223 cliprects
= kcalloc(args
->num_cliprects
,
1226 if (cliprects
== NULL
) {
1231 if (copy_from_user(cliprects
,
1232 to_user_ptr(args
->cliprects_ptr
),
1233 sizeof(*cliprects
)*args
->num_cliprects
)) {
1238 if (args
->DR4
== 0xffffffff) {
1239 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1243 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
1244 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1249 ret
= i915_gem_execbuffer_move_to_gpu(params
->request
, vmas
);
1253 ret
= i915_switch_context(ring
, params
->ctx
);
1257 WARN(params
->ctx
->ppgtt
&& params
->ctx
->ppgtt
->pd_dirty_rings
& (1<<ring
->id
),
1258 "%s didn't clear reload\n", ring
->name
);
1260 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1261 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1262 switch (instp_mode
) {
1263 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1264 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1265 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1266 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
1267 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1272 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1273 if (INTEL_INFO(dev
)->gen
< 4) {
1274 DRM_DEBUG("no rel constants on pre-gen4\n");
1279 if (INTEL_INFO(dev
)->gen
> 5 &&
1280 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1281 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1286 /* The HW changed the meaning on this bit on gen6 */
1287 if (INTEL_INFO(dev
)->gen
>= 6)
1288 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1292 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1297 if (ring
== &dev_priv
->ring
[RCS
] &&
1298 instp_mode
!= dev_priv
->relative_constants_mode
) {
1299 ret
= intel_ring_begin(ring
, 4);
1303 intel_ring_emit(ring
, MI_NOOP
);
1304 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1305 intel_ring_emit(ring
, INSTPM
);
1306 intel_ring_emit(ring
, instp_mask
<< 16 | instp_mode
);
1307 intel_ring_advance(ring
);
1309 dev_priv
->relative_constants_mode
= instp_mode
;
1312 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1313 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1318 exec_len
= args
->batch_len
;
1319 exec_start
= params
->batch_obj_vm_offset
+
1320 params
->args_batch_start_offset
;
1323 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1324 ret
= i915_emit_box(ring
, &cliprects
[i
],
1325 args
->DR1
, args
->DR4
);
1329 ret
= ring
->dispatch_execbuffer(ring
,
1330 exec_start
, exec_len
,
1331 params
->dispatch_flags
);
1336 ret
= ring
->dispatch_execbuffer(ring
,
1337 exec_start
, exec_len
,
1338 params
->dispatch_flags
);
1343 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1345 i915_gem_execbuffer_move_to_active(vmas
, ring
);
1346 i915_gem_execbuffer_retire_commands(params
);
1354 * Find one BSD ring to dispatch the corresponding BSD command.
1355 * The Ring ID is returned.
1357 static int gen8_dispatch_bsd_ring(struct drm_device
*dev
,
1358 struct drm_file
*file
)
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1363 /* Check whether the file_priv is using one ring */
1364 if (file_priv
->bsd_ring
)
1365 return file_priv
->bsd_ring
->id
;
1367 /* If no, use the ping-pong mechanism to select one ring */
1370 mutex_lock(&dev
->struct_mutex
);
1371 if (dev_priv
->mm
.bsd_ring_dispatch_index
== 0) {
1373 dev_priv
->mm
.bsd_ring_dispatch_index
= 1;
1376 dev_priv
->mm
.bsd_ring_dispatch_index
= 0;
1378 file_priv
->bsd_ring
= &dev_priv
->ring
[ring_id
];
1379 mutex_unlock(&dev
->struct_mutex
);
1384 static struct drm_i915_gem_object
*
1385 eb_get_batch(struct eb_vmas
*eb
)
1387 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
1390 * SNA is doing fancy tricks with compressing batch buffers, which leads
1391 * to negative relocation deltas. Usually that works out ok since the
1392 * relocate address is still positive, except when the batch is placed
1393 * very low in the GTT. Ensure this doesn't happen.
1395 * Note that actual hangs have only been observed on gen7, but for
1396 * paranoia do it everywhere.
1398 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
1404 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1405 struct drm_file
*file
,
1406 struct drm_i915_gem_execbuffer2
*args
,
1407 struct drm_i915_gem_exec_object2
*exec
)
1409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1411 struct drm_i915_gem_object
*batch_obj
;
1412 struct drm_i915_gem_exec_object2 shadow_exec_entry
;
1413 struct intel_engine_cs
*ring
;
1414 struct intel_context
*ctx
;
1415 struct i915_address_space
*vm
;
1416 struct i915_execbuffer_params params_master
; /* XXX: will be removed later */
1417 struct i915_execbuffer_params
*params
= ¶ms_master
;
1418 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1423 if (!i915_gem_check_execbuffer(args
))
1426 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1431 if (args
->flags
& I915_EXEC_SECURE
) {
1432 if (!file
->is_master
|| !capable(CAP_SYS_ADMIN
))
1435 dispatch_flags
|= I915_DISPATCH_SECURE
;
1437 if (args
->flags
& I915_EXEC_IS_PINNED
)
1438 dispatch_flags
|= I915_DISPATCH_PINNED
;
1440 if ((args
->flags
& I915_EXEC_RING_MASK
) > LAST_USER_RING
) {
1441 DRM_DEBUG("execbuf with unknown ring: %d\n",
1442 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1446 if (((args
->flags
& I915_EXEC_RING_MASK
) != I915_EXEC_BSD
) &&
1447 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
1448 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1449 "bsd dispatch flags: %d\n", (int)(args
->flags
));
1453 if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_DEFAULT
)
1454 ring
= &dev_priv
->ring
[RCS
];
1455 else if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_BSD
) {
1456 if (HAS_BSD2(dev
)) {
1459 switch (args
->flags
& I915_EXEC_BSD_MASK
) {
1460 case I915_EXEC_BSD_DEFAULT
:
1461 ring_id
= gen8_dispatch_bsd_ring(dev
, file
);
1462 ring
= &dev_priv
->ring
[ring_id
];
1464 case I915_EXEC_BSD_RING1
:
1465 ring
= &dev_priv
->ring
[VCS
];
1467 case I915_EXEC_BSD_RING2
:
1468 ring
= &dev_priv
->ring
[VCS2
];
1471 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1472 (int)(args
->flags
& I915_EXEC_BSD_MASK
));
1476 ring
= &dev_priv
->ring
[VCS
];
1478 ring
= &dev_priv
->ring
[(args
->flags
& I915_EXEC_RING_MASK
) - 1];
1480 if (!intel_ring_initialized(ring
)) {
1481 DRM_DEBUG("execbuf with invalid ring: %d\n",
1482 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1486 if (args
->buffer_count
< 1) {
1487 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1491 intel_runtime_pm_get(dev_priv
);
1493 ret
= i915_mutex_lock_interruptible(dev
);
1497 ctx
= i915_gem_validate_context(dev
, file
, ring
, ctx_id
);
1499 mutex_unlock(&dev
->struct_mutex
);
1504 i915_gem_context_reference(ctx
);
1507 vm
= &ctx
->ppgtt
->base
;
1509 vm
= &dev_priv
->gtt
.base
;
1511 memset(¶ms_master
, 0x00, sizeof(params_master
));
1513 eb
= eb_create(args
);
1515 i915_gem_context_unreference(ctx
);
1516 mutex_unlock(&dev
->struct_mutex
);
1521 /* Look up object handles */
1522 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1526 /* take note of the batch buffer before we might reorder the lists */
1527 batch_obj
= eb_get_batch(eb
);
1529 /* Move the objects en-masse into the GTT, evicting if necessary. */
1530 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1531 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, ctx
, &need_relocs
);
1535 /* The objects are in their final locations, apply the relocations. */
1537 ret
= i915_gem_execbuffer_relocate(eb
);
1539 if (ret
== -EFAULT
) {
1540 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
, ring
,
1542 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1548 /* Set the pending read domains for the batch buffer to COMMAND */
1549 if (batch_obj
->base
.pending_write_domain
) {
1550 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1555 params
->args_batch_start_offset
= args
->batch_start_offset
;
1556 if (i915_needs_cmd_parser(ring
) && args
->batch_len
) {
1557 struct drm_i915_gem_object
*parsed_batch_obj
;
1559 parsed_batch_obj
= i915_gem_execbuffer_parse(ring
,
1563 args
->batch_start_offset
,
1566 if (IS_ERR(parsed_batch_obj
)) {
1567 ret
= PTR_ERR(parsed_batch_obj
);
1572 * parsed_batch_obj == batch_obj means batch not fully parsed:
1573 * Accept, but don't promote to secure.
1576 if (parsed_batch_obj
!= batch_obj
) {
1578 * Batch parsed and accepted:
1580 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1581 * bit from MI_BATCH_BUFFER_START commands issued in
1582 * the dispatch_execbuffer implementations. We
1583 * specifically don't want that set on batches the
1584 * command parser has accepted.
1586 dispatch_flags
|= I915_DISPATCH_SECURE
;
1587 params
->args_batch_start_offset
= 0;
1588 batch_obj
= parsed_batch_obj
;
1592 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1594 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1595 * batch" bit. Hence we need to pin secure batches into the global gtt.
1596 * hsw should have this fixed, but bdw mucks it up again. */
1597 if (dispatch_flags
& I915_DISPATCH_SECURE
) {
1599 * So on first glance it looks freaky that we pin the batch here
1600 * outside of the reservation loop. But:
1601 * - The batch is already pinned into the relevant ppgtt, so we
1602 * already have the backing storage fully allocated.
1603 * - No other BO uses the global gtt (well contexts, but meh),
1604 * so we don't really have issues with multiple objects not
1605 * fitting due to fragmentation.
1606 * So this is actually safe.
1608 ret
= i915_gem_obj_ggtt_pin(batch_obj
, 0, 0);
1612 params
->batch_obj_vm_offset
= i915_gem_obj_ggtt_offset(batch_obj
);
1614 params
->batch_obj_vm_offset
= i915_gem_obj_offset(batch_obj
, vm
);
1616 /* Allocate a request for this batch buffer nice and early. */
1617 ret
= i915_gem_request_alloc(ring
, ctx
, ¶ms
->request
);
1619 goto err_batch_unpin
;
1622 * Save assorted stuff away to pass through to *_submission().
1623 * NB: This data should be 'persistent' and not local as it will
1624 * kept around beyond the duration of the IOCTL once the GPU
1625 * scheduler arrives.
1628 params
->file
= file
;
1629 params
->ring
= ring
;
1630 params
->dispatch_flags
= dispatch_flags
;
1631 params
->batch_obj
= batch_obj
;
1634 ret
= dev_priv
->gt
.execbuf_submit(params
, args
, &eb
->vmas
);
1638 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1639 * batch vma for correctness. For less ugly and less fragility this
1640 * needs to be adjusted to also track the ggtt batch vma properly as
1643 if (dispatch_flags
& I915_DISPATCH_SECURE
)
1644 i915_gem_object_ggtt_unpin(batch_obj
);
1647 /* the request owns the ref now */
1648 i915_gem_context_unreference(ctx
);
1652 * If the request was created but not successfully submitted then it
1653 * must be freed again. If it was submitted then it is being tracked
1654 * on the active request list and no clean up is required here.
1656 if (ret
&& params
->request
) {
1657 i915_gem_request_cancel(params
->request
);
1658 ring
->outstanding_lazy_request
= NULL
;
1661 mutex_unlock(&dev
->struct_mutex
);
1664 /* intel_gpu_busy should also get a ref, so it will free when the device
1665 * is really idle. */
1666 intel_runtime_pm_put(dev_priv
);
1671 * Legacy execbuffer just creates an exec2 list from the original exec object
1672 * list array and passes it to the real function.
1675 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1676 struct drm_file
*file
)
1678 struct drm_i915_gem_execbuffer
*args
= data
;
1679 struct drm_i915_gem_execbuffer2 exec2
;
1680 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1681 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1684 if (args
->buffer_count
< 1) {
1685 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1689 /* Copy in the exec list from userland */
1690 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1691 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1692 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1693 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1694 args
->buffer_count
);
1695 drm_free_large(exec_list
);
1696 drm_free_large(exec2_list
);
1699 ret
= copy_from_user(exec_list
,
1700 to_user_ptr(args
->buffers_ptr
),
1701 sizeof(*exec_list
) * args
->buffer_count
);
1703 DRM_DEBUG("copy %d exec entries failed %d\n",
1704 args
->buffer_count
, ret
);
1705 drm_free_large(exec_list
);
1706 drm_free_large(exec2_list
);
1710 for (i
= 0; i
< args
->buffer_count
; i
++) {
1711 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1712 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1713 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1714 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1715 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1716 if (INTEL_INFO(dev
)->gen
< 4)
1717 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1719 exec2_list
[i
].flags
= 0;
1722 exec2
.buffers_ptr
= args
->buffers_ptr
;
1723 exec2
.buffer_count
= args
->buffer_count
;
1724 exec2
.batch_start_offset
= args
->batch_start_offset
;
1725 exec2
.batch_len
= args
->batch_len
;
1726 exec2
.DR1
= args
->DR1
;
1727 exec2
.DR4
= args
->DR4
;
1728 exec2
.num_cliprects
= args
->num_cliprects
;
1729 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1730 exec2
.flags
= I915_EXEC_RENDER
;
1731 i915_execbuffer2_set_context_id(exec2
, 0);
1733 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1735 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1736 to_user_ptr(args
->buffers_ptr
);
1738 /* Copy the new buffer offsets back to the user's exec list. */
1739 for (i
= 0; i
< args
->buffer_count
; i
++) {
1740 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1741 &exec2_list
[i
].offset
,
1742 sizeof(user_exec_list
[i
].offset
));
1745 DRM_DEBUG("failed to copy %d exec entries "
1746 "back to user (%d)\n",
1747 args
->buffer_count
, ret
);
1753 drm_free_large(exec_list
);
1754 drm_free_large(exec2_list
);
1759 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1760 struct drm_file
*file
)
1762 struct drm_i915_gem_execbuffer2
*args
= data
;
1763 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1766 if (args
->buffer_count
< 1 ||
1767 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1768 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1772 if (args
->rsvd2
!= 0) {
1773 DRM_DEBUG("dirty rvsd2 field\n");
1777 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1778 GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
1779 if (exec2_list
== NULL
)
1780 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1781 args
->buffer_count
);
1782 if (exec2_list
== NULL
) {
1783 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1784 args
->buffer_count
);
1787 ret
= copy_from_user(exec2_list
,
1788 to_user_ptr(args
->buffers_ptr
),
1789 sizeof(*exec2_list
) * args
->buffer_count
);
1791 DRM_DEBUG("copy %d exec entries failed %d\n",
1792 args
->buffer_count
, ret
);
1793 drm_free_large(exec2_list
);
1797 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1799 /* Copy the new buffer offsets back to the user's exec list. */
1800 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1801 to_user_ptr(args
->buffers_ptr
);
1804 for (i
= 0; i
< args
->buffer_count
; i
++) {
1805 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1806 &exec2_list
[i
].offset
,
1807 sizeof(user_exec_list
[i
].offset
));
1810 DRM_DEBUG("failed to copy %d exec entries "
1812 args
->buffer_count
);
1818 drm_free_large(exec2_list
);