projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35 #include <linux/uaccess.h>
36
37 #define __EXEC_OBJECT_HAS_PIN (1<<31)
38 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
39 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
40 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
41
42 #define BATCH_OFFSET_BIAS (256*1024)
43
44 struct eb_vmas {
45 struct list_head vmas;
46 int and;
47 union {
48 struct i915_vma *lut[0];
49 struct hlist_head buckets[0];
50 };
51 };
52
53 static struct eb_vmas *
54 eb_create(struct drm_i915_gem_execbuffer2 *args)
55 {
56 struct eb_vmas *eb = NULL;
57
58 if (args->flags & I915_EXEC_HANDLE_LUT) {
59 unsigned size = args->buffer_count;
60 size *= sizeof(struct i915_vma *);
61 size += sizeof(struct eb_vmas);
62 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
63 }
64
65 if (eb == NULL) {
66 unsigned size = args->buffer_count;
67 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
68 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
69 while (count > 2*size)
70 count >>= 1;
71 eb = kzalloc(count*sizeof(struct hlist_head) +
72 sizeof(struct eb_vmas),
73 GFP_TEMPORARY);
74 if (eb == NULL)
75 return eb;
76
77 eb->and = count - 1;
78 } else
79 eb->and = -args->buffer_count;
80
81 INIT_LIST_HEAD(&eb->vmas);
82 return eb;
83 }
84
85 static void
86 eb_reset(struct eb_vmas *eb)
87 {
88 if (eb->and >= 0)
89 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
90 }
91
92 static int
93 eb_lookup_vmas(struct eb_vmas *eb,
94 struct drm_i915_gem_exec_object2 *exec,
95 const struct drm_i915_gem_execbuffer2 *args,
96 struct i915_address_space *vm,
97 struct drm_file *file)
98 {
99 struct drm_i915_gem_object *obj;
100 struct list_head objects;
101 int i, ret;
102
103 INIT_LIST_HEAD(&objects);
104 spin_lock(&file->table_lock);
105 /* Grab a reference to the object and release the lock so we can lookup
106 * or create the VMA without using GFP_ATOMIC */
107 for (i = 0; i < args->buffer_count; i++) {
108 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
109 if (obj == NULL) {
110 spin_unlock(&file->table_lock);
111 DRM_DEBUG("Invalid object handle %d at index %d\n",
112 exec[i].handle, i);
113 ret = -ENOENT;
114 goto err;
115 }
116
117 if (!list_empty(&obj->obj_exec_link)) {
118 spin_unlock(&file->table_lock);
119 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
120 obj, exec[i].handle, i);
121 ret = -EINVAL;
122 goto err;
123 }
124
125 drm_gem_object_reference(&obj->base);
126 list_add_tail(&obj->obj_exec_link, &objects);
127 }
128 spin_unlock(&file->table_lock);
129
130 i = 0;
131 while (!list_empty(&objects)) {
132 struct i915_vma *vma;
133
134 obj = list_first_entry(&objects,
135 struct drm_i915_gem_object,
136 obj_exec_link);
137
138 /*
139 * NOTE: We can leak any vmas created here when something fails
140 * later on. But that's no issue since vma_unbind can deal with
141 * vmas which are not actually bound. And since only
142 * lookup_or_create exists as an interface to get at the vma
143 * from the (obj, vm) we don't run the risk of creating
144 * duplicated vmas for the same vm.
145 */
146 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
147 if (IS_ERR(vma)) {
148 DRM_DEBUG("Failed to lookup VMA\n");
149 ret = PTR_ERR(vma);
150 goto err;
151 }
152
153 /* Transfer ownership from the objects list to the vmas list. */
154 list_add_tail(&vma->exec_list, &eb->vmas);
155 list_del_init(&obj->obj_exec_link);
156
157 vma->exec_entry = &exec[i];
158 if (eb->and < 0) {
159 eb->lut[i] = vma;
160 } else {
161 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
162 vma->exec_handle = handle;
163 hlist_add_head(&vma->exec_node,
164 &eb->buckets[handle & eb->and]);
165 }
166 ++i;
167 }
168
169 return 0;
170
171
172 err:
173 while (!list_empty(&objects)) {
174 obj = list_first_entry(&objects,
175 struct drm_i915_gem_object,
176 obj_exec_link);
177 list_del_init(&obj->obj_exec_link);
178 drm_gem_object_unreference(&obj->base);
179 }
180 /*
181 * Objects already transfered to the vmas list will be unreferenced by
182 * eb_destroy.
183 */
184
185 return ret;
186 }
187
188 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
189 {
190 if (eb->and < 0) {
191 if (handle >= -eb->and)
192 return NULL;
193 return eb->lut[handle];
194 } else {
195 struct hlist_head *head;
196 struct i915_vma *vma;
197
198 head = &eb->buckets[handle & eb->and];
199 hlist_for_each_entry(vma, head, exec_node) {
200 if (vma->exec_handle == handle)
201 return vma;
202 }
203 return NULL;
204 }
205 }
206
207 static void
208 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
209 {
210 struct drm_i915_gem_exec_object2 *entry;
211 struct drm_i915_gem_object *obj = vma->obj;
212
213 if (!drm_mm_node_allocated(&vma->node))
214 return;
215
216 entry = vma->exec_entry;
217
218 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
219 i915_gem_object_unpin_fence(obj);
220
221 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
222 vma->pin_count--;
223
224 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
225 }
226
227 static void eb_destroy(struct eb_vmas *eb)
228 {
229 while (!list_empty(&eb->vmas)) {
230 struct i915_vma *vma;
231
232 vma = list_first_entry(&eb->vmas,
233 struct i915_vma,
234 exec_list);
235 list_del_init(&vma->exec_list);
236 i915_gem_execbuffer_unreserve_vma(vma);
237 drm_gem_object_unreference(&vma->obj->base);
238 }
239 kfree(eb);
240 }
241
242 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
243 {
244 return (HAS_LLC(obj->base.dev) ||
245 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
246 obj->cache_level != I915_CACHE_NONE);
247 }
248
249 /* Used to convert any address to canonical form.
250 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
251 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
252 * addresses to be in a canonical form:
253 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
254 * canonical form [63:48] == [47]."
255 */
256 #define GEN8_HIGH_ADDRESS_BIT 47
257 static inline uint64_t gen8_canonical_addr(uint64_t address)
258 {
259 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
260 }
261
262 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
263 {
264 return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
265 }
266
267 static inline uint64_t
268 relocation_target(struct drm_i915_gem_relocation_entry *reloc,
269 uint64_t target_offset)
270 {
271 return gen8_canonical_addr((int)reloc->delta + target_offset);
272 }
273
274 static int
275 relocate_entry_cpu(struct drm_i915_gem_object *obj,
276 struct drm_i915_gem_relocation_entry *reloc,
277 uint64_t target_offset)
278 {
279 struct drm_device *dev = obj->base.dev;
280 uint32_t page_offset = offset_in_page(reloc->offset);
281 uint64_t delta = relocation_target(reloc, target_offset);
282 char *vaddr;
283 int ret;
284
285 ret = i915_gem_object_set_to_cpu_domain(obj, true);
286 if (ret)
287 return ret;
288
289 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
290 reloc->offset >> PAGE_SHIFT));
291 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
292
293 if (INTEL_INFO(dev)->gen >= 8) {
294 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
295
296 if (page_offset == 0) {
297 kunmap_atomic(vaddr);
298 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
299 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
300 }
301
302 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
303 }
304
305 kunmap_atomic(vaddr);
306
307 return 0;
308 }
309
310 static int
311 relocate_entry_gtt(struct drm_i915_gem_object *obj,
312 struct drm_i915_gem_relocation_entry *reloc,
313 uint64_t target_offset)
314 {
315 struct drm_device *dev = obj->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 uint64_t delta = relocation_target(reloc, target_offset);
318 uint64_t offset;
319 void __iomem *reloc_page;
320 int ret;
321
322 ret = i915_gem_object_set_to_gtt_domain(obj, true);
323 if (ret)
324 return ret;
325
326 ret = i915_gem_object_put_fence(obj);
327 if (ret)
328 return ret;
329
330 /* Map the page containing the relocation we're going to perform. */
331 offset = i915_gem_obj_ggtt_offset(obj);
332 offset += reloc->offset;
333 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
334 offset & PAGE_MASK);
335 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
336
337 if (INTEL_INFO(dev)->gen >= 8) {
338 offset += sizeof(uint32_t);
339
340 if (offset_in_page(offset) == 0) {
341 io_mapping_unmap_atomic(reloc_page);
342 reloc_page =
343 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
344 offset);
345 }
346
347 iowrite32(upper_32_bits(delta),
348 reloc_page + offset_in_page(offset));
349 }
350
351 io_mapping_unmap_atomic(reloc_page);
352
353 return 0;
354 }
355
356 static void
357 clflush_write32(void *addr, uint32_t value)
358 {
359 /* This is not a fast path, so KISS. */
360 drm_clflush_virt_range(addr, sizeof(uint32_t));
361 *(uint32_t *)addr = value;
362 drm_clflush_virt_range(addr, sizeof(uint32_t));
363 }
364
365 static int
366 relocate_entry_clflush(struct drm_i915_gem_object *obj,
367 struct drm_i915_gem_relocation_entry *reloc,
368 uint64_t target_offset)
369 {
370 struct drm_device *dev = obj->base.dev;
371 uint32_t page_offset = offset_in_page(reloc->offset);
372 uint64_t delta = relocation_target(reloc, target_offset);
373 char *vaddr;
374 int ret;
375
376 ret = i915_gem_object_set_to_gtt_domain(obj, true);
377 if (ret)
378 return ret;
379
380 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
381 reloc->offset >> PAGE_SHIFT));
382 clflush_write32(vaddr + page_offset, lower_32_bits(delta));
383
384 if (INTEL_INFO(dev)->gen >= 8) {
385 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
386
387 if (page_offset == 0) {
388 kunmap_atomic(vaddr);
389 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
390 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
391 }
392
393 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
394 }
395
396 kunmap_atomic(vaddr);
397
398 return 0;
399 }
400
401 static int
402 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
403 struct eb_vmas *eb,
404 struct drm_i915_gem_relocation_entry *reloc)
405 {
406 struct drm_device *dev = obj->base.dev;
407 struct drm_gem_object *target_obj;
408 struct drm_i915_gem_object *target_i915_obj;
409 struct i915_vma *target_vma;
410 uint64_t target_offset;
411 int ret;
412
413 /* we've already hold a reference to all valid objects */
414 target_vma = eb_get_vma(eb, reloc->target_handle);
415 if (unlikely(target_vma == NULL))
416 return -ENOENT;
417 target_i915_obj = target_vma->obj;
418 target_obj = &target_vma->obj->base;
419
420 target_offset = gen8_canonical_addr(target_vma->node.start);
421
422 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
423 * pipe_control writes because the gpu doesn't properly redirect them
424 * through the ppgtt for non_secure batchbuffers. */
425 if (unlikely(IS_GEN6(dev) &&
426 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
427 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
428 PIN_GLOBAL);
429 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
430 return ret;
431 }
432
433 /* Validate that the target is in a valid r/w GPU domain */
434 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
435 DRM_DEBUG("reloc with multiple write domains: "
436 "obj %p target %d offset %d "
437 "read %08x write %08x",
438 obj, reloc->target_handle,
439 (int) reloc->offset,
440 reloc->read_domains,
441 reloc->write_domain);
442 return -EINVAL;
443 }
444 if (unlikely((reloc->write_domain | reloc->read_domains)
445 & ~I915_GEM_GPU_DOMAINS)) {
446 DRM_DEBUG("reloc with read/write non-GPU domains: "
447 "obj %p target %d offset %d "
448 "read %08x write %08x",
449 obj, reloc->target_handle,
450 (int) reloc->offset,
451 reloc->read_domains,
452 reloc->write_domain);
453 return -EINVAL;
454 }
455
456 target_obj->pending_read_domains |= reloc->read_domains;
457 target_obj->pending_write_domain |= reloc->write_domain;
458
459 /* If the relocation already has the right value in it, no
460 * more work needs to be done.
461 */
462 if (target_offset == reloc->presumed_offset)
463 return 0;
464
465 /* Check that the relocation address is valid... */
466 if (unlikely(reloc->offset >
467 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
468 DRM_DEBUG("Relocation beyond object bounds: "
469 "obj %p target %d offset %d size %d.\n",
470 obj, reloc->target_handle,
471 (int) reloc->offset,
472 (int) obj->base.size);
473 return -EINVAL;
474 }
475 if (unlikely(reloc->offset & 3)) {
476 DRM_DEBUG("Relocation not 4-byte aligned: "
477 "obj %p target %d offset %d.\n",
478 obj, reloc->target_handle,
479 (int) reloc->offset);
480 return -EINVAL;
481 }
482
483 /* We can't wait for rendering with pagefaults disabled */
484 if (obj->active && pagefault_disabled())
485 return -EFAULT;
486
487 if (use_cpu_reloc(obj))
488 ret = relocate_entry_cpu(obj, reloc, target_offset);
489 else if (obj->map_and_fenceable)
490 ret = relocate_entry_gtt(obj, reloc, target_offset);
491 else if (cpu_has_clflush)
492 ret = relocate_entry_clflush(obj, reloc, target_offset);
493 else {
494 WARN_ONCE(1, "Impossible case in relocation handling\n");
495 ret = -ENODEV;
496 }
497
498 if (ret)
499 return ret;
500
501 /* and update the user's relocation entry */
502 reloc->presumed_offset = target_offset;
503
504 return 0;
505 }
506
507 static int
508 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
509 struct eb_vmas *eb)
510 {
511 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
512 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
513 struct drm_i915_gem_relocation_entry __user *user_relocs;
514 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
515 int remain, ret;
516
517 user_relocs = to_user_ptr(entry->relocs_ptr);
518
519 remain = entry->relocation_count;
520 while (remain) {
521 struct drm_i915_gem_relocation_entry *r = stack_reloc;
522 int count = remain;
523 if (count > ARRAY_SIZE(stack_reloc))
524 count = ARRAY_SIZE(stack_reloc);
525 remain -= count;
526
527 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
528 return -EFAULT;
529
530 do {
531 u64 offset = r->presumed_offset;
532
533 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
534 if (ret)
535 return ret;
536
537 if (r->presumed_offset != offset &&
538 __copy_to_user_inatomic(&user_relocs->presumed_offset,
539 &r->presumed_offset,
540 sizeof(r->presumed_offset))) {
541 return -EFAULT;
542 }
543
544 user_relocs++;
545 r++;
546 } while (--count);
547 }
548
549 return 0;
550 #undef N_RELOC
551 }
552
553 static int
554 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
555 struct eb_vmas *eb,
556 struct drm_i915_gem_relocation_entry *relocs)
557 {
558 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
559 int i, ret;
560
561 for (i = 0; i < entry->relocation_count; i++) {
562 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
563 if (ret)
564 return ret;
565 }
566
567 return 0;
568 }
569
570 static int
571 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
572 {
573 struct i915_vma *vma;
574 int ret = 0;
575
576 /* This is the fast path and we cannot handle a pagefault whilst
577 * holding the struct mutex lest the user pass in the relocations
578 * contained within a mmaped bo. For in such a case we, the page
579 * fault handler would call i915_gem_fault() and we would try to
580 * acquire the struct mutex again. Obviously this is bad and so
581 * lockdep complains vehemently.
582 */
583 pagefault_disable();
584 list_for_each_entry(vma, &eb->vmas, exec_list) {
585 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
586 if (ret)
587 break;
588 }
589 pagefault_enable();
590
591 return ret;
592 }
593
594 static bool only_mappable_for_reloc(unsigned int flags)
595 {
596 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
597 __EXEC_OBJECT_NEEDS_MAP;
598 }
599
600 static int
601 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
602 struct intel_engine_cs *ring,
603 bool *need_reloc)
604 {
605 struct drm_i915_gem_object *obj = vma->obj;
606 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
607 uint64_t flags;
608 int ret;
609
610 flags = PIN_USER;
611 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
612 flags |= PIN_GLOBAL;
613
614 if (!drm_mm_node_allocated(&vma->node)) {
615 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
616 * limit address to the first 4GBs for unflagged objects.
617 */
618 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
619 flags |= PIN_ZONE_4G;
620 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
621 flags |= PIN_GLOBAL | PIN_MAPPABLE;
622 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
623 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
624 if (entry->flags & EXEC_OBJECT_PINNED)
625 flags |= entry->offset | PIN_OFFSET_FIXED;
626 if ((flags & PIN_MAPPABLE) == 0)
627 flags |= PIN_HIGH;
628 }
629
630 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
631 if ((ret == -ENOSPC || ret == -E2BIG) &&
632 only_mappable_for_reloc(entry->flags))
633 ret = i915_gem_object_pin(obj, vma->vm,
634 entry->alignment,
635 flags & ~PIN_MAPPABLE);
636 if (ret)
637 return ret;
638
639 entry->flags |= __EXEC_OBJECT_HAS_PIN;
640
641 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
642 ret = i915_gem_object_get_fence(obj);
643 if (ret)
644 return ret;
645
646 if (i915_gem_object_pin_fence(obj))
647 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
648 }
649
650 if (entry->offset != vma->node.start) {
651 entry->offset = vma->node.start;
652 *need_reloc = true;
653 }
654
655 if (entry->flags & EXEC_OBJECT_WRITE) {
656 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
657 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
658 }
659
660 return 0;
661 }
662
663 static bool
664 need_reloc_mappable(struct i915_vma *vma)
665 {
666 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
667
668 if (entry->relocation_count == 0)
669 return false;
670
671 if (!i915_is_ggtt(vma->vm))
672 return false;
673
674 /* See also use_cpu_reloc() */
675 if (HAS_LLC(vma->obj->base.dev))
676 return false;
677
678 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
679 return false;
680
681 return true;
682 }
683
684 static bool
685 eb_vma_misplaced(struct i915_vma *vma)
686 {
687 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
688 struct drm_i915_gem_object *obj = vma->obj;
689
690 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
691 !i915_is_ggtt(vma->vm));
692
693 if (entry->alignment &&
694 vma->node.start & (entry->alignment - 1))
695 return true;
696
697 if (entry->flags & EXEC_OBJECT_PINNED &&
698 vma->node.start != entry->offset)
699 return true;
700
701 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
702 vma->node.start < BATCH_OFFSET_BIAS)
703 return true;
704
705 /* avoid costly ping-pong once a batch bo ended up non-mappable */
706 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
707 return !only_mappable_for_reloc(entry->flags);
708
709 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
710 (vma->node.start + vma->node.size - 1) >> 32)
711 return true;
712
713 return false;
714 }
715
716 static int
717 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
718 struct list_head *vmas,
719 struct intel_context *ctx,
720 bool *need_relocs)
721 {
722 struct drm_i915_gem_object *obj;
723 struct i915_vma *vma;
724 struct i915_address_space *vm;
725 struct list_head ordered_vmas;
726 struct list_head pinned_vmas;
727 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
728 int retry;
729
730 i915_gem_retire_requests_ring(ring);
731
732 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
733
734 INIT_LIST_HEAD(&ordered_vmas);
735 INIT_LIST_HEAD(&pinned_vmas);
736 while (!list_empty(vmas)) {
737 struct drm_i915_gem_exec_object2 *entry;
738 bool need_fence, need_mappable;
739
740 vma = list_first_entry(vmas, struct i915_vma, exec_list);
741 obj = vma->obj;
742 entry = vma->exec_entry;
743
744 if (ctx->flags & CONTEXT_NO_ZEROMAP)
745 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
746
747 if (!has_fenced_gpu_access)
748 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
749 need_fence =
750 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
751 obj->tiling_mode != I915_TILING_NONE;
752 need_mappable = need_fence || need_reloc_mappable(vma);
753
754 if (entry->flags & EXEC_OBJECT_PINNED)
755 list_move_tail(&vma->exec_list, &pinned_vmas);
756 else if (need_mappable) {
757 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
758 list_move(&vma->exec_list, &ordered_vmas);
759 } else
760 list_move_tail(&vma->exec_list, &ordered_vmas);
761
762 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
763 obj->base.pending_write_domain = 0;
764 }
765 list_splice(&ordered_vmas, vmas);
766 list_splice(&pinned_vmas, vmas);
767
768 /* Attempt to pin all of the buffers into the GTT.
769 * This is done in 3 phases:
770 *
771 * 1a. Unbind all objects that do not match the GTT constraints for
772 * the execbuffer (fenceable, mappable, alignment etc).
773 * 1b. Increment pin count for already bound objects.
774 * 2. Bind new objects.
775 * 3. Decrement pin count.
776 *
777 * This avoid unnecessary unbinding of later objects in order to make
778 * room for the earlier objects *unless* we need to defragment.
779 */
780 retry = 0;
781 do {
782 int ret = 0;
783
784 /* Unbind any ill-fitting objects or pin. */
785 list_for_each_entry(vma, vmas, exec_list) {
786 if (!drm_mm_node_allocated(&vma->node))
787 continue;
788
789 if (eb_vma_misplaced(vma))
790 ret = i915_vma_unbind(vma);
791 else
792 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
793 if (ret)
794 goto err;
795 }
796
797 /* Bind fresh objects */
798 list_for_each_entry(vma, vmas, exec_list) {
799 if (drm_mm_node_allocated(&vma->node))
800 continue;
801
802 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
803 if (ret)
804 goto err;
805 }
806
807 err:
808 if (ret != -ENOSPC || retry++)
809 return ret;
810
811 /* Decrement pin count for bound objects */
812 list_for_each_entry(vma, vmas, exec_list)
813 i915_gem_execbuffer_unreserve_vma(vma);
814
815 ret = i915_gem_evict_vm(vm, true);
816 if (ret)
817 return ret;
818 } while (1);
819 }
820
821 static int
822 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
823 struct drm_i915_gem_execbuffer2 *args,
824 struct drm_file *file,
825 struct intel_engine_cs *ring,
826 struct eb_vmas *eb,
827 struct drm_i915_gem_exec_object2 *exec,
828 struct intel_context *ctx)
829 {
830 struct drm_i915_gem_relocation_entry *reloc;
831 struct i915_address_space *vm;
832 struct i915_vma *vma;
833 bool need_relocs;
834 int *reloc_offset;
835 int i, total, ret;
836 unsigned count = args->buffer_count;
837
838 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
839
840 /* We may process another execbuffer during the unlock... */
841 while (!list_empty(&eb->vmas)) {
842 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
843 list_del_init(&vma->exec_list);
844 i915_gem_execbuffer_unreserve_vma(vma);
845 drm_gem_object_unreference(&vma->obj->base);
846 }
847
848 mutex_unlock(&dev->struct_mutex);
849
850 total = 0;
851 for (i = 0; i < count; i++)
852 total += exec[i].relocation_count;
853
854 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
855 reloc = drm_malloc_ab(total, sizeof(*reloc));
856 if (reloc == NULL || reloc_offset == NULL) {
857 drm_free_large(reloc);
858 drm_free_large(reloc_offset);
859 mutex_lock(&dev->struct_mutex);
860 return -ENOMEM;
861 }
862
863 total = 0;
864 for (i = 0; i < count; i++) {
865 struct drm_i915_gem_relocation_entry __user *user_relocs;
866 u64 invalid_offset = (u64)-1;
867 int j;
868
869 user_relocs = to_user_ptr(exec[i].relocs_ptr);
870
871 if (copy_from_user(reloc+total, user_relocs,
872 exec[i].relocation_count * sizeof(*reloc))) {
873 ret = -EFAULT;
874 mutex_lock(&dev->struct_mutex);
875 goto err;
876 }
877
878 /* As we do not update the known relocation offsets after
879 * relocating (due to the complexities in lock handling),
880 * we need to mark them as invalid now so that we force the
881 * relocation processing next time. Just in case the target
882 * object is evicted and then rebound into its old
883 * presumed_offset before the next execbuffer - if that
884 * happened we would make the mistake of assuming that the
885 * relocations were valid.
886 */
887 for (j = 0; j < exec[i].relocation_count; j++) {
888 if (__copy_to_user(&user_relocs[j].presumed_offset,
889 &invalid_offset,
890 sizeof(invalid_offset))) {
891 ret = -EFAULT;
892 mutex_lock(&dev->struct_mutex);
893 goto err;
894 }
895 }
896
897 reloc_offset[i] = total;
898 total += exec[i].relocation_count;
899 }
900
901 ret = i915_mutex_lock_interruptible(dev);
902 if (ret) {
903 mutex_lock(&dev->struct_mutex);
904 goto err;
905 }
906
907 /* reacquire the objects */
908 eb_reset(eb);
909 ret = eb_lookup_vmas(eb, exec, args, vm, file);
910 if (ret)
911 goto err;
912
913 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
914 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
915 if (ret)
916 goto err;
917
918 list_for_each_entry(vma, &eb->vmas, exec_list) {
919 int offset = vma->exec_entry - exec;
920 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
921 reloc + reloc_offset[offset]);
922 if (ret)
923 goto err;
924 }
925
926 /* Leave the user relocations as are, this is the painfully slow path,
927 * and we want to avoid the complication of dropping the lock whilst
928 * having buffers reserved in the aperture and so causing spurious
929 * ENOSPC for random operations.
930 */
931
932 err:
933 drm_free_large(reloc);
934 drm_free_large(reloc_offset);
935 return ret;
936 }
937
938 static int
939 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
940 struct list_head *vmas)
941 {
942 const unsigned other_rings = ~intel_ring_flag(req->ring);
943 struct i915_vma *vma;
944 uint32_t flush_domains = 0;
945 bool flush_chipset = false;
946 int ret;
947
948 list_for_each_entry(vma, vmas, exec_list) {
949 struct drm_i915_gem_object *obj = vma->obj;
950
951 if (obj->active & other_rings) {
952 ret = i915_gem_object_sync(obj, req->ring, &req);
953 if (ret)
954 return ret;
955 }
956
957 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
958 flush_chipset |= i915_gem_clflush_object(obj, false);
959
960 flush_domains |= obj->base.write_domain;
961 }
962
963 if (flush_chipset)
964 i915_gem_chipset_flush(req->ring->dev);
965
966 if (flush_domains & I915_GEM_DOMAIN_GTT)
967 wmb();
968
969 /* Unconditionally invalidate gpu caches and ensure that we do flush
970 * any residual writes from the previous batch.
971 */
972 return intel_ring_invalidate_all_caches(req);
973 }
974
975 static bool
976 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
977 {
978 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
979 return false;
980
981 /* Kernel clipping was a DRI1 misfeature */
982 if (exec->num_cliprects || exec->cliprects_ptr)
983 return false;
984
985 if (exec->DR4 == 0xffffffff) {
986 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
987 exec->DR4 = 0;
988 }
989 if (exec->DR1 || exec->DR4)
990 return false;
991
992 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
993 return false;
994
995 return true;
996 }
997
998 static int
999 validate_exec_list(struct drm_device *dev,
1000 struct drm_i915_gem_exec_object2 *exec,
1001 int count)
1002 {
1003 unsigned relocs_total = 0;
1004 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1005 unsigned invalid_flags;
1006 int i;
1007
1008 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1009 if (USES_FULL_PPGTT(dev))
1010 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1011
1012 for (i = 0; i < count; i++) {
1013 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
1014 int length; /* limited by fault_in_pages_readable() */
1015
1016 if (exec[i].flags & invalid_flags)
1017 return -EINVAL;
1018
1019 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1020 * any non-page-aligned or non-canonical addresses.
1021 */
1022 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1023 if (exec[i].offset !=
1024 gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1025 return -EINVAL;
1026
1027 /* From drm_mm perspective address space is continuous,
1028 * so from this point we're always using non-canonical
1029 * form internally.
1030 */
1031 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1032 }
1033
1034 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1035 return -EINVAL;
1036
1037 /* First check for malicious input causing overflow in
1038 * the worst case where we need to allocate the entire
1039 * relocation tree as a single array.
1040 */
1041 if (exec[i].relocation_count > relocs_max - relocs_total)
1042 return -EINVAL;
1043 relocs_total += exec[i].relocation_count;
1044
1045 length = exec[i].relocation_count *
1046 sizeof(struct drm_i915_gem_relocation_entry);
1047 /*
1048 * We must check that the entire relocation array is safe
1049 * to read, but since we may need to update the presumed
1050 * offsets during execution, check for full write access.
1051 */
1052 if (!access_ok(VERIFY_WRITE, ptr, length))
1053 return -EFAULT;
1054
1055 if (likely(!i915.prefault_disable)) {
1056 if (fault_in_multipages_readable(ptr, length))
1057 return -EFAULT;
1058 }
1059 }
1060
1061 return 0;
1062 }
1063
1064 static struct intel_context *
1065 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1066 struct intel_engine_cs *ring, const u32 ctx_id)
1067 {
1068 struct intel_context *ctx = NULL;
1069 struct i915_ctx_hang_stats *hs;
1070
1071 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1072 return ERR_PTR(-EINVAL);
1073
1074 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
1075 if (IS_ERR(ctx))
1076 return ctx;
1077
1078 hs = &ctx->hang_stats;
1079 if (hs->banned) {
1080 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1081 return ERR_PTR(-EIO);
1082 }
1083
1084 if (i915.enable_execlists && !ctx->engine[ring->id].state) {
1085 int ret = intel_lr_context_deferred_alloc(ctx, ring);
1086 if (ret) {
1087 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
1088 return ERR_PTR(ret);
1089 }
1090 }
1091
1092 return ctx;
1093 }
1094
1095 void
1096 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1097 struct drm_i915_gem_request *req)
1098 {
1099 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1100 struct i915_vma *vma;
1101
1102 list_for_each_entry(vma, vmas, exec_list) {
1103 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1104 struct drm_i915_gem_object *obj = vma->obj;
1105 u32 old_read = obj->base.read_domains;
1106 u32 old_write = obj->base.write_domain;
1107
1108 obj->dirty = 1; /* be paranoid */
1109 obj->base.write_domain = obj->base.pending_write_domain;
1110 if (obj->base.write_domain == 0)
1111 obj->base.pending_read_domains |= obj->base.read_domains;
1112 obj->base.read_domains = obj->base.pending_read_domains;
1113
1114 i915_vma_move_to_active(vma, req);
1115 if (obj->base.write_domain) {
1116 i915_gem_request_assign(&obj->last_write_req, req);
1117
1118 intel_fb_obj_invalidate(obj, ORIGIN_CS);
1119
1120 /* update for the implicit flush after a batch */
1121 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1122 }
1123 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1124 i915_gem_request_assign(&obj->last_fenced_req, req);
1125 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1126 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1127 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1128 &dev_priv->mm.fence_list);
1129 }
1130 }
1131
1132 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1133 }
1134 }
1135
1136 void
1137 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
1138 {
1139 /* Unconditionally force add_request to emit a full flush. */
1140 params->ring->gpu_caches_dirty = true;
1141
1142 /* Add a breadcrumb for the completion of the batch buffer */
1143 __i915_add_request(params->request, params->batch_obj, true);
1144 }
1145
1146 static int
1147 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1148 struct drm_i915_gem_request *req)
1149 {
1150 struct intel_engine_cs *ring = req->ring;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 int ret, i;
1153
1154 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1155 DRM_DEBUG("sol reset is gen7/rcs only\n");
1156 return -EINVAL;
1157 }
1158
1159 ret = intel_ring_begin(req, 4 * 3);
1160 if (ret)
1161 return ret;
1162
1163 for (i = 0; i < 4; i++) {
1164 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1165 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1166 intel_ring_emit(ring, 0);
1167 }
1168
1169 intel_ring_advance(ring);
1170
1171 return 0;
1172 }
1173
1174 static struct drm_i915_gem_object*
1175 i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
1176 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1177 struct eb_vmas *eb,
1178 struct drm_i915_gem_object *batch_obj,
1179 u32 batch_start_offset,
1180 u32 batch_len,
1181 bool is_master)
1182 {
1183 struct drm_i915_gem_object *shadow_batch_obj;
1184 struct i915_vma *vma;
1185 int ret;
1186
1187 shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
1188 PAGE_ALIGN(batch_len));
1189 if (IS_ERR(shadow_batch_obj))
1190 return shadow_batch_obj;
1191
1192 ret = i915_parse_cmds(ring,
1193 batch_obj,
1194 shadow_batch_obj,
1195 batch_start_offset,
1196 batch_len,
1197 is_master);
1198 if (ret)
1199 goto err;
1200
1201 ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1202 if (ret)
1203 goto err;
1204
1205 i915_gem_object_unpin_pages(shadow_batch_obj);
1206
1207 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1208
1209 vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1210 vma->exec_entry = shadow_exec_entry;
1211 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1212 drm_gem_object_reference(&shadow_batch_obj->base);
1213 list_add_tail(&vma->exec_list, &eb->vmas);
1214
1215 shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1216
1217 return shadow_batch_obj;
1218
1219 err:
1220 i915_gem_object_unpin_pages(shadow_batch_obj);
1221 if (ret == -EACCES) /* unhandled chained batch */
1222 return batch_obj;
1223 else
1224 return ERR_PTR(ret);
1225 }
1226
1227 int
1228 i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
1229 struct drm_i915_gem_execbuffer2 *args,
1230 struct list_head *vmas)
1231 {
1232 struct drm_device *dev = params->dev;
1233 struct intel_engine_cs *ring = params->ring;
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 u64 exec_start, exec_len;
1236 int instp_mode;
1237 u32 instp_mask;
1238 int ret;
1239
1240 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1241 if (ret)
1242 return ret;
1243
1244 ret = i915_switch_context(params->request);
1245 if (ret)
1246 return ret;
1247
1248 WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
1249 "%s didn't clear reload\n", ring->name);
1250
1251 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1252 instp_mask = I915_EXEC_CONSTANTS_MASK;
1253 switch (instp_mode) {
1254 case I915_EXEC_CONSTANTS_REL_GENERAL:
1255 case I915_EXEC_CONSTANTS_ABSOLUTE:
1256 case I915_EXEC_CONSTANTS_REL_SURFACE:
1257 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1258 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1259 return -EINVAL;
1260 }
1261
1262 if (instp_mode != dev_priv->relative_constants_mode) {
1263 if (INTEL_INFO(dev)->gen < 4) {
1264 DRM_DEBUG("no rel constants on pre-gen4\n");
1265 return -EINVAL;
1266 }
1267
1268 if (INTEL_INFO(dev)->gen > 5 &&
1269 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1270 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1271 return -EINVAL;
1272 }
1273
1274 /* The HW changed the meaning on this bit on gen6 */
1275 if (INTEL_INFO(dev)->gen >= 6)
1276 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1277 }
1278 break;
1279 default:
1280 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1281 return -EINVAL;
1282 }
1283
1284 if (ring == &dev_priv->ring[RCS] &&
1285 instp_mode != dev_priv->relative_constants_mode) {
1286 ret = intel_ring_begin(params->request, 4);
1287 if (ret)
1288 return ret;
1289
1290 intel_ring_emit(ring, MI_NOOP);
1291 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1292 intel_ring_emit_reg(ring, INSTPM);
1293 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1294 intel_ring_advance(ring);
1295
1296 dev_priv->relative_constants_mode = instp_mode;
1297 }
1298
1299 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1300 ret = i915_reset_gen7_sol_offsets(dev, params->request);
1301 if (ret)
1302 return ret;
1303 }
1304
1305 exec_len = args->batch_len;
1306 exec_start = params->batch_obj_vm_offset +
1307 params->args_batch_start_offset;
1308
1309 if (exec_len == 0)
1310 exec_len = params->batch_obj->base.size;
1311
1312 ret = ring->dispatch_execbuffer(params->request,
1313 exec_start, exec_len,
1314 params->dispatch_flags);
1315 if (ret)
1316 return ret;
1317
1318 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1319
1320 i915_gem_execbuffer_move_to_active(vmas, params->request);
1321 i915_gem_execbuffer_retire_commands(params);
1322
1323 return 0;
1324 }
1325
1326 /**
1327 * Find one BSD ring to dispatch the corresponding BSD command.
1328 * The Ring ID is returned.
1329 */
1330 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1331 struct drm_file *file)
1332 {
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct drm_i915_file_private *file_priv = file->driver_priv;
1335
1336 /* Check whether the file_priv is using one ring */
1337 if (file_priv->bsd_ring)
1338 return file_priv->bsd_ring->id;
1339 else {
1340 /* If no, use the ping-pong mechanism to select one ring */
1341 int ring_id;
1342
1343 mutex_lock(&dev->struct_mutex);
1344 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1345 ring_id = VCS;
1346 dev_priv->mm.bsd_ring_dispatch_index = 1;
1347 } else {
1348 ring_id = VCS2;
1349 dev_priv->mm.bsd_ring_dispatch_index = 0;
1350 }
1351 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1352 mutex_unlock(&dev->struct_mutex);
1353 return ring_id;
1354 }
1355 }
1356
1357 static struct drm_i915_gem_object *
1358 eb_get_batch(struct eb_vmas *eb)
1359 {
1360 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1361
1362 /*
1363 * SNA is doing fancy tricks with compressing batch buffers, which leads
1364 * to negative relocation deltas. Usually that works out ok since the
1365 * relocate address is still positive, except when the batch is placed
1366 * very low in the GTT. Ensure this doesn't happen.
1367 *
1368 * Note that actual hangs have only been observed on gen7, but for
1369 * paranoia do it everywhere.
1370 */
1371 if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
1372 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1373
1374 return vma->obj;
1375 }
1376
1377 static int
1378 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1379 struct drm_file *file,
1380 struct drm_i915_gem_execbuffer2 *args,
1381 struct drm_i915_gem_exec_object2 *exec)
1382 {
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 struct drm_i915_gem_request *req = NULL;
1385 struct eb_vmas *eb;
1386 struct drm_i915_gem_object *batch_obj;
1387 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1388 struct intel_engine_cs *ring;
1389 struct intel_context *ctx;
1390 struct i915_address_space *vm;
1391 struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1392 struct i915_execbuffer_params *params = &params_master;
1393 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1394 u32 dispatch_flags;
1395 int ret;
1396 bool need_relocs;
1397
1398 if (!i915_gem_check_execbuffer(args))
1399 return -EINVAL;
1400
1401 ret = validate_exec_list(dev, exec, args->buffer_count);
1402 if (ret)
1403 return ret;
1404
1405 dispatch_flags = 0;
1406 if (args->flags & I915_EXEC_SECURE) {
1407 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1408 return -EPERM;
1409
1410 dispatch_flags |= I915_DISPATCH_SECURE;
1411 }
1412 if (args->flags & I915_EXEC_IS_PINNED)
1413 dispatch_flags |= I915_DISPATCH_PINNED;
1414
1415 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1416 DRM_DEBUG("execbuf with unknown ring: %d\n",
1417 (int)(args->flags & I915_EXEC_RING_MASK));
1418 return -EINVAL;
1419 }
1420
1421 if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
1422 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1423 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1424 "bsd dispatch flags: %d\n", (int)(args->flags));
1425 return -EINVAL;
1426 }
1427
1428 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1429 ring = &dev_priv->ring[RCS];
1430 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1431 if (HAS_BSD2(dev)) {
1432 int ring_id;
1433
1434 switch (args->flags & I915_EXEC_BSD_MASK) {
1435 case I915_EXEC_BSD_DEFAULT:
1436 ring_id = gen8_dispatch_bsd_ring(dev, file);
1437 ring = &dev_priv->ring[ring_id];
1438 break;
1439 case I915_EXEC_BSD_RING1:
1440 ring = &dev_priv->ring[VCS];
1441 break;
1442 case I915_EXEC_BSD_RING2:
1443 ring = &dev_priv->ring[VCS2];
1444 break;
1445 default:
1446 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1447 (int)(args->flags & I915_EXEC_BSD_MASK));
1448 return -EINVAL;
1449 }
1450 } else
1451 ring = &dev_priv->ring[VCS];
1452 } else
1453 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1454
1455 if (!intel_ring_initialized(ring)) {
1456 DRM_DEBUG("execbuf with invalid ring: %d\n",
1457 (int)(args->flags & I915_EXEC_RING_MASK));
1458 return -EINVAL;
1459 }
1460
1461 if (args->buffer_count < 1) {
1462 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1463 return -EINVAL;
1464 }
1465
1466 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1467 if (!HAS_RESOURCE_STREAMER(dev)) {
1468 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1469 return -EINVAL;
1470 }
1471 if (ring->id != RCS) {
1472 DRM_DEBUG("RS is not available on %s\n",
1473 ring->name);
1474 return -EINVAL;
1475 }
1476
1477 dispatch_flags |= I915_DISPATCH_RS;
1478 }
1479
1480 intel_runtime_pm_get(dev_priv);
1481
1482 ret = i915_mutex_lock_interruptible(dev);
1483 if (ret)
1484 goto pre_mutex_err;
1485
1486 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1487 if (IS_ERR(ctx)) {
1488 mutex_unlock(&dev->struct_mutex);
1489 ret = PTR_ERR(ctx);
1490 goto pre_mutex_err;
1491 }
1492
1493 i915_gem_context_reference(ctx);
1494
1495 if (ctx->ppgtt)
1496 vm = &ctx->ppgtt->base;
1497 else
1498 vm = &dev_priv->gtt.base;
1499
1500 memset(&params_master, 0x00, sizeof(params_master));
1501
1502 eb = eb_create(args);
1503 if (eb == NULL) {
1504 i915_gem_context_unreference(ctx);
1505 mutex_unlock(&dev->struct_mutex);
1506 ret = -ENOMEM;
1507 goto pre_mutex_err;
1508 }
1509
1510 /* Look up object handles */
1511 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1512 if (ret)
1513 goto err;
1514
1515 /* take note of the batch buffer before we might reorder the lists */
1516 batch_obj = eb_get_batch(eb);
1517
1518 /* Move the objects en-masse into the GTT, evicting if necessary. */
1519 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1520 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
1521 if (ret)
1522 goto err;
1523
1524 /* The objects are in their final locations, apply the relocations. */
1525 if (need_relocs)
1526 ret = i915_gem_execbuffer_relocate(eb);
1527 if (ret) {
1528 if (ret == -EFAULT) {
1529 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1530 eb, exec, ctx);
1531 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1532 }
1533 if (ret)
1534 goto err;
1535 }
1536
1537 /* Set the pending read domains for the batch buffer to COMMAND */
1538 if (batch_obj->base.pending_write_domain) {
1539 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1540 ret = -EINVAL;
1541 goto err;
1542 }
1543
1544 params->args_batch_start_offset = args->batch_start_offset;
1545 if (i915_needs_cmd_parser(ring) && args->batch_len) {
1546 struct drm_i915_gem_object *parsed_batch_obj;
1547
1548 parsed_batch_obj = i915_gem_execbuffer_parse(ring,
1549 &shadow_exec_entry,
1550 eb,
1551 batch_obj,
1552 args->batch_start_offset,
1553 args->batch_len,
1554 file->is_master);
1555 if (IS_ERR(parsed_batch_obj)) {
1556 ret = PTR_ERR(parsed_batch_obj);
1557 goto err;
1558 }
1559
1560 /*
1561 * parsed_batch_obj == batch_obj means batch not fully parsed:
1562 * Accept, but don't promote to secure.
1563 */
1564
1565 if (parsed_batch_obj != batch_obj) {
1566 /*
1567 * Batch parsed and accepted:
1568 *
1569 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1570 * bit from MI_BATCH_BUFFER_START commands issued in
1571 * the dispatch_execbuffer implementations. We
1572 * specifically don't want that set on batches the
1573 * command parser has accepted.
1574 */
1575 dispatch_flags |= I915_DISPATCH_SECURE;
1576 params->args_batch_start_offset = 0;
1577 batch_obj = parsed_batch_obj;
1578 }
1579 }
1580
1581 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1582
1583 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1584 * batch" bit. Hence we need to pin secure batches into the global gtt.
1585 * hsw should have this fixed, but bdw mucks it up again. */
1586 if (dispatch_flags & I915_DISPATCH_SECURE) {
1587 /*
1588 * So on first glance it looks freaky that we pin the batch here
1589 * outside of the reservation loop. But:
1590 * - The batch is already pinned into the relevant ppgtt, so we
1591 * already have the backing storage fully allocated.
1592 * - No other BO uses the global gtt (well contexts, but meh),
1593 * so we don't really have issues with multiple objects not
1594 * fitting due to fragmentation.
1595 * So this is actually safe.
1596 */
1597 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1598 if (ret)
1599 goto err;
1600
1601 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
1602 } else
1603 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
1604
1605 /* Allocate a request for this batch buffer nice and early. */
1606 req = i915_gem_request_alloc(ring, ctx);
1607 if (IS_ERR(req)) {
1608 ret = PTR_ERR(req);
1609 goto err_batch_unpin;
1610 }
1611
1612 ret = i915_gem_request_add_to_client(req, file);
1613 if (ret)
1614 goto err_batch_unpin;
1615
1616 /*
1617 * Save assorted stuff away to pass through to *_submission().
1618 * NB: This data should be 'persistent' and not local as it will
1619 * kept around beyond the duration of the IOCTL once the GPU
1620 * scheduler arrives.
1621 */
1622 params->dev = dev;
1623 params->file = file;
1624 params->ring = ring;
1625 params->dispatch_flags = dispatch_flags;
1626 params->batch_obj = batch_obj;
1627 params->ctx = ctx;
1628 params->request = req;
1629
1630 ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
1631
1632 err_batch_unpin:
1633 /*
1634 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1635 * batch vma for correctness. For less ugly and less fragility this
1636 * needs to be adjusted to also track the ggtt batch vma properly as
1637 * active.
1638 */
1639 if (dispatch_flags & I915_DISPATCH_SECURE)
1640 i915_gem_object_ggtt_unpin(batch_obj);
1641
1642 err:
1643 /* the request owns the ref now */
1644 i915_gem_context_unreference(ctx);
1645 eb_destroy(eb);
1646
1647 /*
1648 * If the request was created but not successfully submitted then it
1649 * must be freed again. If it was submitted then it is being tracked
1650 * on the active request list and no clean up is required here.
1651 */
1652 if (ret && req)
1653 i915_gem_request_cancel(req);
1654
1655 mutex_unlock(&dev->struct_mutex);
1656
1657 pre_mutex_err:
1658 /* intel_gpu_busy should also get a ref, so it will free when the device
1659 * is really idle. */
1660 intel_runtime_pm_put(dev_priv);
1661 return ret;
1662 }
1663
1664 /*
1665 * Legacy execbuffer just creates an exec2 list from the original exec object
1666 * list array and passes it to the real function.
1667 */
1668 int
1669 i915_gem_execbuffer(struct drm_device *dev, void *data,
1670 struct drm_file *file)
1671 {
1672 struct drm_i915_gem_execbuffer *args = data;
1673 struct drm_i915_gem_execbuffer2 exec2;
1674 struct drm_i915_gem_exec_object *exec_list = NULL;
1675 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1676 int ret, i;
1677
1678 if (args->buffer_count < 1) {
1679 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1680 return -EINVAL;
1681 }
1682
1683 /* Copy in the exec list from userland */
1684 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1685 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1686 if (exec_list == NULL || exec2_list == NULL) {
1687 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1688 args->buffer_count);
1689 drm_free_large(exec_list);
1690 drm_free_large(exec2_list);
1691 return -ENOMEM;
1692 }
1693 ret = copy_from_user(exec_list,
1694 to_user_ptr(args->buffers_ptr),
1695 sizeof(*exec_list) * args->buffer_count);
1696 if (ret != 0) {
1697 DRM_DEBUG("copy %d exec entries failed %d\n",
1698 args->buffer_count, ret);
1699 drm_free_large(exec_list);
1700 drm_free_large(exec2_list);
1701 return -EFAULT;
1702 }
1703
1704 for (i = 0; i < args->buffer_count; i++) {
1705 exec2_list[i].handle = exec_list[i].handle;
1706 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1707 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1708 exec2_list[i].alignment = exec_list[i].alignment;
1709 exec2_list[i].offset = exec_list[i].offset;
1710 if (INTEL_INFO(dev)->gen < 4)
1711 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1712 else
1713 exec2_list[i].flags = 0;
1714 }
1715
1716 exec2.buffers_ptr = args->buffers_ptr;
1717 exec2.buffer_count = args->buffer_count;
1718 exec2.batch_start_offset = args->batch_start_offset;
1719 exec2.batch_len = args->batch_len;
1720 exec2.DR1 = args->DR1;
1721 exec2.DR4 = args->DR4;
1722 exec2.num_cliprects = args->num_cliprects;
1723 exec2.cliprects_ptr = args->cliprects_ptr;
1724 exec2.flags = I915_EXEC_RENDER;
1725 i915_execbuffer2_set_context_id(exec2, 0);
1726
1727 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1728 if (!ret) {
1729 struct drm_i915_gem_exec_object __user *user_exec_list =
1730 to_user_ptr(args->buffers_ptr);
1731
1732 /* Copy the new buffer offsets back to the user's exec list. */
1733 for (i = 0; i < args->buffer_count; i++) {
1734 exec2_list[i].offset =
1735 gen8_canonical_addr(exec2_list[i].offset);
1736 ret = __copy_to_user(&user_exec_list[i].offset,
1737 &exec2_list[i].offset,
1738 sizeof(user_exec_list[i].offset));
1739 if (ret) {
1740 ret = -EFAULT;
1741 DRM_DEBUG("failed to copy %d exec entries "
1742 "back to user (%d)\n",
1743 args->buffer_count, ret);
1744 break;
1745 }
1746 }
1747 }
1748
1749 drm_free_large(exec_list);
1750 drm_free_large(exec2_list);
1751 return ret;
1752 }
1753
1754 int
1755 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1756 struct drm_file *file)
1757 {
1758 struct drm_i915_gem_execbuffer2 *args = data;
1759 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1760 int ret;
1761
1762 if (args->buffer_count < 1 ||
1763 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1764 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1765 return -EINVAL;
1766 }
1767
1768 if (args->rsvd2 != 0) {
1769 DRM_DEBUG("dirty rvsd2 field\n");
1770 return -EINVAL;
1771 }
1772
1773 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1774 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1775 if (exec2_list == NULL)
1776 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1777 args->buffer_count);
1778 if (exec2_list == NULL) {
1779 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1780 args->buffer_count);
1781 return -ENOMEM;
1782 }
1783 ret = copy_from_user(exec2_list,
1784 to_user_ptr(args->buffers_ptr),
1785 sizeof(*exec2_list) * args->buffer_count);
1786 if (ret != 0) {
1787 DRM_DEBUG("copy %d exec entries failed %d\n",
1788 args->buffer_count, ret);
1789 drm_free_large(exec2_list);
1790 return -EFAULT;
1791 }
1792
1793 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1794 if (!ret) {
1795 /* Copy the new buffer offsets back to the user's exec list. */
1796 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1797 to_user_ptr(args->buffers_ptr);
1798 int i;
1799
1800 for (i = 0; i < args->buffer_count; i++) {
1801 exec2_list[i].offset =
1802 gen8_canonical_addr(exec2_list[i].offset);
1803 ret = __copy_to_user(&user_exec_list[i].offset,
1804 &exec2_list[i].offset,
1805 sizeof(user_exec_list[i].offset));
1806 if (ret) {
1807 ret = -EFAULT;
1808 DRM_DEBUG("failed to copy %d exec entries "
1809 "back to user\n",
1810 args->buffer_count);
1811 break;
1812 }
1813 }
1814 }
1815
1816 drm_free_large(exec2_list);
1817 return ret;
1818 }
Linux kernel - Deliverables
This page took 0.067073 seconds and 6 git commands to generate.