drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 typedef uint32_t gen6_gtt_pte_t;
  32
  33 /* PPGTT stuff */
  34 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  35
  36 #define GEN6_PDE_VALID                  (1 << 0)
  37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  38 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  39
  40 #define GEN6_PTE_VALID                  (1 << 0)
  41 #define GEN6_PTE_UNCACHED               (1 << 1)
  42 #define HSW_PTE_UNCACHED                (0)
  43 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  44 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  45 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  46
  47 static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  48                                         dma_addr_t addr,
  49                                         enum i915_cache_level level)
  50 {
  51         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 /* Haswell doesn't set L3 this way */
  57                 if (IS_HASWELL(dev))
  58                         pte |= GEN6_PTE_CACHE_LLC;
  59                 else
  60                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  61                 break;
  62         case I915_CACHE_LLC:
  63                 pte |= GEN6_PTE_CACHE_LLC;
  64                 break;
  65         case I915_CACHE_NONE:
  66                 if (IS_HASWELL(dev))
  67                         pte |= HSW_PTE_UNCACHED;
  68                 else
  69                         pte |= GEN6_PTE_UNCACHED;
  70                 break;
  71         default:
  72                 BUG();
  73         }
  74
  75         return pte;
  76 }
  77
  78 /* PPGTT support for Sandybdrige/Gen6 and later */
  79 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
  80                                    unsigned first_entry,
  81                                    unsigned num_entries)
  82 {
  83         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
  84         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
  85         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
  86         unsigned last_pte, i;
  87
  88         scratch_pte = gen6_pte_encode(ppgtt->dev,
  89                                       ppgtt->scratch_page_dma_addr,
  90                                       I915_CACHE_LLC);
  91
  92         while (num_entries) {
  93                 last_pte = first_pte + num_entries;
  94                 if (last_pte > I915_PPGTT_PT_ENTRIES)
  95                         last_pte = I915_PPGTT_PT_ENTRIES;
  96
  97                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
  98
  99                 for (i = first_pte; i < last_pte; i++)
 100                         pt_vaddr[i] = scratch_pte;
 101
 102                 kunmap_atomic(pt_vaddr);
 103
 104                 num_entries -= last_pte - first_pte;
 105                 first_pte = 0;
 106                 act_pt++;
 107         }
 108 }
 109
 110 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 111                                       struct sg_table *pages,
 112                                       unsigned first_entry,
 113                                       enum i915_cache_level cache_level)
 114 {
 115         gen6_gtt_pte_t *pt_vaddr;
 116         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 117         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 118         struct sg_page_iter sg_iter;
 119
 120         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 121         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 122                 dma_addr_t page_addr;
 123
 124                 page_addr = sg_page_iter_dma_address(&sg_iter);
 125                 pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
 126                                                     cache_level);
 127                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 128                         kunmap_atomic(pt_vaddr);
 129                         act_pt++;
 130                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 131                         act_pte = 0;
 132
 133                 }
 134         }
 135         kunmap_atomic(pt_vaddr);
 136 }
 137
 138 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 139 {
 140         int i;
 141
 142         if (ppgtt->pt_dma_addr) {
 143                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 144                         pci_unmap_page(ppgtt->dev->pdev,
 145                                        ppgtt->pt_dma_addr[i],
 146                                        4096, PCI_DMA_BIDIRECTIONAL);
 147         }
 148
 149         kfree(ppgtt->pt_dma_addr);
 150         for (i = 0; i < ppgtt->num_pd_entries; i++)
 151                 __free_page(ppgtt->pt_pages[i]);
 152         kfree(ppgtt->pt_pages);
 153         kfree(ppgtt);
 154 }
 155
 156 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 157 {
 158         struct drm_device *dev = ppgtt->dev;
 159         struct drm_i915_private *dev_priv = dev->dev_private;
 160         unsigned first_pd_entry_in_global_pt;
 161         int i;
 162         int ret = -ENOMEM;
 163
 164         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 165          * entries. For aliasing ppgtt support we just steal them at the end for
 166          * now. */
 167         first_pd_entry_in_global_pt =
 168                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 169
 170         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 171         ppgtt->clear_range = gen6_ppgtt_clear_range;
 172         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 173         ppgtt->cleanup = gen6_ppgtt_cleanup;
 174         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 175                                   GFP_KERNEL);
 176         if (!ppgtt->pt_pages)
 177                 return -ENOMEM;
 178
 179         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 180                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 181                 if (!ppgtt->pt_pages[i])
 182                         goto err_pt_alloc;
 183         }
 184
 185         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 186                                      GFP_KERNEL);
 187         if (!ppgtt->pt_dma_addr)
 188                 goto err_pt_alloc;
 189
 190         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 191                 dma_addr_t pt_addr;
 192
 193                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 194                                        PCI_DMA_BIDIRECTIONAL);
 195
 196                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 197                         ret = -EIO;
 198                         goto err_pd_pin;
 199
 200                 }
 201                 ppgtt->pt_dma_addr[i] = pt_addr;
 202         }
 203
 204         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 205
 206         ppgtt->clear_range(ppgtt, 0,
 207                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 208
 209         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 210
 211         return 0;
 212
 213 err_pd_pin:
 214         if (ppgtt->pt_dma_addr) {
 215                 for (i--; i >= 0; i--)
 216                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 217                                        4096, PCI_DMA_BIDIRECTIONAL);
 218         }
 219 err_pt_alloc:
 220         kfree(ppgtt->pt_dma_addr);
 221         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 222                 if (ppgtt->pt_pages[i])
 223                         __free_page(ppgtt->pt_pages[i]);
 224         }
 225         kfree(ppgtt->pt_pages);
 226
 227         return ret;
 228 }
 229
 230 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 231 {
 232         struct drm_i915_private *dev_priv = dev->dev_private;
 233         struct i915_hw_ppgtt *ppgtt;
 234         int ret;
 235
 236         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 237         if (!ppgtt)
 238                 return -ENOMEM;
 239
 240         ppgtt->dev = dev;
 241
 242         ret = gen6_ppgtt_init(ppgtt);
 243         if (ret)
 244                 kfree(ppgtt);
 245         else
 246                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 247
 248         return ret;
 249 }
 250
 251 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 255
 256         if (!ppgtt)
 257                 return;
 258
 259         ppgtt->cleanup(ppgtt);
 260 }
 261
 262 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 263                             struct drm_i915_gem_object *obj,
 264                             enum i915_cache_level cache_level)
 265 {
 266         ppgtt->insert_entries(ppgtt, obj->pages,
 267                               obj->gtt_space->start >> PAGE_SHIFT,
 268                               cache_level);
 269 }
 270
 271 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 272                               struct drm_i915_gem_object *obj)
 273 {
 274         ppgtt->clear_range(ppgtt,
 275                            obj->gtt_space->start >> PAGE_SHIFT,
 276                            obj->base.size >> PAGE_SHIFT);
 277 }
 278
 279 void i915_gem_init_ppgtt(struct drm_device *dev)
 280 {
 281         drm_i915_private_t *dev_priv = dev->dev_private;
 282         uint32_t pd_offset;
 283         struct intel_ring_buffer *ring;
 284         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 285         gen6_gtt_pte_t __iomem *pd_addr;
 286         uint32_t pd_entry;
 287         int i;
 288
 289         if (!dev_priv->mm.aliasing_ppgtt)
 290                 return;
 291
 292
 293         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
 294                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 295         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 296                 dma_addr_t pt_addr;
 297
 298                 pt_addr = ppgtt->pt_dma_addr[i];
 299                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 300                 pd_entry |= GEN6_PDE_VALID;
 301
 302                 writel(pd_entry, pd_addr + i);
 303         }
 304         readl(pd_addr);
 305
 306         pd_offset = ppgtt->pd_offset;
 307         pd_offset /= 64; /* in cachelines, */
 308         pd_offset <<= 16;
 309
 310         if (INTEL_INFO(dev)->gen == 6) {
 311                 uint32_t ecochk, gab_ctl, ecobits;
 312
 313                 ecobits = I915_READ(GAC_ECO_BITS);
 314                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 315
 316                 gab_ctl = I915_READ(GAB_CTL);
 317                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 318
 319                 ecochk = I915_READ(GAM_ECOCHK);
 320                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 321                                        ECOCHK_PPGTT_CACHE64B);
 322                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 323         } else if (INTEL_INFO(dev)->gen >= 7) {
 324                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 325                 /* GFX_MODE is per-ring on gen7+ */
 326         }
 327
 328         for_each_ring(ring, dev_priv, i) {
 329                 if (INTEL_INFO(dev)->gen >= 7)
 330                         I915_WRITE(RING_MODE_GEN7(ring),
 331                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 332
 333                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 334                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 335         }
 336 }
 337
 338 extern int intel_iommu_gfx_mapped;
 339 /* Certain Gen5 chipsets require require idling the GPU before
 340  * unmapping anything from the GTT when VT-d is enabled.
 341  */
 342 static inline bool needs_idle_maps(struct drm_device *dev)
 343 {
 344 #ifdef CONFIG_INTEL_IOMMU
 345         /* Query intel_iommu to see if we need the workaround. Presumably that
 346          * was loaded first.
 347          */
 348         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 349                 return true;
 350 #endif
 351         return false;
 352 }
 353
 354 static bool do_idling(struct drm_i915_private *dev_priv)
 355 {
 356         bool ret = dev_priv->mm.interruptible;
 357
 358         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 359                 dev_priv->mm.interruptible = false;
 360                 if (i915_gpu_idle(dev_priv->dev)) {
 361                         DRM_ERROR("Couldn't idle GPU\n");
 362                         /* Wait a bit, in hopes it avoids the hang */
 363                         udelay(10);
 364                 }
 365         }
 366
 367         return ret;
 368 }
 369
 370 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 371 {
 372         if (unlikely(dev_priv->gtt.do_idle_maps))
 373                 dev_priv->mm.interruptible = interruptible;
 374 }
 375
 376 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 377 {
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         struct drm_i915_gem_object *obj;
 380
 381         /* First fill our portion of the GTT with scratch pages */
 382         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 383                                       dev_priv->gtt.total / PAGE_SIZE);
 384
 385         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 386                 i915_gem_clflush_object(obj);
 387                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 388         }
 389
 390         i915_gem_chipset_flush(dev);
 391 }
 392
 393 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 394 {
 395         if (obj->has_dma_mapping)
 396                 return 0;
 397
 398         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 399                         obj->pages->sgl, obj->pages->nents,
 400                         PCI_DMA_BIDIRECTIONAL))
 401                 return -ENOSPC;
 402
 403         return 0;
 404 }
 405
 406 /*
 407  * Binds an object into the global gtt with the specified cache level. The object
 408  * will be accessible to the GPU via commands whose operands reference offsets
 409  * within the global GTT as well as accessible by the GPU through the GMADR
 410  * mapped BAR (dev_priv->mm.gtt->gtt).
 411  */
 412 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 413                                      struct sg_table *st,
 414                                      unsigned int first_entry,
 415                                      enum i915_cache_level level)
 416 {
 417         struct drm_i915_private *dev_priv = dev->dev_private;
 418         gen6_gtt_pte_t __iomem *gtt_entries =
 419                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 420         int i = 0;
 421         struct sg_page_iter sg_iter;
 422         dma_addr_t addr;
 423
 424         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 425                 addr = sg_page_iter_dma_address(&sg_iter);
 426                 iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
 427                 i++;
 428         }
 429
 430         /* XXX: This serves as a posting read to make sure that the PTE has
 431          * actually been updated. There is some concern that even though
 432          * registers and PTEs are within the same BAR that they are potentially
 433          * of NUMA access patterns. Therefore, even with the way we assume
 434          * hardware should work, we must keep this posting read for paranoia.
 435          */
 436         if (i != 0)
 437                 WARN_ON(readl(&gtt_entries[i-1])
 438                         != gen6_pte_encode(dev, addr, level));
 439
 440         /* This next bit makes the above posting read even more important. We
 441          * want to flush the TLBs only after we're certain all the PTE updates
 442          * have finished.
 443          */
 444         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 445         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 446 }
 447
 448 static void gen6_ggtt_clear_range(struct drm_device *dev,
 449                                   unsigned int first_entry,
 450                                   unsigned int num_entries)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 454                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 455         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 456         int i;
 457
 458         if (WARN(num_entries > max_entries,
 459                  "First entry = %d; Num entries = %d (max=%d)\n",
 460                  first_entry, num_entries, max_entries))
 461                 num_entries = max_entries;
 462
 463         scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
 464                                       I915_CACHE_LLC);
 465         for (i = 0; i < num_entries; i++)
 466                 iowrite32(scratch_pte, &gtt_base[i]);
 467         readl(gtt_base);
 468 }
 469
 470
 471 static void i915_ggtt_insert_entries(struct drm_device *dev,
 472                                      struct sg_table *st,
 473                                      unsigned int pg_start,
 474                                      enum i915_cache_level cache_level)
 475 {
 476         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 477                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 478
 479         intel_gtt_insert_sg_entries(st, pg_start, flags);
 480
 481 }
 482
 483 static void i915_ggtt_clear_range(struct drm_device *dev,
 484                                   unsigned int first_entry,
 485                                   unsigned int num_entries)
 486 {
 487         intel_gtt_clear_range(first_entry, num_entries);
 488 }
 489
 490
 491 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 492                               enum i915_cache_level cache_level)
 493 {
 494         struct drm_device *dev = obj->base.dev;
 495         struct drm_i915_private *dev_priv = dev->dev_private;
 496
 497         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 498                                          obj->gtt_space->start >> PAGE_SHIFT,
 499                                          cache_level);
 500
 501         obj->has_global_gtt_mapping = 1;
 502 }
 503
 504 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 505 {
 506         struct drm_device *dev = obj->base.dev;
 507         struct drm_i915_private *dev_priv = dev->dev_private;
 508
 509         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 510                                       obj->gtt_space->start >> PAGE_SHIFT,
 511                                       obj->base.size >> PAGE_SHIFT);
 512
 513         obj->has_global_gtt_mapping = 0;
 514 }
 515
 516 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 517 {
 518         struct drm_device *dev = obj->base.dev;
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         bool interruptible;
 521
 522         interruptible = do_idling(dev_priv);
 523
 524         if (!obj->has_dma_mapping)
 525                 dma_unmap_sg(&dev->pdev->dev,
 526                              obj->pages->sgl, obj->pages->nents,
 527                              PCI_DMA_BIDIRECTIONAL);
 528
 529         undo_idling(dev_priv, interruptible);
 530 }
 531
 532 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 533                                   unsigned long color,
 534                                   unsigned long *start,
 535                                   unsigned long *end)
 536 {
 537         if (node->color != color)
 538                 *start += 4096;
 539
 540         if (!list_empty(&node->node_list)) {
 541                 node = list_entry(node->node_list.next,
 542                                   struct drm_mm_node,
 543                                   node_list);
 544                 if (node->allocated && node->color != color)
 545                         *end -= 4096;
 546         }
 547 }
 548 void i915_gem_setup_global_gtt(struct drm_device *dev,
 549                                unsigned long start,
 550                                unsigned long mappable_end,
 551                                unsigned long end)
 552 {
 553         /* Let GEM Manage all of the aperture.
 554          *
 555          * However, leave one page at the end still bound to the scratch page.
 556          * There are a number of places where the hardware apparently prefetches
 557          * past the end of the object, and we've seen multiple hangs with the
 558          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 559          * aperture.  One page should be enough to keep any prefetching inside
 560          * of the aperture.
 561          */
 562         drm_i915_private_t *dev_priv = dev->dev_private;
 563         struct drm_mm_node *entry;
 564         struct drm_i915_gem_object *obj;
 565         unsigned long hole_start, hole_end;
 566
 567         BUG_ON(mappable_end > end);
 568
 569         /* Subtract the guard page ... */
 570         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 571         if (!HAS_LLC(dev))
 572                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 573
 574         /* Mark any preallocated objects as occupied */
 575         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 576                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 577                               obj->gtt_offset, obj->base.size);
 578
 579                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 580                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 581                                                      obj->gtt_offset,
 582                                                      obj->base.size,
 583                                                      false);
 584                 obj->has_global_gtt_mapping = 1;
 585         }
 586
 587         dev_priv->gtt.start = start;
 588         dev_priv->gtt.total = end - start;
 589
 590         /* Clear any non-preallocated blocks */
 591         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 592                              hole_start, hole_end) {
 593                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 594                               hole_start, hole_end);
 595                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 596                                               (hole_end-hole_start) / PAGE_SIZE);
 597         }
 598
 599         /* And finally clear the reserved guard page */
 600         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 601 }
 602
 603 static bool
 604 intel_enable_ppgtt(struct drm_device *dev)
 605 {
 606         if (i915_enable_ppgtt >= 0)
 607                 return i915_enable_ppgtt;
 608
 609 #ifdef CONFIG_INTEL_IOMMU
 610         /* Disable ppgtt on SNB if VT-d is on. */
 611         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 612                 return false;
 613 #endif
 614
 615         return true;
 616 }
 617
 618 void i915_gem_init_global_gtt(struct drm_device *dev)
 619 {
 620         struct drm_i915_private *dev_priv = dev->dev_private;
 621         unsigned long gtt_size, mappable_size;
 622
 623         gtt_size = dev_priv->gtt.total;
 624         mappable_size = dev_priv->gtt.mappable_end;
 625
 626         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 627                 int ret;
 628                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 629                  * aperture accordingly when using aliasing ppgtt. */
 630                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 631
 632                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 633
 634                 ret = i915_gem_init_aliasing_ppgtt(dev);
 635                 if (!ret)
 636                         return;
 637
 638                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 639                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 640                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 641         }
 642         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 643 }
 644
 645 static int setup_scratch_page(struct drm_device *dev)
 646 {
 647         struct drm_i915_private *dev_priv = dev->dev_private;
 648         struct page *page;
 649         dma_addr_t dma_addr;
 650
 651         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 652         if (page == NULL)
 653                 return -ENOMEM;
 654         get_page(page);
 655         set_pages_uc(page, 1);
 656
 657 #ifdef CONFIG_INTEL_IOMMU
 658         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 659                                 PCI_DMA_BIDIRECTIONAL);
 660         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 661                 return -EINVAL;
 662 #else
 663         dma_addr = page_to_phys(page);
 664 #endif
 665         dev_priv->gtt.scratch_page = page;
 666         dev_priv->gtt.scratch_page_dma = dma_addr;
 667
 668         return 0;
 669 }
 670
 671 static void teardown_scratch_page(struct drm_device *dev)
 672 {
 673         struct drm_i915_private *dev_priv = dev->dev_private;
 674         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 675         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 676                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 677         put_page(dev_priv->gtt.scratch_page);
 678         __free_page(dev_priv->gtt.scratch_page);
 679 }
 680
 681 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 682 {
 683         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 684         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 685         return snb_gmch_ctl << 20;
 686 }
 687
 688 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 689 {
 690         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 691         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 692         return snb_gmch_ctl << 25; /* 32 MB units */
 693 }
 694
 695 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 696 {
 697         static const int stolen_decoder[] = {
 698                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 699         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 700         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 701         return stolen_decoder[snb_gmch_ctl] << 20;
 702 }
 703
 704 static int gen6_gmch_probe(struct drm_device *dev,
 705                            size_t *gtt_total,
 706                            size_t *stolen,
 707                            phys_addr_t *mappable_base,
 708                            unsigned long *mappable_end)
 709 {
 710         struct drm_i915_private *dev_priv = dev->dev_private;
 711         phys_addr_t gtt_bus_addr;
 712         unsigned int gtt_size;
 713         u16 snb_gmch_ctl;
 714         int ret;
 715
 716         *mappable_base = pci_resource_start(dev->pdev, 2);
 717         *mappable_end = pci_resource_len(dev->pdev, 2);
 718
 719         /* 64/512MB is the current min/max we actually know of, but this is just
 720          * a coarse sanity check.
 721          */
 722         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 723                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 724                           dev_priv->gtt.mappable_end);
 725                 return -ENXIO;
 726         }
 727
 728         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 729                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 730         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 731         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 732
 733         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 734                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 735         else
 736                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 737
 738         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 739
 740         /* For Modern GENs the PTEs and register space are split in the BAR */
 741         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 742                 (pci_resource_len(dev->pdev, 0) / 2);
 743
 744         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 745         if (!dev_priv->gtt.gsm) {
 746                 DRM_ERROR("Failed to map the gtt page table\n");
 747                 return -ENOMEM;
 748         }
 749
 750         ret = setup_scratch_page(dev);
 751         if (ret)
 752                 DRM_ERROR("Scratch setup failed\n");
 753
 754         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 755         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 756
 757         return ret;
 758 }
 759
 760 static void gen6_gmch_remove(struct drm_device *dev)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         iounmap(dev_priv->gtt.gsm);
 764         teardown_scratch_page(dev_priv->dev);
 765 }
 766
 767 static int i915_gmch_probe(struct drm_device *dev,
 768                            size_t *gtt_total,
 769                            size_t *stolen,
 770                            phys_addr_t *mappable_base,
 771                            unsigned long *mappable_end)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         int ret;
 775
 776         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 777         if (!ret) {
 778                 DRM_ERROR("failed to set up gmch\n");
 779                 return -EIO;
 780         }
 781
 782         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 783
 784         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 785         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 786         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 787
 788         return 0;
 789 }
 790
 791 static void i915_gmch_remove(struct drm_device *dev)
 792 {
 793         intel_gmch_remove();
 794 }
 795
 796 int i915_gem_gtt_init(struct drm_device *dev)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         struct i915_gtt *gtt = &dev_priv->gtt;
 800         unsigned long gtt_size;
 801         int ret;
 802
 803         if (INTEL_INFO(dev)->gen <= 5) {
 804                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 805                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 806         } else {
 807                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 808                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 809         }
 810
 811         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 812                                      &dev_priv->gtt.stolen_size,
 813                                      &gtt->mappable_base,
 814                                      &gtt->mappable_end);
 815         if (ret)
 816                 return ret;
 817
 818         gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gen6_gtt_pte_t);
 819
 820         /* GMADR is the PCI mmio aperture into the global GTT. */
 821         DRM_INFO("Memory usable by graphics device = %zdM\n",
 822                  dev_priv->gtt.total >> 20);
 823         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 824                          dev_priv->gtt.mappable_end >> 20);
 825         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 826                          dev_priv->gtt.stolen_size >> 20);
 827
 828         return 0;
 829 }