2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(struct drm_device
*dev
,
197 enum i915_cache_level level
)
199 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
201 if (level
!= I915_CACHE_NONE
)
202 pde
|= PPAT_CACHED_PDE_INDEX
;
204 pde
|= PPAT_UNCACHED_INDEX
;
208 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
209 enum i915_cache_level level
,
210 bool valid
, u32 unused
)
212 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
213 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
216 case I915_CACHE_L3_LLC
:
218 pte
|= GEN6_PTE_CACHE_LLC
;
220 case I915_CACHE_NONE
:
221 pte
|= GEN6_PTE_UNCACHED
;
230 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
231 enum i915_cache_level level
,
232 bool valid
, u32 unused
)
234 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
235 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
238 case I915_CACHE_L3_LLC
:
239 pte
|= GEN7_PTE_CACHE_L3_LLC
;
242 pte
|= GEN6_PTE_CACHE_LLC
;
244 case I915_CACHE_NONE
:
245 pte
|= GEN6_PTE_UNCACHED
;
254 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
255 enum i915_cache_level level
,
256 bool valid
, u32 flags
)
258 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
259 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
261 if (!(flags
& PTE_READ_ONLY
))
262 pte
|= BYT_PTE_WRITEABLE
;
264 if (level
!= I915_CACHE_NONE
)
265 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
270 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
271 enum i915_cache_level level
,
272 bool valid
, u32 unused
)
274 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
275 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
277 if (level
!= I915_CACHE_NONE
)
278 pte
|= HSW_WB_LLC_AGE3
;
283 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
284 enum i915_cache_level level
,
285 bool valid
, u32 unused
)
287 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
288 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
291 case I915_CACHE_NONE
:
294 pte
|= HSW_WT_ELLC_LLC_AGE3
;
297 pte
|= HSW_WB_ELLC_LLC_AGE3
;
304 static int __setup_page_dma(struct drm_device
*dev
,
305 struct i915_page_dma
*p
, gfp_t flags
)
307 struct device
*device
= &dev
->pdev
->dev
;
309 p
->page
= alloc_page(flags
);
313 p
->daddr
= dma_map_page(device
,
314 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
316 if (dma_mapping_error(device
, p
->daddr
)) {
317 __free_page(p
->page
);
324 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
326 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
329 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
331 if (WARN_ON(!p
->page
))
334 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
335 __free_page(p
->page
);
336 memset(p
, 0, sizeof(*p
));
339 static void *kmap_page_dma(struct i915_page_dma
*p
)
341 return kmap_atomic(p
->page
);
344 /* We use the flushing unmap only with ppgtt structures:
345 * page directories, page tables and scratch pages.
347 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
349 /* There are only few exceptions for gen >=6. chv and bxt.
350 * And we are not sure about the latter so play safe for now.
352 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
353 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
355 kunmap_atomic(vaddr
);
358 #define kmap_px(px) kmap_page_dma(px_base(px))
359 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
361 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
362 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
363 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
364 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
366 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
370 uint64_t * const vaddr
= kmap_page_dma(p
);
372 for (i
= 0; i
< 512; i
++)
375 kunmap_page_dma(dev
, vaddr
);
378 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
379 const uint32_t val32
)
385 fill_page_dma(dev
, p
, v
);
388 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
391 kfree(pt
->used_ptes
);
395 static void gen8_initialize_pt(struct i915_address_space
*vm
,
396 struct i915_page_table
*pt
)
398 gen8_pte_t scratch_pte
;
400 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
401 I915_CACHE_LLC
, true);
403 fill_px(vm
->dev
, pt
, scratch_pte
);
406 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
408 struct i915_page_table
*pt
;
409 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
410 GEN8_PTES
: GEN6_PTES
;
413 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
415 return ERR_PTR(-ENOMEM
);
417 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
423 ret
= setup_px(dev
, pt
);
430 kfree(pt
->used_ptes
);
437 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
441 kfree(pd
->used_pdes
);
446 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
448 struct i915_page_directory
*pd
;
451 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
453 return ERR_PTR(-ENOMEM
);
455 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
456 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
460 ret
= setup_px(dev
, pd
);
467 kfree(pd
->used_pdes
);
474 /* Broadwell Page Directory Pointer Descriptors */
475 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
479 struct intel_engine_cs
*ring
= req
->ring
;
484 ret
= intel_ring_begin(req
, 6);
488 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
489 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
490 intel_ring_emit(ring
, upper_32_bits(addr
));
491 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
492 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
493 intel_ring_emit(ring
, lower_32_bits(addr
));
494 intel_ring_advance(ring
);
499 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
500 struct drm_i915_gem_request
*req
)
504 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
505 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
507 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
515 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
520 struct i915_hw_ppgtt
*ppgtt
=
521 container_of(vm
, struct i915_hw_ppgtt
, base
);
522 gen8_pte_t
*pt_vaddr
, scratch_pte
;
523 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
524 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
525 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
526 unsigned num_entries
= length
>> PAGE_SHIFT
;
527 unsigned last_pte
, i
;
529 scratch_pte
= gen8_pte_encode(px_dma(ppgtt
->base
.scratch_page
),
530 I915_CACHE_LLC
, use_scratch
);
532 while (num_entries
) {
533 struct i915_page_directory
*pd
;
534 struct i915_page_table
*pt
;
536 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
539 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
541 if (WARN_ON(!pd
->page_table
[pde
]))
544 pt
= pd
->page_table
[pde
];
546 if (WARN_ON(!px_page(pt
)))
549 last_pte
= pte
+ num_entries
;
550 if (last_pte
> GEN8_PTES
)
551 last_pte
= GEN8_PTES
;
553 pt_vaddr
= kmap_px(pt
);
555 for (i
= pte
; i
< last_pte
; i
++) {
556 pt_vaddr
[i
] = scratch_pte
;
560 kunmap_px(ppgtt
, pt
);
563 if (++pde
== I915_PDES
) {
570 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
571 struct sg_table
*pages
,
573 enum i915_cache_level cache_level
, u32 unused
)
575 struct i915_hw_ppgtt
*ppgtt
=
576 container_of(vm
, struct i915_hw_ppgtt
, base
);
577 gen8_pte_t
*pt_vaddr
;
578 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
579 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
580 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
581 struct sg_page_iter sg_iter
;
585 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
586 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
589 if (pt_vaddr
== NULL
) {
590 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
591 struct i915_page_table
*pt
= pd
->page_table
[pde
];
592 pt_vaddr
= kmap_px(pt
);
596 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
598 if (++pte
== GEN8_PTES
) {
599 kunmap_px(ppgtt
, pt_vaddr
);
601 if (++pde
== I915_PDES
) {
610 kunmap_px(ppgtt
, pt_vaddr
);
613 static void __gen8_do_map_pt(gen8_pde_t
* const pde
,
614 struct i915_page_table
*pt
,
615 struct drm_device
*dev
)
618 gen8_pde_encode(dev
, px_dma(pt
), I915_CACHE_LLC
);
622 static void gen8_initialize_pd(struct i915_address_space
*vm
,
623 struct i915_page_directory
*pd
)
625 struct i915_hw_ppgtt
*ppgtt
=
626 container_of(vm
, struct i915_hw_ppgtt
, base
);
627 gen8_pde_t scratch_pde
;
629 scratch_pde
= gen8_pde_encode(vm
->dev
, px_dma(ppgtt
->scratch_pt
),
632 fill_px(vm
->dev
, pd
, scratch_pde
);
635 static void gen8_free_page_tables(struct i915_page_directory
*pd
, struct drm_device
*dev
)
642 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
643 if (WARN_ON(!pd
->page_table
[i
]))
646 free_pt(dev
, pd
->page_table
[i
]);
647 pd
->page_table
[i
] = NULL
;
651 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
653 struct i915_hw_ppgtt
*ppgtt
=
654 container_of(vm
, struct i915_hw_ppgtt
, base
);
657 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
, GEN8_LEGACY_PDPES
) {
658 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
661 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
662 free_pd(ppgtt
->base
.dev
, ppgtt
->pdp
.page_directory
[i
]);
665 free_pd(ppgtt
->base
.dev
, ppgtt
->scratch_pd
);
666 free_pt(ppgtt
->base
.dev
, ppgtt
->scratch_pt
);
670 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
671 * @ppgtt: Master ppgtt structure.
672 * @pd: Page directory for this address range.
673 * @start: Starting virtual address to begin allocations.
674 * @length Size of the allocations.
675 * @new_pts: Bitmap set by function with new allocations. Likely used by the
676 * caller to free on error.
678 * Allocate the required number of page tables. Extremely similar to
679 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
680 * the page directory boundary (instead of the page directory pointer). That
681 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
682 * possible, and likely that the caller will need to use multiple calls of this
683 * function to achieve the appropriate allocation.
685 * Return: 0 if success; negative error code otherwise.
687 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
688 struct i915_page_directory
*pd
,
691 unsigned long *new_pts
)
693 struct drm_device
*dev
= ppgtt
->base
.dev
;
694 struct i915_page_table
*pt
;
698 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
699 /* Don't reallocate page tables */
701 /* Scratch is never allocated this way */
702 WARN_ON(pt
== ppgtt
->scratch_pt
);
710 gen8_initialize_pt(&ppgtt
->base
, pt
);
711 pd
->page_table
[pde
] = pt
;
712 set_bit(pde
, new_pts
);
718 for_each_set_bit(pde
, new_pts
, I915_PDES
)
719 free_pt(dev
, pd
->page_table
[pde
]);
725 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
726 * @ppgtt: Master ppgtt structure.
727 * @pdp: Page directory pointer for this address range.
728 * @start: Starting virtual address to begin allocations.
729 * @length Size of the allocations.
730 * @new_pds Bitmap set by function with new allocations. Likely used by the
731 * caller to free on error.
733 * Allocate the required number of page directories starting at the pde index of
734 * @start, and ending at the pde index @start + @length. This function will skip
735 * over already allocated page directories within the range, and only allocate
736 * new ones, setting the appropriate pointer within the pdp as well as the
737 * correct position in the bitmap @new_pds.
739 * The function will only allocate the pages within the range for a give page
740 * directory pointer. In other words, if @start + @length straddles a virtually
741 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
742 * required by the caller, This is not currently possible, and the BUG in the
743 * code will prevent it.
745 * Return: 0 if success; negative error code otherwise.
747 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
748 struct i915_page_directory_pointer
*pdp
,
751 unsigned long *new_pds
)
753 struct drm_device
*dev
= ppgtt
->base
.dev
;
754 struct i915_page_directory
*pd
;
758 WARN_ON(!bitmap_empty(new_pds
, GEN8_LEGACY_PDPES
));
760 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
768 gen8_initialize_pd(&ppgtt
->base
, pd
);
769 pdp
->page_directory
[pdpe
] = pd
;
770 set_bit(pdpe
, new_pds
);
776 for_each_set_bit(pdpe
, new_pds
, GEN8_LEGACY_PDPES
)
777 free_pd(dev
, pdp
->page_directory
[pdpe
]);
783 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
)
787 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++)
793 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
794 * of these are based on the number of PDPEs in the system.
797 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
798 unsigned long ***new_pts
)
804 pds
= kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES
), sizeof(unsigned long), GFP_KERNEL
);
808 pts
= kcalloc(GEN8_LEGACY_PDPES
, sizeof(unsigned long *), GFP_KERNEL
);
814 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
815 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
816 sizeof(unsigned long), GFP_KERNEL
);
827 free_gen8_temp_bitmaps(pds
, pts
);
831 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
832 * the page table structures, we mark them dirty so that
833 * context switching/execlist queuing code takes extra steps
834 * to ensure that tlbs are flushed.
836 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
838 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
841 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
845 struct i915_hw_ppgtt
*ppgtt
=
846 container_of(vm
, struct i915_hw_ppgtt
, base
);
847 unsigned long *new_page_dirs
, **new_page_tables
;
848 struct i915_page_directory
*pd
;
849 const uint64_t orig_start
= start
;
850 const uint64_t orig_length
= length
;
855 /* Wrap is never okay since we can only represent 48b, and we don't
856 * actually use the other side of the canonical address space.
858 if (WARN_ON(start
+ length
< start
))
861 if (WARN_ON(start
+ length
> ppgtt
->base
.total
))
864 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
);
868 /* Do the allocations first so we can easily bail out */
869 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
872 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
876 /* For every page directory referenced, allocate page tables */
877 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
878 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
879 new_page_tables
[pdpe
]);
885 length
= orig_length
;
887 /* Allocations have completed successfully, so set the bitmaps, and do
889 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
890 gen8_pde_t
*const page_directory
= kmap_px(pd
);
891 struct i915_page_table
*pt
;
892 uint64_t pd_len
= gen8_clamp_pd(start
, length
);
893 uint64_t pd_start
= start
;
896 /* Every pd should be allocated, we just did that above. */
899 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
900 /* Same reasoning as pd */
903 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
905 /* Set our used ptes within the page table */
906 bitmap_set(pt
->used_ptes
,
907 gen8_pte_index(pd_start
),
908 gen8_pte_count(pd_start
, pd_len
));
910 /* Our pde is now pointing to the pagetable, pt */
911 set_bit(pde
, pd
->used_pdes
);
913 /* Map the PDE to the page table */
914 __gen8_do_map_pt(page_directory
+ pde
, pt
, vm
->dev
);
916 /* NB: We haven't yet mapped ptes to pages. At this
917 * point we're still relying on insert_entries() */
920 kunmap_px(ppgtt
, page_directory
);
922 set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
925 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
926 mark_tlbs_dirty(ppgtt
);
931 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
932 free_pt(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
]);
935 for_each_set_bit(pdpe
, new_page_dirs
, GEN8_LEGACY_PDPES
)
936 free_pd(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]);
938 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
939 mark_tlbs_dirty(ppgtt
);
944 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
945 * with a net effect resembling a 2-level page table in normal x86 terms. Each
946 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
950 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
952 ppgtt
->scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
953 if (IS_ERR(ppgtt
->scratch_pt
))
954 return PTR_ERR(ppgtt
->scratch_pt
);
956 ppgtt
->scratch_pd
= alloc_pd(ppgtt
->base
.dev
);
957 if (IS_ERR(ppgtt
->scratch_pd
))
958 return PTR_ERR(ppgtt
->scratch_pd
);
960 gen8_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
961 gen8_initialize_pd(&ppgtt
->base
, ppgtt
->scratch_pd
);
963 ppgtt
->base
.start
= 0;
964 ppgtt
->base
.total
= 1ULL << 32;
965 if (IS_ENABLED(CONFIG_X86_32
))
966 /* While we have a proliferation of size_t variables
967 * we cannot represent the full ppgtt size on 32bit,
968 * so limit it to the same size as the GGTT (currently
971 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
972 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
973 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
974 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
975 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
976 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
977 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
979 ppgtt
->switch_mm
= gen8_mm_switch
;
984 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
986 struct i915_address_space
*vm
= &ppgtt
->base
;
987 struct i915_page_table
*unused
;
988 gen6_pte_t scratch_pte
;
990 uint32_t pte
, pde
, temp
;
991 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
993 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
), I915_CACHE_LLC
, true, 0);
995 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
997 gen6_pte_t
*pt_vaddr
;
998 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
999 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1000 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1002 if (pd_entry
!= expected
)
1003 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1007 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1009 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1011 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1013 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1017 for (i
= 0; i
< 4; i
++)
1018 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1023 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1024 for (i
= 0; i
< 4; i
++) {
1025 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1026 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1028 seq_puts(m
, " SCRATCH ");
1032 kunmap_px(ppgtt
, pt_vaddr
);
1036 /* Write pde (index) from the page directory @pd to the page table @pt */
1037 static void gen6_write_pde(struct i915_page_directory
*pd
,
1038 const int pde
, struct i915_page_table
*pt
)
1040 /* Caller needs to make sure the write completes if necessary */
1041 struct i915_hw_ppgtt
*ppgtt
=
1042 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1045 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1046 pd_entry
|= GEN6_PDE_VALID
;
1048 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1051 /* Write all the page tables found in the ppgtt structure to incrementing page
1053 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1054 struct i915_page_directory
*pd
,
1055 uint32_t start
, uint32_t length
)
1057 struct i915_page_table
*pt
;
1060 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1061 gen6_write_pde(pd
, pde
, pt
);
1063 /* Make sure write is complete before other code can use this page
1064 * table. Also require for WC mapped PTEs */
1065 readl(dev_priv
->gtt
.gsm
);
1068 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1070 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1072 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1075 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1076 struct drm_i915_gem_request
*req
)
1078 struct intel_engine_cs
*ring
= req
->ring
;
1081 /* NB: TLBs must be flushed and invalidated before a switch */
1082 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1086 ret
= intel_ring_begin(req
, 6);
1090 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1091 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1092 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1093 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1094 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1095 intel_ring_emit(ring
, MI_NOOP
);
1096 intel_ring_advance(ring
);
1101 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1102 struct drm_i915_gem_request
*req
)
1104 struct intel_engine_cs
*ring
= req
->ring
;
1105 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1107 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1108 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1112 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1113 struct drm_i915_gem_request
*req
)
1115 struct intel_engine_cs
*ring
= req
->ring
;
1118 /* NB: TLBs must be flushed and invalidated before a switch */
1119 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1123 ret
= intel_ring_begin(req
, 6);
1127 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1128 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1129 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1130 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1131 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1132 intel_ring_emit(ring
, MI_NOOP
);
1133 intel_ring_advance(ring
);
1135 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1136 if (ring
->id
!= RCS
) {
1137 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1145 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1146 struct drm_i915_gem_request
*req
)
1148 struct intel_engine_cs
*ring
= req
->ring
;
1149 struct drm_device
*dev
= ppgtt
->base
.dev
;
1150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1153 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1154 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1156 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1161 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1164 struct intel_engine_cs
*ring
;
1167 for_each_ring(ring
, dev_priv
, j
) {
1168 I915_WRITE(RING_MODE_GEN7(ring
),
1169 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1173 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 struct intel_engine_cs
*ring
;
1177 uint32_t ecochk
, ecobits
;
1180 ecobits
= I915_READ(GAC_ECO_BITS
);
1181 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1183 ecochk
= I915_READ(GAM_ECOCHK
);
1184 if (IS_HASWELL(dev
)) {
1185 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1187 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1188 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1190 I915_WRITE(GAM_ECOCHK
, ecochk
);
1192 for_each_ring(ring
, dev_priv
, i
) {
1193 /* GFX_MODE is per-ring on gen7+ */
1194 I915_WRITE(RING_MODE_GEN7(ring
),
1195 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1199 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1202 uint32_t ecochk
, gab_ctl
, ecobits
;
1204 ecobits
= I915_READ(GAC_ECO_BITS
);
1205 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1206 ECOBITS_PPGTT_CACHE64B
);
1208 gab_ctl
= I915_READ(GAB_CTL
);
1209 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1211 ecochk
= I915_READ(GAM_ECOCHK
);
1212 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1214 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1217 /* PPGTT support for Sandybdrige/Gen6 and later */
1218 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1223 struct i915_hw_ppgtt
*ppgtt
=
1224 container_of(vm
, struct i915_hw_ppgtt
, base
);
1225 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1226 unsigned first_entry
= start
>> PAGE_SHIFT
;
1227 unsigned num_entries
= length
>> PAGE_SHIFT
;
1228 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1229 unsigned first_pte
= first_entry
% GEN6_PTES
;
1230 unsigned last_pte
, i
;
1232 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1233 I915_CACHE_LLC
, true, 0);
1235 while (num_entries
) {
1236 last_pte
= first_pte
+ num_entries
;
1237 if (last_pte
> GEN6_PTES
)
1238 last_pte
= GEN6_PTES
;
1240 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1242 for (i
= first_pte
; i
< last_pte
; i
++)
1243 pt_vaddr
[i
] = scratch_pte
;
1245 kunmap_px(ppgtt
, pt_vaddr
);
1247 num_entries
-= last_pte
- first_pte
;
1253 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1254 struct sg_table
*pages
,
1256 enum i915_cache_level cache_level
, u32 flags
)
1258 struct i915_hw_ppgtt
*ppgtt
=
1259 container_of(vm
, struct i915_hw_ppgtt
, base
);
1260 gen6_pte_t
*pt_vaddr
;
1261 unsigned first_entry
= start
>> PAGE_SHIFT
;
1262 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1263 unsigned act_pte
= first_entry
% GEN6_PTES
;
1264 struct sg_page_iter sg_iter
;
1267 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1268 if (pt_vaddr
== NULL
)
1269 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1272 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1273 cache_level
, true, flags
);
1275 if (++act_pte
== GEN6_PTES
) {
1276 kunmap_px(ppgtt
, pt_vaddr
);
1283 kunmap_px(ppgtt
, pt_vaddr
);
1286 static void gen6_initialize_pt(struct i915_address_space
*vm
,
1287 struct i915_page_table
*pt
)
1289 gen6_pte_t scratch_pte
;
1291 WARN_ON(px_dma(vm
->scratch_page
) == 0);
1293 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1294 I915_CACHE_LLC
, true, 0);
1296 fill32_px(vm
->dev
, pt
, scratch_pte
);
1299 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1300 uint64_t start_in
, uint64_t length_in
)
1302 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1303 struct drm_device
*dev
= vm
->dev
;
1304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1305 struct i915_hw_ppgtt
*ppgtt
=
1306 container_of(vm
, struct i915_hw_ppgtt
, base
);
1307 struct i915_page_table
*pt
;
1308 uint32_t start
, length
, start_save
, length_save
;
1312 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1315 start
= start_save
= start_in
;
1316 length
= length_save
= length_in
;
1318 bitmap_zero(new_page_tables
, I915_PDES
);
1320 /* The allocation is done in two stages so that we can bail out with
1321 * minimal amount of pain. The first stage finds new page tables that
1322 * need allocation. The second stage marks use ptes within the page
1325 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1326 if (pt
!= ppgtt
->scratch_pt
) {
1327 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1331 /* We've already allocated a page table */
1332 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1340 gen6_initialize_pt(vm
, pt
);
1342 ppgtt
->pd
.page_table
[pde
] = pt
;
1343 set_bit(pde
, new_page_tables
);
1344 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1348 length
= length_save
;
1350 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1351 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1353 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1354 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1355 gen6_pte_count(start
, length
));
1357 if (test_and_clear_bit(pde
, new_page_tables
))
1358 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1360 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1361 gen6_pte_index(start
),
1362 gen6_pte_count(start
, length
),
1364 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1368 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1370 /* Make sure write is complete before other code can use this page
1371 * table. Also require for WC mapped PTEs */
1372 readl(dev_priv
->gtt
.gsm
);
1374 mark_tlbs_dirty(ppgtt
);
1378 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1379 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1381 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1382 free_pt(vm
->dev
, pt
);
1385 mark_tlbs_dirty(ppgtt
);
1389 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1391 struct i915_hw_ppgtt
*ppgtt
=
1392 container_of(vm
, struct i915_hw_ppgtt
, base
);
1393 struct i915_page_table
*pt
;
1397 drm_mm_remove_node(&ppgtt
->node
);
1399 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1400 if (pt
!= ppgtt
->scratch_pt
)
1401 free_pt(ppgtt
->base
.dev
, pt
);
1404 free_pt(ppgtt
->base
.dev
, ppgtt
->scratch_pt
);
1407 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1409 struct drm_device
*dev
= ppgtt
->base
.dev
;
1410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1411 bool retried
= false;
1414 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1415 * allocator works in address space sizes, so it's multiplied by page
1416 * size. We allocate at the top of the GTT to avoid fragmentation.
1418 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1419 ppgtt
->scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
1420 if (IS_ERR(ppgtt
->scratch_pt
))
1421 return PTR_ERR(ppgtt
->scratch_pt
);
1423 gen6_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1426 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1427 &ppgtt
->node
, GEN6_PD_SIZE
,
1429 0, dev_priv
->gtt
.base
.total
,
1431 if (ret
== -ENOSPC
&& !retried
) {
1432 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1433 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1435 0, dev_priv
->gtt
.base
.total
,
1448 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1449 DRM_DEBUG("Forced to use aperture for PDEs\n");
1454 free_pt(ppgtt
->base
.dev
, ppgtt
->scratch_pt
);
1458 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1460 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1463 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1464 uint64_t start
, uint64_t length
)
1466 struct i915_page_table
*unused
;
1469 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1470 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1473 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1475 struct drm_device
*dev
= ppgtt
->base
.dev
;
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1479 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1481 ppgtt
->switch_mm
= gen6_mm_switch
;
1482 } else if (IS_HASWELL(dev
)) {
1483 ppgtt
->switch_mm
= hsw_mm_switch
;
1484 } else if (IS_GEN7(dev
)) {
1485 ppgtt
->switch_mm
= gen7_mm_switch
;
1489 if (intel_vgpu_active(dev
))
1490 ppgtt
->switch_mm
= vgpu_mm_switch
;
1492 ret
= gen6_ppgtt_alloc(ppgtt
);
1496 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1497 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1498 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1499 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1500 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1501 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1502 ppgtt
->base
.start
= 0;
1503 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1504 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1506 ppgtt
->pd
.base
.ggtt_offset
=
1507 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1509 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1510 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1512 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1514 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1516 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1517 ppgtt
->node
.size
>> 20,
1518 ppgtt
->node
.start
/ PAGE_SIZE
);
1520 DRM_DEBUG("Adding PPGTT at offset %x\n",
1521 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1526 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1530 ppgtt
->base
.dev
= dev
;
1531 ppgtt
->base
.scratch_page
= dev_priv
->gtt
.base
.scratch_page
;
1533 if (INTEL_INFO(dev
)->gen
< 8)
1534 return gen6_ppgtt_init(ppgtt
);
1536 return gen8_ppgtt_init(ppgtt
);
1539 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1544 ret
= __hw_ppgtt_init(dev
, ppgtt
);
1546 kref_init(&ppgtt
->ref
);
1547 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1549 i915_init_vm(dev_priv
, &ppgtt
->base
);
1555 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1557 /* In the case of execlists, PPGTT is enabled by the context descriptor
1558 * and the PDPs are contained within the context itself. We don't
1559 * need to do anything here. */
1560 if (i915
.enable_execlists
)
1563 if (!USES_PPGTT(dev
))
1567 gen6_ppgtt_enable(dev
);
1568 else if (IS_GEN7(dev
))
1569 gen7_ppgtt_enable(dev
);
1570 else if (INTEL_INFO(dev
)->gen
>= 8)
1571 gen8_ppgtt_enable(dev
);
1573 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1578 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1580 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1581 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1583 if (i915
.enable_execlists
)
1589 return ppgtt
->switch_mm(ppgtt
, req
);
1592 struct i915_hw_ppgtt
*
1593 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1595 struct i915_hw_ppgtt
*ppgtt
;
1598 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1600 return ERR_PTR(-ENOMEM
);
1602 ret
= i915_ppgtt_init(dev
, ppgtt
);
1605 return ERR_PTR(ret
);
1608 ppgtt
->file_priv
= fpriv
;
1610 trace_i915_ppgtt_create(&ppgtt
->base
);
1615 void i915_ppgtt_release(struct kref
*kref
)
1617 struct i915_hw_ppgtt
*ppgtt
=
1618 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1620 trace_i915_ppgtt_release(&ppgtt
->base
);
1622 /* vmas should already be unbound */
1623 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1624 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1626 list_del(&ppgtt
->base
.global_link
);
1627 drm_mm_takedown(&ppgtt
->base
.mm
);
1629 ppgtt
->base
.cleanup(&ppgtt
->base
);
1633 extern int intel_iommu_gfx_mapped
;
1634 /* Certain Gen5 chipsets require require idling the GPU before
1635 * unmapping anything from the GTT when VT-d is enabled.
1637 static bool needs_idle_maps(struct drm_device
*dev
)
1639 #ifdef CONFIG_INTEL_IOMMU
1640 /* Query intel_iommu to see if we need the workaround. Presumably that
1643 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1649 static bool do_idling(struct drm_i915_private
*dev_priv
)
1651 bool ret
= dev_priv
->mm
.interruptible
;
1653 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1654 dev_priv
->mm
.interruptible
= false;
1655 if (i915_gpu_idle(dev_priv
->dev
)) {
1656 DRM_ERROR("Couldn't idle GPU\n");
1657 /* Wait a bit, in hopes it avoids the hang */
1665 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1667 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1668 dev_priv
->mm
.interruptible
= interruptible
;
1671 void i915_check_and_clear_faults(struct drm_device
*dev
)
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 struct intel_engine_cs
*ring
;
1677 if (INTEL_INFO(dev
)->gen
< 6)
1680 for_each_ring(ring
, dev_priv
, i
) {
1682 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1683 if (fault_reg
& RING_FAULT_VALID
) {
1684 DRM_DEBUG_DRIVER("Unexpected fault\n"
1686 "\tAddress space: %s\n"
1689 fault_reg
& PAGE_MASK
,
1690 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1691 RING_FAULT_SRCID(fault_reg
),
1692 RING_FAULT_FAULT_TYPE(fault_reg
));
1693 I915_WRITE(RING_FAULT_REG(ring
),
1694 fault_reg
& ~RING_FAULT_VALID
);
1697 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1700 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1702 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1703 intel_gtt_chipset_flush();
1705 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1706 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1710 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1714 /* Don't bother messing with faults pre GEN6 as we have little
1715 * documentation supporting that it's a good idea.
1717 if (INTEL_INFO(dev
)->gen
< 6)
1720 i915_check_and_clear_faults(dev
);
1722 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1723 dev_priv
->gtt
.base
.start
,
1724 dev_priv
->gtt
.base
.total
,
1727 i915_ggtt_flush(dev_priv
);
1730 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1732 if (obj
->has_dma_mapping
)
1735 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1736 obj
->pages
->sgl
, obj
->pages
->nents
,
1737 PCI_DMA_BIDIRECTIONAL
))
1743 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1748 iowrite32((u32
)pte
, addr
);
1749 iowrite32(pte
>> 32, addr
+ 4);
1753 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1754 struct sg_table
*st
,
1756 enum i915_cache_level level
, u32 unused
)
1758 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1759 unsigned first_entry
= start
>> PAGE_SHIFT
;
1760 gen8_pte_t __iomem
*gtt_entries
=
1761 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1763 struct sg_page_iter sg_iter
;
1764 dma_addr_t addr
= 0; /* shut up gcc */
1766 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1767 addr
= sg_dma_address(sg_iter
.sg
) +
1768 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1769 gen8_set_pte(>t_entries
[i
],
1770 gen8_pte_encode(addr
, level
, true));
1775 * XXX: This serves as a posting read to make sure that the PTE has
1776 * actually been updated. There is some concern that even though
1777 * registers and PTEs are within the same BAR that they are potentially
1778 * of NUMA access patterns. Therefore, even with the way we assume
1779 * hardware should work, we must keep this posting read for paranoia.
1782 WARN_ON(readq(>t_entries
[i
-1])
1783 != gen8_pte_encode(addr
, level
, true));
1785 /* This next bit makes the above posting read even more important. We
1786 * want to flush the TLBs only after we're certain all the PTE updates
1789 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1790 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1794 * Binds an object into the global gtt with the specified cache level. The object
1795 * will be accessible to the GPU via commands whose operands reference offsets
1796 * within the global GTT as well as accessible by the GPU through the GMADR
1797 * mapped BAR (dev_priv->mm.gtt->gtt).
1799 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1800 struct sg_table
*st
,
1802 enum i915_cache_level level
, u32 flags
)
1804 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1805 unsigned first_entry
= start
>> PAGE_SHIFT
;
1806 gen6_pte_t __iomem
*gtt_entries
=
1807 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1809 struct sg_page_iter sg_iter
;
1810 dma_addr_t addr
= 0;
1812 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1813 addr
= sg_page_iter_dma_address(&sg_iter
);
1814 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1818 /* XXX: This serves as a posting read to make sure that the PTE has
1819 * actually been updated. There is some concern that even though
1820 * registers and PTEs are within the same BAR that they are potentially
1821 * of NUMA access patterns. Therefore, even with the way we assume
1822 * hardware should work, we must keep this posting read for paranoia.
1825 unsigned long gtt
= readl(>t_entries
[i
-1]);
1826 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1829 /* This next bit makes the above posting read even more important. We
1830 * want to flush the TLBs only after we're certain all the PTE updates
1833 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1834 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1837 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1842 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1843 unsigned first_entry
= start
>> PAGE_SHIFT
;
1844 unsigned num_entries
= length
>> PAGE_SHIFT
;
1845 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1846 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1847 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1850 if (WARN(num_entries
> max_entries
,
1851 "First entry = %d; Num entries = %d (max=%d)\n",
1852 first_entry
, num_entries
, max_entries
))
1853 num_entries
= max_entries
;
1855 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1858 for (i
= 0; i
< num_entries
; i
++)
1859 gen8_set_pte(>t_base
[i
], scratch_pte
);
1863 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1868 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1869 unsigned first_entry
= start
>> PAGE_SHIFT
;
1870 unsigned num_entries
= length
>> PAGE_SHIFT
;
1871 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1872 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1873 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1876 if (WARN(num_entries
> max_entries
,
1877 "First entry = %d; Num entries = %d (max=%d)\n",
1878 first_entry
, num_entries
, max_entries
))
1879 num_entries
= max_entries
;
1881 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1882 I915_CACHE_LLC
, use_scratch
, 0);
1884 for (i
= 0; i
< num_entries
; i
++)
1885 iowrite32(scratch_pte
, >t_base
[i
]);
1889 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
1890 struct sg_table
*pages
,
1892 enum i915_cache_level cache_level
, u32 unused
)
1894 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1895 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1897 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
1901 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1906 unsigned first_entry
= start
>> PAGE_SHIFT
;
1907 unsigned num_entries
= length
>> PAGE_SHIFT
;
1908 intel_gtt_clear_range(first_entry
, num_entries
);
1911 static int ggtt_bind_vma(struct i915_vma
*vma
,
1912 enum i915_cache_level cache_level
,
1915 struct drm_device
*dev
= vma
->vm
->dev
;
1916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1917 struct drm_i915_gem_object
*obj
= vma
->obj
;
1918 struct sg_table
*pages
= obj
->pages
;
1922 ret
= i915_get_ggtt_vma_pages(vma
);
1925 pages
= vma
->ggtt_view
.pages
;
1927 /* Currently applicable only to VLV */
1929 pte_flags
|= PTE_READ_ONLY
;
1932 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1933 vma
->vm
->insert_entries(vma
->vm
, pages
,
1935 cache_level
, pte_flags
);
1938 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
1939 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1940 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
1942 cache_level
, pte_flags
);
1948 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1950 struct drm_device
*dev
= vma
->vm
->dev
;
1951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1952 struct drm_i915_gem_object
*obj
= vma
->obj
;
1953 const uint64_t size
= min_t(uint64_t,
1957 if (vma
->bound
& GLOBAL_BIND
) {
1958 vma
->vm
->clear_range(vma
->vm
,
1964 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
1965 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1967 appgtt
->base
.clear_range(&appgtt
->base
,
1974 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1976 struct drm_device
*dev
= obj
->base
.dev
;
1977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1980 interruptible
= do_idling(dev_priv
);
1982 if (!obj
->has_dma_mapping
)
1983 dma_unmap_sg(&dev
->pdev
->dev
,
1984 obj
->pages
->sgl
, obj
->pages
->nents
,
1985 PCI_DMA_BIDIRECTIONAL
);
1987 undo_idling(dev_priv
, interruptible
);
1990 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1991 unsigned long color
,
1995 if (node
->color
!= color
)
1998 if (!list_empty(&node
->node_list
)) {
1999 node
= list_entry(node
->node_list
.next
,
2002 if (node
->allocated
&& node
->color
!= color
)
2007 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2008 unsigned long start
,
2009 unsigned long mappable_end
,
2012 /* Let GEM Manage all of the aperture.
2014 * However, leave one page at the end still bound to the scratch page.
2015 * There are a number of places where the hardware apparently prefetches
2016 * past the end of the object, and we've seen multiple hangs with the
2017 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2018 * aperture. One page should be enough to keep any prefetching inside
2021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2022 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2023 struct drm_mm_node
*entry
;
2024 struct drm_i915_gem_object
*obj
;
2025 unsigned long hole_start
, hole_end
;
2028 BUG_ON(mappable_end
> end
);
2030 /* Subtract the guard page ... */
2031 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2033 dev_priv
->gtt
.base
.start
= start
;
2034 dev_priv
->gtt
.base
.total
= end
- start
;
2036 if (intel_vgpu_active(dev
)) {
2037 ret
= intel_vgt_balloon(dev
);
2043 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2045 /* Mark any preallocated objects as occupied */
2046 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2047 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2049 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2050 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2052 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2053 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2055 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2058 vma
->bound
|= GLOBAL_BIND
;
2061 /* Clear any non-preallocated blocks */
2062 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2063 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2064 hole_start
, hole_end
);
2065 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2066 hole_end
- hole_start
, true);
2069 /* And finally clear the reserved guard page */
2070 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2072 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2073 struct i915_hw_ppgtt
*ppgtt
;
2075 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2079 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2081 ppgtt
->base
.cleanup(&ppgtt
->base
);
2086 if (ppgtt
->base
.allocate_va_range
)
2087 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2090 ppgtt
->base
.cleanup(&ppgtt
->base
);
2095 ppgtt
->base
.clear_range(&ppgtt
->base
,
2100 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2106 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2109 u64 gtt_size
, mappable_size
;
2111 gtt_size
= dev_priv
->gtt
.base
.total
;
2112 mappable_size
= dev_priv
->gtt
.mappable_end
;
2114 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2117 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2120 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2122 if (dev_priv
->mm
.aliasing_ppgtt
) {
2123 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2125 ppgtt
->base
.cleanup(&ppgtt
->base
);
2128 if (drm_mm_initialized(&vm
->mm
)) {
2129 if (intel_vgpu_active(dev
))
2130 intel_vgt_deballoon();
2132 drm_mm_takedown(&vm
->mm
);
2133 list_del(&vm
->global_link
);
2139 static int alloc_scratch_page(struct i915_address_space
*vm
)
2141 struct i915_page_scratch
*sp
;
2144 WARN_ON(vm
->scratch_page
);
2146 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
2150 ret
= __setup_page_dma(vm
->dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
2156 set_pages_uc(px_page(sp
), 1);
2158 vm
->scratch_page
= sp
;
2163 static void free_scratch_page(struct i915_address_space
*vm
)
2165 struct i915_page_scratch
*sp
= vm
->scratch_page
;
2167 set_pages_wb(px_page(sp
), 1);
2169 cleanup_px(vm
->dev
, sp
);
2172 vm
->scratch_page
= NULL
;
2175 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2177 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2178 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2179 return snb_gmch_ctl
<< 20;
2182 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2184 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2185 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2187 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2189 #ifdef CONFIG_X86_32
2190 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2191 if (bdw_gmch_ctl
> 4)
2195 return bdw_gmch_ctl
<< 20;
2198 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2200 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2201 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2204 return 1 << (20 + gmch_ctrl
);
2209 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2211 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2212 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2213 return snb_gmch_ctl
<< 25; /* 32 MB units */
2216 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2218 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2219 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2220 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2223 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2225 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2226 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2229 * 0x0 to 0x10: 32MB increments starting at 0MB
2230 * 0x11 to 0x16: 4MB increments starting at 8MB
2231 * 0x17 to 0x1d: 4MB increments start at 36MB
2233 if (gmch_ctrl
< 0x11)
2234 return gmch_ctrl
<< 25;
2235 else if (gmch_ctrl
< 0x17)
2236 return (gmch_ctrl
- 0x11 + 2) << 22;
2238 return (gmch_ctrl
- 0x17 + 9) << 22;
2241 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2243 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2244 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2246 if (gen9_gmch_ctl
< 0xf0)
2247 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2249 /* 4MB increments starting at 0xf0 for 4MB */
2250 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2253 static int ggtt_probe_common(struct drm_device
*dev
,
2256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2257 phys_addr_t gtt_phys_addr
;
2260 /* For Modern GENs the PTEs and register space are split in the BAR */
2261 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2262 (pci_resource_len(dev
->pdev
, 0) / 2);
2265 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2266 * dropped. For WC mappings in general we have 64 byte burst writes
2267 * when the WC buffer is flushed, so we can't use it, but have to
2268 * resort to an uncached mapping. The WC issue is easily caught by the
2269 * readback check when writing GTT PTE entries.
2271 if (IS_BROXTON(dev
))
2272 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2274 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2275 if (!dev_priv
->gtt
.gsm
) {
2276 DRM_ERROR("Failed to map the gtt page table\n");
2280 ret
= alloc_scratch_page(&dev_priv
->gtt
.base
);
2282 DRM_ERROR("Scratch setup failed\n");
2283 /* iounmap will also get called at remove, but meh */
2284 iounmap(dev_priv
->gtt
.gsm
);
2290 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2291 * bits. When using advanced contexts each context stores its own PAT, but
2292 * writing this data shouldn't be harmful even in those cases. */
2293 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2297 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2298 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2299 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2300 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2301 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2302 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2303 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2304 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2306 if (!USES_PPGTT(dev_priv
->dev
))
2307 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2308 * so RTL will always use the value corresponding to
2310 * So let's disable cache for GGTT to avoid screen corruptions.
2311 * MOCS still can be used though.
2312 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2313 * before this patch, i.e. the same uncached + snooping access
2314 * like on gen6/7 seems to be in effect.
2315 * - So this just fixes blitter/render access. Again it looks
2316 * like it's not just uncached access, but uncached + snooping.
2317 * So we can still hold onto all our assumptions wrt cpu
2318 * clflushing on LLC machines.
2320 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2322 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2323 * write would work. */
2324 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2325 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2328 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2333 * Map WB on BDW to snooped on CHV.
2335 * Only the snoop bit has meaning for CHV, the rest is
2338 * The hardware will never snoop for certain types of accesses:
2339 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2340 * - PPGTT page tables
2341 * - some other special cycles
2343 * As with BDW, we also need to consider the following for GT accesses:
2344 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2345 * so RTL will always use the value corresponding to
2347 * Which means we must set the snoop bit in PAT entry 0
2348 * in order to keep the global status page working.
2350 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2354 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2355 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2356 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2357 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2359 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2360 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2363 static int gen8_gmch_probe(struct drm_device
*dev
,
2366 phys_addr_t
*mappable_base
,
2369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2374 /* TODO: We're not aware of mappable constraints on gen8 yet */
2375 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2376 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2378 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2379 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2381 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2383 if (INTEL_INFO(dev
)->gen
>= 9) {
2384 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2385 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2386 } else if (IS_CHERRYVIEW(dev
)) {
2387 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2388 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2390 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2391 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2394 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2396 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2397 chv_setup_private_ppat(dev_priv
);
2399 bdw_setup_private_ppat(dev_priv
);
2401 ret
= ggtt_probe_common(dev
, gtt_size
);
2403 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2404 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2405 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2406 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2411 static int gen6_gmch_probe(struct drm_device
*dev
,
2414 phys_addr_t
*mappable_base
,
2417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 unsigned int gtt_size
;
2422 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2423 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2425 /* 64/512MB is the current min/max we actually know of, but this is just
2426 * a coarse sanity check.
2428 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2429 DRM_ERROR("Unknown GMADR size (%llx)\n",
2430 dev_priv
->gtt
.mappable_end
);
2434 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2435 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2436 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2438 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2440 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2441 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2443 ret
= ggtt_probe_common(dev
, gtt_size
);
2445 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2446 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2447 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2448 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2453 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2456 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2459 free_scratch_page(vm
);
2462 static int i915_gmch_probe(struct drm_device
*dev
,
2465 phys_addr_t
*mappable_base
,
2468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2473 DRM_ERROR("failed to set up gmch\n");
2477 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2479 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2480 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2481 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2482 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2483 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2485 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2486 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2491 static void i915_gmch_remove(struct i915_address_space
*vm
)
2493 intel_gmch_remove();
2496 int i915_gem_gtt_init(struct drm_device
*dev
)
2498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2499 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2502 if (INTEL_INFO(dev
)->gen
<= 5) {
2503 gtt
->gtt_probe
= i915_gmch_probe
;
2504 gtt
->base
.cleanup
= i915_gmch_remove
;
2505 } else if (INTEL_INFO(dev
)->gen
< 8) {
2506 gtt
->gtt_probe
= gen6_gmch_probe
;
2507 gtt
->base
.cleanup
= gen6_gmch_remove
;
2508 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2509 gtt
->base
.pte_encode
= iris_pte_encode
;
2510 else if (IS_HASWELL(dev
))
2511 gtt
->base
.pte_encode
= hsw_pte_encode
;
2512 else if (IS_VALLEYVIEW(dev
))
2513 gtt
->base
.pte_encode
= byt_pte_encode
;
2514 else if (INTEL_INFO(dev
)->gen
>= 7)
2515 gtt
->base
.pte_encode
= ivb_pte_encode
;
2517 gtt
->base
.pte_encode
= snb_pte_encode
;
2519 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2520 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2523 gtt
->base
.dev
= dev
;
2525 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2526 >t
->mappable_base
, >t
->mappable_end
);
2530 /* GMADR is the PCI mmio aperture into the global GTT. */
2531 DRM_INFO("Memory usable by graphics device = %lluM\n",
2532 gtt
->base
.total
>> 20);
2533 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
2534 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2535 #ifdef CONFIG_INTEL_IOMMU
2536 if (intel_iommu_gfx_mapped
)
2537 DRM_INFO("VT-d active for gfx access\n");
2540 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2541 * user's requested state against the hardware/driver capabilities. We
2542 * do this now so that we can print out any log messages once rather
2543 * than every time we check intel_enable_ppgtt().
2545 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2546 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2551 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2554 struct drm_i915_gem_object
*obj
;
2555 struct i915_address_space
*vm
;
2557 i915_check_and_clear_faults(dev
);
2559 /* First fill our portion of the GTT with scratch pages */
2560 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2561 dev_priv
->gtt
.base
.start
,
2562 dev_priv
->gtt
.base
.total
,
2565 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2566 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
2567 &dev_priv
->gtt
.base
);
2571 i915_gem_clflush_object(obj
, obj
->pin_display
);
2572 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, PIN_UPDATE
));
2576 if (INTEL_INFO(dev
)->gen
>= 8) {
2577 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2578 chv_setup_private_ppat(dev_priv
);
2580 bdw_setup_private_ppat(dev_priv
);
2585 if (USES_PPGTT(dev
)) {
2586 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2587 /* TODO: Perhaps it shouldn't be gen6 specific */
2589 struct i915_hw_ppgtt
*ppgtt
=
2590 container_of(vm
, struct i915_hw_ppgtt
,
2593 if (i915_is_ggtt(vm
))
2594 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2596 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2597 0, ppgtt
->base
.total
);
2601 i915_ggtt_flush(dev_priv
);
2604 static struct i915_vma
*
2605 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2606 struct i915_address_space
*vm
,
2607 const struct i915_ggtt_view
*ggtt_view
)
2609 struct i915_vma
*vma
;
2611 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2612 return ERR_PTR(-EINVAL
);
2614 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
2616 return ERR_PTR(-ENOMEM
);
2618 INIT_LIST_HEAD(&vma
->vma_link
);
2619 INIT_LIST_HEAD(&vma
->mm_list
);
2620 INIT_LIST_HEAD(&vma
->exec_list
);
2624 if (i915_is_ggtt(vm
))
2625 vma
->ggtt_view
= *ggtt_view
;
2627 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2628 if (!i915_is_ggtt(vm
))
2629 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2635 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2636 struct i915_address_space
*vm
)
2638 struct i915_vma
*vma
;
2640 vma
= i915_gem_obj_to_vma(obj
, vm
);
2642 vma
= __i915_gem_vma_create(obj
, vm
,
2643 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2649 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2650 const struct i915_ggtt_view
*view
)
2652 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2653 struct i915_vma
*vma
;
2656 return ERR_PTR(-EINVAL
);
2658 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2664 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2671 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2672 struct sg_table
*st
)
2674 unsigned int column
, row
;
2675 unsigned int src_idx
;
2676 struct scatterlist
*sg
= st
->sgl
;
2680 for (column
= 0; column
< width
; column
++) {
2681 src_idx
= width
* (height
- 1) + column
;
2682 for (row
= 0; row
< height
; row
++) {
2684 /* We don't need the pages, but need to initialize
2685 * the entries so the sg list can be happily traversed.
2686 * The only thing we need are DMA addresses.
2688 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2689 sg_dma_address(sg
) = in
[src_idx
];
2690 sg_dma_len(sg
) = PAGE_SIZE
;
2697 static struct sg_table
*
2698 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2699 struct drm_i915_gem_object
*obj
)
2701 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2702 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
2703 struct sg_page_iter sg_iter
;
2705 dma_addr_t
*page_addr_list
;
2706 struct sg_table
*st
;
2709 /* Allocate a temporary list of source pages for random access. */
2710 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
2711 sizeof(dma_addr_t
));
2712 if (!page_addr_list
)
2713 return ERR_PTR(ret
);
2715 /* Allocate target SG list. */
2716 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2720 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
2724 /* Populate source page list from the object. */
2726 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2727 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2731 /* Rotate the pages. */
2732 rotate_pages(page_addr_list
,
2733 rot_info
->width_pages
, rot_info
->height_pages
,
2737 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2738 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
2739 rot_info
->pixel_format
, rot_info
->width_pages
,
2740 rot_info
->height_pages
, size_pages
);
2742 drm_free_large(page_addr_list
);
2749 drm_free_large(page_addr_list
);
2752 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2753 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
2754 rot_info
->pixel_format
, rot_info
->width_pages
,
2755 rot_info
->height_pages
, size_pages
);
2756 return ERR_PTR(ret
);
2759 static struct sg_table
*
2760 intel_partial_pages(const struct i915_ggtt_view
*view
,
2761 struct drm_i915_gem_object
*obj
)
2763 struct sg_table
*st
;
2764 struct scatterlist
*sg
;
2765 struct sg_page_iter obj_sg_iter
;
2768 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2772 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2778 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2779 view
->params
.partial
.offset
)
2781 if (st
->nents
>= view
->params
.partial
.size
)
2784 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2785 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2786 sg_dma_len(sg
) = PAGE_SIZE
;
2797 return ERR_PTR(ret
);
2801 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2805 if (vma
->ggtt_view
.pages
)
2808 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2809 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2810 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2811 vma
->ggtt_view
.pages
=
2812 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2813 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2814 vma
->ggtt_view
.pages
=
2815 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2817 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2818 vma
->ggtt_view
.type
);
2820 if (!vma
->ggtt_view
.pages
) {
2821 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2822 vma
->ggtt_view
.type
);
2824 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2825 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2826 vma
->ggtt_view
.pages
= NULL
;
2827 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2828 vma
->ggtt_view
.type
, ret
);
2835 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2837 * @cache_level: mapping cache level
2838 * @flags: flags like global or local mapping
2840 * DMA addresses are taken from the scatter-gather table of this object (or of
2841 * this VMA in case of non-default GGTT views) and PTE entries set up.
2842 * Note that DMA addresses are also the only part of the SG table we care about.
2844 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2850 if (WARN_ON(flags
== 0))
2854 if (flags
& PIN_GLOBAL
)
2855 bind_flags
|= GLOBAL_BIND
;
2856 if (flags
& PIN_USER
)
2857 bind_flags
|= LOCAL_BIND
;
2859 if (flags
& PIN_UPDATE
)
2860 bind_flags
|= vma
->bound
;
2862 bind_flags
&= ~vma
->bound
;
2864 if (bind_flags
== 0)
2867 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
2868 trace_i915_va_alloc(vma
->vm
,
2871 VM_TO_TRACE_NAME(vma
->vm
));
2873 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
2880 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
2884 vma
->bound
|= bind_flags
;
2890 * i915_ggtt_view_size - Get the size of a GGTT view.
2891 * @obj: Object the view is of.
2892 * @view: The view in question.
2894 * @return The size of the GGTT view in bytes.
2897 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
2898 const struct i915_ggtt_view
*view
)
2900 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
2901 return obj
->base
.size
;
2902 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
2903 return view
->rotation_info
.size
;
2904 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
2905 return view
->params
.partial
.size
<< PAGE_SHIFT
;
2907 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
2908 return obj
->base
.size
;