2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
36 * DOC: Global GTT views
38 * Background and previous state
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
65 * Implementation and usage
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
70 * A new flavour of core GEM functions which work with GGTT bound objects were
71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
80 * Code wanting to add or use a new GGTT view needs to:
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
96 static inline struct i915_ggtt
*
97 i915_vm_to_ggtt(struct i915_address_space
*vm
)
99 GEM_BUG_ON(!i915_is_ggtt(vm
));
100 return container_of(vm
, struct i915_ggtt
, base
);
104 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
106 const struct i915_ggtt_view i915_ggtt_view_normal
= {
107 .type
= I915_GGTT_VIEW_NORMAL
,
109 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
110 .type
= I915_GGTT_VIEW_ROTATED
,
113 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
116 bool has_aliasing_ppgtt
;
118 bool has_full_48bit_ppgtt
;
120 has_aliasing_ppgtt
= INTEL_GEN(dev_priv
) >= 6;
121 has_full_ppgtt
= INTEL_GEN(dev_priv
) >= 7;
122 has_full_48bit_ppgtt
=
123 IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9;
125 if (intel_vgpu_active(dev_priv
))
126 has_full_ppgtt
= false; /* emulation is too hard */
128 if (!has_aliasing_ppgtt
)
132 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
133 * execlists, the sole mechanism available to submit work.
135 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
138 if (enable_ppgtt
== 1)
141 if (enable_ppgtt
== 2 && has_full_ppgtt
)
144 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
147 #ifdef CONFIG_INTEL_IOMMU
148 /* Disable ppgtt on SNB if VT-d is on. */
149 if (IS_GEN6(dev_priv
) && intel_iommu_gfx_mapped
) {
150 DRM_INFO("Disabling PPGTT because VT-d is on\n");
155 /* Early VLV doesn't have this */
156 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
157 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
161 if (INTEL_GEN(dev_priv
) >= 8 && i915
.enable_execlists
)
162 return has_full_48bit_ppgtt
? 3 : 2;
164 return has_aliasing_ppgtt
? 1 : 0;
167 static int ppgtt_bind_vma(struct i915_vma
*vma
,
168 enum i915_cache_level cache_level
,
173 /* Currently applicable only to VLV */
175 pte_flags
|= PTE_READ_ONLY
;
177 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
178 cache_level
, pte_flags
);
183 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
185 vma
->vm
->clear_range(vma
->vm
,
191 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
192 enum i915_cache_level level
,
195 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
199 case I915_CACHE_NONE
:
200 pte
|= PPAT_UNCACHED_INDEX
;
203 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
206 pte
|= PPAT_CACHED_INDEX
;
213 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
214 const enum i915_cache_level level
)
216 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
218 if (level
!= I915_CACHE_NONE
)
219 pde
|= PPAT_CACHED_PDE_INDEX
;
221 pde
|= PPAT_UNCACHED_INDEX
;
225 #define gen8_pdpe_encode gen8_pde_encode
226 #define gen8_pml4e_encode gen8_pde_encode
228 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
229 enum i915_cache_level level
,
230 bool valid
, u32 unused
)
232 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
233 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
236 case I915_CACHE_L3_LLC
:
238 pte
|= GEN6_PTE_CACHE_LLC
;
240 case I915_CACHE_NONE
:
241 pte
|= GEN6_PTE_UNCACHED
;
250 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
251 enum i915_cache_level level
,
252 bool valid
, u32 unused
)
254 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
255 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
258 case I915_CACHE_L3_LLC
:
259 pte
|= GEN7_PTE_CACHE_L3_LLC
;
262 pte
|= GEN6_PTE_CACHE_LLC
;
264 case I915_CACHE_NONE
:
265 pte
|= GEN6_PTE_UNCACHED
;
274 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
275 enum i915_cache_level level
,
276 bool valid
, u32 flags
)
278 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
279 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
281 if (!(flags
& PTE_READ_ONLY
))
282 pte
|= BYT_PTE_WRITEABLE
;
284 if (level
!= I915_CACHE_NONE
)
285 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
290 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
291 enum i915_cache_level level
,
292 bool valid
, u32 unused
)
294 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
295 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
297 if (level
!= I915_CACHE_NONE
)
298 pte
|= HSW_WB_LLC_AGE3
;
303 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
304 enum i915_cache_level level
,
305 bool valid
, u32 unused
)
307 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
308 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
311 case I915_CACHE_NONE
:
314 pte
|= HSW_WT_ELLC_LLC_AGE3
;
317 pte
|= HSW_WB_ELLC_LLC_AGE3
;
324 static int __setup_page_dma(struct drm_device
*dev
,
325 struct i915_page_dma
*p
, gfp_t flags
)
327 struct device
*device
= &dev
->pdev
->dev
;
329 p
->page
= alloc_page(flags
);
333 p
->daddr
= dma_map_page(device
,
334 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
336 if (dma_mapping_error(device
, p
->daddr
)) {
337 __free_page(p
->page
);
344 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
346 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
349 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
351 if (WARN_ON(!p
->page
))
354 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
355 __free_page(p
->page
);
356 memset(p
, 0, sizeof(*p
));
359 static void *kmap_page_dma(struct i915_page_dma
*p
)
361 return kmap_atomic(p
->page
);
364 /* We use the flushing unmap only with ppgtt structures:
365 * page directories, page tables and scratch pages.
367 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
369 /* There are only few exceptions for gen >=6. chv and bxt.
370 * And we are not sure about the latter so play safe for now.
372 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
373 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
375 kunmap_atomic(vaddr
);
378 #define kmap_px(px) kmap_page_dma(px_base(px))
379 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
381 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
382 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
383 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
384 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
386 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
390 uint64_t * const vaddr
= kmap_page_dma(p
);
392 for (i
= 0; i
< 512; i
++)
395 kunmap_page_dma(dev
, vaddr
);
398 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
399 const uint32_t val32
)
405 fill_page_dma(dev
, p
, v
);
408 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
410 struct i915_page_scratch
*sp
;
413 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
415 return ERR_PTR(-ENOMEM
);
417 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
423 set_pages_uc(px_page(sp
), 1);
428 static void free_scratch_page(struct drm_device
*dev
,
429 struct i915_page_scratch
*sp
)
431 set_pages_wb(px_page(sp
), 1);
437 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
439 struct i915_page_table
*pt
;
440 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
441 GEN8_PTES
: GEN6_PTES
;
444 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
446 return ERR_PTR(-ENOMEM
);
448 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
454 ret
= setup_px(dev
, pt
);
461 kfree(pt
->used_ptes
);
468 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
471 kfree(pt
->used_ptes
);
475 static void gen8_initialize_pt(struct i915_address_space
*vm
,
476 struct i915_page_table
*pt
)
478 gen8_pte_t scratch_pte
;
480 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
481 I915_CACHE_LLC
, true);
483 fill_px(vm
->dev
, pt
, scratch_pte
);
486 static void gen6_initialize_pt(struct i915_address_space
*vm
,
487 struct i915_page_table
*pt
)
489 gen6_pte_t scratch_pte
;
491 WARN_ON(px_dma(vm
->scratch_page
) == 0);
493 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
494 I915_CACHE_LLC
, true, 0);
496 fill32_px(vm
->dev
, pt
, scratch_pte
);
499 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
501 struct i915_page_directory
*pd
;
504 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
506 return ERR_PTR(-ENOMEM
);
508 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
509 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
513 ret
= setup_px(dev
, pd
);
520 kfree(pd
->used_pdes
);
527 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
531 kfree(pd
->used_pdes
);
536 static void gen8_initialize_pd(struct i915_address_space
*vm
,
537 struct i915_page_directory
*pd
)
539 gen8_pde_t scratch_pde
;
541 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
543 fill_px(vm
->dev
, pd
, scratch_pde
);
546 static int __pdp_init(struct drm_device
*dev
,
547 struct i915_page_directory_pointer
*pdp
)
549 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
551 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
552 sizeof(unsigned long),
554 if (!pdp
->used_pdpes
)
557 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
559 if (!pdp
->page_directory
) {
560 kfree(pdp
->used_pdpes
);
561 /* the PDP might be the statically allocated top level. Keep it
562 * as clean as possible */
563 pdp
->used_pdpes
= NULL
;
570 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
572 kfree(pdp
->used_pdpes
);
573 kfree(pdp
->page_directory
);
574 pdp
->page_directory
= NULL
;
578 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
580 struct i915_page_directory_pointer
*pdp
;
583 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
585 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
587 return ERR_PTR(-ENOMEM
);
589 ret
= __pdp_init(dev
, pdp
);
593 ret
= setup_px(dev
, pdp
);
607 static void free_pdp(struct drm_device
*dev
,
608 struct i915_page_directory_pointer
*pdp
)
611 if (USES_FULL_48BIT_PPGTT(dev
)) {
612 cleanup_px(dev
, pdp
);
617 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
618 struct i915_page_directory_pointer
*pdp
)
620 gen8_ppgtt_pdpe_t scratch_pdpe
;
622 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
624 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
627 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
628 struct i915_pml4
*pml4
)
630 gen8_ppgtt_pml4e_t scratch_pml4e
;
632 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
635 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
639 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
640 struct i915_page_directory_pointer
*pdp
,
641 struct i915_page_directory
*pd
,
644 gen8_ppgtt_pdpe_t
*page_directorypo
;
646 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
649 page_directorypo
= kmap_px(pdp
);
650 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
651 kunmap_px(ppgtt
, page_directorypo
);
655 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
656 struct i915_pml4
*pml4
,
657 struct i915_page_directory_pointer
*pdp
,
660 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
662 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
663 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
664 kunmap_px(ppgtt
, pagemap
);
667 /* Broadwell Page Directory Pointer Descriptors */
668 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
672 struct intel_ring
*ring
= req
->ring
;
673 struct intel_engine_cs
*engine
= req
->engine
;
678 ret
= intel_ring_begin(req
, 6);
682 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
683 intel_ring_emit_reg(ring
, GEN8_RING_PDP_UDW(engine
, entry
));
684 intel_ring_emit(ring
, upper_32_bits(addr
));
685 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
686 intel_ring_emit_reg(ring
, GEN8_RING_PDP_LDW(engine
, entry
));
687 intel_ring_emit(ring
, lower_32_bits(addr
));
688 intel_ring_advance(ring
);
693 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
694 struct drm_i915_gem_request
*req
)
698 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
699 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
701 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
709 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
710 struct drm_i915_gem_request
*req
)
712 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
715 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
716 struct i915_page_directory_pointer
*pdp
,
719 gen8_pte_t scratch_pte
)
721 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
722 gen8_pte_t
*pt_vaddr
;
723 unsigned pdpe
= gen8_pdpe_index(start
);
724 unsigned pde
= gen8_pde_index(start
);
725 unsigned pte
= gen8_pte_index(start
);
726 unsigned num_entries
= length
>> PAGE_SHIFT
;
727 unsigned last_pte
, i
;
732 while (num_entries
) {
733 struct i915_page_directory
*pd
;
734 struct i915_page_table
*pt
;
736 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
739 pd
= pdp
->page_directory
[pdpe
];
741 if (WARN_ON(!pd
->page_table
[pde
]))
744 pt
= pd
->page_table
[pde
];
746 if (WARN_ON(!px_page(pt
)))
749 last_pte
= pte
+ num_entries
;
750 if (last_pte
> GEN8_PTES
)
751 last_pte
= GEN8_PTES
;
753 pt_vaddr
= kmap_px(pt
);
755 for (i
= pte
; i
< last_pte
; i
++) {
756 pt_vaddr
[i
] = scratch_pte
;
760 kunmap_px(ppgtt
, pt_vaddr
);
763 if (++pde
== I915_PDES
) {
764 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
771 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
776 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
777 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
778 I915_CACHE_LLC
, use_scratch
);
780 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
781 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
785 struct i915_page_directory_pointer
*pdp
;
787 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
788 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
795 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
796 struct i915_page_directory_pointer
*pdp
,
797 struct sg_page_iter
*sg_iter
,
799 enum i915_cache_level cache_level
)
801 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
802 gen8_pte_t
*pt_vaddr
;
803 unsigned pdpe
= gen8_pdpe_index(start
);
804 unsigned pde
= gen8_pde_index(start
);
805 unsigned pte
= gen8_pte_index(start
);
809 while (__sg_page_iter_next(sg_iter
)) {
810 if (pt_vaddr
== NULL
) {
811 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
812 struct i915_page_table
*pt
= pd
->page_table
[pde
];
813 pt_vaddr
= kmap_px(pt
);
817 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
819 if (++pte
== GEN8_PTES
) {
820 kunmap_px(ppgtt
, pt_vaddr
);
822 if (++pde
== I915_PDES
) {
823 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
832 kunmap_px(ppgtt
, pt_vaddr
);
835 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
836 struct sg_table
*pages
,
838 enum i915_cache_level cache_level
,
841 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
842 struct sg_page_iter sg_iter
;
844 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
846 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
847 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
850 struct i915_page_directory_pointer
*pdp
;
852 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
854 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
855 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
861 static void gen8_free_page_tables(struct drm_device
*dev
,
862 struct i915_page_directory
*pd
)
869 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
870 if (WARN_ON(!pd
->page_table
[i
]))
873 free_pt(dev
, pd
->page_table
[i
]);
874 pd
->page_table
[i
] = NULL
;
878 static int gen8_init_scratch(struct i915_address_space
*vm
)
880 struct drm_device
*dev
= vm
->dev
;
883 vm
->scratch_page
= alloc_scratch_page(dev
);
884 if (IS_ERR(vm
->scratch_page
))
885 return PTR_ERR(vm
->scratch_page
);
887 vm
->scratch_pt
= alloc_pt(dev
);
888 if (IS_ERR(vm
->scratch_pt
)) {
889 ret
= PTR_ERR(vm
->scratch_pt
);
890 goto free_scratch_page
;
893 vm
->scratch_pd
= alloc_pd(dev
);
894 if (IS_ERR(vm
->scratch_pd
)) {
895 ret
= PTR_ERR(vm
->scratch_pd
);
899 if (USES_FULL_48BIT_PPGTT(dev
)) {
900 vm
->scratch_pdp
= alloc_pdp(dev
);
901 if (IS_ERR(vm
->scratch_pdp
)) {
902 ret
= PTR_ERR(vm
->scratch_pdp
);
907 gen8_initialize_pt(vm
, vm
->scratch_pt
);
908 gen8_initialize_pd(vm
, vm
->scratch_pd
);
909 if (USES_FULL_48BIT_PPGTT(dev
))
910 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
915 free_pd(dev
, vm
->scratch_pd
);
917 free_pt(dev
, vm
->scratch_pt
);
919 free_scratch_page(dev
, vm
->scratch_page
);
924 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
926 enum vgt_g2v_type msg
;
927 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
930 if (USES_FULL_48BIT_PPGTT(dev_priv
)) {
931 u64 daddr
= px_dma(&ppgtt
->pml4
);
933 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
934 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
936 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
937 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
939 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
940 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
942 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
943 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
946 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
947 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
950 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
955 static void gen8_free_scratch(struct i915_address_space
*vm
)
957 struct drm_device
*dev
= vm
->dev
;
959 if (USES_FULL_48BIT_PPGTT(dev
))
960 free_pdp(dev
, vm
->scratch_pdp
);
961 free_pd(dev
, vm
->scratch_pd
);
962 free_pt(dev
, vm
->scratch_pt
);
963 free_scratch_page(dev
, vm
->scratch_page
);
966 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
967 struct i915_page_directory_pointer
*pdp
)
971 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
972 if (WARN_ON(!pdp
->page_directory
[i
]))
975 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
976 free_pd(dev
, pdp
->page_directory
[i
]);
982 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
986 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
987 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
990 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
993 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
996 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
998 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1000 if (intel_vgpu_active(to_i915(vm
->dev
)))
1001 gen8_ppgtt_notify_vgt(ppgtt
, false);
1003 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
1004 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1006 gen8_ppgtt_cleanup_4lvl(ppgtt
);
1008 gen8_free_scratch(vm
);
1012 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1013 * @vm: Master vm structure.
1014 * @pd: Page directory for this address range.
1015 * @start: Starting virtual address to begin allocations.
1016 * @length: Size of the allocations.
1017 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1018 * caller to free on error.
1020 * Allocate the required number of page tables. Extremely similar to
1021 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1022 * the page directory boundary (instead of the page directory pointer). That
1023 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1024 * possible, and likely that the caller will need to use multiple calls of this
1025 * function to achieve the appropriate allocation.
1027 * Return: 0 if success; negative error code otherwise.
1029 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1030 struct i915_page_directory
*pd
,
1033 unsigned long *new_pts
)
1035 struct drm_device
*dev
= vm
->dev
;
1036 struct i915_page_table
*pt
;
1039 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1040 /* Don't reallocate page tables */
1041 if (test_bit(pde
, pd
->used_pdes
)) {
1042 /* Scratch is never allocated this way */
1043 WARN_ON(pt
== vm
->scratch_pt
);
1051 gen8_initialize_pt(vm
, pt
);
1052 pd
->page_table
[pde
] = pt
;
1053 __set_bit(pde
, new_pts
);
1054 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1060 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1061 free_pt(dev
, pd
->page_table
[pde
]);
1067 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1068 * @vm: Master vm structure.
1069 * @pdp: Page directory pointer for this address range.
1070 * @start: Starting virtual address to begin allocations.
1071 * @length: Size of the allocations.
1072 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1073 * caller to free on error.
1075 * Allocate the required number of page directories starting at the pde index of
1076 * @start, and ending at the pde index @start + @length. This function will skip
1077 * over already allocated page directories within the range, and only allocate
1078 * new ones, setting the appropriate pointer within the pdp as well as the
1079 * correct position in the bitmap @new_pds.
1081 * The function will only allocate the pages within the range for a give page
1082 * directory pointer. In other words, if @start + @length straddles a virtually
1083 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1084 * required by the caller, This is not currently possible, and the BUG in the
1085 * code will prevent it.
1087 * Return: 0 if success; negative error code otherwise.
1090 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1091 struct i915_page_directory_pointer
*pdp
,
1094 unsigned long *new_pds
)
1096 struct drm_device
*dev
= vm
->dev
;
1097 struct i915_page_directory
*pd
;
1099 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1101 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1103 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1104 if (test_bit(pdpe
, pdp
->used_pdpes
))
1111 gen8_initialize_pd(vm
, pd
);
1112 pdp
->page_directory
[pdpe
] = pd
;
1113 __set_bit(pdpe
, new_pds
);
1114 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1120 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1121 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1127 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1128 * @vm: Master vm structure.
1129 * @pml4: Page map level 4 for this address range.
1130 * @start: Starting virtual address to begin allocations.
1131 * @length: Size of the allocations.
1132 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1133 * caller to free on error.
1135 * Allocate the required number of page directory pointers. Extremely similar to
1136 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1137 * The main difference is here we are limited by the pml4 boundary (instead of
1138 * the page directory pointer).
1140 * Return: 0 if success; negative error code otherwise.
1143 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1144 struct i915_pml4
*pml4
,
1147 unsigned long *new_pdps
)
1149 struct drm_device
*dev
= vm
->dev
;
1150 struct i915_page_directory_pointer
*pdp
;
1153 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1155 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1156 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1157 pdp
= alloc_pdp(dev
);
1161 gen8_initialize_pdp(vm
, pdp
);
1162 pml4
->pdps
[pml4e
] = pdp
;
1163 __set_bit(pml4e
, new_pdps
);
1164 trace_i915_page_directory_pointer_entry_alloc(vm
,
1174 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1175 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1181 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1187 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1188 * of these are based on the number of PDPEs in the system.
1191 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1192 unsigned long **new_pts
,
1198 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1202 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1213 free_gen8_temp_bitmaps(pds
, pts
);
1217 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1218 * the page table structures, we mark them dirty so that
1219 * context switching/execlist queuing code takes extra steps
1220 * to ensure that tlbs are flushed.
1222 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1224 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1227 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1228 struct i915_page_directory_pointer
*pdp
,
1232 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1233 unsigned long *new_page_dirs
, *new_page_tables
;
1234 struct drm_device
*dev
= vm
->dev
;
1235 struct i915_page_directory
*pd
;
1236 const uint64_t orig_start
= start
;
1237 const uint64_t orig_length
= length
;
1239 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1242 /* Wrap is never okay since we can only represent 48b, and we don't
1243 * actually use the other side of the canonical address space.
1245 if (WARN_ON(start
+ length
< start
))
1248 if (WARN_ON(start
+ length
> vm
->total
))
1251 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1255 /* Do the allocations first so we can easily bail out */
1256 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1259 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1263 /* For every page directory referenced, allocate page tables */
1264 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1265 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1266 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1272 length
= orig_length
;
1274 /* Allocations have completed successfully, so set the bitmaps, and do
1276 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1277 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1278 struct i915_page_table
*pt
;
1279 uint64_t pd_len
= length
;
1280 uint64_t pd_start
= start
;
1283 /* Every pd should be allocated, we just did that above. */
1286 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1287 /* Same reasoning as pd */
1290 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1292 /* Set our used ptes within the page table */
1293 bitmap_set(pt
->used_ptes
,
1294 gen8_pte_index(pd_start
),
1295 gen8_pte_count(pd_start
, pd_len
));
1297 /* Our pde is now pointing to the pagetable, pt */
1298 __set_bit(pde
, pd
->used_pdes
);
1300 /* Map the PDE to the page table */
1301 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1303 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1304 gen8_pte_index(start
),
1305 gen8_pte_count(start
, length
),
1308 /* NB: We haven't yet mapped ptes to pages. At this
1309 * point we're still relying on insert_entries() */
1312 kunmap_px(ppgtt
, page_directory
);
1313 __set_bit(pdpe
, pdp
->used_pdpes
);
1314 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1317 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1318 mark_tlbs_dirty(ppgtt
);
1325 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1326 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1327 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1330 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1331 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1333 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1334 mark_tlbs_dirty(ppgtt
);
1338 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1339 struct i915_pml4
*pml4
,
1343 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1344 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1345 struct i915_page_directory_pointer
*pdp
;
1349 /* Do the pml4 allocations first, so we don't need to track the newly
1350 * allocated tables below the pdp */
1351 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1353 /* The pagedirectory and pagetable allocations are done in the shared 3
1354 * and 4 level code. Just allocate the pdps.
1356 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1361 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1362 "The allocation has spanned more than 512GB. "
1363 "It is highly likely this is incorrect.");
1365 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1368 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1372 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1375 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1376 GEN8_PML4ES_PER_PML4
);
1381 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1382 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1387 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1388 uint64_t start
, uint64_t length
)
1390 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1392 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1393 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1395 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1398 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1399 uint64_t start
, uint64_t length
,
1400 gen8_pte_t scratch_pte
,
1403 struct i915_page_directory
*pd
;
1406 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1407 struct i915_page_table
*pt
;
1408 uint64_t pd_len
= length
;
1409 uint64_t pd_start
= start
;
1412 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1415 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1416 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1418 gen8_pte_t
*pt_vaddr
;
1420 if (!test_bit(pde
, pd
->used_pdes
))
1423 pt_vaddr
= kmap_px(pt
);
1424 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1426 (pdpe
<< GEN8_PDPE_SHIFT
) |
1427 (pde
<< GEN8_PDE_SHIFT
) |
1428 (pte
<< GEN8_PTE_SHIFT
);
1432 for (i
= 0; i
< 4; i
++)
1433 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1438 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1439 for (i
= 0; i
< 4; i
++) {
1440 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1441 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1443 seq_puts(m
, " SCRATCH ");
1447 /* don't use kunmap_px, it could trigger
1448 * an unnecessary flush.
1450 kunmap_atomic(pt_vaddr
);
1455 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1457 struct i915_address_space
*vm
= &ppgtt
->base
;
1458 uint64_t start
= ppgtt
->base
.start
;
1459 uint64_t length
= ppgtt
->base
.total
;
1460 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1461 I915_CACHE_LLC
, true);
1463 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1464 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1467 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1468 struct i915_page_directory_pointer
*pdp
;
1470 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1471 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1474 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1475 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1480 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1482 unsigned long *new_page_dirs
, *new_page_tables
;
1483 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1486 /* We allocate temp bitmap for page tables for no gain
1487 * but as this is for init only, lets keep the things simple
1489 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1493 /* Allocate for all pdps regardless of how the ppgtt
1496 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1500 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1502 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1508 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1509 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1510 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1514 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1518 ret
= gen8_init_scratch(&ppgtt
->base
);
1522 ppgtt
->base
.start
= 0;
1523 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1524 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1525 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1526 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1527 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1528 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1529 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1531 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1532 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1536 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1538 ppgtt
->base
.total
= 1ULL << 48;
1539 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1541 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1545 ppgtt
->base
.total
= 1ULL << 32;
1546 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1547 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1551 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
))) {
1552 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1558 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
)))
1559 gen8_ppgtt_notify_vgt(ppgtt
, true);
1564 gen8_free_scratch(&ppgtt
->base
);
1568 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1570 struct i915_address_space
*vm
= &ppgtt
->base
;
1571 struct i915_page_table
*unused
;
1572 gen6_pte_t scratch_pte
;
1575 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1577 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1578 I915_CACHE_LLC
, true, 0);
1580 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1582 gen6_pte_t
*pt_vaddr
;
1583 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1584 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1585 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1587 if (pd_entry
!= expected
)
1588 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1592 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1594 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1596 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1598 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1602 for (i
= 0; i
< 4; i
++)
1603 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1608 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1609 for (i
= 0; i
< 4; i
++) {
1610 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1611 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1613 seq_puts(m
, " SCRATCH ");
1617 kunmap_px(ppgtt
, pt_vaddr
);
1621 /* Write pde (index) from the page directory @pd to the page table @pt */
1622 static void gen6_write_pde(struct i915_page_directory
*pd
,
1623 const int pde
, struct i915_page_table
*pt
)
1625 /* Caller needs to make sure the write completes if necessary */
1626 struct i915_hw_ppgtt
*ppgtt
=
1627 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1630 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1631 pd_entry
|= GEN6_PDE_VALID
;
1633 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1636 /* Write all the page tables found in the ppgtt structure to incrementing page
1638 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1639 struct i915_page_directory
*pd
,
1640 uint32_t start
, uint32_t length
)
1642 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1643 struct i915_page_table
*pt
;
1646 gen6_for_each_pde(pt
, pd
, start
, length
, pde
)
1647 gen6_write_pde(pd
, pde
, pt
);
1649 /* Make sure write is complete before other code can use this page
1650 * table. Also require for WC mapped PTEs */
1654 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1656 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1658 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1661 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1662 struct drm_i915_gem_request
*req
)
1664 struct intel_ring
*ring
= req
->ring
;
1665 struct intel_engine_cs
*engine
= req
->engine
;
1668 /* NB: TLBs must be flushed and invalidated before a switch */
1669 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1673 ret
= intel_ring_begin(req
, 6);
1677 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1678 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(engine
));
1679 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1680 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(engine
));
1681 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1682 intel_ring_emit(ring
, MI_NOOP
);
1683 intel_ring_advance(ring
);
1688 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1689 struct drm_i915_gem_request
*req
)
1691 struct intel_ring
*ring
= req
->ring
;
1692 struct intel_engine_cs
*engine
= req
->engine
;
1695 /* NB: TLBs must be flushed and invalidated before a switch */
1696 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1700 ret
= intel_ring_begin(req
, 6);
1704 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1705 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(engine
));
1706 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1707 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(engine
));
1708 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1709 intel_ring_emit(ring
, MI_NOOP
);
1710 intel_ring_advance(ring
);
1712 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1713 if (engine
->id
!= RCS
) {
1714 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1722 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1723 struct drm_i915_gem_request
*req
)
1725 struct intel_engine_cs
*engine
= req
->engine
;
1726 struct drm_i915_private
*dev_priv
= req
->i915
;
1728 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1729 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1733 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1735 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1736 struct intel_engine_cs
*engine
;
1738 for_each_engine(engine
, dev_priv
) {
1739 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1740 I915_WRITE(RING_MODE_GEN7(engine
),
1741 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1745 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1747 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1748 struct intel_engine_cs
*engine
;
1749 uint32_t ecochk
, ecobits
;
1751 ecobits
= I915_READ(GAC_ECO_BITS
);
1752 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1754 ecochk
= I915_READ(GAM_ECOCHK
);
1755 if (IS_HASWELL(dev
)) {
1756 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1758 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1759 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1761 I915_WRITE(GAM_ECOCHK
, ecochk
);
1763 for_each_engine(engine
, dev_priv
) {
1764 /* GFX_MODE is per-ring on gen7+ */
1765 I915_WRITE(RING_MODE_GEN7(engine
),
1766 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1770 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1772 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1773 uint32_t ecochk
, gab_ctl
, ecobits
;
1775 ecobits
= I915_READ(GAC_ECO_BITS
);
1776 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1777 ECOBITS_PPGTT_CACHE64B
);
1779 gab_ctl
= I915_READ(GAB_CTL
);
1780 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1782 ecochk
= I915_READ(GAM_ECOCHK
);
1783 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1785 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1788 /* PPGTT support for Sandybdrige/Gen6 and later */
1789 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1794 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1795 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1796 unsigned first_entry
= start
>> PAGE_SHIFT
;
1797 unsigned num_entries
= length
>> PAGE_SHIFT
;
1798 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1799 unsigned first_pte
= first_entry
% GEN6_PTES
;
1800 unsigned last_pte
, i
;
1802 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1803 I915_CACHE_LLC
, true, 0);
1805 while (num_entries
) {
1806 last_pte
= first_pte
+ num_entries
;
1807 if (last_pte
> GEN6_PTES
)
1808 last_pte
= GEN6_PTES
;
1810 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1812 for (i
= first_pte
; i
< last_pte
; i
++)
1813 pt_vaddr
[i
] = scratch_pte
;
1815 kunmap_px(ppgtt
, pt_vaddr
);
1817 num_entries
-= last_pte
- first_pte
;
1823 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1824 struct sg_table
*pages
,
1826 enum i915_cache_level cache_level
, u32 flags
)
1828 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1829 unsigned first_entry
= start
>> PAGE_SHIFT
;
1830 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1831 unsigned act_pte
= first_entry
% GEN6_PTES
;
1832 gen6_pte_t
*pt_vaddr
= NULL
;
1833 struct sgt_iter sgt_iter
;
1836 for_each_sgt_dma(addr
, sgt_iter
, pages
) {
1837 if (pt_vaddr
== NULL
)
1838 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1841 vm
->pte_encode(addr
, cache_level
, true, flags
);
1843 if (++act_pte
== GEN6_PTES
) {
1844 kunmap_px(ppgtt
, pt_vaddr
);
1852 kunmap_px(ppgtt
, pt_vaddr
);
1855 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1856 uint64_t start_in
, uint64_t length_in
)
1858 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1859 struct drm_device
*dev
= vm
->dev
;
1860 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1861 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1862 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1863 struct i915_page_table
*pt
;
1864 uint32_t start
, length
, start_save
, length_save
;
1868 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1871 start
= start_save
= start_in
;
1872 length
= length_save
= length_in
;
1874 bitmap_zero(new_page_tables
, I915_PDES
);
1876 /* The allocation is done in two stages so that we can bail out with
1877 * minimal amount of pain. The first stage finds new page tables that
1878 * need allocation. The second stage marks use ptes within the page
1881 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1882 if (pt
!= vm
->scratch_pt
) {
1883 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1887 /* We've already allocated a page table */
1888 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1896 gen6_initialize_pt(vm
, pt
);
1898 ppgtt
->pd
.page_table
[pde
] = pt
;
1899 __set_bit(pde
, new_page_tables
);
1900 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1904 length
= length_save
;
1906 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1907 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1909 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1910 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1911 gen6_pte_count(start
, length
));
1913 if (__test_and_clear_bit(pde
, new_page_tables
))
1914 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1916 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1917 gen6_pte_index(start
),
1918 gen6_pte_count(start
, length
),
1920 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1924 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1926 /* Make sure write is complete before other code can use this page
1927 * table. Also require for WC mapped PTEs */
1930 mark_tlbs_dirty(ppgtt
);
1934 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1935 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1937 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1938 free_pt(vm
->dev
, pt
);
1941 mark_tlbs_dirty(ppgtt
);
1945 static int gen6_init_scratch(struct i915_address_space
*vm
)
1947 struct drm_device
*dev
= vm
->dev
;
1949 vm
->scratch_page
= alloc_scratch_page(dev
);
1950 if (IS_ERR(vm
->scratch_page
))
1951 return PTR_ERR(vm
->scratch_page
);
1953 vm
->scratch_pt
= alloc_pt(dev
);
1954 if (IS_ERR(vm
->scratch_pt
)) {
1955 free_scratch_page(dev
, vm
->scratch_page
);
1956 return PTR_ERR(vm
->scratch_pt
);
1959 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1964 static void gen6_free_scratch(struct i915_address_space
*vm
)
1966 struct drm_device
*dev
= vm
->dev
;
1968 free_pt(dev
, vm
->scratch_pt
);
1969 free_scratch_page(dev
, vm
->scratch_page
);
1972 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1974 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1975 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1976 struct drm_device
*dev
= vm
->dev
;
1977 struct i915_page_table
*pt
;
1980 drm_mm_remove_node(&ppgtt
->node
);
1982 gen6_for_all_pdes(pt
, pd
, pde
)
1983 if (pt
!= vm
->scratch_pt
)
1986 gen6_free_scratch(vm
);
1989 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1991 struct i915_address_space
*vm
= &ppgtt
->base
;
1992 struct drm_device
*dev
= ppgtt
->base
.dev
;
1993 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1994 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1995 bool retried
= false;
1998 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1999 * allocator works in address space sizes, so it's multiplied by page
2000 * size. We allocate at the top of the GTT to avoid fragmentation.
2002 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
2004 ret
= gen6_init_scratch(vm
);
2009 ret
= drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
,
2010 &ppgtt
->node
, GEN6_PD_SIZE
,
2012 0, ggtt
->base
.total
,
2014 if (ret
== -ENOSPC
&& !retried
) {
2015 ret
= i915_gem_evict_something(&ggtt
->base
,
2016 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2018 0, ggtt
->base
.total
,
2031 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
2032 DRM_DEBUG("Forced to use aperture for PDEs\n");
2037 gen6_free_scratch(vm
);
2041 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2043 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2046 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2047 uint64_t start
, uint64_t length
)
2049 struct i915_page_table
*unused
;
2052 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
2053 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2056 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2058 struct drm_device
*dev
= ppgtt
->base
.dev
;
2059 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2060 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2063 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
2064 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev
))
2065 ppgtt
->switch_mm
= gen6_mm_switch
;
2066 else if (IS_HASWELL(dev
))
2067 ppgtt
->switch_mm
= hsw_mm_switch
;
2068 else if (IS_GEN7(dev
))
2069 ppgtt
->switch_mm
= gen7_mm_switch
;
2073 ret
= gen6_ppgtt_alloc(ppgtt
);
2077 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2078 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2079 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2080 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2081 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2082 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2083 ppgtt
->base
.start
= 0;
2084 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2085 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2087 ppgtt
->pd
.base
.ggtt_offset
=
2088 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2090 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
2091 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2093 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2095 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2097 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2098 ppgtt
->node
.size
>> 20,
2099 ppgtt
->node
.start
/ PAGE_SIZE
);
2101 DRM_DEBUG("Adding PPGTT at offset %x\n",
2102 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2107 static int __hw_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2108 struct drm_i915_private
*dev_priv
)
2110 ppgtt
->base
.dev
= &dev_priv
->drm
;
2112 if (INTEL_INFO(dev_priv
)->gen
< 8)
2113 return gen6_ppgtt_init(ppgtt
);
2115 return gen8_ppgtt_init(ppgtt
);
2118 static void i915_address_space_init(struct i915_address_space
*vm
,
2119 struct drm_i915_private
*dev_priv
)
2121 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2122 INIT_LIST_HEAD(&vm
->active_list
);
2123 INIT_LIST_HEAD(&vm
->inactive_list
);
2124 INIT_LIST_HEAD(&vm
->unbound_list
);
2125 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2128 static void gtt_write_workarounds(struct drm_device
*dev
)
2130 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2132 /* This function is for gtt related workarounds. This function is
2133 * called on driver load and after a GPU reset, so you can place
2134 * workarounds here even if they get overwritten by GPU reset.
2136 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2137 if (IS_BROADWELL(dev
))
2138 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
2139 else if (IS_CHERRYVIEW(dev
))
2140 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
2141 else if (IS_SKYLAKE(dev
))
2142 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
2143 else if (IS_BROXTON(dev
))
2144 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
2147 static int i915_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2148 struct drm_i915_private
*dev_priv
,
2149 struct drm_i915_file_private
*file_priv
)
2153 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2155 kref_init(&ppgtt
->ref
);
2156 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2157 ppgtt
->base
.file
= file_priv
;
2163 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2165 gtt_write_workarounds(dev
);
2167 /* In the case of execlists, PPGTT is enabled by the context descriptor
2168 * and the PDPs are contained within the context itself. We don't
2169 * need to do anything here. */
2170 if (i915
.enable_execlists
)
2173 if (!USES_PPGTT(dev
))
2177 gen6_ppgtt_enable(dev
);
2178 else if (IS_GEN7(dev
))
2179 gen7_ppgtt_enable(dev
);
2180 else if (INTEL_INFO(dev
)->gen
>= 8)
2181 gen8_ppgtt_enable(dev
);
2183 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2188 struct i915_hw_ppgtt
*
2189 i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
2190 struct drm_i915_file_private
*fpriv
)
2192 struct i915_hw_ppgtt
*ppgtt
;
2195 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2197 return ERR_PTR(-ENOMEM
);
2199 ret
= i915_ppgtt_init(ppgtt
, dev_priv
, fpriv
);
2202 return ERR_PTR(ret
);
2205 trace_i915_ppgtt_create(&ppgtt
->base
);
2210 void i915_ppgtt_release(struct kref
*kref
)
2212 struct i915_hw_ppgtt
*ppgtt
=
2213 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2215 trace_i915_ppgtt_release(&ppgtt
->base
);
2217 /* vmas should already be unbound and destroyed */
2218 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2219 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2220 WARN_ON(!list_empty(&ppgtt
->base
.unbound_list
));
2222 list_del(&ppgtt
->base
.global_link
);
2223 drm_mm_takedown(&ppgtt
->base
.mm
);
2225 ppgtt
->base
.cleanup(&ppgtt
->base
);
2229 /* Certain Gen5 chipsets require require idling the GPU before
2230 * unmapping anything from the GTT when VT-d is enabled.
2232 static bool needs_idle_maps(struct drm_i915_private
*dev_priv
)
2234 #ifdef CONFIG_INTEL_IOMMU
2235 /* Query intel_iommu to see if we need the workaround. Presumably that
2238 if (IS_GEN5(dev_priv
) && IS_MOBILE(dev_priv
) && intel_iommu_gfx_mapped
)
2244 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2246 struct intel_engine_cs
*engine
;
2248 if (INTEL_INFO(dev_priv
)->gen
< 6)
2251 for_each_engine(engine
, dev_priv
) {
2253 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2254 if (fault_reg
& RING_FAULT_VALID
) {
2255 DRM_DEBUG_DRIVER("Unexpected fault\n"
2257 "\tAddress space: %s\n"
2260 fault_reg
& PAGE_MASK
,
2261 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2262 RING_FAULT_SRCID(fault_reg
),
2263 RING_FAULT_FAULT_TYPE(fault_reg
));
2264 I915_WRITE(RING_FAULT_REG(engine
),
2265 fault_reg
& ~RING_FAULT_VALID
);
2268 POSTING_READ(RING_FAULT_REG(&dev_priv
->engine
[RCS
]));
2271 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2273 if (INTEL_INFO(dev_priv
)->gen
< 6) {
2274 intel_gtt_chipset_flush();
2276 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2277 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2281 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2283 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2284 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2286 /* Don't bother messing with faults pre GEN6 as we have little
2287 * documentation supporting that it's a good idea.
2289 if (INTEL_INFO(dev
)->gen
< 6)
2292 i915_check_and_clear_faults(dev_priv
);
2294 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
2297 i915_ggtt_flush(dev_priv
);
2300 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2302 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2303 obj
->pages
->sgl
, obj
->pages
->nents
,
2304 PCI_DMA_BIDIRECTIONAL
))
2310 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2315 iowrite32((u32
)pte
, addr
);
2316 iowrite32(pte
>> 32, addr
+ 4);
2320 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2323 enum i915_cache_level level
,
2326 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2327 gen8_pte_t __iomem
*pte
=
2328 (gen8_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2329 (offset
>> PAGE_SHIFT
);
2332 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2334 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
, true));
2336 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2337 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2339 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2342 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2343 struct sg_table
*st
,
2345 enum i915_cache_level level
, u32 unused
)
2347 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2348 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2349 struct sgt_iter sgt_iter
;
2350 gen8_pte_t __iomem
*gtt_entries
;
2351 gen8_pte_t gtt_entry
;
2356 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2358 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2360 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2361 gtt_entry
= gen8_pte_encode(addr
, level
, true);
2362 gen8_set_pte(>t_entries
[i
++], gtt_entry
);
2366 * XXX: This serves as a posting read to make sure that the PTE has
2367 * actually been updated. There is some concern that even though
2368 * registers and PTEs are within the same BAR that they are potentially
2369 * of NUMA access patterns. Therefore, even with the way we assume
2370 * hardware should work, we must keep this posting read for paranoia.
2373 WARN_ON(readq(>t_entries
[i
-1]) != gtt_entry
);
2375 /* This next bit makes the above posting read even more important. We
2376 * want to flush the TLBs only after we're certain all the PTE updates
2379 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2380 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2382 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2385 struct insert_entries
{
2386 struct i915_address_space
*vm
;
2387 struct sg_table
*st
;
2389 enum i915_cache_level level
;
2393 static int gen8_ggtt_insert_entries__cb(void *_arg
)
2395 struct insert_entries
*arg
= _arg
;
2396 gen8_ggtt_insert_entries(arg
->vm
, arg
->st
,
2397 arg
->start
, arg
->level
, arg
->flags
);
2401 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2402 struct sg_table
*st
,
2404 enum i915_cache_level level
,
2407 struct insert_entries arg
= { vm
, st
, start
, level
, flags
};
2408 stop_machine(gen8_ggtt_insert_entries__cb
, &arg
, NULL
);
2411 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2414 enum i915_cache_level level
,
2417 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2418 gen6_pte_t __iomem
*pte
=
2419 (gen6_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2420 (offset
>> PAGE_SHIFT
);
2423 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2425 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), pte
);
2427 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2428 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2430 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2434 * Binds an object into the global gtt with the specified cache level. The object
2435 * will be accessible to the GPU via commands whose operands reference offsets
2436 * within the global GTT as well as accessible by the GPU through the GMADR
2437 * mapped BAR (dev_priv->mm.gtt->gtt).
2439 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2440 struct sg_table
*st
,
2442 enum i915_cache_level level
, u32 flags
)
2444 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2445 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2446 struct sgt_iter sgt_iter
;
2447 gen6_pte_t __iomem
*gtt_entries
;
2448 gen6_pte_t gtt_entry
;
2453 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2455 gtt_entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2457 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2458 gtt_entry
= vm
->pte_encode(addr
, level
, true, flags
);
2459 iowrite32(gtt_entry
, >t_entries
[i
++]);
2462 /* XXX: This serves as a posting read to make sure that the PTE has
2463 * actually been updated. There is some concern that even though
2464 * registers and PTEs are within the same BAR that they are potentially
2465 * of NUMA access patterns. Therefore, even with the way we assume
2466 * hardware should work, we must keep this posting read for paranoia.
2469 WARN_ON(readl(>t_entries
[i
-1]) != gtt_entry
);
2471 /* This next bit makes the above posting read even more important. We
2472 * want to flush the TLBs only after we're certain all the PTE updates
2475 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2476 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2478 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2481 static void nop_clear_range(struct i915_address_space
*vm
,
2488 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2493 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2494 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2495 unsigned first_entry
= start
>> PAGE_SHIFT
;
2496 unsigned num_entries
= length
>> PAGE_SHIFT
;
2497 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2498 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2499 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2503 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2505 if (WARN(num_entries
> max_entries
,
2506 "First entry = %d; Num entries = %d (max=%d)\n",
2507 first_entry
, num_entries
, max_entries
))
2508 num_entries
= max_entries
;
2510 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2513 for (i
= 0; i
< num_entries
; i
++)
2514 gen8_set_pte(>t_base
[i
], scratch_pte
);
2517 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2520 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2525 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2526 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2527 unsigned first_entry
= start
>> PAGE_SHIFT
;
2528 unsigned num_entries
= length
>> PAGE_SHIFT
;
2529 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2530 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2531 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2535 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2537 if (WARN(num_entries
> max_entries
,
2538 "First entry = %d; Num entries = %d (max=%d)\n",
2539 first_entry
, num_entries
, max_entries
))
2540 num_entries
= max_entries
;
2542 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2543 I915_CACHE_LLC
, use_scratch
, 0);
2545 for (i
= 0; i
< num_entries
; i
++)
2546 iowrite32(scratch_pte
, >t_base
[i
]);
2549 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2552 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2555 enum i915_cache_level cache_level
,
2558 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2559 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2560 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2563 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2565 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2567 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2570 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2571 struct sg_table
*pages
,
2573 enum i915_cache_level cache_level
, u32 unused
)
2575 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2576 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2577 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2580 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2582 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2584 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2588 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2593 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2594 unsigned first_entry
= start
>> PAGE_SHIFT
;
2595 unsigned num_entries
= length
>> PAGE_SHIFT
;
2598 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2600 intel_gtt_clear_range(first_entry
, num_entries
);
2602 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2605 static int ggtt_bind_vma(struct i915_vma
*vma
,
2606 enum i915_cache_level cache_level
,
2609 struct drm_i915_gem_object
*obj
= vma
->obj
;
2613 ret
= i915_get_ggtt_vma_pages(vma
);
2617 /* Currently applicable only to VLV */
2619 pte_flags
|= PTE_READ_ONLY
;
2621 vma
->vm
->insert_entries(vma
->vm
, vma
->ggtt_view
.pages
,
2623 cache_level
, pte_flags
);
2626 * Without aliasing PPGTT there's no difference between
2627 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2628 * upgrade to both bound if we bind either to avoid double-binding.
2630 vma
->flags
|= I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
;
2635 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2636 enum i915_cache_level cache_level
,
2642 ret
= i915_get_ggtt_vma_pages(vma
);
2646 /* Currently applicable only to VLV */
2648 if (vma
->obj
->gt_ro
)
2649 pte_flags
|= PTE_READ_ONLY
;
2652 if (flags
& I915_VMA_GLOBAL_BIND
) {
2653 vma
->vm
->insert_entries(vma
->vm
,
2654 vma
->ggtt_view
.pages
,
2656 cache_level
, pte_flags
);
2659 if (flags
& I915_VMA_LOCAL_BIND
) {
2660 struct i915_hw_ppgtt
*appgtt
=
2661 to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2662 appgtt
->base
.insert_entries(&appgtt
->base
,
2663 vma
->ggtt_view
.pages
,
2665 cache_level
, pte_flags
);
2671 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2673 struct i915_hw_ppgtt
*appgtt
= to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2674 const u64 size
= min(vma
->size
, vma
->node
.size
);
2676 if (vma
->flags
& I915_VMA_GLOBAL_BIND
)
2677 vma
->vm
->clear_range(vma
->vm
,
2678 vma
->node
.start
, size
,
2681 if (vma
->flags
& I915_VMA_LOCAL_BIND
&& appgtt
)
2682 appgtt
->base
.clear_range(&appgtt
->base
,
2683 vma
->node
.start
, size
,
2687 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2689 struct drm_device
*dev
= obj
->base
.dev
;
2690 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2691 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2693 if (unlikely(ggtt
->do_idle_maps
)) {
2694 if (i915_gem_wait_for_idle(dev_priv
, false)) {
2695 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2696 /* Wait a bit, in hopes it avoids the hang */
2701 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2702 PCI_DMA_BIDIRECTIONAL
);
2705 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2706 unsigned long color
,
2710 if (node
->color
!= color
)
2713 node
= list_first_entry_or_null(&node
->node_list
,
2716 if (node
&& node
->allocated
&& node
->color
!= color
)
2720 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
)
2722 /* Let GEM Manage all of the aperture.
2724 * However, leave one page at the end still bound to the scratch page.
2725 * There are a number of places where the hardware apparently prefetches
2726 * past the end of the object, and we've seen multiple hangs with the
2727 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2728 * aperture. One page should be enough to keep any prefetching inside
2731 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2732 unsigned long hole_start
, hole_end
;
2733 struct drm_mm_node
*entry
;
2736 ret
= intel_vgt_balloon(dev_priv
);
2740 /* Clear any non-preallocated blocks */
2741 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2742 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2743 hole_start
, hole_end
);
2744 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2745 hole_end
- hole_start
, true);
2748 /* And finally clear the reserved guard page */
2749 ggtt
->base
.clear_range(&ggtt
->base
,
2750 ggtt
->base
.total
- PAGE_SIZE
, PAGE_SIZE
,
2753 if (USES_PPGTT(dev_priv
) && !USES_FULL_PPGTT(dev_priv
)) {
2754 struct i915_hw_ppgtt
*ppgtt
;
2756 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2760 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2766 if (ppgtt
->base
.allocate_va_range
)
2767 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2770 ppgtt
->base
.cleanup(&ppgtt
->base
);
2775 ppgtt
->base
.clear_range(&ppgtt
->base
,
2780 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2781 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2782 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2789 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2790 * @dev_priv: i915 device
2792 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
)
2794 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2796 if (dev_priv
->mm
.aliasing_ppgtt
) {
2797 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2799 ppgtt
->base
.cleanup(&ppgtt
->base
);
2803 i915_gem_cleanup_stolen(&dev_priv
->drm
);
2805 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2806 intel_vgt_deballoon(dev_priv
);
2808 drm_mm_takedown(&ggtt
->base
.mm
);
2809 list_del(&ggtt
->base
.global_link
);
2812 ggtt
->base
.cleanup(&ggtt
->base
);
2814 arch_phys_wc_del(ggtt
->mtrr
);
2815 io_mapping_free(ggtt
->mappable
);
2818 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2820 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2821 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2822 return snb_gmch_ctl
<< 20;
2825 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2827 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2828 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2830 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2832 #ifdef CONFIG_X86_32
2833 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2834 if (bdw_gmch_ctl
> 4)
2838 return bdw_gmch_ctl
<< 20;
2841 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2843 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2844 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2847 return 1 << (20 + gmch_ctrl
);
2852 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2854 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2855 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2856 return snb_gmch_ctl
<< 25; /* 32 MB units */
2859 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2861 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2862 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2863 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2866 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2868 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2869 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2872 * 0x0 to 0x10: 32MB increments starting at 0MB
2873 * 0x11 to 0x16: 4MB increments starting at 8MB
2874 * 0x17 to 0x1d: 4MB increments start at 36MB
2876 if (gmch_ctrl
< 0x11)
2877 return gmch_ctrl
<< 25;
2878 else if (gmch_ctrl
< 0x17)
2879 return (gmch_ctrl
- 0x11 + 2) << 22;
2881 return (gmch_ctrl
- 0x17 + 9) << 22;
2884 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2886 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2887 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2889 if (gen9_gmch_ctl
< 0xf0)
2890 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2892 /* 4MB increments starting at 0xf0 for 4MB */
2893 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2896 static int ggtt_probe_common(struct i915_ggtt
*ggtt
, u64 size
)
2898 struct pci_dev
*pdev
= ggtt
->base
.dev
->pdev
;
2899 struct i915_page_scratch
*scratch_page
;
2900 phys_addr_t phys_addr
;
2902 /* For Modern GENs the PTEs and register space are split in the BAR */
2903 phys_addr
= pci_resource_start(pdev
, 0) + pci_resource_len(pdev
, 0) / 2;
2906 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2907 * dropped. For WC mappings in general we have 64 byte burst writes
2908 * when the WC buffer is flushed, so we can't use it, but have to
2909 * resort to an uncached mapping. The WC issue is easily caught by the
2910 * readback check when writing GTT PTE entries.
2912 if (IS_BROXTON(ggtt
->base
.dev
))
2913 ggtt
->gsm
= ioremap_nocache(phys_addr
, size
);
2915 ggtt
->gsm
= ioremap_wc(phys_addr
, size
);
2917 DRM_ERROR("Failed to map the ggtt page table\n");
2921 scratch_page
= alloc_scratch_page(ggtt
->base
.dev
);
2922 if (IS_ERR(scratch_page
)) {
2923 DRM_ERROR("Scratch setup failed\n");
2924 /* iounmap will also get called at remove, but meh */
2926 return PTR_ERR(scratch_page
);
2929 ggtt
->base
.scratch_page
= scratch_page
;
2934 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2935 * bits. When using advanced contexts each context stores its own PAT, but
2936 * writing this data shouldn't be harmful even in those cases. */
2937 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2941 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2942 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2943 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2944 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2945 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2946 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2947 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2948 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2950 if (!USES_PPGTT(dev_priv
))
2951 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2952 * so RTL will always use the value corresponding to
2954 * So let's disable cache for GGTT to avoid screen corruptions.
2955 * MOCS still can be used though.
2956 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2957 * before this patch, i.e. the same uncached + snooping access
2958 * like on gen6/7 seems to be in effect.
2959 * - So this just fixes blitter/render access. Again it looks
2960 * like it's not just uncached access, but uncached + snooping.
2961 * So we can still hold onto all our assumptions wrt cpu
2962 * clflushing on LLC machines.
2964 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2966 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2967 * write would work. */
2968 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2969 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2972 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2977 * Map WB on BDW to snooped on CHV.
2979 * Only the snoop bit has meaning for CHV, the rest is
2982 * The hardware will never snoop for certain types of accesses:
2983 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2984 * - PPGTT page tables
2985 * - some other special cycles
2987 * As with BDW, we also need to consider the following for GT accesses:
2988 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2989 * so RTL will always use the value corresponding to
2991 * Which means we must set the snoop bit in PAT entry 0
2992 * in order to keep the global status page working.
2994 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2998 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2999 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
3000 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
3001 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
3003 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
3004 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
3007 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3009 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
3012 free_scratch_page(vm
->dev
, vm
->scratch_page
);
3015 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
3017 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3018 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3022 /* TODO: We're not aware of mappable constraints on gen8 yet */
3023 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
3024 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
3026 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(39)))
3027 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(39));
3029 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3031 if (INTEL_GEN(dev_priv
) >= 9) {
3032 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
3033 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3034 } else if (IS_CHERRYVIEW(dev_priv
)) {
3035 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
3036 size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3038 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
3039 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3042 ggtt
->base
.total
= (size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3044 if (IS_CHERRYVIEW(dev_priv
) || IS_BROXTON(dev_priv
))
3045 chv_setup_private_ppat(dev_priv
);
3047 bdw_setup_private_ppat(dev_priv
);
3049 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3050 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3051 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3052 ggtt
->base
.insert_page
= gen8_ggtt_insert_page
;
3053 ggtt
->base
.clear_range
= nop_clear_range
;
3054 if (!USES_FULL_PPGTT(dev_priv
) || intel_scanout_needs_vtd_wa(dev_priv
))
3055 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
3057 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
3058 if (IS_CHERRYVIEW(dev_priv
))
3059 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries__BKL
;
3061 return ggtt_probe_common(ggtt
, size
);
3064 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
3066 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3067 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3071 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
3072 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
3074 /* 64/512MB is the current min/max we actually know of, but this is just
3075 * a coarse sanity check.
3077 if (ggtt
->mappable_end
< (64<<20) || ggtt
->mappable_end
> (512<<20)) {
3078 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
3082 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
3083 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40));
3084 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3086 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
3088 size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3089 ggtt
->base
.total
= (size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3091 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
3092 ggtt
->base
.insert_page
= gen6_ggtt_insert_page
;
3093 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
3094 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3095 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3096 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3098 if (HAS_EDRAM(dev_priv
))
3099 ggtt
->base
.pte_encode
= iris_pte_encode
;
3100 else if (IS_HASWELL(dev_priv
))
3101 ggtt
->base
.pte_encode
= hsw_pte_encode
;
3102 else if (IS_VALLEYVIEW(dev_priv
))
3103 ggtt
->base
.pte_encode
= byt_pte_encode
;
3104 else if (INTEL_GEN(dev_priv
) >= 7)
3105 ggtt
->base
.pte_encode
= ivb_pte_encode
;
3107 ggtt
->base
.pte_encode
= snb_pte_encode
;
3109 return ggtt_probe_common(ggtt
, size
);
3112 static void i915_gmch_remove(struct i915_address_space
*vm
)
3114 intel_gmch_remove();
3117 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
3119 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3122 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
3124 DRM_ERROR("failed to set up gmch\n");
3128 intel_gtt_get(&ggtt
->base
.total
, &ggtt
->stolen_size
,
3129 &ggtt
->mappable_base
, &ggtt
->mappable_end
);
3131 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
);
3132 ggtt
->base
.insert_page
= i915_ggtt_insert_page
;
3133 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
3134 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
3135 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3136 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3137 ggtt
->base
.cleanup
= i915_gmch_remove
;
3139 if (unlikely(ggtt
->do_idle_maps
))
3140 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3146 * i915_ggtt_probe_hw - Probe GGTT hardware location
3147 * @dev_priv: i915 device
3149 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
)
3151 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3154 ggtt
->base
.dev
= &dev_priv
->drm
;
3156 if (INTEL_GEN(dev_priv
) <= 5)
3157 ret
= i915_gmch_probe(ggtt
);
3158 else if (INTEL_GEN(dev_priv
) < 8)
3159 ret
= gen6_gmch_probe(ggtt
);
3161 ret
= gen8_gmch_probe(ggtt
);
3165 if ((ggtt
->base
.total
- 1) >> 32) {
3166 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3167 " of address space! Found %lldM!\n",
3168 ggtt
->base
.total
>> 20);
3169 ggtt
->base
.total
= 1ULL << 32;
3170 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3173 if (ggtt
->mappable_end
> ggtt
->base
.total
) {
3174 DRM_ERROR("mappable aperture extends past end of GGTT,"
3175 " aperture=%llx, total=%llx\n",
3176 ggtt
->mappable_end
, ggtt
->base
.total
);
3177 ggtt
->mappable_end
= ggtt
->base
.total
;
3180 /* GMADR is the PCI mmio aperture into the global GTT. */
3181 DRM_INFO("Memory usable by graphics device = %lluM\n",
3182 ggtt
->base
.total
>> 20);
3183 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
3184 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt
->stolen_size
>> 20);
3185 #ifdef CONFIG_INTEL_IOMMU
3186 if (intel_iommu_gfx_mapped
)
3187 DRM_INFO("VT-d active for gfx access\n");
3194 * i915_ggtt_init_hw - Initialize GGTT hardware
3195 * @dev_priv: i915 device
3197 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
)
3199 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3202 INIT_LIST_HEAD(&dev_priv
->vm_list
);
3204 /* Subtract the guard page before address space initialization to
3205 * shrink the range used by drm_mm.
3207 ggtt
->base
.total
-= PAGE_SIZE
;
3208 i915_address_space_init(&ggtt
->base
, dev_priv
);
3209 ggtt
->base
.total
+= PAGE_SIZE
;
3210 if (!HAS_LLC(dev_priv
))
3211 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
3214 io_mapping_create_wc(ggtt
->mappable_base
, ggtt
->mappable_end
);
3215 if (!ggtt
->mappable
) {
3217 goto out_gtt_cleanup
;
3220 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->mappable_base
, ggtt
->mappable_end
);
3223 * Initialise stolen early so that we may reserve preallocated
3224 * objects for the BIOS to KMS transition.
3226 ret
= i915_gem_init_stolen(&dev_priv
->drm
);
3228 goto out_gtt_cleanup
;
3233 ggtt
->base
.cleanup(&ggtt
->base
);
3237 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
)
3239 if (INTEL_GEN(dev_priv
) < 6 && !intel_enable_gtt())
3245 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3247 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3248 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3249 struct drm_i915_gem_object
*obj
;
3250 struct i915_vma
*vma
;
3252 i915_check_and_clear_faults(dev_priv
);
3254 /* First fill our portion of the GTT with scratch pages */
3255 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
3258 /* Cache flush objects bound into GGTT and rebind them. */
3259 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3260 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3261 if (vma
->vm
!= &ggtt
->base
)
3264 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3268 if (obj
->pin_display
)
3269 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3272 if (INTEL_INFO(dev
)->gen
>= 8) {
3273 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3274 chv_setup_private_ppat(dev_priv
);
3276 bdw_setup_private_ppat(dev_priv
);
3281 if (USES_PPGTT(dev
)) {
3282 struct i915_address_space
*vm
;
3284 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3285 /* TODO: Perhaps it shouldn't be gen6 specific */
3287 struct i915_hw_ppgtt
*ppgtt
;
3289 if (i915_is_ggtt(vm
))
3290 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3292 ppgtt
= i915_vm_to_ppgtt(vm
);
3294 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3295 0, ppgtt
->base
.total
);
3299 i915_ggtt_flush(dev_priv
);
3303 i915_vma_retire(struct i915_gem_active
*active
,
3304 struct drm_i915_gem_request
*rq
)
3306 const unsigned int idx
= rq
->engine
->id
;
3307 struct i915_vma
*vma
=
3308 container_of(active
, struct i915_vma
, last_read
[idx
]);
3310 GEM_BUG_ON(!i915_vma_has_active_engine(vma
, idx
));
3312 i915_vma_clear_active(vma
, idx
);
3313 if (i915_vma_is_active(vma
))
3316 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
3317 if (unlikely(i915_vma_is_closed(vma
) && !i915_vma_is_pinned(vma
)))
3318 WARN_ON(i915_vma_unbind(vma
));
3321 void i915_vma_destroy(struct i915_vma
*vma
)
3323 GEM_BUG_ON(vma
->node
.allocated
);
3324 GEM_BUG_ON(i915_vma_is_active(vma
));
3325 GEM_BUG_ON(!i915_vma_is_closed(vma
));
3327 list_del(&vma
->vm_link
);
3328 if (!i915_vma_is_ggtt(vma
))
3329 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
3331 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
3334 void i915_vma_close(struct i915_vma
*vma
)
3336 GEM_BUG_ON(i915_vma_is_closed(vma
));
3337 vma
->flags
|= I915_VMA_CLOSED
;
3339 list_del_init(&vma
->obj_link
);
3340 if (!i915_vma_is_active(vma
) && !i915_vma_is_pinned(vma
))
3341 WARN_ON(i915_vma_unbind(vma
));
3344 static struct i915_vma
*
3345 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
3346 struct i915_address_space
*vm
,
3347 const struct i915_ggtt_view
*view
)
3349 struct i915_vma
*vma
;
3352 GEM_BUG_ON(vm
->closed
);
3354 if (WARN_ON(i915_is_ggtt(vm
) != !!view
))
3355 return ERR_PTR(-EINVAL
);
3357 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3359 return ERR_PTR(-ENOMEM
);
3361 INIT_LIST_HEAD(&vma
->obj_link
);
3362 INIT_LIST_HEAD(&vma
->exec_list
);
3363 for (i
= 0; i
< ARRAY_SIZE(vma
->last_read
); i
++)
3364 init_request_active(&vma
->last_read
[i
], i915_vma_retire
);
3365 list_add(&vma
->vm_link
, &vm
->unbound_list
);
3368 vma
->size
= obj
->base
.size
;
3370 if (i915_is_ggtt(vm
)) {
3371 vma
->flags
|= I915_VMA_GGTT
;
3372 vma
->ggtt_view
= *view
;
3373 if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3374 vma
->size
= view
->params
.partial
.size
;
3375 vma
->size
<<= PAGE_SHIFT
;
3376 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3378 intel_rotation_info_size(&view
->params
.rotated
);
3379 vma
->size
<<= PAGE_SHIFT
;
3382 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3385 list_add_tail(&vma
->obj_link
, &obj
->vma_list
);
3391 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3392 struct i915_address_space
*vm
)
3394 struct i915_vma
*vma
;
3396 vma
= i915_gem_obj_to_vma(obj
, vm
);
3398 vma
= __i915_gem_vma_create(obj
, vm
,
3399 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3405 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3406 const struct i915_ggtt_view
*view
)
3408 struct drm_device
*dev
= obj
->base
.dev
;
3409 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3410 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3411 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3416 vma
= __i915_gem_vma_create(obj
, &ggtt
->base
, view
);
3418 GEM_BUG_ON(i915_vma_is_closed(vma
));
3423 static struct scatterlist
*
3424 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3425 unsigned int width
, unsigned int height
,
3426 unsigned int stride
,
3427 struct sg_table
*st
, struct scatterlist
*sg
)
3429 unsigned int column
, row
;
3430 unsigned int src_idx
;
3432 for (column
= 0; column
< width
; column
++) {
3433 src_idx
= stride
* (height
- 1) + column
;
3434 for (row
= 0; row
< height
; row
++) {
3436 /* We don't need the pages, but need to initialize
3437 * the entries so the sg list can be happily traversed.
3438 * The only thing we need are DMA addresses.
3440 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3441 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3442 sg_dma_len(sg
) = PAGE_SIZE
;
3451 static struct sg_table
*
3452 intel_rotate_fb_obj_pages(struct intel_rotation_info
*rot_info
,
3453 struct drm_i915_gem_object
*obj
)
3455 const size_t n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3456 unsigned int size_pages
= rot_info
->plane
[0].width
* rot_info
->plane
[0].height
;
3457 unsigned int size_pages_uv
;
3458 struct sgt_iter sgt_iter
;
3459 dma_addr_t dma_addr
;
3461 dma_addr_t
*page_addr_list
;
3462 struct sg_table
*st
;
3463 unsigned int uv_start_page
;
3464 struct scatterlist
*sg
;
3467 /* Allocate a temporary list of source pages for random access. */
3468 page_addr_list
= drm_malloc_gfp(n_pages
,
3471 if (!page_addr_list
)
3472 return ERR_PTR(ret
);
3474 /* Account for UV plane with NV12. */
3475 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
)
3476 size_pages_uv
= rot_info
->plane
[1].width
* rot_info
->plane
[1].height
;
3480 /* Allocate target SG list. */
3481 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3485 ret
= sg_alloc_table(st
, size_pages
+ size_pages_uv
, GFP_KERNEL
);
3489 /* Populate source page list from the object. */
3491 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->pages
)
3492 page_addr_list
[i
++] = dma_addr
;
3494 GEM_BUG_ON(i
!= n_pages
);
3498 /* Rotate the pages. */
3499 sg
= rotate_pages(page_addr_list
, 0,
3500 rot_info
->plane
[0].width
, rot_info
->plane
[0].height
,
3501 rot_info
->plane
[0].width
,
3504 /* Append the UV plane if NV12. */
3505 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
) {
3506 uv_start_page
= size_pages
;
3508 /* Check for tile-row un-alignment. */
3509 if (offset_in_page(rot_info
->uv_offset
))
3512 rot_info
->uv_start_page
= uv_start_page
;
3514 sg
= rotate_pages(page_addr_list
, rot_info
->uv_start_page
,
3515 rot_info
->plane
[1].width
, rot_info
->plane
[1].height
,
3516 rot_info
->plane
[1].width
,
3520 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3521 obj
->base
.size
, rot_info
->plane
[0].width
,
3522 rot_info
->plane
[0].height
, size_pages
+ size_pages_uv
,
3525 drm_free_large(page_addr_list
);
3532 drm_free_large(page_addr_list
);
3534 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3535 obj
->base
.size
, ret
, rot_info
->plane
[0].width
,
3536 rot_info
->plane
[0].height
, size_pages
+ size_pages_uv
,
3538 return ERR_PTR(ret
);
3541 static struct sg_table
*
3542 intel_partial_pages(const struct i915_ggtt_view
*view
,
3543 struct drm_i915_gem_object
*obj
)
3545 struct sg_table
*st
;
3546 struct scatterlist
*sg
;
3547 struct sg_page_iter obj_sg_iter
;
3550 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3554 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3560 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3561 view
->params
.partial
.offset
)
3563 if (st
->nents
>= view
->params
.partial
.size
)
3566 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3567 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3568 sg_dma_len(sg
) = PAGE_SIZE
;
3579 return ERR_PTR(ret
);
3583 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3587 if (vma
->ggtt_view
.pages
)
3590 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3591 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3592 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3593 vma
->ggtt_view
.pages
=
3594 intel_rotate_fb_obj_pages(&vma
->ggtt_view
.params
.rotated
, vma
->obj
);
3595 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3596 vma
->ggtt_view
.pages
=
3597 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3599 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3600 vma
->ggtt_view
.type
);
3602 if (!vma
->ggtt_view
.pages
) {
3603 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3604 vma
->ggtt_view
.type
);
3606 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3607 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3608 vma
->ggtt_view
.pages
= NULL
;
3609 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3610 vma
->ggtt_view
.type
, ret
);
3617 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3619 * @cache_level: mapping cache level
3620 * @flags: flags like global or local mapping
3622 * DMA addresses are taken from the scatter-gather table of this object (or of
3623 * this VMA in case of non-default GGTT views) and PTE entries set up.
3624 * Note that DMA addresses are also the only part of the SG table we care about.
3626 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3633 if (WARN_ON(flags
== 0))
3637 if (flags
& PIN_GLOBAL
)
3638 bind_flags
|= I915_VMA_GLOBAL_BIND
;
3639 if (flags
& PIN_USER
)
3640 bind_flags
|= I915_VMA_LOCAL_BIND
;
3642 vma_flags
= vma
->flags
& (I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
);
3643 if (flags
& PIN_UPDATE
)
3644 bind_flags
|= vma_flags
;
3646 bind_flags
&= ~vma_flags
;
3647 if (bind_flags
== 0)
3650 if (vma_flags
== 0 && vma
->vm
->allocate_va_range
) {
3651 trace_i915_va_alloc(vma
);
3652 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3659 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3663 vma
->flags
|= bind_flags
;
3667 void __iomem
*i915_vma_pin_iomap(struct i915_vma
*vma
)
3671 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3672 if (WARN_ON(!vma
->obj
->map_and_fenceable
))
3673 return IO_ERR_PTR(-ENODEV
);
3675 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
3676 GEM_BUG_ON((vma
->flags
& I915_VMA_GLOBAL_BIND
) == 0);
3680 ptr
= io_mapping_map_wc(i915_vm_to_ggtt(vma
->vm
)->mappable
,
3684 return IO_ERR_PTR(-ENOMEM
);
3689 __i915_vma_pin(vma
);