2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
36 * DOC: Global GTT views
38 * Background and previous state
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
65 * Implementation and usage
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
70 * A new flavour of core GEM functions which work with GGTT bound objects were
71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
80 * Code wanting to add or use a new GGTT view needs to:
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
97 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
99 const struct i915_ggtt_view i915_ggtt_view_normal
;
100 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
101 .type
= I915_GGTT_VIEW_ROTATED
104 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
106 bool has_aliasing_ppgtt
;
108 bool has_full_48bit_ppgtt
;
110 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
111 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
112 has_full_48bit_ppgtt
= IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9;
114 if (intel_vgpu_active(dev
))
115 has_full_ppgtt
= false; /* emulation is too hard */
118 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
119 * execlists, the sole mechanism available to submit work.
121 if (INTEL_INFO(dev
)->gen
< 9 &&
122 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
125 if (enable_ppgtt
== 1)
128 if (enable_ppgtt
== 2 && has_full_ppgtt
)
131 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
134 #ifdef CONFIG_INTEL_IOMMU
135 /* Disable ppgtt on SNB if VT-d is on. */
136 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
137 DRM_INFO("Disabling PPGTT because VT-d is on\n");
142 /* Early VLV doesn't have this */
143 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
144 dev
->pdev
->revision
< 0xb) {
145 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
149 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
150 return has_full_48bit_ppgtt
? 3 : 2;
152 return has_aliasing_ppgtt
? 1 : 0;
155 static int ppgtt_bind_vma(struct i915_vma
*vma
,
156 enum i915_cache_level cache_level
,
161 /* Currently applicable only to VLV */
163 pte_flags
|= PTE_READ_ONLY
;
165 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
166 cache_level
, pte_flags
);
171 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
173 vma
->vm
->clear_range(vma
->vm
,
179 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
180 enum i915_cache_level level
,
183 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
187 case I915_CACHE_NONE
:
188 pte
|= PPAT_UNCACHED_INDEX
;
191 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
194 pte
|= PPAT_CACHED_INDEX
;
201 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
202 const enum i915_cache_level level
)
204 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
206 if (level
!= I915_CACHE_NONE
)
207 pde
|= PPAT_CACHED_PDE_INDEX
;
209 pde
|= PPAT_UNCACHED_INDEX
;
213 #define gen8_pdpe_encode gen8_pde_encode
214 #define gen8_pml4e_encode gen8_pde_encode
216 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
217 enum i915_cache_level level
,
218 bool valid
, u32 unused
)
220 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
221 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
224 case I915_CACHE_L3_LLC
:
226 pte
|= GEN6_PTE_CACHE_LLC
;
228 case I915_CACHE_NONE
:
229 pte
|= GEN6_PTE_UNCACHED
;
238 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
239 enum i915_cache_level level
,
240 bool valid
, u32 unused
)
242 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
243 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
246 case I915_CACHE_L3_LLC
:
247 pte
|= GEN7_PTE_CACHE_L3_LLC
;
250 pte
|= GEN6_PTE_CACHE_LLC
;
252 case I915_CACHE_NONE
:
253 pte
|= GEN6_PTE_UNCACHED
;
262 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
263 enum i915_cache_level level
,
264 bool valid
, u32 flags
)
266 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
267 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
269 if (!(flags
& PTE_READ_ONLY
))
270 pte
|= BYT_PTE_WRITEABLE
;
272 if (level
!= I915_CACHE_NONE
)
273 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
278 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
279 enum i915_cache_level level
,
280 bool valid
, u32 unused
)
282 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
283 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
285 if (level
!= I915_CACHE_NONE
)
286 pte
|= HSW_WB_LLC_AGE3
;
291 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
292 enum i915_cache_level level
,
293 bool valid
, u32 unused
)
295 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
296 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
299 case I915_CACHE_NONE
:
302 pte
|= HSW_WT_ELLC_LLC_AGE3
;
305 pte
|= HSW_WB_ELLC_LLC_AGE3
;
312 static int __setup_page_dma(struct drm_device
*dev
,
313 struct i915_page_dma
*p
, gfp_t flags
)
315 struct device
*device
= &dev
->pdev
->dev
;
317 p
->page
= alloc_page(flags
);
321 p
->daddr
= dma_map_page(device
,
322 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
324 if (dma_mapping_error(device
, p
->daddr
)) {
325 __free_page(p
->page
);
332 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
334 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
337 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
339 if (WARN_ON(!p
->page
))
342 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
343 __free_page(p
->page
);
344 memset(p
, 0, sizeof(*p
));
347 static void *kmap_page_dma(struct i915_page_dma
*p
)
349 return kmap_atomic(p
->page
);
352 /* We use the flushing unmap only with ppgtt structures:
353 * page directories, page tables and scratch pages.
355 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
357 /* There are only few exceptions for gen >=6. chv and bxt.
358 * And we are not sure about the latter so play safe for now.
360 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
361 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
363 kunmap_atomic(vaddr
);
366 #define kmap_px(px) kmap_page_dma(px_base(px))
367 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
369 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
370 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
371 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
372 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
374 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
378 uint64_t * const vaddr
= kmap_page_dma(p
);
380 for (i
= 0; i
< 512; i
++)
383 kunmap_page_dma(dev
, vaddr
);
386 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
387 const uint32_t val32
)
393 fill_page_dma(dev
, p
, v
);
396 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
398 struct i915_page_scratch
*sp
;
401 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
403 return ERR_PTR(-ENOMEM
);
405 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
411 set_pages_uc(px_page(sp
), 1);
416 static void free_scratch_page(struct drm_device
*dev
,
417 struct i915_page_scratch
*sp
)
419 set_pages_wb(px_page(sp
), 1);
425 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
427 struct i915_page_table
*pt
;
428 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
429 GEN8_PTES
: GEN6_PTES
;
432 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
434 return ERR_PTR(-ENOMEM
);
436 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
442 ret
= setup_px(dev
, pt
);
449 kfree(pt
->used_ptes
);
456 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
459 kfree(pt
->used_ptes
);
463 static void gen8_initialize_pt(struct i915_address_space
*vm
,
464 struct i915_page_table
*pt
)
466 gen8_pte_t scratch_pte
;
468 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
469 I915_CACHE_LLC
, true);
471 fill_px(vm
->dev
, pt
, scratch_pte
);
474 static void gen6_initialize_pt(struct i915_address_space
*vm
,
475 struct i915_page_table
*pt
)
477 gen6_pte_t scratch_pte
;
479 WARN_ON(px_dma(vm
->scratch_page
) == 0);
481 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
482 I915_CACHE_LLC
, true, 0);
484 fill32_px(vm
->dev
, pt
, scratch_pte
);
487 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
489 struct i915_page_directory
*pd
;
492 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
494 return ERR_PTR(-ENOMEM
);
496 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
497 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
501 ret
= setup_px(dev
, pd
);
508 kfree(pd
->used_pdes
);
515 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
519 kfree(pd
->used_pdes
);
524 static void gen8_initialize_pd(struct i915_address_space
*vm
,
525 struct i915_page_directory
*pd
)
527 gen8_pde_t scratch_pde
;
529 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
531 fill_px(vm
->dev
, pd
, scratch_pde
);
534 static int __pdp_init(struct drm_device
*dev
,
535 struct i915_page_directory_pointer
*pdp
)
537 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
539 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
540 sizeof(unsigned long),
542 if (!pdp
->used_pdpes
)
545 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
547 if (!pdp
->page_directory
) {
548 kfree(pdp
->used_pdpes
);
549 /* the PDP might be the statically allocated top level. Keep it
550 * as clean as possible */
551 pdp
->used_pdpes
= NULL
;
558 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
560 kfree(pdp
->used_pdpes
);
561 kfree(pdp
->page_directory
);
562 pdp
->page_directory
= NULL
;
566 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
568 struct i915_page_directory_pointer
*pdp
;
571 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
573 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
575 return ERR_PTR(-ENOMEM
);
577 ret
= __pdp_init(dev
, pdp
);
581 ret
= setup_px(dev
, pdp
);
595 static void free_pdp(struct drm_device
*dev
,
596 struct i915_page_directory_pointer
*pdp
)
599 if (USES_FULL_48BIT_PPGTT(dev
)) {
600 cleanup_px(dev
, pdp
);
605 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
606 struct i915_page_directory_pointer
*pdp
)
608 gen8_ppgtt_pdpe_t scratch_pdpe
;
610 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
612 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
615 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
616 struct i915_pml4
*pml4
)
618 gen8_ppgtt_pml4e_t scratch_pml4e
;
620 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
623 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
627 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
628 struct i915_page_directory_pointer
*pdp
,
629 struct i915_page_directory
*pd
,
632 gen8_ppgtt_pdpe_t
*page_directorypo
;
634 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
637 page_directorypo
= kmap_px(pdp
);
638 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
639 kunmap_px(ppgtt
, page_directorypo
);
643 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
644 struct i915_pml4
*pml4
,
645 struct i915_page_directory_pointer
*pdp
,
648 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
650 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
651 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
652 kunmap_px(ppgtt
, pagemap
);
655 /* Broadwell Page Directory Pointer Descriptors */
656 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
660 struct intel_engine_cs
*ring
= req
->ring
;
665 ret
= intel_ring_begin(req
, 6);
669 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
670 intel_ring_emit_reg(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
671 intel_ring_emit(ring
, upper_32_bits(addr
));
672 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
673 intel_ring_emit_reg(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
674 intel_ring_emit(ring
, lower_32_bits(addr
));
675 intel_ring_advance(ring
);
680 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
681 struct drm_i915_gem_request
*req
)
685 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
686 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
688 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
696 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
697 struct drm_i915_gem_request
*req
)
699 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
702 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
703 struct i915_page_directory_pointer
*pdp
,
706 gen8_pte_t scratch_pte
)
708 struct i915_hw_ppgtt
*ppgtt
=
709 container_of(vm
, struct i915_hw_ppgtt
, base
);
710 gen8_pte_t
*pt_vaddr
;
711 unsigned pdpe
= gen8_pdpe_index(start
);
712 unsigned pde
= gen8_pde_index(start
);
713 unsigned pte
= gen8_pte_index(start
);
714 unsigned num_entries
= length
>> PAGE_SHIFT
;
715 unsigned last_pte
, i
;
720 while (num_entries
) {
721 struct i915_page_directory
*pd
;
722 struct i915_page_table
*pt
;
724 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
727 pd
= pdp
->page_directory
[pdpe
];
729 if (WARN_ON(!pd
->page_table
[pde
]))
732 pt
= pd
->page_table
[pde
];
734 if (WARN_ON(!px_page(pt
)))
737 last_pte
= pte
+ num_entries
;
738 if (last_pte
> GEN8_PTES
)
739 last_pte
= GEN8_PTES
;
741 pt_vaddr
= kmap_px(pt
);
743 for (i
= pte
; i
< last_pte
; i
++) {
744 pt_vaddr
[i
] = scratch_pte
;
748 kunmap_px(ppgtt
, pt
);
751 if (++pde
== I915_PDES
) {
752 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
759 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
764 struct i915_hw_ppgtt
*ppgtt
=
765 container_of(vm
, struct i915_hw_ppgtt
, base
);
766 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
767 I915_CACHE_LLC
, use_scratch
);
769 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
770 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
773 uint64_t templ4
, pml4e
;
774 struct i915_page_directory_pointer
*pdp
;
776 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, templ4
, pml4e
) {
777 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
784 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
785 struct i915_page_directory_pointer
*pdp
,
786 struct sg_page_iter
*sg_iter
,
788 enum i915_cache_level cache_level
)
790 struct i915_hw_ppgtt
*ppgtt
=
791 container_of(vm
, struct i915_hw_ppgtt
, base
);
792 gen8_pte_t
*pt_vaddr
;
793 unsigned pdpe
= gen8_pdpe_index(start
);
794 unsigned pde
= gen8_pde_index(start
);
795 unsigned pte
= gen8_pte_index(start
);
799 while (__sg_page_iter_next(sg_iter
)) {
800 if (pt_vaddr
== NULL
) {
801 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
802 struct i915_page_table
*pt
= pd
->page_table
[pde
];
803 pt_vaddr
= kmap_px(pt
);
807 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
809 if (++pte
== GEN8_PTES
) {
810 kunmap_px(ppgtt
, pt_vaddr
);
812 if (++pde
== I915_PDES
) {
813 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
822 kunmap_px(ppgtt
, pt_vaddr
);
825 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
826 struct sg_table
*pages
,
828 enum i915_cache_level cache_level
,
831 struct i915_hw_ppgtt
*ppgtt
=
832 container_of(vm
, struct i915_hw_ppgtt
, base
);
833 struct sg_page_iter sg_iter
;
835 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
837 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
838 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
841 struct i915_page_directory_pointer
*pdp
;
842 uint64_t templ4
, pml4e
;
843 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
845 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, templ4
, pml4e
) {
846 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
852 static void gen8_free_page_tables(struct drm_device
*dev
,
853 struct i915_page_directory
*pd
)
860 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
861 if (WARN_ON(!pd
->page_table
[i
]))
864 free_pt(dev
, pd
->page_table
[i
]);
865 pd
->page_table
[i
] = NULL
;
869 static int gen8_init_scratch(struct i915_address_space
*vm
)
871 struct drm_device
*dev
= vm
->dev
;
873 vm
->scratch_page
= alloc_scratch_page(dev
);
874 if (IS_ERR(vm
->scratch_page
))
875 return PTR_ERR(vm
->scratch_page
);
877 vm
->scratch_pt
= alloc_pt(dev
);
878 if (IS_ERR(vm
->scratch_pt
)) {
879 free_scratch_page(dev
, vm
->scratch_page
);
880 return PTR_ERR(vm
->scratch_pt
);
883 vm
->scratch_pd
= alloc_pd(dev
);
884 if (IS_ERR(vm
->scratch_pd
)) {
885 free_pt(dev
, vm
->scratch_pt
);
886 free_scratch_page(dev
, vm
->scratch_page
);
887 return PTR_ERR(vm
->scratch_pd
);
890 if (USES_FULL_48BIT_PPGTT(dev
)) {
891 vm
->scratch_pdp
= alloc_pdp(dev
);
892 if (IS_ERR(vm
->scratch_pdp
)) {
893 free_pd(dev
, vm
->scratch_pd
);
894 free_pt(dev
, vm
->scratch_pt
);
895 free_scratch_page(dev
, vm
->scratch_page
);
896 return PTR_ERR(vm
->scratch_pdp
);
900 gen8_initialize_pt(vm
, vm
->scratch_pt
);
901 gen8_initialize_pd(vm
, vm
->scratch_pd
);
902 if (USES_FULL_48BIT_PPGTT(dev
))
903 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
908 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
910 enum vgt_g2v_type msg
;
911 struct drm_device
*dev
= ppgtt
->base
.dev
;
912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
913 unsigned int offset
= vgtif_reg(pdp0_lo
);
916 if (USES_FULL_48BIT_PPGTT(dev
)) {
917 u64 daddr
= px_dma(&ppgtt
->pml4
);
919 I915_WRITE(offset
, lower_32_bits(daddr
));
920 I915_WRITE(offset
+ 4, upper_32_bits(daddr
));
922 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
923 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
925 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
926 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
928 I915_WRITE(offset
, lower_32_bits(daddr
));
929 I915_WRITE(offset
+ 4, upper_32_bits(daddr
));
934 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
935 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
938 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
943 static void gen8_free_scratch(struct i915_address_space
*vm
)
945 struct drm_device
*dev
= vm
->dev
;
947 if (USES_FULL_48BIT_PPGTT(dev
))
948 free_pdp(dev
, vm
->scratch_pdp
);
949 free_pd(dev
, vm
->scratch_pd
);
950 free_pt(dev
, vm
->scratch_pt
);
951 free_scratch_page(dev
, vm
->scratch_page
);
954 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
955 struct i915_page_directory_pointer
*pdp
)
959 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
960 if (WARN_ON(!pdp
->page_directory
[i
]))
963 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
964 free_pd(dev
, pdp
->page_directory
[i
]);
970 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
974 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
975 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
978 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
981 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
984 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
986 struct i915_hw_ppgtt
*ppgtt
=
987 container_of(vm
, struct i915_hw_ppgtt
, base
);
989 if (intel_vgpu_active(vm
->dev
))
990 gen8_ppgtt_notify_vgt(ppgtt
, false);
992 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
993 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
995 gen8_ppgtt_cleanup_4lvl(ppgtt
);
997 gen8_free_scratch(vm
);
1001 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1002 * @vm: Master vm structure.
1003 * @pd: Page directory for this address range.
1004 * @start: Starting virtual address to begin allocations.
1005 * @length: Size of the allocations.
1006 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1007 * caller to free on error.
1009 * Allocate the required number of page tables. Extremely similar to
1010 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1011 * the page directory boundary (instead of the page directory pointer). That
1012 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1013 * possible, and likely that the caller will need to use multiple calls of this
1014 * function to achieve the appropriate allocation.
1016 * Return: 0 if success; negative error code otherwise.
1018 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1019 struct i915_page_directory
*pd
,
1022 unsigned long *new_pts
)
1024 struct drm_device
*dev
= vm
->dev
;
1025 struct i915_page_table
*pt
;
1029 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
1030 /* Don't reallocate page tables */
1031 if (test_bit(pde
, pd
->used_pdes
)) {
1032 /* Scratch is never allocated this way */
1033 WARN_ON(pt
== vm
->scratch_pt
);
1041 gen8_initialize_pt(vm
, pt
);
1042 pd
->page_table
[pde
] = pt
;
1043 __set_bit(pde
, new_pts
);
1044 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1050 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1051 free_pt(dev
, pd
->page_table
[pde
]);
1057 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1058 * @vm: Master vm structure.
1059 * @pdp: Page directory pointer for this address range.
1060 * @start: Starting virtual address to begin allocations.
1061 * @length: Size of the allocations.
1062 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1063 * caller to free on error.
1065 * Allocate the required number of page directories starting at the pde index of
1066 * @start, and ending at the pde index @start + @length. This function will skip
1067 * over already allocated page directories within the range, and only allocate
1068 * new ones, setting the appropriate pointer within the pdp as well as the
1069 * correct position in the bitmap @new_pds.
1071 * The function will only allocate the pages within the range for a give page
1072 * directory pointer. In other words, if @start + @length straddles a virtually
1073 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1074 * required by the caller, This is not currently possible, and the BUG in the
1075 * code will prevent it.
1077 * Return: 0 if success; negative error code otherwise.
1080 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1081 struct i915_page_directory_pointer
*pdp
,
1084 unsigned long *new_pds
)
1086 struct drm_device
*dev
= vm
->dev
;
1087 struct i915_page_directory
*pd
;
1090 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1092 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1094 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1095 if (test_bit(pdpe
, pdp
->used_pdpes
))
1102 gen8_initialize_pd(vm
, pd
);
1103 pdp
->page_directory
[pdpe
] = pd
;
1104 __set_bit(pdpe
, new_pds
);
1105 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1111 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1112 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1118 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1119 * @vm: Master vm structure.
1120 * @pml4: Page map level 4 for this address range.
1121 * @start: Starting virtual address to begin allocations.
1122 * @length: Size of the allocations.
1123 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1124 * caller to free on error.
1126 * Allocate the required number of page directory pointers. Extremely similar to
1127 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1128 * The main difference is here we are limited by the pml4 boundary (instead of
1129 * the page directory pointer).
1131 * Return: 0 if success; negative error code otherwise.
1134 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1135 struct i915_pml4
*pml4
,
1138 unsigned long *new_pdps
)
1140 struct drm_device
*dev
= vm
->dev
;
1141 struct i915_page_directory_pointer
*pdp
;
1145 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1147 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1148 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1149 pdp
= alloc_pdp(dev
);
1153 gen8_initialize_pdp(vm
, pdp
);
1154 pml4
->pdps
[pml4e
] = pdp
;
1155 __set_bit(pml4e
, new_pdps
);
1156 trace_i915_page_directory_pointer_entry_alloc(vm
,
1166 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1167 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1173 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1179 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1180 * of these are based on the number of PDPEs in the system.
1183 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1184 unsigned long **new_pts
,
1190 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1194 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1205 free_gen8_temp_bitmaps(pds
, pts
);
1209 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1210 * the page table structures, we mark them dirty so that
1211 * context switching/execlist queuing code takes extra steps
1212 * to ensure that tlbs are flushed.
1214 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1216 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1219 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1220 struct i915_page_directory_pointer
*pdp
,
1224 struct i915_hw_ppgtt
*ppgtt
=
1225 container_of(vm
, struct i915_hw_ppgtt
, base
);
1226 unsigned long *new_page_dirs
, *new_page_tables
;
1227 struct drm_device
*dev
= vm
->dev
;
1228 struct i915_page_directory
*pd
;
1229 const uint64_t orig_start
= start
;
1230 const uint64_t orig_length
= length
;
1233 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1236 /* Wrap is never okay since we can only represent 48b, and we don't
1237 * actually use the other side of the canonical address space.
1239 if (WARN_ON(start
+ length
< start
))
1242 if (WARN_ON(start
+ length
> vm
->total
))
1245 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1249 /* Do the allocations first so we can easily bail out */
1250 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1253 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1257 /* For every page directory referenced, allocate page tables */
1258 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1259 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1260 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1266 length
= orig_length
;
1268 /* Allocations have completed successfully, so set the bitmaps, and do
1270 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1271 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1272 struct i915_page_table
*pt
;
1273 uint64_t pd_len
= length
;
1274 uint64_t pd_start
= start
;
1277 /* Every pd should be allocated, we just did that above. */
1280 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1281 /* Same reasoning as pd */
1284 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1286 /* Set our used ptes within the page table */
1287 bitmap_set(pt
->used_ptes
,
1288 gen8_pte_index(pd_start
),
1289 gen8_pte_count(pd_start
, pd_len
));
1291 /* Our pde is now pointing to the pagetable, pt */
1292 __set_bit(pde
, pd
->used_pdes
);
1294 /* Map the PDE to the page table */
1295 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1297 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1298 gen8_pte_index(start
),
1299 gen8_pte_count(start
, length
),
1302 /* NB: We haven't yet mapped ptes to pages. At this
1303 * point we're still relying on insert_entries() */
1306 kunmap_px(ppgtt
, page_directory
);
1307 __set_bit(pdpe
, pdp
->used_pdpes
);
1308 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1311 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1312 mark_tlbs_dirty(ppgtt
);
1317 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1318 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1319 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1322 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1323 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1325 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1326 mark_tlbs_dirty(ppgtt
);
1330 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1331 struct i915_pml4
*pml4
,
1335 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1336 struct i915_hw_ppgtt
*ppgtt
=
1337 container_of(vm
, struct i915_hw_ppgtt
, base
);
1338 struct i915_page_directory_pointer
*pdp
;
1339 uint64_t temp
, pml4e
;
1342 /* Do the pml4 allocations first, so we don't need to track the newly
1343 * allocated tables below the pdp */
1344 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1346 /* The pagedirectory and pagetable allocations are done in the shared 3
1347 * and 4 level code. Just allocate the pdps.
1349 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1354 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1355 "The allocation has spanned more than 512GB. "
1356 "It is highly likely this is incorrect.");
1358 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1361 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1365 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1368 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1369 GEN8_PML4ES_PER_PML4
);
1374 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1375 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1380 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1381 uint64_t start
, uint64_t length
)
1383 struct i915_hw_ppgtt
*ppgtt
=
1384 container_of(vm
, struct i915_hw_ppgtt
, base
);
1386 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1387 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1389 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1392 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1393 uint64_t start
, uint64_t length
,
1394 gen8_pte_t scratch_pte
,
1397 struct i915_page_directory
*pd
;
1401 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1402 struct i915_page_table
*pt
;
1403 uint64_t pd_len
= length
;
1404 uint64_t pd_start
= start
;
1407 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1410 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1411 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1413 gen8_pte_t
*pt_vaddr
;
1415 if (!test_bit(pde
, pd
->used_pdes
))
1418 pt_vaddr
= kmap_px(pt
);
1419 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1421 (pdpe
<< GEN8_PDPE_SHIFT
) |
1422 (pde
<< GEN8_PDE_SHIFT
) |
1423 (pte
<< GEN8_PTE_SHIFT
);
1427 for (i
= 0; i
< 4; i
++)
1428 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1433 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1434 for (i
= 0; i
< 4; i
++) {
1435 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1436 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1438 seq_puts(m
, " SCRATCH ");
1442 /* don't use kunmap_px, it could trigger
1443 * an unnecessary flush.
1445 kunmap_atomic(pt_vaddr
);
1450 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1452 struct i915_address_space
*vm
= &ppgtt
->base
;
1453 uint64_t start
= ppgtt
->base
.start
;
1454 uint64_t length
= ppgtt
->base
.total
;
1455 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1456 I915_CACHE_LLC
, true);
1458 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1459 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1461 uint64_t templ4
, pml4e
;
1462 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1463 struct i915_page_directory_pointer
*pdp
;
1465 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, templ4
, pml4e
) {
1466 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1469 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1470 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1475 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1477 unsigned long *new_page_dirs
, *new_page_tables
;
1478 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1481 /* We allocate temp bitmap for page tables for no gain
1482 * but as this is for init only, lets keep the things simple
1484 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1488 /* Allocate for all pdps regardless of how the ppgtt
1491 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1495 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1497 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1503 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1504 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1505 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1509 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1513 ret
= gen8_init_scratch(&ppgtt
->base
);
1517 ppgtt
->base
.start
= 0;
1518 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1519 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1520 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1521 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1522 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1523 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1524 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1526 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1527 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1531 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1533 ppgtt
->base
.total
= 1ULL << 48;
1534 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1536 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1540 ppgtt
->base
.total
= 1ULL << 32;
1541 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1542 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1546 if (intel_vgpu_active(ppgtt
->base
.dev
)) {
1547 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1553 if (intel_vgpu_active(ppgtt
->base
.dev
))
1554 gen8_ppgtt_notify_vgt(ppgtt
, true);
1559 gen8_free_scratch(&ppgtt
->base
);
1563 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1565 struct i915_address_space
*vm
= &ppgtt
->base
;
1566 struct i915_page_table
*unused
;
1567 gen6_pte_t scratch_pte
;
1569 uint32_t pte
, pde
, temp
;
1570 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1572 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1573 I915_CACHE_LLC
, true, 0);
1575 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1577 gen6_pte_t
*pt_vaddr
;
1578 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1579 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1580 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1582 if (pd_entry
!= expected
)
1583 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1587 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1589 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1591 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1593 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1597 for (i
= 0; i
< 4; i
++)
1598 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1603 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1604 for (i
= 0; i
< 4; i
++) {
1605 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1606 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1608 seq_puts(m
, " SCRATCH ");
1612 kunmap_px(ppgtt
, pt_vaddr
);
1616 /* Write pde (index) from the page directory @pd to the page table @pt */
1617 static void gen6_write_pde(struct i915_page_directory
*pd
,
1618 const int pde
, struct i915_page_table
*pt
)
1620 /* Caller needs to make sure the write completes if necessary */
1621 struct i915_hw_ppgtt
*ppgtt
=
1622 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1625 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1626 pd_entry
|= GEN6_PDE_VALID
;
1628 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1631 /* Write all the page tables found in the ppgtt structure to incrementing page
1633 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1634 struct i915_page_directory
*pd
,
1635 uint32_t start
, uint32_t length
)
1637 struct i915_page_table
*pt
;
1640 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1641 gen6_write_pde(pd
, pde
, pt
);
1643 /* Make sure write is complete before other code can use this page
1644 * table. Also require for WC mapped PTEs */
1645 readl(dev_priv
->gtt
.gsm
);
1648 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1650 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1652 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1655 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1656 struct drm_i915_gem_request
*req
)
1658 struct intel_engine_cs
*ring
= req
->ring
;
1661 /* NB: TLBs must be flushed and invalidated before a switch */
1662 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1666 ret
= intel_ring_begin(req
, 6);
1670 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1671 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(ring
));
1672 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1673 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(ring
));
1674 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1675 intel_ring_emit(ring
, MI_NOOP
);
1676 intel_ring_advance(ring
);
1681 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1682 struct drm_i915_gem_request
*req
)
1684 struct intel_engine_cs
*ring
= req
->ring
;
1685 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1687 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1688 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1692 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1693 struct drm_i915_gem_request
*req
)
1695 struct intel_engine_cs
*ring
= req
->ring
;
1698 /* NB: TLBs must be flushed and invalidated before a switch */
1699 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1703 ret
= intel_ring_begin(req
, 6);
1707 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1708 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(ring
));
1709 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1710 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(ring
));
1711 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1712 intel_ring_emit(ring
, MI_NOOP
);
1713 intel_ring_advance(ring
);
1715 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1716 if (ring
->id
!= RCS
) {
1717 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1725 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1726 struct drm_i915_gem_request
*req
)
1728 struct intel_engine_cs
*ring
= req
->ring
;
1729 struct drm_device
*dev
= ppgtt
->base
.dev
;
1730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1733 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1734 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1736 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1741 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1744 struct intel_engine_cs
*ring
;
1747 for_each_ring(ring
, dev_priv
, j
) {
1748 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1749 I915_WRITE(RING_MODE_GEN7(ring
),
1750 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1754 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1757 struct intel_engine_cs
*ring
;
1758 uint32_t ecochk
, ecobits
;
1761 ecobits
= I915_READ(GAC_ECO_BITS
);
1762 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1764 ecochk
= I915_READ(GAM_ECOCHK
);
1765 if (IS_HASWELL(dev
)) {
1766 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1768 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1769 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1771 I915_WRITE(GAM_ECOCHK
, ecochk
);
1773 for_each_ring(ring
, dev_priv
, i
) {
1774 /* GFX_MODE is per-ring on gen7+ */
1775 I915_WRITE(RING_MODE_GEN7(ring
),
1776 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1780 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1783 uint32_t ecochk
, gab_ctl
, ecobits
;
1785 ecobits
= I915_READ(GAC_ECO_BITS
);
1786 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1787 ECOBITS_PPGTT_CACHE64B
);
1789 gab_ctl
= I915_READ(GAB_CTL
);
1790 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1792 ecochk
= I915_READ(GAM_ECOCHK
);
1793 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1795 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1798 /* PPGTT support for Sandybdrige/Gen6 and later */
1799 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1804 struct i915_hw_ppgtt
*ppgtt
=
1805 container_of(vm
, struct i915_hw_ppgtt
, base
);
1806 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1807 unsigned first_entry
= start
>> PAGE_SHIFT
;
1808 unsigned num_entries
= length
>> PAGE_SHIFT
;
1809 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1810 unsigned first_pte
= first_entry
% GEN6_PTES
;
1811 unsigned last_pte
, i
;
1813 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1814 I915_CACHE_LLC
, true, 0);
1816 while (num_entries
) {
1817 last_pte
= first_pte
+ num_entries
;
1818 if (last_pte
> GEN6_PTES
)
1819 last_pte
= GEN6_PTES
;
1821 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1823 for (i
= first_pte
; i
< last_pte
; i
++)
1824 pt_vaddr
[i
] = scratch_pte
;
1826 kunmap_px(ppgtt
, pt_vaddr
);
1828 num_entries
-= last_pte
- first_pte
;
1834 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1835 struct sg_table
*pages
,
1837 enum i915_cache_level cache_level
, u32 flags
)
1839 struct i915_hw_ppgtt
*ppgtt
=
1840 container_of(vm
, struct i915_hw_ppgtt
, base
);
1841 gen6_pte_t
*pt_vaddr
;
1842 unsigned first_entry
= start
>> PAGE_SHIFT
;
1843 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1844 unsigned act_pte
= first_entry
% GEN6_PTES
;
1845 struct sg_page_iter sg_iter
;
1848 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1849 if (pt_vaddr
== NULL
)
1850 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1853 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1854 cache_level
, true, flags
);
1856 if (++act_pte
== GEN6_PTES
) {
1857 kunmap_px(ppgtt
, pt_vaddr
);
1864 kunmap_px(ppgtt
, pt_vaddr
);
1867 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1868 uint64_t start_in
, uint64_t length_in
)
1870 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1871 struct drm_device
*dev
= vm
->dev
;
1872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1873 struct i915_hw_ppgtt
*ppgtt
=
1874 container_of(vm
, struct i915_hw_ppgtt
, base
);
1875 struct i915_page_table
*pt
;
1876 uint32_t start
, length
, start_save
, length_save
;
1880 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1883 start
= start_save
= start_in
;
1884 length
= length_save
= length_in
;
1886 bitmap_zero(new_page_tables
, I915_PDES
);
1888 /* The allocation is done in two stages so that we can bail out with
1889 * minimal amount of pain. The first stage finds new page tables that
1890 * need allocation. The second stage marks use ptes within the page
1893 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1894 if (pt
!= vm
->scratch_pt
) {
1895 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1899 /* We've already allocated a page table */
1900 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1908 gen6_initialize_pt(vm
, pt
);
1910 ppgtt
->pd
.page_table
[pde
] = pt
;
1911 __set_bit(pde
, new_page_tables
);
1912 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1916 length
= length_save
;
1918 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1919 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1921 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1922 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1923 gen6_pte_count(start
, length
));
1925 if (__test_and_clear_bit(pde
, new_page_tables
))
1926 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1928 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1929 gen6_pte_index(start
),
1930 gen6_pte_count(start
, length
),
1932 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1936 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1938 /* Make sure write is complete before other code can use this page
1939 * table. Also require for WC mapped PTEs */
1940 readl(dev_priv
->gtt
.gsm
);
1942 mark_tlbs_dirty(ppgtt
);
1946 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1947 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1949 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1950 free_pt(vm
->dev
, pt
);
1953 mark_tlbs_dirty(ppgtt
);
1957 static int gen6_init_scratch(struct i915_address_space
*vm
)
1959 struct drm_device
*dev
= vm
->dev
;
1961 vm
->scratch_page
= alloc_scratch_page(dev
);
1962 if (IS_ERR(vm
->scratch_page
))
1963 return PTR_ERR(vm
->scratch_page
);
1965 vm
->scratch_pt
= alloc_pt(dev
);
1966 if (IS_ERR(vm
->scratch_pt
)) {
1967 free_scratch_page(dev
, vm
->scratch_page
);
1968 return PTR_ERR(vm
->scratch_pt
);
1971 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1976 static void gen6_free_scratch(struct i915_address_space
*vm
)
1978 struct drm_device
*dev
= vm
->dev
;
1980 free_pt(dev
, vm
->scratch_pt
);
1981 free_scratch_page(dev
, vm
->scratch_page
);
1984 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1986 struct i915_hw_ppgtt
*ppgtt
=
1987 container_of(vm
, struct i915_hw_ppgtt
, base
);
1988 struct i915_page_table
*pt
;
1991 drm_mm_remove_node(&ppgtt
->node
);
1993 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1994 if (pt
!= vm
->scratch_pt
)
1995 free_pt(ppgtt
->base
.dev
, pt
);
1998 gen6_free_scratch(vm
);
2001 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
2003 struct i915_address_space
*vm
= &ppgtt
->base
;
2004 struct drm_device
*dev
= ppgtt
->base
.dev
;
2005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2006 bool retried
= false;
2009 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2010 * allocator works in address space sizes, so it's multiplied by page
2011 * size. We allocate at the top of the GTT to avoid fragmentation.
2013 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
2015 ret
= gen6_init_scratch(vm
);
2020 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
2021 &ppgtt
->node
, GEN6_PD_SIZE
,
2023 0, dev_priv
->gtt
.base
.total
,
2025 if (ret
== -ENOSPC
&& !retried
) {
2026 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
2027 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2029 0, dev_priv
->gtt
.base
.total
,
2042 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
2043 DRM_DEBUG("Forced to use aperture for PDEs\n");
2048 gen6_free_scratch(vm
);
2052 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2054 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2057 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2058 uint64_t start
, uint64_t length
)
2060 struct i915_page_table
*unused
;
2063 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
2064 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2067 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2069 struct drm_device
*dev
= ppgtt
->base
.dev
;
2070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2073 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
2075 ppgtt
->switch_mm
= gen6_mm_switch
;
2076 } else if (IS_HASWELL(dev
)) {
2077 ppgtt
->switch_mm
= hsw_mm_switch
;
2078 } else if (IS_GEN7(dev
)) {
2079 ppgtt
->switch_mm
= gen7_mm_switch
;
2083 if (intel_vgpu_active(dev
))
2084 ppgtt
->switch_mm
= vgpu_mm_switch
;
2086 ret
= gen6_ppgtt_alloc(ppgtt
);
2090 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2091 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2092 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2093 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2094 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2095 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2096 ppgtt
->base
.start
= 0;
2097 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2098 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2100 ppgtt
->pd
.base
.ggtt_offset
=
2101 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2103 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
2104 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2106 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2108 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2110 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2111 ppgtt
->node
.size
>> 20,
2112 ppgtt
->node
.start
/ PAGE_SIZE
);
2114 DRM_DEBUG("Adding PPGTT at offset %x\n",
2115 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2120 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2122 ppgtt
->base
.dev
= dev
;
2124 if (INTEL_INFO(dev
)->gen
< 8)
2125 return gen6_ppgtt_init(ppgtt
);
2127 return gen8_ppgtt_init(ppgtt
);
2130 static void i915_address_space_init(struct i915_address_space
*vm
,
2131 struct drm_i915_private
*dev_priv
)
2133 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2134 vm
->dev
= dev_priv
->dev
;
2135 INIT_LIST_HEAD(&vm
->active_list
);
2136 INIT_LIST_HEAD(&vm
->inactive_list
);
2137 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2140 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2145 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2147 kref_init(&ppgtt
->ref
);
2148 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2154 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2156 /* In the case of execlists, PPGTT is enabled by the context descriptor
2157 * and the PDPs are contained within the context itself. We don't
2158 * need to do anything here. */
2159 if (i915
.enable_execlists
)
2162 if (!USES_PPGTT(dev
))
2166 gen6_ppgtt_enable(dev
);
2167 else if (IS_GEN7(dev
))
2168 gen7_ppgtt_enable(dev
);
2169 else if (INTEL_INFO(dev
)->gen
>= 8)
2170 gen8_ppgtt_enable(dev
);
2172 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2177 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
2179 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
2180 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2182 if (i915
.enable_execlists
)
2188 return ppgtt
->switch_mm(ppgtt
, req
);
2191 struct i915_hw_ppgtt
*
2192 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
2194 struct i915_hw_ppgtt
*ppgtt
;
2197 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2199 return ERR_PTR(-ENOMEM
);
2201 ret
= i915_ppgtt_init(dev
, ppgtt
);
2204 return ERR_PTR(ret
);
2207 ppgtt
->file_priv
= fpriv
;
2209 trace_i915_ppgtt_create(&ppgtt
->base
);
2214 void i915_ppgtt_release(struct kref
*kref
)
2216 struct i915_hw_ppgtt
*ppgtt
=
2217 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2219 trace_i915_ppgtt_release(&ppgtt
->base
);
2221 /* vmas should already be unbound */
2222 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2223 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2225 list_del(&ppgtt
->base
.global_link
);
2226 drm_mm_takedown(&ppgtt
->base
.mm
);
2228 ppgtt
->base
.cleanup(&ppgtt
->base
);
2232 extern int intel_iommu_gfx_mapped
;
2233 /* Certain Gen5 chipsets require require idling the GPU before
2234 * unmapping anything from the GTT when VT-d is enabled.
2236 static bool needs_idle_maps(struct drm_device
*dev
)
2238 #ifdef CONFIG_INTEL_IOMMU
2239 /* Query intel_iommu to see if we need the workaround. Presumably that
2242 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
2248 static bool do_idling(struct drm_i915_private
*dev_priv
)
2250 bool ret
= dev_priv
->mm
.interruptible
;
2252 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
2253 dev_priv
->mm
.interruptible
= false;
2254 if (i915_gpu_idle(dev_priv
->dev
)) {
2255 DRM_ERROR("Couldn't idle GPU\n");
2256 /* Wait a bit, in hopes it avoids the hang */
2264 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
2266 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2267 dev_priv
->mm
.interruptible
= interruptible
;
2270 void i915_check_and_clear_faults(struct drm_device
*dev
)
2272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2273 struct intel_engine_cs
*ring
;
2276 if (INTEL_INFO(dev
)->gen
< 6)
2279 for_each_ring(ring
, dev_priv
, i
) {
2281 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
2282 if (fault_reg
& RING_FAULT_VALID
) {
2283 DRM_DEBUG_DRIVER("Unexpected fault\n"
2285 "\tAddress space: %s\n"
2288 fault_reg
& PAGE_MASK
,
2289 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2290 RING_FAULT_SRCID(fault_reg
),
2291 RING_FAULT_FAULT_TYPE(fault_reg
));
2292 I915_WRITE(RING_FAULT_REG(ring
),
2293 fault_reg
& ~RING_FAULT_VALID
);
2296 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
2299 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2301 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
2302 intel_gtt_chipset_flush();
2304 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2305 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2309 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2313 /* Don't bother messing with faults pre GEN6 as we have little
2314 * documentation supporting that it's a good idea.
2316 if (INTEL_INFO(dev
)->gen
< 6)
2319 i915_check_and_clear_faults(dev
);
2321 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2322 dev_priv
->gtt
.base
.start
,
2323 dev_priv
->gtt
.base
.total
,
2326 i915_ggtt_flush(dev_priv
);
2329 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2331 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2332 obj
->pages
->sgl
, obj
->pages
->nents
,
2333 PCI_DMA_BIDIRECTIONAL
))
2339 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2344 iowrite32((u32
)pte
, addr
);
2345 iowrite32(pte
>> 32, addr
+ 4);
2349 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2350 struct sg_table
*st
,
2352 enum i915_cache_level level
, u32 unused
)
2354 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2355 unsigned first_entry
= start
>> PAGE_SHIFT
;
2356 gen8_pte_t __iomem
*gtt_entries
=
2357 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2359 struct sg_page_iter sg_iter
;
2360 dma_addr_t addr
= 0; /* shut up gcc */
2362 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2363 addr
= sg_dma_address(sg_iter
.sg
) +
2364 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
2365 gen8_set_pte(>t_entries
[i
],
2366 gen8_pte_encode(addr
, level
, true));
2371 * XXX: This serves as a posting read to make sure that the PTE has
2372 * actually been updated. There is some concern that even though
2373 * registers and PTEs are within the same BAR that they are potentially
2374 * of NUMA access patterns. Therefore, even with the way we assume
2375 * hardware should work, we must keep this posting read for paranoia.
2378 WARN_ON(readq(>t_entries
[i
-1])
2379 != gen8_pte_encode(addr
, level
, true));
2381 /* This next bit makes the above posting read even more important. We
2382 * want to flush the TLBs only after we're certain all the PTE updates
2385 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2386 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2390 * Binds an object into the global gtt with the specified cache level. The object
2391 * will be accessible to the GPU via commands whose operands reference offsets
2392 * within the global GTT as well as accessible by the GPU through the GMADR
2393 * mapped BAR (dev_priv->mm.gtt->gtt).
2395 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2396 struct sg_table
*st
,
2398 enum i915_cache_level level
, u32 flags
)
2400 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2401 unsigned first_entry
= start
>> PAGE_SHIFT
;
2402 gen6_pte_t __iomem
*gtt_entries
=
2403 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2405 struct sg_page_iter sg_iter
;
2406 dma_addr_t addr
= 0;
2408 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2409 addr
= sg_page_iter_dma_address(&sg_iter
);
2410 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
2414 /* XXX: This serves as a posting read to make sure that the PTE has
2415 * actually been updated. There is some concern that even though
2416 * registers and PTEs are within the same BAR that they are potentially
2417 * of NUMA access patterns. Therefore, even with the way we assume
2418 * hardware should work, we must keep this posting read for paranoia.
2421 unsigned long gtt
= readl(>t_entries
[i
-1]);
2422 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
2425 /* This next bit makes the above posting read even more important. We
2426 * want to flush the TLBs only after we're certain all the PTE updates
2429 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2430 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2433 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2438 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2439 unsigned first_entry
= start
>> PAGE_SHIFT
;
2440 unsigned num_entries
= length
>> PAGE_SHIFT
;
2441 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2442 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2443 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2446 if (WARN(num_entries
> max_entries
,
2447 "First entry = %d; Num entries = %d (max=%d)\n",
2448 first_entry
, num_entries
, max_entries
))
2449 num_entries
= max_entries
;
2451 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2454 for (i
= 0; i
< num_entries
; i
++)
2455 gen8_set_pte(>t_base
[i
], scratch_pte
);
2459 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2464 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2465 unsigned first_entry
= start
>> PAGE_SHIFT
;
2466 unsigned num_entries
= length
>> PAGE_SHIFT
;
2467 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2468 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2469 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2472 if (WARN(num_entries
> max_entries
,
2473 "First entry = %d; Num entries = %d (max=%d)\n",
2474 first_entry
, num_entries
, max_entries
))
2475 num_entries
= max_entries
;
2477 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2478 I915_CACHE_LLC
, use_scratch
, 0);
2480 for (i
= 0; i
< num_entries
; i
++)
2481 iowrite32(scratch_pte
, >t_base
[i
]);
2485 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2486 struct sg_table
*pages
,
2488 enum i915_cache_level cache_level
, u32 unused
)
2490 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2491 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2493 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2497 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2502 unsigned first_entry
= start
>> PAGE_SHIFT
;
2503 unsigned num_entries
= length
>> PAGE_SHIFT
;
2504 intel_gtt_clear_range(first_entry
, num_entries
);
2507 static int ggtt_bind_vma(struct i915_vma
*vma
,
2508 enum i915_cache_level cache_level
,
2511 struct drm_i915_gem_object
*obj
= vma
->obj
;
2515 ret
= i915_get_ggtt_vma_pages(vma
);
2519 /* Currently applicable only to VLV */
2521 pte_flags
|= PTE_READ_ONLY
;
2523 vma
->vm
->insert_entries(vma
->vm
, vma
->ggtt_view
.pages
,
2525 cache_level
, pte_flags
);
2528 * Without aliasing PPGTT there's no difference between
2529 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2530 * upgrade to both bound if we bind either to avoid double-binding.
2532 vma
->bound
|= GLOBAL_BIND
| LOCAL_BIND
;
2537 struct ggtt_bind_vma__cb
{
2538 struct i915_vma
*vma
;
2539 enum i915_cache_level cache_level
;
2543 static int ggtt_bind_vma__cb(void *_arg
)
2545 struct ggtt_bind_vma__cb
*arg
= _arg
;
2546 return ggtt_bind_vma(arg
->vma
, arg
->cache_level
, arg
->flags
);
2549 static int ggtt_bind_vma__BKL(struct i915_vma
*vma
,
2550 enum i915_cache_level cache_level
,
2553 struct ggtt_bind_vma__cb arg
= { vma
, cache_level
, flags
};
2554 return stop_machine(ggtt_bind_vma__cb
, &arg
, NULL
);
2557 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2558 enum i915_cache_level cache_level
,
2561 struct drm_device
*dev
= vma
->vm
->dev
;
2562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2563 struct drm_i915_gem_object
*obj
= vma
->obj
;
2564 struct sg_table
*pages
= obj
->pages
;
2568 ret
= i915_get_ggtt_vma_pages(vma
);
2571 pages
= vma
->ggtt_view
.pages
;
2573 /* Currently applicable only to VLV */
2575 pte_flags
|= PTE_READ_ONLY
;
2578 if (flags
& GLOBAL_BIND
) {
2579 vma
->vm
->insert_entries(vma
->vm
, pages
,
2581 cache_level
, pte_flags
);
2584 if (flags
& LOCAL_BIND
) {
2585 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2586 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2588 cache_level
, pte_flags
);
2594 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2596 struct drm_device
*dev
= vma
->vm
->dev
;
2597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2598 struct drm_i915_gem_object
*obj
= vma
->obj
;
2599 const uint64_t size
= min_t(uint64_t,
2603 if (vma
->bound
& GLOBAL_BIND
) {
2604 vma
->vm
->clear_range(vma
->vm
,
2610 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2611 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2613 appgtt
->base
.clear_range(&appgtt
->base
,
2620 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2622 struct drm_device
*dev
= obj
->base
.dev
;
2623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 interruptible
= do_idling(dev_priv
);
2628 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2629 PCI_DMA_BIDIRECTIONAL
);
2631 undo_idling(dev_priv
, interruptible
);
2634 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2635 unsigned long color
,
2639 if (node
->color
!= color
)
2642 if (!list_empty(&node
->node_list
)) {
2643 node
= list_entry(node
->node_list
.next
,
2646 if (node
->allocated
&& node
->color
!= color
)
2651 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2656 /* Let GEM Manage all of the aperture.
2658 * However, leave one page at the end still bound to the scratch page.
2659 * There are a number of places where the hardware apparently prefetches
2660 * past the end of the object, and we've seen multiple hangs with the
2661 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2662 * aperture. One page should be enough to keep any prefetching inside
2665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2666 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2667 struct drm_mm_node
*entry
;
2668 struct drm_i915_gem_object
*obj
;
2669 unsigned long hole_start
, hole_end
;
2672 BUG_ON(mappable_end
> end
);
2674 ggtt_vm
->start
= start
;
2676 /* Subtract the guard page before address space initialization to
2677 * shrink the range used by drm_mm */
2678 ggtt_vm
->total
= end
- start
- PAGE_SIZE
;
2679 i915_address_space_init(ggtt_vm
, dev_priv
);
2680 ggtt_vm
->total
+= PAGE_SIZE
;
2682 if (intel_vgpu_active(dev
)) {
2683 ret
= intel_vgt_balloon(dev
);
2689 ggtt_vm
->mm
.color_adjust
= i915_gtt_color_adjust
;
2691 /* Mark any preallocated objects as occupied */
2692 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2693 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2695 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2696 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2698 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2699 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2701 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2704 vma
->bound
|= GLOBAL_BIND
;
2705 list_add_tail(&vma
->mm_list
, &ggtt_vm
->inactive_list
);
2708 /* Clear any non-preallocated blocks */
2709 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2710 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2711 hole_start
, hole_end
);
2712 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2713 hole_end
- hole_start
, true);
2716 /* And finally clear the reserved guard page */
2717 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2719 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2720 struct i915_hw_ppgtt
*ppgtt
;
2722 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2726 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2728 ppgtt
->base
.cleanup(&ppgtt
->base
);
2733 if (ppgtt
->base
.allocate_va_range
)
2734 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2737 ppgtt
->base
.cleanup(&ppgtt
->base
);
2742 ppgtt
->base
.clear_range(&ppgtt
->base
,
2747 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2748 WARN_ON(dev_priv
->gtt
.base
.bind_vma
!= ggtt_bind_vma
);
2749 dev_priv
->gtt
.base
.bind_vma
= aliasing_gtt_bind_vma
;
2755 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2758 u64 gtt_size
, mappable_size
;
2760 gtt_size
= dev_priv
->gtt
.base
.total
;
2761 mappable_size
= dev_priv
->gtt
.mappable_end
;
2763 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2766 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2769 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2771 if (dev_priv
->mm
.aliasing_ppgtt
) {
2772 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2774 ppgtt
->base
.cleanup(&ppgtt
->base
);
2777 if (drm_mm_initialized(&vm
->mm
)) {
2778 if (intel_vgpu_active(dev
))
2779 intel_vgt_deballoon();
2781 drm_mm_takedown(&vm
->mm
);
2782 list_del(&vm
->global_link
);
2788 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2790 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2791 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2792 return snb_gmch_ctl
<< 20;
2795 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2797 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2798 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2800 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2802 #ifdef CONFIG_X86_32
2803 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2804 if (bdw_gmch_ctl
> 4)
2808 return bdw_gmch_ctl
<< 20;
2811 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2813 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2814 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2817 return 1 << (20 + gmch_ctrl
);
2822 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2824 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2825 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2826 return snb_gmch_ctl
<< 25; /* 32 MB units */
2829 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2831 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2832 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2833 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2836 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2838 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2839 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2842 * 0x0 to 0x10: 32MB increments starting at 0MB
2843 * 0x11 to 0x16: 4MB increments starting at 8MB
2844 * 0x17 to 0x1d: 4MB increments start at 36MB
2846 if (gmch_ctrl
< 0x11)
2847 return gmch_ctrl
<< 25;
2848 else if (gmch_ctrl
< 0x17)
2849 return (gmch_ctrl
- 0x11 + 2) << 22;
2851 return (gmch_ctrl
- 0x17 + 9) << 22;
2854 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2856 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2857 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2859 if (gen9_gmch_ctl
< 0xf0)
2860 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2862 /* 4MB increments starting at 0xf0 for 4MB */
2863 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2866 static int ggtt_probe_common(struct drm_device
*dev
,
2869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2870 struct i915_page_scratch
*scratch_page
;
2871 phys_addr_t gtt_phys_addr
;
2873 /* For Modern GENs the PTEs and register space are split in the BAR */
2874 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2875 (pci_resource_len(dev
->pdev
, 0) / 2);
2878 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2879 * dropped. For WC mappings in general we have 64 byte burst writes
2880 * when the WC buffer is flushed, so we can't use it, but have to
2881 * resort to an uncached mapping. The WC issue is easily caught by the
2882 * readback check when writing GTT PTE entries.
2884 if (IS_BROXTON(dev
))
2885 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2887 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2888 if (!dev_priv
->gtt
.gsm
) {
2889 DRM_ERROR("Failed to map the gtt page table\n");
2893 scratch_page
= alloc_scratch_page(dev
);
2894 if (IS_ERR(scratch_page
)) {
2895 DRM_ERROR("Scratch setup failed\n");
2896 /* iounmap will also get called at remove, but meh */
2897 iounmap(dev_priv
->gtt
.gsm
);
2898 return PTR_ERR(scratch_page
);
2901 dev_priv
->gtt
.base
.scratch_page
= scratch_page
;
2906 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2907 * bits. When using advanced contexts each context stores its own PAT, but
2908 * writing this data shouldn't be harmful even in those cases. */
2909 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2913 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2914 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2915 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2916 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2917 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2918 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2919 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2920 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2922 if (!USES_PPGTT(dev_priv
->dev
))
2923 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2924 * so RTL will always use the value corresponding to
2926 * So let's disable cache for GGTT to avoid screen corruptions.
2927 * MOCS still can be used though.
2928 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2929 * before this patch, i.e. the same uncached + snooping access
2930 * like on gen6/7 seems to be in effect.
2931 * - So this just fixes blitter/render access. Again it looks
2932 * like it's not just uncached access, but uncached + snooping.
2933 * So we can still hold onto all our assumptions wrt cpu
2934 * clflushing on LLC machines.
2936 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2938 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2939 * write would work. */
2940 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2941 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2944 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2949 * Map WB on BDW to snooped on CHV.
2951 * Only the snoop bit has meaning for CHV, the rest is
2954 * The hardware will never snoop for certain types of accesses:
2955 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2956 * - PPGTT page tables
2957 * - some other special cycles
2959 * As with BDW, we also need to consider the following for GT accesses:
2960 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2961 * so RTL will always use the value corresponding to
2963 * Which means we must set the snoop bit in PAT entry 0
2964 * in order to keep the global status page working.
2966 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2970 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2971 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2972 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2973 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2975 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2976 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2979 static int gen8_gmch_probe(struct drm_device
*dev
,
2982 phys_addr_t
*mappable_base
,
2985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2990 /* TODO: We're not aware of mappable constraints on gen8 yet */
2991 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2992 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2994 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2995 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2997 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2999 if (INTEL_INFO(dev
)->gen
>= 9) {
3000 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
3001 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3002 } else if (IS_CHERRYVIEW(dev
)) {
3003 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
3004 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3006 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
3007 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3010 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3012 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3013 chv_setup_private_ppat(dev_priv
);
3015 bdw_setup_private_ppat(dev_priv
);
3017 ret
= ggtt_probe_common(dev
, gtt_size
);
3019 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
3020 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
3021 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
3022 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
3024 if (IS_CHERRYVIEW(dev
))
3025 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma__BKL
;
3030 static int gen6_gmch_probe(struct drm_device
*dev
,
3033 phys_addr_t
*mappable_base
,
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3037 unsigned int gtt_size
;
3041 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
3042 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
3044 /* 64/512MB is the current min/max we actually know of, but this is just
3045 * a coarse sanity check.
3047 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
3048 DRM_ERROR("Unknown GMADR size (%llx)\n",
3049 dev_priv
->gtt
.mappable_end
);
3053 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
3054 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
3055 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3057 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
3059 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3060 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3062 ret
= ggtt_probe_common(dev
, gtt_size
);
3064 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
3065 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
3066 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
3067 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
3072 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3075 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
3078 free_scratch_page(vm
->dev
, vm
->scratch_page
);
3081 static int i915_gmch_probe(struct drm_device
*dev
,
3084 phys_addr_t
*mappable_base
,
3087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3090 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
3092 DRM_ERROR("failed to set up gmch\n");
3096 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
3098 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
3099 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
3100 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
3101 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
3102 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
3104 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
3105 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3110 static void i915_gmch_remove(struct i915_address_space
*vm
)
3112 intel_gmch_remove();
3115 int i915_gem_gtt_init(struct drm_device
*dev
)
3117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3118 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3121 if (INTEL_INFO(dev
)->gen
<= 5) {
3122 gtt
->gtt_probe
= i915_gmch_probe
;
3123 gtt
->base
.cleanup
= i915_gmch_remove
;
3124 } else if (INTEL_INFO(dev
)->gen
< 8) {
3125 gtt
->gtt_probe
= gen6_gmch_probe
;
3126 gtt
->base
.cleanup
= gen6_gmch_remove
;
3127 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
3128 gtt
->base
.pte_encode
= iris_pte_encode
;
3129 else if (IS_HASWELL(dev
))
3130 gtt
->base
.pte_encode
= hsw_pte_encode
;
3131 else if (IS_VALLEYVIEW(dev
))
3132 gtt
->base
.pte_encode
= byt_pte_encode
;
3133 else if (INTEL_INFO(dev
)->gen
>= 7)
3134 gtt
->base
.pte_encode
= ivb_pte_encode
;
3136 gtt
->base
.pte_encode
= snb_pte_encode
;
3138 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
3139 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
3142 gtt
->base
.dev
= dev
;
3144 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
3145 >t
->mappable_base
, >t
->mappable_end
);
3149 /* GMADR is the PCI mmio aperture into the global GTT. */
3150 DRM_INFO("Memory usable by graphics device = %lluM\n",
3151 gtt
->base
.total
>> 20);
3152 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
3153 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
3154 #ifdef CONFIG_INTEL_IOMMU
3155 if (intel_iommu_gfx_mapped
)
3156 DRM_INFO("VT-d active for gfx access\n");
3159 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3160 * user's requested state against the hardware/driver capabilities. We
3161 * do this now so that we can print out any log messages once rather
3162 * than every time we check intel_enable_ppgtt().
3164 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
3165 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
3170 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3173 struct drm_i915_gem_object
*obj
;
3174 struct i915_address_space
*vm
;
3175 struct i915_vma
*vma
;
3178 i915_check_and_clear_faults(dev
);
3180 /* First fill our portion of the GTT with scratch pages */
3181 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
3182 dev_priv
->gtt
.base
.start
,
3183 dev_priv
->gtt
.base
.total
,
3186 /* Cache flush objects bound into GGTT and rebind them. */
3187 vm
= &dev_priv
->gtt
.base
;
3188 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3190 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3194 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3201 i915_gem_clflush_object(obj
, obj
->pin_display
);
3204 if (INTEL_INFO(dev
)->gen
>= 8) {
3205 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3206 chv_setup_private_ppat(dev_priv
);
3208 bdw_setup_private_ppat(dev_priv
);
3213 if (USES_PPGTT(dev
)) {
3214 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3215 /* TODO: Perhaps it shouldn't be gen6 specific */
3217 struct i915_hw_ppgtt
*ppgtt
=
3218 container_of(vm
, struct i915_hw_ppgtt
,
3221 if (i915_is_ggtt(vm
))
3222 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3224 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3225 0, ppgtt
->base
.total
);
3229 i915_ggtt_flush(dev_priv
);
3232 static struct i915_vma
*
3233 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
3234 struct i915_address_space
*vm
,
3235 const struct i915_ggtt_view
*ggtt_view
)
3237 struct i915_vma
*vma
;
3239 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3240 return ERR_PTR(-EINVAL
);
3242 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3244 return ERR_PTR(-ENOMEM
);
3246 INIT_LIST_HEAD(&vma
->vma_link
);
3247 INIT_LIST_HEAD(&vma
->mm_list
);
3248 INIT_LIST_HEAD(&vma
->exec_list
);
3252 if (i915_is_ggtt(vm
))
3253 vma
->ggtt_view
= *ggtt_view
;
3255 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
3256 if (!i915_is_ggtt(vm
))
3257 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3263 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3264 struct i915_address_space
*vm
)
3266 struct i915_vma
*vma
;
3268 vma
= i915_gem_obj_to_vma(obj
, vm
);
3270 vma
= __i915_gem_vma_create(obj
, vm
,
3271 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3277 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3278 const struct i915_ggtt_view
*view
)
3280 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
3281 struct i915_vma
*vma
;
3284 return ERR_PTR(-EINVAL
);
3286 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3292 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
3298 static struct scatterlist
*
3299 rotate_pages(dma_addr_t
*in
, unsigned int offset
,
3300 unsigned int width
, unsigned int height
,
3301 struct sg_table
*st
, struct scatterlist
*sg
)
3303 unsigned int column
, row
;
3304 unsigned int src_idx
;
3311 for (column
= 0; column
< width
; column
++) {
3312 src_idx
= width
* (height
- 1) + column
;
3313 for (row
= 0; row
< height
; row
++) {
3315 /* We don't need the pages, but need to initialize
3316 * the entries so the sg list can be happily traversed.
3317 * The only thing we need are DMA addresses.
3319 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3320 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3321 sg_dma_len(sg
) = PAGE_SIZE
;
3330 static struct sg_table
*
3331 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
3332 struct drm_i915_gem_object
*obj
)
3334 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
3335 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
3336 unsigned int size_pages_uv
;
3337 struct sg_page_iter sg_iter
;
3339 dma_addr_t
*page_addr_list
;
3340 struct sg_table
*st
;
3341 unsigned int uv_start_page
;
3342 struct scatterlist
*sg
;
3345 /* Allocate a temporary list of source pages for random access. */
3346 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
3347 sizeof(dma_addr_t
));
3348 if (!page_addr_list
)
3349 return ERR_PTR(ret
);
3351 /* Account for UV plane with NV12. */
3352 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
)
3353 size_pages_uv
= rot_info
->size_uv
>> PAGE_SHIFT
;
3357 /* Allocate target SG list. */
3358 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3362 ret
= sg_alloc_table(st
, size_pages
+ size_pages_uv
, GFP_KERNEL
);
3366 /* Populate source page list from the object. */
3368 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
3369 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
3373 /* Rotate the pages. */
3374 sg
= rotate_pages(page_addr_list
, 0,
3375 rot_info
->width_pages
, rot_info
->height_pages
,
3378 /* Append the UV plane if NV12. */
3379 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
) {
3380 uv_start_page
= size_pages
;
3382 /* Check for tile-row un-alignment. */
3383 if (offset_in_page(rot_info
->uv_offset
))
3386 rot_info
->uv_start_page
= uv_start_page
;
3388 rotate_pages(page_addr_list
, uv_start_page
,
3389 rot_info
->width_pages_uv
,
3390 rot_info
->height_pages_uv
,
3395 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3396 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
3397 rot_info
->pixel_format
, rot_info
->width_pages
,
3398 rot_info
->height_pages
, size_pages
+ size_pages_uv
,
3401 drm_free_large(page_addr_list
);
3408 drm_free_large(page_addr_list
);
3411 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3412 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
3413 rot_info
->pixel_format
, rot_info
->width_pages
,
3414 rot_info
->height_pages
, size_pages
+ size_pages_uv
,
3416 return ERR_PTR(ret
);
3419 static struct sg_table
*
3420 intel_partial_pages(const struct i915_ggtt_view
*view
,
3421 struct drm_i915_gem_object
*obj
)
3423 struct sg_table
*st
;
3424 struct scatterlist
*sg
;
3425 struct sg_page_iter obj_sg_iter
;
3428 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3432 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3438 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3439 view
->params
.partial
.offset
)
3441 if (st
->nents
>= view
->params
.partial
.size
)
3444 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3445 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3446 sg_dma_len(sg
) = PAGE_SIZE
;
3457 return ERR_PTR(ret
);
3461 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3465 if (vma
->ggtt_view
.pages
)
3468 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3469 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3470 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3471 vma
->ggtt_view
.pages
=
3472 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
3473 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3474 vma
->ggtt_view
.pages
=
3475 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3477 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3478 vma
->ggtt_view
.type
);
3480 if (!vma
->ggtt_view
.pages
) {
3481 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3482 vma
->ggtt_view
.type
);
3484 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3485 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3486 vma
->ggtt_view
.pages
= NULL
;
3487 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3488 vma
->ggtt_view
.type
, ret
);
3495 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3497 * @cache_level: mapping cache level
3498 * @flags: flags like global or local mapping
3500 * DMA addresses are taken from the scatter-gather table of this object (or of
3501 * this VMA in case of non-default GGTT views) and PTE entries set up.
3502 * Note that DMA addresses are also the only part of the SG table we care about.
3504 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3510 if (WARN_ON(flags
== 0))
3514 if (flags
& PIN_GLOBAL
)
3515 bind_flags
|= GLOBAL_BIND
;
3516 if (flags
& PIN_USER
)
3517 bind_flags
|= LOCAL_BIND
;
3519 if (flags
& PIN_UPDATE
)
3520 bind_flags
|= vma
->bound
;
3522 bind_flags
&= ~vma
->bound
;
3524 if (bind_flags
== 0)
3527 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3528 trace_i915_va_alloc(vma
->vm
,
3531 VM_TO_TRACE_NAME(vma
->vm
));
3533 /* XXX: i915_vma_pin() will fix this +- hack */
3535 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3543 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3547 vma
->bound
|= bind_flags
;
3553 * i915_ggtt_view_size - Get the size of a GGTT view.
3554 * @obj: Object the view is of.
3555 * @view: The view in question.
3557 * @return The size of the GGTT view in bytes.
3560 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3561 const struct i915_ggtt_view
*view
)
3563 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3564 return obj
->base
.size
;
3565 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3566 return view
->rotation_info
.size
;
3567 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3568 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3570 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3571 return obj
->base
.size
;