2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 typedef uint32_t gtt_pte_t
;
34 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
36 #define GEN6_PDE_VALID (1 << 0)
37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
38 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
40 #define GEN6_PTE_VALID (1 << 0)
41 #define GEN6_PTE_UNCACHED (1 << 1)
42 #define HSW_PTE_UNCACHED (0)
43 #define GEN6_PTE_CACHE_LLC (2 << 1)
44 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
45 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
47 static inline gtt_pte_t
gen6_pte_encode(struct drm_device
*dev
,
49 enum i915_cache_level level
)
51 gtt_pte_t pte
= GEN6_PTE_VALID
;
52 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
55 case I915_CACHE_LLC_MLC
:
56 /* Haswell doesn't set L3 this way */
58 pte
|= GEN6_PTE_CACHE_LLC
;
60 pte
|= GEN6_PTE_CACHE_LLC_MLC
;
63 pte
|= GEN6_PTE_CACHE_LLC
;
67 pte
|= HSW_PTE_UNCACHED
;
69 pte
|= GEN6_PTE_UNCACHED
;
79 /* PPGTT support for Sandybdrige/Gen6 and later */
80 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt
*ppgtt
,
85 gtt_pte_t scratch_pte
;
86 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
87 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
90 scratch_pte
= gen6_pte_encode(ppgtt
->dev
,
91 ppgtt
->scratch_page_dma_addr
,
95 last_pte
= first_pte
+ num_entries
;
96 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
97 last_pte
= I915_PPGTT_PT_ENTRIES
;
99 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
101 for (i
= first_pte
; i
< last_pte
; i
++)
102 pt_vaddr
[i
] = scratch_pte
;
104 kunmap_atomic(pt_vaddr
);
106 num_entries
-= last_pte
- first_pte
;
112 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt
*ppgtt
,
113 struct sg_table
*pages
,
114 unsigned first_entry
,
115 enum i915_cache_level cache_level
)
118 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
119 unsigned act_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
120 struct sg_page_iter sg_iter
;
122 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
123 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
124 dma_addr_t page_addr
;
126 page_addr
= sg_page_iter_dma_address(&sg_iter
);
127 pt_vaddr
[act_pte
] = gen6_pte_encode(ppgtt
->dev
, page_addr
,
129 if (++act_pte
== I915_PPGTT_PT_ENTRIES
) {
130 kunmap_atomic(pt_vaddr
);
132 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
137 kunmap_atomic(pt_vaddr
);
140 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt
*ppgtt
)
144 if (ppgtt
->pt_dma_addr
) {
145 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
146 pci_unmap_page(ppgtt
->dev
->pdev
,
147 ppgtt
->pt_dma_addr
[i
],
148 4096, PCI_DMA_BIDIRECTIONAL
);
151 kfree(ppgtt
->pt_dma_addr
);
152 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
153 __free_page(ppgtt
->pt_pages
[i
]);
154 kfree(ppgtt
->pt_pages
);
158 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
160 struct drm_device
*dev
= ppgtt
->dev
;
161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
162 unsigned first_pd_entry_in_global_pt
;
166 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
167 * entries. For aliasing ppgtt support we just steal them at the end for
169 first_pd_entry_in_global_pt
=
170 gtt_total_entries(dev_priv
->gtt
) - I915_PPGTT_PD_ENTRIES
;
172 ppgtt
->num_pd_entries
= I915_PPGTT_PD_ENTRIES
;
173 ppgtt
->clear_range
= gen6_ppgtt_clear_range
;
174 ppgtt
->insert_entries
= gen6_ppgtt_insert_entries
;
175 ppgtt
->cleanup
= gen6_ppgtt_cleanup
;
176 ppgtt
->pt_pages
= kzalloc(sizeof(struct page
*)*ppgtt
->num_pd_entries
,
178 if (!ppgtt
->pt_pages
)
181 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
182 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
183 if (!ppgtt
->pt_pages
[i
])
187 ppgtt
->pt_dma_addr
= kzalloc(sizeof(dma_addr_t
) *ppgtt
->num_pd_entries
,
189 if (!ppgtt
->pt_dma_addr
)
192 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
195 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
196 PCI_DMA_BIDIRECTIONAL
);
198 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
203 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
206 ppgtt
->scratch_page_dma_addr
= dev_priv
->gtt
.scratch_page_dma
;
208 ppgtt
->clear_range(ppgtt
, 0,
209 ppgtt
->num_pd_entries
*I915_PPGTT_PT_ENTRIES
);
211 ppgtt
->pd_offset
= (first_pd_entry_in_global_pt
)*sizeof(gtt_pte_t
);
216 if (ppgtt
->pt_dma_addr
) {
217 for (i
--; i
>= 0; i
--)
218 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
219 4096, PCI_DMA_BIDIRECTIONAL
);
222 kfree(ppgtt
->pt_dma_addr
);
223 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
224 if (ppgtt
->pt_pages
[i
])
225 __free_page(ppgtt
->pt_pages
[i
]);
227 kfree(ppgtt
->pt_pages
);
232 static int i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
)
234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
235 struct i915_hw_ppgtt
*ppgtt
;
238 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
244 ret
= gen6_ppgtt_init(ppgtt
);
248 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
253 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
)
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
256 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
261 ppgtt
->cleanup(ppgtt
);
264 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
265 struct drm_i915_gem_object
*obj
,
266 enum i915_cache_level cache_level
)
268 ppgtt
->insert_entries(ppgtt
, obj
->pages
,
269 obj
->gtt_space
->start
>> PAGE_SHIFT
,
273 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
274 struct drm_i915_gem_object
*obj
)
276 ppgtt
->clear_range(ppgtt
,
277 obj
->gtt_space
->start
>> PAGE_SHIFT
,
278 obj
->base
.size
>> PAGE_SHIFT
);
281 void i915_gem_init_ppgtt(struct drm_device
*dev
)
283 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
285 struct intel_ring_buffer
*ring
;
286 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
287 gtt_pte_t __iomem
*pd_addr
;
291 if (!dev_priv
->mm
.aliasing_ppgtt
)
295 pd_addr
= (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ ppgtt
->pd_offset
/sizeof(gtt_pte_t
);
296 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
299 pt_addr
= ppgtt
->pt_dma_addr
[i
];
300 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
301 pd_entry
|= GEN6_PDE_VALID
;
303 writel(pd_entry
, pd_addr
+ i
);
307 pd_offset
= ppgtt
->pd_offset
;
308 pd_offset
/= 64; /* in cachelines, */
311 if (INTEL_INFO(dev
)->gen
== 6) {
312 uint32_t ecochk
, gab_ctl
, ecobits
;
314 ecobits
= I915_READ(GAC_ECO_BITS
);
315 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
317 gab_ctl
= I915_READ(GAB_CTL
);
318 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
320 ecochk
= I915_READ(GAM_ECOCHK
);
321 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
322 ECOCHK_PPGTT_CACHE64B
);
323 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
324 } else if (INTEL_INFO(dev
)->gen
>= 7) {
325 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
326 /* GFX_MODE is per-ring on gen7+ */
329 for_each_ring(ring
, dev_priv
, i
) {
330 if (INTEL_INFO(dev
)->gen
>= 7)
331 I915_WRITE(RING_MODE_GEN7(ring
),
332 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
334 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
335 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
339 extern int intel_iommu_gfx_mapped
;
340 /* Certain Gen5 chipsets require require idling the GPU before
341 * unmapping anything from the GTT when VT-d is enabled.
343 static inline bool needs_idle_maps(struct drm_device
*dev
)
345 #ifdef CONFIG_INTEL_IOMMU
346 /* Query intel_iommu to see if we need the workaround. Presumably that
349 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
355 static bool do_idling(struct drm_i915_private
*dev_priv
)
357 bool ret
= dev_priv
->mm
.interruptible
;
359 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
360 dev_priv
->mm
.interruptible
= false;
361 if (i915_gpu_idle(dev_priv
->dev
)) {
362 DRM_ERROR("Couldn't idle GPU\n");
363 /* Wait a bit, in hopes it avoids the hang */
371 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
373 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
374 dev_priv
->mm
.interruptible
= interruptible
;
377 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
380 struct drm_i915_gem_object
*obj
;
382 /* First fill our portion of the GTT with scratch pages */
383 dev_priv
->gtt
.gtt_clear_range(dev
, dev_priv
->gtt
.start
/ PAGE_SIZE
,
384 dev_priv
->gtt
.total
/ PAGE_SIZE
);
386 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
387 i915_gem_clflush_object(obj
);
388 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
391 i915_gem_chipset_flush(dev
);
394 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
396 if (obj
->has_dma_mapping
)
399 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
400 obj
->pages
->sgl
, obj
->pages
->nents
,
401 PCI_DMA_BIDIRECTIONAL
))
408 * Binds an object into the global gtt with the specified cache level. The object
409 * will be accessible to the GPU via commands whose operands reference offsets
410 * within the global GTT as well as accessible by the GPU through the GMADR
411 * mapped BAR (dev_priv->mm.gtt->gtt).
413 static void gen6_ggtt_insert_entries(struct drm_device
*dev
,
415 unsigned int first_entry
,
416 enum i915_cache_level level
)
418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
419 gtt_pte_t __iomem
*gtt_entries
=
420 (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
422 struct sg_page_iter sg_iter
;
425 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
426 addr
= sg_page_iter_dma_address(&sg_iter
);
427 iowrite32(gen6_pte_encode(dev
, addr
, level
), >t_entries
[i
]);
431 /* XXX: This serves as a posting read to make sure that the PTE has
432 * actually been updated. There is some concern that even though
433 * registers and PTEs are within the same BAR that they are potentially
434 * of NUMA access patterns. Therefore, even with the way we assume
435 * hardware should work, we must keep this posting read for paranoia.
438 WARN_ON(readl(>t_entries
[i
-1])
439 != gen6_pte_encode(dev
, addr
, level
));
441 /* This next bit makes the above posting read even more important. We
442 * want to flush the TLBs only after we're certain all the PTE updates
445 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
446 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
449 static void gen6_ggtt_clear_range(struct drm_device
*dev
,
450 unsigned int first_entry
,
451 unsigned int num_entries
)
453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
454 gtt_pte_t scratch_pte
;
455 gtt_pte_t __iomem
*gtt_base
= (gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
456 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
459 if (WARN(num_entries
> max_entries
,
460 "First entry = %d; Num entries = %d (max=%d)\n",
461 first_entry
, num_entries
, max_entries
))
462 num_entries
= max_entries
;
464 scratch_pte
= gen6_pte_encode(dev
, dev_priv
->gtt
.scratch_page_dma
,
466 for (i
= 0; i
< num_entries
; i
++)
467 iowrite32(scratch_pte
, >t_base
[i
]);
472 static void i915_ggtt_insert_entries(struct drm_device
*dev
,
474 unsigned int pg_start
,
475 enum i915_cache_level cache_level
)
477 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
478 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
480 intel_gtt_insert_sg_entries(st
, pg_start
, flags
);
484 static void i915_ggtt_clear_range(struct drm_device
*dev
,
485 unsigned int first_entry
,
486 unsigned int num_entries
)
488 intel_gtt_clear_range(first_entry
, num_entries
);
492 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
493 enum i915_cache_level cache_level
)
495 struct drm_device
*dev
= obj
->base
.dev
;
496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
498 dev_priv
->gtt
.gtt_insert_entries(dev
, obj
->pages
,
499 obj
->gtt_space
->start
>> PAGE_SHIFT
,
502 obj
->has_global_gtt_mapping
= 1;
505 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
)
507 struct drm_device
*dev
= obj
->base
.dev
;
508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
510 dev_priv
->gtt
.gtt_clear_range(obj
->base
.dev
,
511 obj
->gtt_space
->start
>> PAGE_SHIFT
,
512 obj
->base
.size
>> PAGE_SHIFT
);
514 obj
->has_global_gtt_mapping
= 0;
517 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
519 struct drm_device
*dev
= obj
->base
.dev
;
520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
523 interruptible
= do_idling(dev_priv
);
525 if (!obj
->has_dma_mapping
)
526 dma_unmap_sg(&dev
->pdev
->dev
,
527 obj
->pages
->sgl
, obj
->pages
->nents
,
528 PCI_DMA_BIDIRECTIONAL
);
530 undo_idling(dev_priv
, interruptible
);
533 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
535 unsigned long *start
,
538 if (node
->color
!= color
)
541 if (!list_empty(&node
->node_list
)) {
542 node
= list_entry(node
->node_list
.next
,
545 if (node
->allocated
&& node
->color
!= color
)
549 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
551 unsigned long mappable_end
,
554 /* Let GEM Manage all of the aperture.
556 * However, leave one page at the end still bound to the scratch page.
557 * There are a number of places where the hardware apparently prefetches
558 * past the end of the object, and we've seen multiple hangs with the
559 * GPU head pointer stuck in a batchbuffer bound at the last page of the
560 * aperture. One page should be enough to keep any prefetching inside
563 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
564 struct drm_mm_node
*entry
;
565 struct drm_i915_gem_object
*obj
;
566 unsigned long hole_start
, hole_end
;
568 BUG_ON(mappable_end
> end
);
570 /* Subtract the guard page ... */
571 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
- PAGE_SIZE
);
573 dev_priv
->mm
.gtt_space
.color_adjust
= i915_gtt_color_adjust
;
575 /* Mark any preallocated objects as occupied */
576 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
577 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
578 obj
->gtt_offset
, obj
->base
.size
);
580 BUG_ON(obj
->gtt_space
!= I915_GTT_RESERVED
);
581 obj
->gtt_space
= drm_mm_create_block(&dev_priv
->mm
.gtt_space
,
585 obj
->has_global_gtt_mapping
= 1;
588 dev_priv
->gtt
.start
= start
;
589 dev_priv
->gtt
.total
= end
- start
;
591 /* Clear any non-preallocated blocks */
592 drm_mm_for_each_hole(entry
, &dev_priv
->mm
.gtt_space
,
593 hole_start
, hole_end
) {
594 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
595 hole_start
, hole_end
);
596 dev_priv
->gtt
.gtt_clear_range(dev
, hole_start
/ PAGE_SIZE
,
597 (hole_end
-hole_start
) / PAGE_SIZE
);
600 /* And finally clear the reserved guard page */
601 dev_priv
->gtt
.gtt_clear_range(dev
, end
/ PAGE_SIZE
- 1, 1);
605 intel_enable_ppgtt(struct drm_device
*dev
)
607 if (i915_enable_ppgtt
>= 0)
608 return i915_enable_ppgtt
;
610 #ifdef CONFIG_INTEL_IOMMU
611 /* Disable ppgtt on SNB if VT-d is on. */
612 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
619 void i915_gem_init_global_gtt(struct drm_device
*dev
)
621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
622 unsigned long gtt_size
, mappable_size
;
624 gtt_size
= dev_priv
->gtt
.total
;
625 mappable_size
= dev_priv
->gtt
.mappable_end
;
627 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
629 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
630 * aperture accordingly when using aliasing ppgtt. */
631 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
633 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
635 ret
= i915_gem_init_aliasing_ppgtt(dev
);
639 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret
);
640 drm_mm_takedown(&dev_priv
->mm
.gtt_space
);
641 gtt_size
+= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
643 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
646 static int setup_scratch_page(struct drm_device
*dev
)
648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
652 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
656 set_pages_uc(page
, 1);
658 #ifdef CONFIG_INTEL_IOMMU
659 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
660 PCI_DMA_BIDIRECTIONAL
);
661 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
664 dma_addr
= page_to_phys(page
);
666 dev_priv
->gtt
.scratch_page
= page
;
667 dev_priv
->gtt
.scratch_page_dma
= dma_addr
;
672 static void teardown_scratch_page(struct drm_device
*dev
)
674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
675 set_pages_wb(dev_priv
->gtt
.scratch_page
, 1);
676 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.scratch_page_dma
,
677 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
678 put_page(dev_priv
->gtt
.scratch_page
);
679 __free_page(dev_priv
->gtt
.scratch_page
);
682 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
684 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
685 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
686 return snb_gmch_ctl
<< 20;
689 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
691 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
692 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
693 return snb_gmch_ctl
<< 25; /* 32 MB units */
696 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl
)
698 static const int stolen_decoder
[] = {
699 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
700 snb_gmch_ctl
>>= IVB_GMCH_GMS_SHIFT
;
701 snb_gmch_ctl
&= IVB_GMCH_GMS_MASK
;
702 return stolen_decoder
[snb_gmch_ctl
] << 20;
705 static int gen6_gmch_probe(struct drm_device
*dev
,
708 phys_addr_t
*mappable_base
,
709 unsigned long *mappable_end
)
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 phys_addr_t gtt_bus_addr
;
713 unsigned int gtt_size
;
717 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
718 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
720 /* 64/512MB is the current min/max we actually know of, but this is just
721 * a coarse sanity check.
723 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
724 DRM_ERROR("Unknown GMADR size (%lx)\n",
725 dev_priv
->gtt
.mappable_end
);
729 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
730 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
731 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
732 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
734 if (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
))
735 *stolen
= gen7_get_stolen_size(snb_gmch_ctl
);
737 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
739 *gtt_total
= (gtt_size
/ sizeof(gtt_pte_t
)) << PAGE_SHIFT
;
741 /* For Modern GENs the PTEs and register space are split in the BAR */
742 gtt_bus_addr
= pci_resource_start(dev
->pdev
, 0) +
743 (pci_resource_len(dev
->pdev
, 0) / 2);
745 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_bus_addr
, gtt_size
);
746 if (!dev_priv
->gtt
.gsm
) {
747 DRM_ERROR("Failed to map the gtt page table\n");
751 ret
= setup_scratch_page(dev
);
753 DRM_ERROR("Scratch setup failed\n");
755 dev_priv
->gtt
.gtt_clear_range
= gen6_ggtt_clear_range
;
756 dev_priv
->gtt
.gtt_insert_entries
= gen6_ggtt_insert_entries
;
761 static void gen6_gmch_remove(struct drm_device
*dev
)
763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
764 iounmap(dev_priv
->gtt
.gsm
);
765 teardown_scratch_page(dev_priv
->dev
);
768 static int i915_gmch_probe(struct drm_device
*dev
,
771 phys_addr_t
*mappable_base
,
772 unsigned long *mappable_end
)
774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
777 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
779 DRM_ERROR("failed to set up gmch\n");
783 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
785 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
786 dev_priv
->gtt
.gtt_clear_range
= i915_ggtt_clear_range
;
787 dev_priv
->gtt
.gtt_insert_entries
= i915_ggtt_insert_entries
;
792 static void i915_gmch_remove(struct drm_device
*dev
)
797 int i915_gem_gtt_init(struct drm_device
*dev
)
799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
800 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
801 unsigned long gtt_size
;
804 if (INTEL_INFO(dev
)->gen
<= 5) {
805 dev_priv
->gtt
.gtt_probe
= i915_gmch_probe
;
806 dev_priv
->gtt
.gtt_remove
= i915_gmch_remove
;
808 dev_priv
->gtt
.gtt_probe
= gen6_gmch_probe
;
809 dev_priv
->gtt
.gtt_remove
= gen6_gmch_remove
;
812 ret
= dev_priv
->gtt
.gtt_probe(dev
, &dev_priv
->gtt
.total
,
813 &dev_priv
->gtt
.stolen_size
,
819 gtt_size
= (dev_priv
->gtt
.total
>> PAGE_SHIFT
) * sizeof(gtt_pte_t
);
821 /* GMADR is the PCI mmio aperture into the global GTT. */
822 DRM_INFO("Memory usable by graphics device = %zdM\n",
823 dev_priv
->gtt
.total
>> 20);
824 DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
825 dev_priv
->gtt
.mappable_end
>> 20);
826 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
827 dev_priv
->gtt
.stolen_size
>> 20);