2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
196 const enum i915_cache_level level
)
198 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
200 if (level
!= I915_CACHE_NONE
)
201 pde
|= PPAT_CACHED_PDE_INDEX
;
203 pde
|= PPAT_UNCACHED_INDEX
;
207 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
208 enum i915_cache_level level
,
209 bool valid
, u32 unused
)
211 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
212 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
215 case I915_CACHE_L3_LLC
:
217 pte
|= GEN6_PTE_CACHE_LLC
;
219 case I915_CACHE_NONE
:
220 pte
|= GEN6_PTE_UNCACHED
;
229 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
230 enum i915_cache_level level
,
231 bool valid
, u32 unused
)
233 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
234 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
237 case I915_CACHE_L3_LLC
:
238 pte
|= GEN7_PTE_CACHE_L3_LLC
;
241 pte
|= GEN6_PTE_CACHE_LLC
;
243 case I915_CACHE_NONE
:
244 pte
|= GEN6_PTE_UNCACHED
;
253 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
254 enum i915_cache_level level
,
255 bool valid
, u32 flags
)
257 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
258 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
260 if (!(flags
& PTE_READ_ONLY
))
261 pte
|= BYT_PTE_WRITEABLE
;
263 if (level
!= I915_CACHE_NONE
)
264 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
269 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
270 enum i915_cache_level level
,
271 bool valid
, u32 unused
)
273 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
274 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
276 if (level
!= I915_CACHE_NONE
)
277 pte
|= HSW_WB_LLC_AGE3
;
282 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
283 enum i915_cache_level level
,
284 bool valid
, u32 unused
)
286 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
287 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
290 case I915_CACHE_NONE
:
293 pte
|= HSW_WT_ELLC_LLC_AGE3
;
296 pte
|= HSW_WB_ELLC_LLC_AGE3
;
303 static int __setup_page_dma(struct drm_device
*dev
,
304 struct i915_page_dma
*p
, gfp_t flags
)
306 struct device
*device
= &dev
->pdev
->dev
;
308 p
->page
= alloc_page(flags
);
312 p
->daddr
= dma_map_page(device
,
313 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
315 if (dma_mapping_error(device
, p
->daddr
)) {
316 __free_page(p
->page
);
323 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
325 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
328 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
330 if (WARN_ON(!p
->page
))
333 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
334 __free_page(p
->page
);
335 memset(p
, 0, sizeof(*p
));
338 static void *kmap_page_dma(struct i915_page_dma
*p
)
340 return kmap_atomic(p
->page
);
343 /* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
346 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
351 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
352 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
354 kunmap_atomic(vaddr
);
357 #define kmap_px(px) kmap_page_dma(px_base(px))
358 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
360 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
365 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
369 uint64_t * const vaddr
= kmap_page_dma(p
);
371 for (i
= 0; i
< 512; i
++)
374 kunmap_page_dma(dev
, vaddr
);
377 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
378 const uint32_t val32
)
384 fill_page_dma(dev
, p
, v
);
387 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
390 kfree(pt
->used_ptes
);
394 static void gen8_initialize_pt(struct i915_address_space
*vm
,
395 struct i915_page_table
*pt
)
397 gen8_pte_t scratch_pte
;
399 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
400 I915_CACHE_LLC
, true);
402 fill_px(vm
->dev
, pt
, scratch_pte
);
405 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
407 struct i915_page_table
*pt
;
408 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
409 GEN8_PTES
: GEN6_PTES
;
412 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
414 return ERR_PTR(-ENOMEM
);
416 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
422 ret
= setup_px(dev
, pt
);
429 kfree(pt
->used_ptes
);
436 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
440 kfree(pd
->used_pdes
);
445 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
447 struct i915_page_directory
*pd
;
450 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
452 return ERR_PTR(-ENOMEM
);
454 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
455 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
459 ret
= setup_px(dev
, pd
);
466 kfree(pd
->used_pdes
);
473 /* Broadwell Page Directory Pointer Descriptors */
474 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
478 struct intel_engine_cs
*ring
= req
->ring
;
483 ret
= intel_ring_begin(req
, 6);
487 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
488 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
489 intel_ring_emit(ring
, upper_32_bits(addr
));
490 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
491 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
492 intel_ring_emit(ring
, lower_32_bits(addr
));
493 intel_ring_advance(ring
);
498 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
499 struct drm_i915_gem_request
*req
)
503 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
504 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
506 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
514 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
519 struct i915_hw_ppgtt
*ppgtt
=
520 container_of(vm
, struct i915_hw_ppgtt
, base
);
521 gen8_pte_t
*pt_vaddr
, scratch_pte
;
522 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
523 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
524 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
525 unsigned num_entries
= length
>> PAGE_SHIFT
;
526 unsigned last_pte
, i
;
528 scratch_pte
= gen8_pte_encode(px_dma(ppgtt
->base
.scratch_page
),
529 I915_CACHE_LLC
, use_scratch
);
531 while (num_entries
) {
532 struct i915_page_directory
*pd
;
533 struct i915_page_table
*pt
;
535 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
538 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
540 if (WARN_ON(!pd
->page_table
[pde
]))
543 pt
= pd
->page_table
[pde
];
545 if (WARN_ON(!px_page(pt
)))
548 last_pte
= pte
+ num_entries
;
549 if (last_pte
> GEN8_PTES
)
550 last_pte
= GEN8_PTES
;
552 pt_vaddr
= kmap_px(pt
);
554 for (i
= pte
; i
< last_pte
; i
++) {
555 pt_vaddr
[i
] = scratch_pte
;
559 kunmap_px(ppgtt
, pt
);
562 if (++pde
== I915_PDES
) {
569 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
570 struct sg_table
*pages
,
572 enum i915_cache_level cache_level
, u32 unused
)
574 struct i915_hw_ppgtt
*ppgtt
=
575 container_of(vm
, struct i915_hw_ppgtt
, base
);
576 gen8_pte_t
*pt_vaddr
;
577 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
578 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
579 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
580 struct sg_page_iter sg_iter
;
584 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
585 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
588 if (pt_vaddr
== NULL
) {
589 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
590 struct i915_page_table
*pt
= pd
->page_table
[pde
];
591 pt_vaddr
= kmap_px(pt
);
595 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
597 if (++pte
== GEN8_PTES
) {
598 kunmap_px(ppgtt
, pt_vaddr
);
600 if (++pde
== I915_PDES
) {
609 kunmap_px(ppgtt
, pt_vaddr
);
612 static void gen8_initialize_pd(struct i915_address_space
*vm
,
613 struct i915_page_directory
*pd
)
615 gen8_pde_t scratch_pde
;
617 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
619 fill_px(vm
->dev
, pd
, scratch_pde
);
622 static void gen8_free_page_tables(struct i915_page_directory
*pd
, struct drm_device
*dev
)
629 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
630 if (WARN_ON(!pd
->page_table
[i
]))
633 free_pt(dev
, pd
->page_table
[i
]);
634 pd
->page_table
[i
] = NULL
;
638 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
640 struct i915_hw_ppgtt
*ppgtt
=
641 container_of(vm
, struct i915_hw_ppgtt
, base
);
644 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
, GEN8_LEGACY_PDPES
) {
645 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
648 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
649 free_pd(ppgtt
->base
.dev
, ppgtt
->pdp
.page_directory
[i
]);
652 free_pd(vm
->dev
, vm
->scratch_pd
);
653 free_pt(vm
->dev
, vm
->scratch_pt
);
657 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
658 * @ppgtt: Master ppgtt structure.
659 * @pd: Page directory for this address range.
660 * @start: Starting virtual address to begin allocations.
661 * @length Size of the allocations.
662 * @new_pts: Bitmap set by function with new allocations. Likely used by the
663 * caller to free on error.
665 * Allocate the required number of page tables. Extremely similar to
666 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
667 * the page directory boundary (instead of the page directory pointer). That
668 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
669 * possible, and likely that the caller will need to use multiple calls of this
670 * function to achieve the appropriate allocation.
672 * Return: 0 if success; negative error code otherwise.
674 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
675 struct i915_page_directory
*pd
,
678 unsigned long *new_pts
)
680 struct drm_device
*dev
= ppgtt
->base
.dev
;
681 struct i915_page_table
*pt
;
685 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
686 /* Don't reallocate page tables */
688 /* Scratch is never allocated this way */
689 WARN_ON(pt
== ppgtt
->base
.scratch_pt
);
697 gen8_initialize_pt(&ppgtt
->base
, pt
);
698 pd
->page_table
[pde
] = pt
;
699 set_bit(pde
, new_pts
);
705 for_each_set_bit(pde
, new_pts
, I915_PDES
)
706 free_pt(dev
, pd
->page_table
[pde
]);
712 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
713 * @ppgtt: Master ppgtt structure.
714 * @pdp: Page directory pointer for this address range.
715 * @start: Starting virtual address to begin allocations.
716 * @length Size of the allocations.
717 * @new_pds Bitmap set by function with new allocations. Likely used by the
718 * caller to free on error.
720 * Allocate the required number of page directories starting at the pde index of
721 * @start, and ending at the pde index @start + @length. This function will skip
722 * over already allocated page directories within the range, and only allocate
723 * new ones, setting the appropriate pointer within the pdp as well as the
724 * correct position in the bitmap @new_pds.
726 * The function will only allocate the pages within the range for a give page
727 * directory pointer. In other words, if @start + @length straddles a virtually
728 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
729 * required by the caller, This is not currently possible, and the BUG in the
730 * code will prevent it.
732 * Return: 0 if success; negative error code otherwise.
734 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
735 struct i915_page_directory_pointer
*pdp
,
738 unsigned long *new_pds
)
740 struct drm_device
*dev
= ppgtt
->base
.dev
;
741 struct i915_page_directory
*pd
;
745 WARN_ON(!bitmap_empty(new_pds
, GEN8_LEGACY_PDPES
));
747 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
755 gen8_initialize_pd(&ppgtt
->base
, pd
);
756 pdp
->page_directory
[pdpe
] = pd
;
757 set_bit(pdpe
, new_pds
);
763 for_each_set_bit(pdpe
, new_pds
, GEN8_LEGACY_PDPES
)
764 free_pd(dev
, pdp
->page_directory
[pdpe
]);
770 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
)
774 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++)
780 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
781 * of these are based on the number of PDPEs in the system.
784 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
785 unsigned long ***new_pts
)
791 pds
= kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES
), sizeof(unsigned long), GFP_KERNEL
);
795 pts
= kcalloc(GEN8_LEGACY_PDPES
, sizeof(unsigned long *), GFP_KERNEL
);
801 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
802 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
803 sizeof(unsigned long), GFP_KERNEL
);
814 free_gen8_temp_bitmaps(pds
, pts
);
818 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
819 * the page table structures, we mark them dirty so that
820 * context switching/execlist queuing code takes extra steps
821 * to ensure that tlbs are flushed.
823 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
825 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
828 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
832 struct i915_hw_ppgtt
*ppgtt
=
833 container_of(vm
, struct i915_hw_ppgtt
, base
);
834 unsigned long *new_page_dirs
, **new_page_tables
;
835 struct i915_page_directory
*pd
;
836 const uint64_t orig_start
= start
;
837 const uint64_t orig_length
= length
;
842 /* Wrap is never okay since we can only represent 48b, and we don't
843 * actually use the other side of the canonical address space.
845 if (WARN_ON(start
+ length
< start
))
848 if (WARN_ON(start
+ length
> ppgtt
->base
.total
))
851 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
);
855 /* Do the allocations first so we can easily bail out */
856 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
859 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
863 /* For every page directory referenced, allocate page tables */
864 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
865 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
866 new_page_tables
[pdpe
]);
872 length
= orig_length
;
874 /* Allocations have completed successfully, so set the bitmaps, and do
876 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
877 gen8_pde_t
*const page_directory
= kmap_px(pd
);
878 struct i915_page_table
*pt
;
879 uint64_t pd_len
= gen8_clamp_pd(start
, length
);
880 uint64_t pd_start
= start
;
883 /* Every pd should be allocated, we just did that above. */
886 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
887 /* Same reasoning as pd */
890 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
892 /* Set our used ptes within the page table */
893 bitmap_set(pt
->used_ptes
,
894 gen8_pte_index(pd_start
),
895 gen8_pte_count(pd_start
, pd_len
));
897 /* Our pde is now pointing to the pagetable, pt */
898 set_bit(pde
, pd
->used_pdes
);
900 /* Map the PDE to the page table */
901 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
904 /* NB: We haven't yet mapped ptes to pages. At this
905 * point we're still relying on insert_entries() */
908 kunmap_px(ppgtt
, page_directory
);
910 set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
913 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
914 mark_tlbs_dirty(ppgtt
);
919 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
920 free_pt(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
]);
923 for_each_set_bit(pdpe
, new_page_dirs
, GEN8_LEGACY_PDPES
)
924 free_pd(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]);
926 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
927 mark_tlbs_dirty(ppgtt
);
932 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
933 * with a net effect resembling a 2-level page table in normal x86 terms. Each
934 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
938 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
940 ppgtt
->base
.scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
941 if (IS_ERR(ppgtt
->base
.scratch_pt
))
942 return PTR_ERR(ppgtt
->base
.scratch_pt
);
944 ppgtt
->base
.scratch_pd
= alloc_pd(ppgtt
->base
.dev
);
945 if (IS_ERR(ppgtt
->base
.scratch_pd
))
946 return PTR_ERR(ppgtt
->base
.scratch_pd
);
948 gen8_initialize_pt(&ppgtt
->base
, ppgtt
->base
.scratch_pt
);
949 gen8_initialize_pd(&ppgtt
->base
, ppgtt
->base
.scratch_pd
);
951 ppgtt
->base
.start
= 0;
952 ppgtt
->base
.total
= 1ULL << 32;
953 if (IS_ENABLED(CONFIG_X86_32
))
954 /* While we have a proliferation of size_t variables
955 * we cannot represent the full ppgtt size on 32bit,
956 * so limit it to the same size as the GGTT (currently
959 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
960 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
961 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
962 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
963 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
964 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
965 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
967 ppgtt
->switch_mm
= gen8_mm_switch
;
972 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
974 struct i915_address_space
*vm
= &ppgtt
->base
;
975 struct i915_page_table
*unused
;
976 gen6_pte_t scratch_pte
;
978 uint32_t pte
, pde
, temp
;
979 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
981 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
982 I915_CACHE_LLC
, true, 0);
984 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
986 gen6_pte_t
*pt_vaddr
;
987 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
988 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
989 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
991 if (pd_entry
!= expected
)
992 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
996 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
998 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1000 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1002 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1006 for (i
= 0; i
< 4; i
++)
1007 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1012 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1013 for (i
= 0; i
< 4; i
++) {
1014 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1015 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1017 seq_puts(m
, " SCRATCH ");
1021 kunmap_px(ppgtt
, pt_vaddr
);
1025 /* Write pde (index) from the page directory @pd to the page table @pt */
1026 static void gen6_write_pde(struct i915_page_directory
*pd
,
1027 const int pde
, struct i915_page_table
*pt
)
1029 /* Caller needs to make sure the write completes if necessary */
1030 struct i915_hw_ppgtt
*ppgtt
=
1031 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1034 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1035 pd_entry
|= GEN6_PDE_VALID
;
1037 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1040 /* Write all the page tables found in the ppgtt structure to incrementing page
1042 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1043 struct i915_page_directory
*pd
,
1044 uint32_t start
, uint32_t length
)
1046 struct i915_page_table
*pt
;
1049 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1050 gen6_write_pde(pd
, pde
, pt
);
1052 /* Make sure write is complete before other code can use this page
1053 * table. Also require for WC mapped PTEs */
1054 readl(dev_priv
->gtt
.gsm
);
1057 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1059 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1061 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1064 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1065 struct drm_i915_gem_request
*req
)
1067 struct intel_engine_cs
*ring
= req
->ring
;
1070 /* NB: TLBs must be flushed and invalidated before a switch */
1071 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1075 ret
= intel_ring_begin(req
, 6);
1079 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1080 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1081 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1082 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1083 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1084 intel_ring_emit(ring
, MI_NOOP
);
1085 intel_ring_advance(ring
);
1090 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1091 struct drm_i915_gem_request
*req
)
1093 struct intel_engine_cs
*ring
= req
->ring
;
1094 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1096 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1097 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1101 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1102 struct drm_i915_gem_request
*req
)
1104 struct intel_engine_cs
*ring
= req
->ring
;
1107 /* NB: TLBs must be flushed and invalidated before a switch */
1108 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1112 ret
= intel_ring_begin(req
, 6);
1116 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1117 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1118 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1119 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1120 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1121 intel_ring_emit(ring
, MI_NOOP
);
1122 intel_ring_advance(ring
);
1124 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1125 if (ring
->id
!= RCS
) {
1126 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1134 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1135 struct drm_i915_gem_request
*req
)
1137 struct intel_engine_cs
*ring
= req
->ring
;
1138 struct drm_device
*dev
= ppgtt
->base
.dev
;
1139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1142 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1143 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1145 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1150 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1153 struct intel_engine_cs
*ring
;
1156 for_each_ring(ring
, dev_priv
, j
) {
1157 I915_WRITE(RING_MODE_GEN7(ring
),
1158 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1162 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1165 struct intel_engine_cs
*ring
;
1166 uint32_t ecochk
, ecobits
;
1169 ecobits
= I915_READ(GAC_ECO_BITS
);
1170 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1172 ecochk
= I915_READ(GAM_ECOCHK
);
1173 if (IS_HASWELL(dev
)) {
1174 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1176 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1177 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1179 I915_WRITE(GAM_ECOCHK
, ecochk
);
1181 for_each_ring(ring
, dev_priv
, i
) {
1182 /* GFX_MODE is per-ring on gen7+ */
1183 I915_WRITE(RING_MODE_GEN7(ring
),
1184 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1188 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1191 uint32_t ecochk
, gab_ctl
, ecobits
;
1193 ecobits
= I915_READ(GAC_ECO_BITS
);
1194 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1195 ECOBITS_PPGTT_CACHE64B
);
1197 gab_ctl
= I915_READ(GAB_CTL
);
1198 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1200 ecochk
= I915_READ(GAM_ECOCHK
);
1201 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1203 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1206 /* PPGTT support for Sandybdrige/Gen6 and later */
1207 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1212 struct i915_hw_ppgtt
*ppgtt
=
1213 container_of(vm
, struct i915_hw_ppgtt
, base
);
1214 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1215 unsigned first_entry
= start
>> PAGE_SHIFT
;
1216 unsigned num_entries
= length
>> PAGE_SHIFT
;
1217 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1218 unsigned first_pte
= first_entry
% GEN6_PTES
;
1219 unsigned last_pte
, i
;
1221 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1222 I915_CACHE_LLC
, true, 0);
1224 while (num_entries
) {
1225 last_pte
= first_pte
+ num_entries
;
1226 if (last_pte
> GEN6_PTES
)
1227 last_pte
= GEN6_PTES
;
1229 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1231 for (i
= first_pte
; i
< last_pte
; i
++)
1232 pt_vaddr
[i
] = scratch_pte
;
1234 kunmap_px(ppgtt
, pt_vaddr
);
1236 num_entries
-= last_pte
- first_pte
;
1242 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1243 struct sg_table
*pages
,
1245 enum i915_cache_level cache_level
, u32 flags
)
1247 struct i915_hw_ppgtt
*ppgtt
=
1248 container_of(vm
, struct i915_hw_ppgtt
, base
);
1249 gen6_pte_t
*pt_vaddr
;
1250 unsigned first_entry
= start
>> PAGE_SHIFT
;
1251 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1252 unsigned act_pte
= first_entry
% GEN6_PTES
;
1253 struct sg_page_iter sg_iter
;
1256 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1257 if (pt_vaddr
== NULL
)
1258 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1261 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1262 cache_level
, true, flags
);
1264 if (++act_pte
== GEN6_PTES
) {
1265 kunmap_px(ppgtt
, pt_vaddr
);
1272 kunmap_px(ppgtt
, pt_vaddr
);
1275 static void gen6_initialize_pt(struct i915_address_space
*vm
,
1276 struct i915_page_table
*pt
)
1278 gen6_pte_t scratch_pte
;
1280 WARN_ON(px_dma(vm
->scratch_page
) == 0);
1282 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1283 I915_CACHE_LLC
, true, 0);
1285 fill32_px(vm
->dev
, pt
, scratch_pte
);
1288 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1289 uint64_t start_in
, uint64_t length_in
)
1291 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1292 struct drm_device
*dev
= vm
->dev
;
1293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1294 struct i915_hw_ppgtt
*ppgtt
=
1295 container_of(vm
, struct i915_hw_ppgtt
, base
);
1296 struct i915_page_table
*pt
;
1297 uint32_t start
, length
, start_save
, length_save
;
1301 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1304 start
= start_save
= start_in
;
1305 length
= length_save
= length_in
;
1307 bitmap_zero(new_page_tables
, I915_PDES
);
1309 /* The allocation is done in two stages so that we can bail out with
1310 * minimal amount of pain. The first stage finds new page tables that
1311 * need allocation. The second stage marks use ptes within the page
1314 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1315 if (pt
!= vm
->scratch_pt
) {
1316 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1320 /* We've already allocated a page table */
1321 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1329 gen6_initialize_pt(vm
, pt
);
1331 ppgtt
->pd
.page_table
[pde
] = pt
;
1332 set_bit(pde
, new_page_tables
);
1333 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1337 length
= length_save
;
1339 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1340 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1342 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1343 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1344 gen6_pte_count(start
, length
));
1346 if (test_and_clear_bit(pde
, new_page_tables
))
1347 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1349 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1350 gen6_pte_index(start
),
1351 gen6_pte_count(start
, length
),
1353 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1357 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1359 /* Make sure write is complete before other code can use this page
1360 * table. Also require for WC mapped PTEs */
1361 readl(dev_priv
->gtt
.gsm
);
1363 mark_tlbs_dirty(ppgtt
);
1367 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1368 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1370 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1371 free_pt(vm
->dev
, pt
);
1374 mark_tlbs_dirty(ppgtt
);
1378 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1380 struct i915_hw_ppgtt
*ppgtt
=
1381 container_of(vm
, struct i915_hw_ppgtt
, base
);
1382 struct i915_page_table
*pt
;
1385 drm_mm_remove_node(&ppgtt
->node
);
1387 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1388 if (pt
!= vm
->scratch_pt
)
1389 free_pt(ppgtt
->base
.dev
, pt
);
1392 free_pt(vm
->dev
, vm
->scratch_pt
);
1395 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1397 struct drm_device
*dev
= ppgtt
->base
.dev
;
1398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1399 bool retried
= false;
1402 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1403 * allocator works in address space sizes, so it's multiplied by page
1404 * size. We allocate at the top of the GTT to avoid fragmentation.
1406 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1407 ppgtt
->base
.scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
1408 if (IS_ERR(ppgtt
->base
.scratch_pt
))
1409 return PTR_ERR(ppgtt
->base
.scratch_pt
);
1411 gen6_initialize_pt(&ppgtt
->base
, ppgtt
->base
.scratch_pt
);
1414 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1415 &ppgtt
->node
, GEN6_PD_SIZE
,
1417 0, dev_priv
->gtt
.base
.total
,
1419 if (ret
== -ENOSPC
&& !retried
) {
1420 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1421 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1423 0, dev_priv
->gtt
.base
.total
,
1436 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1437 DRM_DEBUG("Forced to use aperture for PDEs\n");
1442 free_pt(ppgtt
->base
.dev
, ppgtt
->base
.scratch_pt
);
1446 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1448 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1451 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1452 uint64_t start
, uint64_t length
)
1454 struct i915_page_table
*unused
;
1457 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1458 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
1461 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1463 struct drm_device
*dev
= ppgtt
->base
.dev
;
1464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1469 ppgtt
->switch_mm
= gen6_mm_switch
;
1470 } else if (IS_HASWELL(dev
)) {
1471 ppgtt
->switch_mm
= hsw_mm_switch
;
1472 } else if (IS_GEN7(dev
)) {
1473 ppgtt
->switch_mm
= gen7_mm_switch
;
1477 if (intel_vgpu_active(dev
))
1478 ppgtt
->switch_mm
= vgpu_mm_switch
;
1480 ret
= gen6_ppgtt_alloc(ppgtt
);
1484 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1485 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1486 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1487 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1488 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1489 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1490 ppgtt
->base
.start
= 0;
1491 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1492 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1494 ppgtt
->pd
.base
.ggtt_offset
=
1495 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1497 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1498 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1500 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1502 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1504 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1505 ppgtt
->node
.size
>> 20,
1506 ppgtt
->node
.start
/ PAGE_SIZE
);
1508 DRM_DEBUG("Adding PPGTT at offset %x\n",
1509 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1514 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1518 ppgtt
->base
.dev
= dev
;
1519 ppgtt
->base
.scratch_page
= dev_priv
->gtt
.base
.scratch_page
;
1521 if (INTEL_INFO(dev
)->gen
< 8)
1522 return gen6_ppgtt_init(ppgtt
);
1524 return gen8_ppgtt_init(ppgtt
);
1527 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1532 ret
= __hw_ppgtt_init(dev
, ppgtt
);
1534 kref_init(&ppgtt
->ref
);
1535 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1537 i915_init_vm(dev_priv
, &ppgtt
->base
);
1543 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1545 /* In the case of execlists, PPGTT is enabled by the context descriptor
1546 * and the PDPs are contained within the context itself. We don't
1547 * need to do anything here. */
1548 if (i915
.enable_execlists
)
1551 if (!USES_PPGTT(dev
))
1555 gen6_ppgtt_enable(dev
);
1556 else if (IS_GEN7(dev
))
1557 gen7_ppgtt_enable(dev
);
1558 else if (INTEL_INFO(dev
)->gen
>= 8)
1559 gen8_ppgtt_enable(dev
);
1561 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1566 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1568 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1569 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1571 if (i915
.enable_execlists
)
1577 return ppgtt
->switch_mm(ppgtt
, req
);
1580 struct i915_hw_ppgtt
*
1581 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1583 struct i915_hw_ppgtt
*ppgtt
;
1586 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1588 return ERR_PTR(-ENOMEM
);
1590 ret
= i915_ppgtt_init(dev
, ppgtt
);
1593 return ERR_PTR(ret
);
1596 ppgtt
->file_priv
= fpriv
;
1598 trace_i915_ppgtt_create(&ppgtt
->base
);
1603 void i915_ppgtt_release(struct kref
*kref
)
1605 struct i915_hw_ppgtt
*ppgtt
=
1606 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1608 trace_i915_ppgtt_release(&ppgtt
->base
);
1610 /* vmas should already be unbound */
1611 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1612 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1614 list_del(&ppgtt
->base
.global_link
);
1615 drm_mm_takedown(&ppgtt
->base
.mm
);
1617 ppgtt
->base
.cleanup(&ppgtt
->base
);
1621 extern int intel_iommu_gfx_mapped
;
1622 /* Certain Gen5 chipsets require require idling the GPU before
1623 * unmapping anything from the GTT when VT-d is enabled.
1625 static bool needs_idle_maps(struct drm_device
*dev
)
1627 #ifdef CONFIG_INTEL_IOMMU
1628 /* Query intel_iommu to see if we need the workaround. Presumably that
1631 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1637 static bool do_idling(struct drm_i915_private
*dev_priv
)
1639 bool ret
= dev_priv
->mm
.interruptible
;
1641 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1642 dev_priv
->mm
.interruptible
= false;
1643 if (i915_gpu_idle(dev_priv
->dev
)) {
1644 DRM_ERROR("Couldn't idle GPU\n");
1645 /* Wait a bit, in hopes it avoids the hang */
1653 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1655 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1656 dev_priv
->mm
.interruptible
= interruptible
;
1659 void i915_check_and_clear_faults(struct drm_device
*dev
)
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1662 struct intel_engine_cs
*ring
;
1665 if (INTEL_INFO(dev
)->gen
< 6)
1668 for_each_ring(ring
, dev_priv
, i
) {
1670 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1671 if (fault_reg
& RING_FAULT_VALID
) {
1672 DRM_DEBUG_DRIVER("Unexpected fault\n"
1674 "\tAddress space: %s\n"
1677 fault_reg
& PAGE_MASK
,
1678 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1679 RING_FAULT_SRCID(fault_reg
),
1680 RING_FAULT_FAULT_TYPE(fault_reg
));
1681 I915_WRITE(RING_FAULT_REG(ring
),
1682 fault_reg
& ~RING_FAULT_VALID
);
1685 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1688 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1690 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1691 intel_gtt_chipset_flush();
1693 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1694 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1698 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1702 /* Don't bother messing with faults pre GEN6 as we have little
1703 * documentation supporting that it's a good idea.
1705 if (INTEL_INFO(dev
)->gen
< 6)
1708 i915_check_and_clear_faults(dev
);
1710 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1711 dev_priv
->gtt
.base
.start
,
1712 dev_priv
->gtt
.base
.total
,
1715 i915_ggtt_flush(dev_priv
);
1718 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1720 if (obj
->has_dma_mapping
)
1723 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1724 obj
->pages
->sgl
, obj
->pages
->nents
,
1725 PCI_DMA_BIDIRECTIONAL
))
1731 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1736 iowrite32((u32
)pte
, addr
);
1737 iowrite32(pte
>> 32, addr
+ 4);
1741 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1742 struct sg_table
*st
,
1744 enum i915_cache_level level
, u32 unused
)
1746 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1747 unsigned first_entry
= start
>> PAGE_SHIFT
;
1748 gen8_pte_t __iomem
*gtt_entries
=
1749 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1751 struct sg_page_iter sg_iter
;
1752 dma_addr_t addr
= 0; /* shut up gcc */
1754 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1755 addr
= sg_dma_address(sg_iter
.sg
) +
1756 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1757 gen8_set_pte(>t_entries
[i
],
1758 gen8_pte_encode(addr
, level
, true));
1763 * XXX: This serves as a posting read to make sure that the PTE has
1764 * actually been updated. There is some concern that even though
1765 * registers and PTEs are within the same BAR that they are potentially
1766 * of NUMA access patterns. Therefore, even with the way we assume
1767 * hardware should work, we must keep this posting read for paranoia.
1770 WARN_ON(readq(>t_entries
[i
-1])
1771 != gen8_pte_encode(addr
, level
, true));
1773 /* This next bit makes the above posting read even more important. We
1774 * want to flush the TLBs only after we're certain all the PTE updates
1777 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1778 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1782 * Binds an object into the global gtt with the specified cache level. The object
1783 * will be accessible to the GPU via commands whose operands reference offsets
1784 * within the global GTT as well as accessible by the GPU through the GMADR
1785 * mapped BAR (dev_priv->mm.gtt->gtt).
1787 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1788 struct sg_table
*st
,
1790 enum i915_cache_level level
, u32 flags
)
1792 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1793 unsigned first_entry
= start
>> PAGE_SHIFT
;
1794 gen6_pte_t __iomem
*gtt_entries
=
1795 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1797 struct sg_page_iter sg_iter
;
1798 dma_addr_t addr
= 0;
1800 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1801 addr
= sg_page_iter_dma_address(&sg_iter
);
1802 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1806 /* XXX: This serves as a posting read to make sure that the PTE has
1807 * actually been updated. There is some concern that even though
1808 * registers and PTEs are within the same BAR that they are potentially
1809 * of NUMA access patterns. Therefore, even with the way we assume
1810 * hardware should work, we must keep this posting read for paranoia.
1813 unsigned long gtt
= readl(>t_entries
[i
-1]);
1814 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1817 /* This next bit makes the above posting read even more important. We
1818 * want to flush the TLBs only after we're certain all the PTE updates
1821 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1822 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1825 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1830 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1831 unsigned first_entry
= start
>> PAGE_SHIFT
;
1832 unsigned num_entries
= length
>> PAGE_SHIFT
;
1833 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1834 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1835 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1838 if (WARN(num_entries
> max_entries
,
1839 "First entry = %d; Num entries = %d (max=%d)\n",
1840 first_entry
, num_entries
, max_entries
))
1841 num_entries
= max_entries
;
1843 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1846 for (i
= 0; i
< num_entries
; i
++)
1847 gen8_set_pte(>t_base
[i
], scratch_pte
);
1851 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1856 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1857 unsigned first_entry
= start
>> PAGE_SHIFT
;
1858 unsigned num_entries
= length
>> PAGE_SHIFT
;
1859 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1860 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1861 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1864 if (WARN(num_entries
> max_entries
,
1865 "First entry = %d; Num entries = %d (max=%d)\n",
1866 first_entry
, num_entries
, max_entries
))
1867 num_entries
= max_entries
;
1869 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1870 I915_CACHE_LLC
, use_scratch
, 0);
1872 for (i
= 0; i
< num_entries
; i
++)
1873 iowrite32(scratch_pte
, >t_base
[i
]);
1877 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
1878 struct sg_table
*pages
,
1880 enum i915_cache_level cache_level
, u32 unused
)
1882 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1883 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1885 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
1889 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1894 unsigned first_entry
= start
>> PAGE_SHIFT
;
1895 unsigned num_entries
= length
>> PAGE_SHIFT
;
1896 intel_gtt_clear_range(first_entry
, num_entries
);
1899 static int ggtt_bind_vma(struct i915_vma
*vma
,
1900 enum i915_cache_level cache_level
,
1903 struct drm_device
*dev
= vma
->vm
->dev
;
1904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1905 struct drm_i915_gem_object
*obj
= vma
->obj
;
1906 struct sg_table
*pages
= obj
->pages
;
1910 ret
= i915_get_ggtt_vma_pages(vma
);
1913 pages
= vma
->ggtt_view
.pages
;
1915 /* Currently applicable only to VLV */
1917 pte_flags
|= PTE_READ_ONLY
;
1920 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1921 vma
->vm
->insert_entries(vma
->vm
, pages
,
1923 cache_level
, pte_flags
);
1926 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
1927 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1928 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
1930 cache_level
, pte_flags
);
1936 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1938 struct drm_device
*dev
= vma
->vm
->dev
;
1939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1940 struct drm_i915_gem_object
*obj
= vma
->obj
;
1941 const uint64_t size
= min_t(uint64_t,
1945 if (vma
->bound
& GLOBAL_BIND
) {
1946 vma
->vm
->clear_range(vma
->vm
,
1952 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
1953 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1955 appgtt
->base
.clear_range(&appgtt
->base
,
1962 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1964 struct drm_device
*dev
= obj
->base
.dev
;
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1968 interruptible
= do_idling(dev_priv
);
1970 if (!obj
->has_dma_mapping
)
1971 dma_unmap_sg(&dev
->pdev
->dev
,
1972 obj
->pages
->sgl
, obj
->pages
->nents
,
1973 PCI_DMA_BIDIRECTIONAL
);
1975 undo_idling(dev_priv
, interruptible
);
1978 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1979 unsigned long color
,
1983 if (node
->color
!= color
)
1986 if (!list_empty(&node
->node_list
)) {
1987 node
= list_entry(node
->node_list
.next
,
1990 if (node
->allocated
&& node
->color
!= color
)
1995 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
1996 unsigned long start
,
1997 unsigned long mappable_end
,
2000 /* Let GEM Manage all of the aperture.
2002 * However, leave one page at the end still bound to the scratch page.
2003 * There are a number of places where the hardware apparently prefetches
2004 * past the end of the object, and we've seen multiple hangs with the
2005 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2006 * aperture. One page should be enough to keep any prefetching inside
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2011 struct drm_mm_node
*entry
;
2012 struct drm_i915_gem_object
*obj
;
2013 unsigned long hole_start
, hole_end
;
2016 BUG_ON(mappable_end
> end
);
2018 /* Subtract the guard page ... */
2019 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2021 dev_priv
->gtt
.base
.start
= start
;
2022 dev_priv
->gtt
.base
.total
= end
- start
;
2024 if (intel_vgpu_active(dev
)) {
2025 ret
= intel_vgt_balloon(dev
);
2031 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2033 /* Mark any preallocated objects as occupied */
2034 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2035 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2037 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2038 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2040 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2041 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2043 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2046 vma
->bound
|= GLOBAL_BIND
;
2049 /* Clear any non-preallocated blocks */
2050 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2051 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2052 hole_start
, hole_end
);
2053 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2054 hole_end
- hole_start
, true);
2057 /* And finally clear the reserved guard page */
2058 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2060 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2061 struct i915_hw_ppgtt
*ppgtt
;
2063 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2067 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2069 ppgtt
->base
.cleanup(&ppgtt
->base
);
2074 if (ppgtt
->base
.allocate_va_range
)
2075 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2078 ppgtt
->base
.cleanup(&ppgtt
->base
);
2083 ppgtt
->base
.clear_range(&ppgtt
->base
,
2088 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2094 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2097 u64 gtt_size
, mappable_size
;
2099 gtt_size
= dev_priv
->gtt
.base
.total
;
2100 mappable_size
= dev_priv
->gtt
.mappable_end
;
2102 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2105 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2108 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2110 if (dev_priv
->mm
.aliasing_ppgtt
) {
2111 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2113 ppgtt
->base
.cleanup(&ppgtt
->base
);
2116 if (drm_mm_initialized(&vm
->mm
)) {
2117 if (intel_vgpu_active(dev
))
2118 intel_vgt_deballoon();
2120 drm_mm_takedown(&vm
->mm
);
2121 list_del(&vm
->global_link
);
2127 static int alloc_scratch_page(struct i915_address_space
*vm
)
2129 struct i915_page_scratch
*sp
;
2132 WARN_ON(vm
->scratch_page
);
2134 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
2138 ret
= __setup_page_dma(vm
->dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
2144 set_pages_uc(px_page(sp
), 1);
2146 vm
->scratch_page
= sp
;
2151 static void free_scratch_page(struct i915_address_space
*vm
)
2153 struct i915_page_scratch
*sp
= vm
->scratch_page
;
2155 set_pages_wb(px_page(sp
), 1);
2157 cleanup_px(vm
->dev
, sp
);
2160 vm
->scratch_page
= NULL
;
2163 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2165 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2166 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2167 return snb_gmch_ctl
<< 20;
2170 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2172 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2173 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2175 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2177 #ifdef CONFIG_X86_32
2178 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2179 if (bdw_gmch_ctl
> 4)
2183 return bdw_gmch_ctl
<< 20;
2186 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2188 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2189 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2192 return 1 << (20 + gmch_ctrl
);
2197 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2199 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2200 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2201 return snb_gmch_ctl
<< 25; /* 32 MB units */
2204 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2206 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2207 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2208 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2211 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2213 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2214 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2217 * 0x0 to 0x10: 32MB increments starting at 0MB
2218 * 0x11 to 0x16: 4MB increments starting at 8MB
2219 * 0x17 to 0x1d: 4MB increments start at 36MB
2221 if (gmch_ctrl
< 0x11)
2222 return gmch_ctrl
<< 25;
2223 else if (gmch_ctrl
< 0x17)
2224 return (gmch_ctrl
- 0x11 + 2) << 22;
2226 return (gmch_ctrl
- 0x17 + 9) << 22;
2229 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2231 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2232 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2234 if (gen9_gmch_ctl
< 0xf0)
2235 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2237 /* 4MB increments starting at 0xf0 for 4MB */
2238 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2241 static int ggtt_probe_common(struct drm_device
*dev
,
2244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2245 phys_addr_t gtt_phys_addr
;
2248 /* For Modern GENs the PTEs and register space are split in the BAR */
2249 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2250 (pci_resource_len(dev
->pdev
, 0) / 2);
2253 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2254 * dropped. For WC mappings in general we have 64 byte burst writes
2255 * when the WC buffer is flushed, so we can't use it, but have to
2256 * resort to an uncached mapping. The WC issue is easily caught by the
2257 * readback check when writing GTT PTE entries.
2259 if (IS_BROXTON(dev
))
2260 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2262 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2263 if (!dev_priv
->gtt
.gsm
) {
2264 DRM_ERROR("Failed to map the gtt page table\n");
2268 ret
= alloc_scratch_page(&dev_priv
->gtt
.base
);
2270 DRM_ERROR("Scratch setup failed\n");
2271 /* iounmap will also get called at remove, but meh */
2272 iounmap(dev_priv
->gtt
.gsm
);
2278 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2279 * bits. When using advanced contexts each context stores its own PAT, but
2280 * writing this data shouldn't be harmful even in those cases. */
2281 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2285 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2286 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2287 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2288 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2289 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2290 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2291 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2292 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2294 if (!USES_PPGTT(dev_priv
->dev
))
2295 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2296 * so RTL will always use the value corresponding to
2298 * So let's disable cache for GGTT to avoid screen corruptions.
2299 * MOCS still can be used though.
2300 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2301 * before this patch, i.e. the same uncached + snooping access
2302 * like on gen6/7 seems to be in effect.
2303 * - So this just fixes blitter/render access. Again it looks
2304 * like it's not just uncached access, but uncached + snooping.
2305 * So we can still hold onto all our assumptions wrt cpu
2306 * clflushing on LLC machines.
2308 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2310 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2311 * write would work. */
2312 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2313 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2316 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2321 * Map WB on BDW to snooped on CHV.
2323 * Only the snoop bit has meaning for CHV, the rest is
2326 * The hardware will never snoop for certain types of accesses:
2327 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2328 * - PPGTT page tables
2329 * - some other special cycles
2331 * As with BDW, we also need to consider the following for GT accesses:
2332 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2333 * so RTL will always use the value corresponding to
2335 * Which means we must set the snoop bit in PAT entry 0
2336 * in order to keep the global status page working.
2338 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2342 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2343 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2344 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2345 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2347 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2348 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2351 static int gen8_gmch_probe(struct drm_device
*dev
,
2354 phys_addr_t
*mappable_base
,
2357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2362 /* TODO: We're not aware of mappable constraints on gen8 yet */
2363 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2364 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2366 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2367 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2369 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2371 if (INTEL_INFO(dev
)->gen
>= 9) {
2372 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2373 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2374 } else if (IS_CHERRYVIEW(dev
)) {
2375 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2376 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2378 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2379 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2382 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2384 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2385 chv_setup_private_ppat(dev_priv
);
2387 bdw_setup_private_ppat(dev_priv
);
2389 ret
= ggtt_probe_common(dev
, gtt_size
);
2391 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2392 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2393 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2394 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2399 static int gen6_gmch_probe(struct drm_device
*dev
,
2402 phys_addr_t
*mappable_base
,
2405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2406 unsigned int gtt_size
;
2410 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2411 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2413 /* 64/512MB is the current min/max we actually know of, but this is just
2414 * a coarse sanity check.
2416 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2417 DRM_ERROR("Unknown GMADR size (%llx)\n",
2418 dev_priv
->gtt
.mappable_end
);
2422 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2423 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2424 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2426 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2428 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2429 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2431 ret
= ggtt_probe_common(dev
, gtt_size
);
2433 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2434 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2435 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2436 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2441 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2444 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2447 free_scratch_page(vm
);
2450 static int i915_gmch_probe(struct drm_device
*dev
,
2453 phys_addr_t
*mappable_base
,
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2459 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2461 DRM_ERROR("failed to set up gmch\n");
2465 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2467 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2468 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2469 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2470 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2471 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2473 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2474 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2479 static void i915_gmch_remove(struct i915_address_space
*vm
)
2481 intel_gmch_remove();
2484 int i915_gem_gtt_init(struct drm_device
*dev
)
2486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2487 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2490 if (INTEL_INFO(dev
)->gen
<= 5) {
2491 gtt
->gtt_probe
= i915_gmch_probe
;
2492 gtt
->base
.cleanup
= i915_gmch_remove
;
2493 } else if (INTEL_INFO(dev
)->gen
< 8) {
2494 gtt
->gtt_probe
= gen6_gmch_probe
;
2495 gtt
->base
.cleanup
= gen6_gmch_remove
;
2496 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2497 gtt
->base
.pte_encode
= iris_pte_encode
;
2498 else if (IS_HASWELL(dev
))
2499 gtt
->base
.pte_encode
= hsw_pte_encode
;
2500 else if (IS_VALLEYVIEW(dev
))
2501 gtt
->base
.pte_encode
= byt_pte_encode
;
2502 else if (INTEL_INFO(dev
)->gen
>= 7)
2503 gtt
->base
.pte_encode
= ivb_pte_encode
;
2505 gtt
->base
.pte_encode
= snb_pte_encode
;
2507 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2508 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2511 gtt
->base
.dev
= dev
;
2513 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2514 >t
->mappable_base
, >t
->mappable_end
);
2518 /* GMADR is the PCI mmio aperture into the global GTT. */
2519 DRM_INFO("Memory usable by graphics device = %lluM\n",
2520 gtt
->base
.total
>> 20);
2521 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
2522 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2523 #ifdef CONFIG_INTEL_IOMMU
2524 if (intel_iommu_gfx_mapped
)
2525 DRM_INFO("VT-d active for gfx access\n");
2528 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2529 * user's requested state against the hardware/driver capabilities. We
2530 * do this now so that we can print out any log messages once rather
2531 * than every time we check intel_enable_ppgtt().
2533 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2534 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2539 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2542 struct drm_i915_gem_object
*obj
;
2543 struct i915_address_space
*vm
;
2545 i915_check_and_clear_faults(dev
);
2547 /* First fill our portion of the GTT with scratch pages */
2548 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2549 dev_priv
->gtt
.base
.start
,
2550 dev_priv
->gtt
.base
.total
,
2553 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2554 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
2555 &dev_priv
->gtt
.base
);
2559 i915_gem_clflush_object(obj
, obj
->pin_display
);
2560 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, PIN_UPDATE
));
2564 if (INTEL_INFO(dev
)->gen
>= 8) {
2565 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2566 chv_setup_private_ppat(dev_priv
);
2568 bdw_setup_private_ppat(dev_priv
);
2573 if (USES_PPGTT(dev
)) {
2574 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2575 /* TODO: Perhaps it shouldn't be gen6 specific */
2577 struct i915_hw_ppgtt
*ppgtt
=
2578 container_of(vm
, struct i915_hw_ppgtt
,
2581 if (i915_is_ggtt(vm
))
2582 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2584 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2585 0, ppgtt
->base
.total
);
2589 i915_ggtt_flush(dev_priv
);
2592 static struct i915_vma
*
2593 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2594 struct i915_address_space
*vm
,
2595 const struct i915_ggtt_view
*ggtt_view
)
2597 struct i915_vma
*vma
;
2599 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2600 return ERR_PTR(-EINVAL
);
2602 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
2604 return ERR_PTR(-ENOMEM
);
2606 INIT_LIST_HEAD(&vma
->vma_link
);
2607 INIT_LIST_HEAD(&vma
->mm_list
);
2608 INIT_LIST_HEAD(&vma
->exec_list
);
2612 if (i915_is_ggtt(vm
))
2613 vma
->ggtt_view
= *ggtt_view
;
2615 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2616 if (!i915_is_ggtt(vm
))
2617 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2623 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2624 struct i915_address_space
*vm
)
2626 struct i915_vma
*vma
;
2628 vma
= i915_gem_obj_to_vma(obj
, vm
);
2630 vma
= __i915_gem_vma_create(obj
, vm
,
2631 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2637 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2638 const struct i915_ggtt_view
*view
)
2640 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2641 struct i915_vma
*vma
;
2644 return ERR_PTR(-EINVAL
);
2646 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2652 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2659 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2660 struct sg_table
*st
)
2662 unsigned int column
, row
;
2663 unsigned int src_idx
;
2664 struct scatterlist
*sg
= st
->sgl
;
2668 for (column
= 0; column
< width
; column
++) {
2669 src_idx
= width
* (height
- 1) + column
;
2670 for (row
= 0; row
< height
; row
++) {
2672 /* We don't need the pages, but need to initialize
2673 * the entries so the sg list can be happily traversed.
2674 * The only thing we need are DMA addresses.
2676 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2677 sg_dma_address(sg
) = in
[src_idx
];
2678 sg_dma_len(sg
) = PAGE_SIZE
;
2685 static struct sg_table
*
2686 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2687 struct drm_i915_gem_object
*obj
)
2689 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2690 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
2691 struct sg_page_iter sg_iter
;
2693 dma_addr_t
*page_addr_list
;
2694 struct sg_table
*st
;
2697 /* Allocate a temporary list of source pages for random access. */
2698 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
2699 sizeof(dma_addr_t
));
2700 if (!page_addr_list
)
2701 return ERR_PTR(ret
);
2703 /* Allocate target SG list. */
2704 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2708 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
2712 /* Populate source page list from the object. */
2714 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2715 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2719 /* Rotate the pages. */
2720 rotate_pages(page_addr_list
,
2721 rot_info
->width_pages
, rot_info
->height_pages
,
2725 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2726 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
2727 rot_info
->pixel_format
, rot_info
->width_pages
,
2728 rot_info
->height_pages
, size_pages
);
2730 drm_free_large(page_addr_list
);
2737 drm_free_large(page_addr_list
);
2740 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2741 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
2742 rot_info
->pixel_format
, rot_info
->width_pages
,
2743 rot_info
->height_pages
, size_pages
);
2744 return ERR_PTR(ret
);
2747 static struct sg_table
*
2748 intel_partial_pages(const struct i915_ggtt_view
*view
,
2749 struct drm_i915_gem_object
*obj
)
2751 struct sg_table
*st
;
2752 struct scatterlist
*sg
;
2753 struct sg_page_iter obj_sg_iter
;
2756 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2760 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2766 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2767 view
->params
.partial
.offset
)
2769 if (st
->nents
>= view
->params
.partial
.size
)
2772 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2773 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2774 sg_dma_len(sg
) = PAGE_SIZE
;
2785 return ERR_PTR(ret
);
2789 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2793 if (vma
->ggtt_view
.pages
)
2796 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2797 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2798 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2799 vma
->ggtt_view
.pages
=
2800 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2801 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2802 vma
->ggtt_view
.pages
=
2803 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2805 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2806 vma
->ggtt_view
.type
);
2808 if (!vma
->ggtt_view
.pages
) {
2809 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2810 vma
->ggtt_view
.type
);
2812 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2813 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2814 vma
->ggtt_view
.pages
= NULL
;
2815 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2816 vma
->ggtt_view
.type
, ret
);
2823 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2825 * @cache_level: mapping cache level
2826 * @flags: flags like global or local mapping
2828 * DMA addresses are taken from the scatter-gather table of this object (or of
2829 * this VMA in case of non-default GGTT views) and PTE entries set up.
2830 * Note that DMA addresses are also the only part of the SG table we care about.
2832 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2838 if (WARN_ON(flags
== 0))
2842 if (flags
& PIN_GLOBAL
)
2843 bind_flags
|= GLOBAL_BIND
;
2844 if (flags
& PIN_USER
)
2845 bind_flags
|= LOCAL_BIND
;
2847 if (flags
& PIN_UPDATE
)
2848 bind_flags
|= vma
->bound
;
2850 bind_flags
&= ~vma
->bound
;
2852 if (bind_flags
== 0)
2855 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
2856 trace_i915_va_alloc(vma
->vm
,
2859 VM_TO_TRACE_NAME(vma
->vm
));
2861 /* XXX: i915_vma_pin() will fix this +- hack */
2863 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
2871 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
2875 vma
->bound
|= bind_flags
;
2881 * i915_ggtt_view_size - Get the size of a GGTT view.
2882 * @obj: Object the view is of.
2883 * @view: The view in question.
2885 * @return The size of the GGTT view in bytes.
2888 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
2889 const struct i915_ggtt_view
*view
)
2891 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
2892 return obj
->base
.size
;
2893 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
2894 return view
->rotation_info
.size
;
2895 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
2896 return view
->params
.partial
.size
<< PAGE_SHIFT
;
2898 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
2899 return obj
->base
.size
;