2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
35 #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM)
38 * DOC: Global GTT views
40 * Background and previous state
42 * Historically objects could exists (be bound) in global GTT space only as
43 * singular instances with a view representing all of the object's backing pages
44 * in a linear fashion. This view will be called a normal view.
46 * To support multiple views of the same object, where the number of mapped
47 * pages is not equal to the backing store, or where the layout of the pages
48 * is not linear, concept of a GGTT view was added.
50 * One example of an alternative view is a stereo display driven by a single
51 * image. In this case we would have a framebuffer looking like this
57 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
58 * rendering. In contrast, fed to the display engine would be an alternative
59 * view which could look something like this:
64 * In this example both the size and layout of pages in the alternative view is
65 * different from the normal view.
67 * Implementation and usage
69 * GGTT views are implemented using VMAs and are distinguished via enum
70 * i915_ggtt_view_type and struct i915_ggtt_view.
72 * A new flavour of core GEM functions which work with GGTT bound objects were
73 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
74 * renaming in large amounts of code. They take the struct i915_ggtt_view
75 * parameter encapsulating all metadata required to implement a view.
77 * As a helper for callers which are only interested in the normal view,
78 * globally const i915_ggtt_view_normal singleton instance exists. All old core
79 * GEM API functions, the ones not taking the view parameter, are operating on,
80 * or with the normal GGTT view.
82 * Code wanting to add or use a new GGTT view needs to:
84 * 1. Add a new enum with a suitable name.
85 * 2. Extend the metadata in the i915_ggtt_view structure if required.
86 * 3. Add support to i915_get_vma_pages().
88 * New views are required to build a scatter-gather table from within the
89 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
90 * exists for the lifetime of an VMA.
92 * Core API is designed to have copy semantics which means that passed in
93 * struct i915_ggtt_view does not need to be persistent (left around after
94 * calling the core API functions).
98 static inline struct i915_ggtt
*
99 i915_vm_to_ggtt(struct i915_address_space
*vm
)
101 GEM_BUG_ON(!i915_is_ggtt(vm
));
102 return container_of(vm
, struct i915_ggtt
, base
);
106 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
108 const struct i915_ggtt_view i915_ggtt_view_normal
= {
109 .type
= I915_GGTT_VIEW_NORMAL
,
111 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
112 .type
= I915_GGTT_VIEW_ROTATED
,
115 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
118 bool has_aliasing_ppgtt
;
120 bool has_full_48bit_ppgtt
;
122 has_aliasing_ppgtt
= INTEL_GEN(dev_priv
) >= 6;
123 has_full_ppgtt
= INTEL_GEN(dev_priv
) >= 7;
124 has_full_48bit_ppgtt
=
125 IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9;
127 if (intel_vgpu_active(dev_priv
))
128 has_full_ppgtt
= false; /* emulation is too hard */
130 if (!has_aliasing_ppgtt
)
134 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
135 * execlists, the sole mechanism available to submit work.
137 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
140 if (enable_ppgtt
== 1)
143 if (enable_ppgtt
== 2 && has_full_ppgtt
)
146 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
149 #ifdef CONFIG_INTEL_IOMMU
150 /* Disable ppgtt on SNB if VT-d is on. */
151 if (IS_GEN6(dev_priv
) && intel_iommu_gfx_mapped
) {
152 DRM_INFO("Disabling PPGTT because VT-d is on\n");
157 /* Early VLV doesn't have this */
158 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
159 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
163 if (INTEL_GEN(dev_priv
) >= 8 && i915
.enable_execlists
)
164 return has_full_48bit_ppgtt
? 3 : 2;
166 return has_aliasing_ppgtt
? 1 : 0;
169 static int ppgtt_bind_vma(struct i915_vma
*vma
,
170 enum i915_cache_level cache_level
,
175 vma
->pages
= vma
->obj
->pages
;
177 /* Currently applicable only to VLV */
179 pte_flags
|= PTE_READ_ONLY
;
181 vma
->vm
->insert_entries(vma
->vm
, vma
->pages
, vma
->node
.start
,
182 cache_level
, pte_flags
);
187 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
189 vma
->vm
->clear_range(vma
->vm
,
195 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
196 enum i915_cache_level level
,
199 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
203 case I915_CACHE_NONE
:
204 pte
|= PPAT_UNCACHED_INDEX
;
207 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
210 pte
|= PPAT_CACHED_INDEX
;
217 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
218 const enum i915_cache_level level
)
220 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
222 if (level
!= I915_CACHE_NONE
)
223 pde
|= PPAT_CACHED_PDE_INDEX
;
225 pde
|= PPAT_UNCACHED_INDEX
;
229 #define gen8_pdpe_encode gen8_pde_encode
230 #define gen8_pml4e_encode gen8_pde_encode
232 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
233 enum i915_cache_level level
,
234 bool valid
, u32 unused
)
236 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
237 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
240 case I915_CACHE_L3_LLC
:
242 pte
|= GEN6_PTE_CACHE_LLC
;
244 case I915_CACHE_NONE
:
245 pte
|= GEN6_PTE_UNCACHED
;
254 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
255 enum i915_cache_level level
,
256 bool valid
, u32 unused
)
258 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
259 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
262 case I915_CACHE_L3_LLC
:
263 pte
|= GEN7_PTE_CACHE_L3_LLC
;
266 pte
|= GEN6_PTE_CACHE_LLC
;
268 case I915_CACHE_NONE
:
269 pte
|= GEN6_PTE_UNCACHED
;
278 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
279 enum i915_cache_level level
,
280 bool valid
, u32 flags
)
282 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
283 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
285 if (!(flags
& PTE_READ_ONLY
))
286 pte
|= BYT_PTE_WRITEABLE
;
288 if (level
!= I915_CACHE_NONE
)
289 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
294 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
295 enum i915_cache_level level
,
296 bool valid
, u32 unused
)
298 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
299 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
301 if (level
!= I915_CACHE_NONE
)
302 pte
|= HSW_WB_LLC_AGE3
;
307 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
308 enum i915_cache_level level
,
309 bool valid
, u32 unused
)
311 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
312 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
315 case I915_CACHE_NONE
:
318 pte
|= HSW_WT_ELLC_LLC_AGE3
;
321 pte
|= HSW_WB_ELLC_LLC_AGE3
;
328 static int __setup_page_dma(struct drm_device
*dev
,
329 struct i915_page_dma
*p
, gfp_t flags
)
331 struct device
*kdev
= &dev
->pdev
->dev
;
333 p
->page
= alloc_page(flags
);
337 p
->daddr
= dma_map_page(kdev
,
338 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
340 if (dma_mapping_error(kdev
, p
->daddr
)) {
341 __free_page(p
->page
);
348 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
350 return __setup_page_dma(dev
, p
, I915_GFP_DMA
);
353 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
355 struct pci_dev
*pdev
= dev
->pdev
;
357 if (WARN_ON(!p
->page
))
360 dma_unmap_page(&pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
361 __free_page(p
->page
);
362 memset(p
, 0, sizeof(*p
));
365 static void *kmap_page_dma(struct i915_page_dma
*p
)
367 return kmap_atomic(p
->page
);
370 /* We use the flushing unmap only with ppgtt structures:
371 * page directories, page tables and scratch pages.
373 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
375 /* There are only few exceptions for gen >=6. chv and bxt.
376 * And we are not sure about the latter so play safe for now.
378 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
379 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
381 kunmap_atomic(vaddr
);
384 #define kmap_px(px) kmap_page_dma(px_base(px))
385 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
387 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
388 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
389 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
390 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
392 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
396 uint64_t * const vaddr
= kmap_page_dma(p
);
398 for (i
= 0; i
< 512; i
++)
401 kunmap_page_dma(dev
, vaddr
);
404 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
405 const uint32_t val32
)
411 fill_page_dma(dev
, p
, v
);
415 setup_scratch_page(struct drm_device
*dev
,
416 struct i915_page_dma
*scratch
,
419 return __setup_page_dma(dev
, scratch
, gfp
| __GFP_ZERO
);
422 static void cleanup_scratch_page(struct drm_device
*dev
,
423 struct i915_page_dma
*scratch
)
425 cleanup_page_dma(dev
, scratch
);
428 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
430 struct i915_page_table
*pt
;
431 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
432 GEN8_PTES
: GEN6_PTES
;
435 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
437 return ERR_PTR(-ENOMEM
);
439 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
445 ret
= setup_px(dev
, pt
);
452 kfree(pt
->used_ptes
);
459 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
462 kfree(pt
->used_ptes
);
466 static void gen8_initialize_pt(struct i915_address_space
*vm
,
467 struct i915_page_table
*pt
)
469 gen8_pte_t scratch_pte
;
471 scratch_pte
= gen8_pte_encode(vm
->scratch_page
.daddr
,
472 I915_CACHE_LLC
, true);
474 fill_px(vm
->dev
, pt
, scratch_pte
);
477 static void gen6_initialize_pt(struct i915_address_space
*vm
,
478 struct i915_page_table
*pt
)
480 gen6_pte_t scratch_pte
;
482 WARN_ON(vm
->scratch_page
.daddr
== 0);
484 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
485 I915_CACHE_LLC
, true, 0);
487 fill32_px(vm
->dev
, pt
, scratch_pte
);
490 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
492 struct i915_page_directory
*pd
;
495 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
497 return ERR_PTR(-ENOMEM
);
499 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
500 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
504 ret
= setup_px(dev
, pd
);
511 kfree(pd
->used_pdes
);
518 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
522 kfree(pd
->used_pdes
);
527 static void gen8_initialize_pd(struct i915_address_space
*vm
,
528 struct i915_page_directory
*pd
)
530 gen8_pde_t scratch_pde
;
532 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
534 fill_px(vm
->dev
, pd
, scratch_pde
);
537 static int __pdp_init(struct drm_device
*dev
,
538 struct i915_page_directory_pointer
*pdp
)
540 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
542 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
543 sizeof(unsigned long),
545 if (!pdp
->used_pdpes
)
548 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
550 if (!pdp
->page_directory
) {
551 kfree(pdp
->used_pdpes
);
552 /* the PDP might be the statically allocated top level. Keep it
553 * as clean as possible */
554 pdp
->used_pdpes
= NULL
;
561 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
563 kfree(pdp
->used_pdpes
);
564 kfree(pdp
->page_directory
);
565 pdp
->page_directory
= NULL
;
569 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
571 struct i915_page_directory_pointer
*pdp
;
574 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
576 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
578 return ERR_PTR(-ENOMEM
);
580 ret
= __pdp_init(dev
, pdp
);
584 ret
= setup_px(dev
, pdp
);
598 static void free_pdp(struct drm_device
*dev
,
599 struct i915_page_directory_pointer
*pdp
)
602 if (USES_FULL_48BIT_PPGTT(dev
)) {
603 cleanup_px(dev
, pdp
);
608 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
609 struct i915_page_directory_pointer
*pdp
)
611 gen8_ppgtt_pdpe_t scratch_pdpe
;
613 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
615 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
618 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
619 struct i915_pml4
*pml4
)
621 gen8_ppgtt_pml4e_t scratch_pml4e
;
623 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
626 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
630 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
631 struct i915_page_directory_pointer
*pdp
,
632 struct i915_page_directory
*pd
,
635 gen8_ppgtt_pdpe_t
*page_directorypo
;
637 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
640 page_directorypo
= kmap_px(pdp
);
641 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
642 kunmap_px(ppgtt
, page_directorypo
);
646 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
647 struct i915_pml4
*pml4
,
648 struct i915_page_directory_pointer
*pdp
,
651 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
653 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
654 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
655 kunmap_px(ppgtt
, pagemap
);
658 /* Broadwell Page Directory Pointer Descriptors */
659 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
663 struct intel_ring
*ring
= req
->ring
;
664 struct intel_engine_cs
*engine
= req
->engine
;
669 ret
= intel_ring_begin(req
, 6);
673 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
674 intel_ring_emit_reg(ring
, GEN8_RING_PDP_UDW(engine
, entry
));
675 intel_ring_emit(ring
, upper_32_bits(addr
));
676 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
677 intel_ring_emit_reg(ring
, GEN8_RING_PDP_LDW(engine
, entry
));
678 intel_ring_emit(ring
, lower_32_bits(addr
));
679 intel_ring_advance(ring
);
684 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
685 struct drm_i915_gem_request
*req
)
689 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
690 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
692 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
700 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
701 struct drm_i915_gem_request
*req
)
703 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
706 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
707 struct i915_page_directory_pointer
*pdp
,
710 gen8_pte_t scratch_pte
)
712 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
713 gen8_pte_t
*pt_vaddr
;
714 unsigned pdpe
= gen8_pdpe_index(start
);
715 unsigned pde
= gen8_pde_index(start
);
716 unsigned pte
= gen8_pte_index(start
);
717 unsigned num_entries
= length
>> PAGE_SHIFT
;
718 unsigned last_pte
, i
;
723 while (num_entries
) {
724 struct i915_page_directory
*pd
;
725 struct i915_page_table
*pt
;
727 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
730 pd
= pdp
->page_directory
[pdpe
];
732 if (WARN_ON(!pd
->page_table
[pde
]))
735 pt
= pd
->page_table
[pde
];
737 if (WARN_ON(!px_page(pt
)))
740 last_pte
= pte
+ num_entries
;
741 if (last_pte
> GEN8_PTES
)
742 last_pte
= GEN8_PTES
;
744 pt_vaddr
= kmap_px(pt
);
746 for (i
= pte
; i
< last_pte
; i
++) {
747 pt_vaddr
[i
] = scratch_pte
;
751 kunmap_px(ppgtt
, pt_vaddr
);
754 if (++pde
== I915_PDES
) {
755 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
762 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
767 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
768 gen8_pte_t scratch_pte
= gen8_pte_encode(vm
->scratch_page
.daddr
,
769 I915_CACHE_LLC
, use_scratch
);
771 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
772 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
776 struct i915_page_directory_pointer
*pdp
;
778 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
779 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
786 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
787 struct i915_page_directory_pointer
*pdp
,
788 struct sg_page_iter
*sg_iter
,
790 enum i915_cache_level cache_level
)
792 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
793 gen8_pte_t
*pt_vaddr
;
794 unsigned pdpe
= gen8_pdpe_index(start
);
795 unsigned pde
= gen8_pde_index(start
);
796 unsigned pte
= gen8_pte_index(start
);
800 while (__sg_page_iter_next(sg_iter
)) {
801 if (pt_vaddr
== NULL
) {
802 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
803 struct i915_page_table
*pt
= pd
->page_table
[pde
];
804 pt_vaddr
= kmap_px(pt
);
808 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
810 if (++pte
== GEN8_PTES
) {
811 kunmap_px(ppgtt
, pt_vaddr
);
813 if (++pde
== I915_PDES
) {
814 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
823 kunmap_px(ppgtt
, pt_vaddr
);
826 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
827 struct sg_table
*pages
,
829 enum i915_cache_level cache_level
,
832 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
833 struct sg_page_iter sg_iter
;
835 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
837 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
838 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
841 struct i915_page_directory_pointer
*pdp
;
843 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
845 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
846 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
852 static void gen8_free_page_tables(struct drm_device
*dev
,
853 struct i915_page_directory
*pd
)
860 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
861 if (WARN_ON(!pd
->page_table
[i
]))
864 free_pt(dev
, pd
->page_table
[i
]);
865 pd
->page_table
[i
] = NULL
;
869 static int gen8_init_scratch(struct i915_address_space
*vm
)
871 struct drm_device
*dev
= vm
->dev
;
874 ret
= setup_scratch_page(dev
, &vm
->scratch_page
, I915_GFP_DMA
);
878 vm
->scratch_pt
= alloc_pt(dev
);
879 if (IS_ERR(vm
->scratch_pt
)) {
880 ret
= PTR_ERR(vm
->scratch_pt
);
881 goto free_scratch_page
;
884 vm
->scratch_pd
= alloc_pd(dev
);
885 if (IS_ERR(vm
->scratch_pd
)) {
886 ret
= PTR_ERR(vm
->scratch_pd
);
890 if (USES_FULL_48BIT_PPGTT(dev
)) {
891 vm
->scratch_pdp
= alloc_pdp(dev
);
892 if (IS_ERR(vm
->scratch_pdp
)) {
893 ret
= PTR_ERR(vm
->scratch_pdp
);
898 gen8_initialize_pt(vm
, vm
->scratch_pt
);
899 gen8_initialize_pd(vm
, vm
->scratch_pd
);
900 if (USES_FULL_48BIT_PPGTT(dev
))
901 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
906 free_pd(dev
, vm
->scratch_pd
);
908 free_pt(dev
, vm
->scratch_pt
);
910 cleanup_scratch_page(dev
, &vm
->scratch_page
);
915 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
917 enum vgt_g2v_type msg
;
918 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
921 if (USES_FULL_48BIT_PPGTT(dev_priv
)) {
922 u64 daddr
= px_dma(&ppgtt
->pml4
);
924 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
925 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
927 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
928 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
930 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
931 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
933 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
934 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
937 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
938 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
941 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
946 static void gen8_free_scratch(struct i915_address_space
*vm
)
948 struct drm_device
*dev
= vm
->dev
;
950 if (USES_FULL_48BIT_PPGTT(dev
))
951 free_pdp(dev
, vm
->scratch_pdp
);
952 free_pd(dev
, vm
->scratch_pd
);
953 free_pt(dev
, vm
->scratch_pt
);
954 cleanup_scratch_page(dev
, &vm
->scratch_page
);
957 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
958 struct i915_page_directory_pointer
*pdp
)
962 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
963 if (WARN_ON(!pdp
->page_directory
[i
]))
966 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
967 free_pd(dev
, pdp
->page_directory
[i
]);
973 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
977 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
978 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
981 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
984 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
987 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
989 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
991 if (intel_vgpu_active(to_i915(vm
->dev
)))
992 gen8_ppgtt_notify_vgt(ppgtt
, false);
994 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
995 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
997 gen8_ppgtt_cleanup_4lvl(ppgtt
);
999 gen8_free_scratch(vm
);
1003 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1004 * @vm: Master vm structure.
1005 * @pd: Page directory for this address range.
1006 * @start: Starting virtual address to begin allocations.
1007 * @length: Size of the allocations.
1008 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1009 * caller to free on error.
1011 * Allocate the required number of page tables. Extremely similar to
1012 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1013 * the page directory boundary (instead of the page directory pointer). That
1014 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1015 * possible, and likely that the caller will need to use multiple calls of this
1016 * function to achieve the appropriate allocation.
1018 * Return: 0 if success; negative error code otherwise.
1020 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1021 struct i915_page_directory
*pd
,
1024 unsigned long *new_pts
)
1026 struct drm_device
*dev
= vm
->dev
;
1027 struct i915_page_table
*pt
;
1030 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1031 /* Don't reallocate page tables */
1032 if (test_bit(pde
, pd
->used_pdes
)) {
1033 /* Scratch is never allocated this way */
1034 WARN_ON(pt
== vm
->scratch_pt
);
1042 gen8_initialize_pt(vm
, pt
);
1043 pd
->page_table
[pde
] = pt
;
1044 __set_bit(pde
, new_pts
);
1045 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1051 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1052 free_pt(dev
, pd
->page_table
[pde
]);
1058 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1059 * @vm: Master vm structure.
1060 * @pdp: Page directory pointer for this address range.
1061 * @start: Starting virtual address to begin allocations.
1062 * @length: Size of the allocations.
1063 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1064 * caller to free on error.
1066 * Allocate the required number of page directories starting at the pde index of
1067 * @start, and ending at the pde index @start + @length. This function will skip
1068 * over already allocated page directories within the range, and only allocate
1069 * new ones, setting the appropriate pointer within the pdp as well as the
1070 * correct position in the bitmap @new_pds.
1072 * The function will only allocate the pages within the range for a give page
1073 * directory pointer. In other words, if @start + @length straddles a virtually
1074 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1075 * required by the caller, This is not currently possible, and the BUG in the
1076 * code will prevent it.
1078 * Return: 0 if success; negative error code otherwise.
1081 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1082 struct i915_page_directory_pointer
*pdp
,
1085 unsigned long *new_pds
)
1087 struct drm_device
*dev
= vm
->dev
;
1088 struct i915_page_directory
*pd
;
1090 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1092 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1094 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1095 if (test_bit(pdpe
, pdp
->used_pdpes
))
1102 gen8_initialize_pd(vm
, pd
);
1103 pdp
->page_directory
[pdpe
] = pd
;
1104 __set_bit(pdpe
, new_pds
);
1105 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1111 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1112 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1118 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1119 * @vm: Master vm structure.
1120 * @pml4: Page map level 4 for this address range.
1121 * @start: Starting virtual address to begin allocations.
1122 * @length: Size of the allocations.
1123 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1124 * caller to free on error.
1126 * Allocate the required number of page directory pointers. Extremely similar to
1127 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1128 * The main difference is here we are limited by the pml4 boundary (instead of
1129 * the page directory pointer).
1131 * Return: 0 if success; negative error code otherwise.
1134 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1135 struct i915_pml4
*pml4
,
1138 unsigned long *new_pdps
)
1140 struct drm_device
*dev
= vm
->dev
;
1141 struct i915_page_directory_pointer
*pdp
;
1144 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1146 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1147 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1148 pdp
= alloc_pdp(dev
);
1152 gen8_initialize_pdp(vm
, pdp
);
1153 pml4
->pdps
[pml4e
] = pdp
;
1154 __set_bit(pml4e
, new_pdps
);
1155 trace_i915_page_directory_pointer_entry_alloc(vm
,
1165 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1166 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1172 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1178 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1179 * of these are based on the number of PDPEs in the system.
1182 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1183 unsigned long **new_pts
,
1189 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1193 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1204 free_gen8_temp_bitmaps(pds
, pts
);
1208 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1209 * the page table structures, we mark them dirty so that
1210 * context switching/execlist queuing code takes extra steps
1211 * to ensure that tlbs are flushed.
1213 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1215 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1218 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1219 struct i915_page_directory_pointer
*pdp
,
1223 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1224 unsigned long *new_page_dirs
, *new_page_tables
;
1225 struct drm_device
*dev
= vm
->dev
;
1226 struct i915_page_directory
*pd
;
1227 const uint64_t orig_start
= start
;
1228 const uint64_t orig_length
= length
;
1230 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1233 /* Wrap is never okay since we can only represent 48b, and we don't
1234 * actually use the other side of the canonical address space.
1236 if (WARN_ON(start
+ length
< start
))
1239 if (WARN_ON(start
+ length
> vm
->total
))
1242 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1246 /* Do the allocations first so we can easily bail out */
1247 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1250 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1254 /* For every page directory referenced, allocate page tables */
1255 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1256 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1257 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1263 length
= orig_length
;
1265 /* Allocations have completed successfully, so set the bitmaps, and do
1267 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1268 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1269 struct i915_page_table
*pt
;
1270 uint64_t pd_len
= length
;
1271 uint64_t pd_start
= start
;
1274 /* Every pd should be allocated, we just did that above. */
1277 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1278 /* Same reasoning as pd */
1281 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1283 /* Set our used ptes within the page table */
1284 bitmap_set(pt
->used_ptes
,
1285 gen8_pte_index(pd_start
),
1286 gen8_pte_count(pd_start
, pd_len
));
1288 /* Our pde is now pointing to the pagetable, pt */
1289 __set_bit(pde
, pd
->used_pdes
);
1291 /* Map the PDE to the page table */
1292 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1294 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1295 gen8_pte_index(start
),
1296 gen8_pte_count(start
, length
),
1299 /* NB: We haven't yet mapped ptes to pages. At this
1300 * point we're still relying on insert_entries() */
1303 kunmap_px(ppgtt
, page_directory
);
1304 __set_bit(pdpe
, pdp
->used_pdpes
);
1305 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1308 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1309 mark_tlbs_dirty(ppgtt
);
1316 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1317 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1318 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1321 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1322 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1324 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1325 mark_tlbs_dirty(ppgtt
);
1329 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1330 struct i915_pml4
*pml4
,
1334 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1335 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1336 struct i915_page_directory_pointer
*pdp
;
1340 /* Do the pml4 allocations first, so we don't need to track the newly
1341 * allocated tables below the pdp */
1342 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1344 /* The pagedirectory and pagetable allocations are done in the shared 3
1345 * and 4 level code. Just allocate the pdps.
1347 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1352 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1353 "The allocation has spanned more than 512GB. "
1354 "It is highly likely this is incorrect.");
1356 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1359 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1363 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1366 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1367 GEN8_PML4ES_PER_PML4
);
1372 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1373 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1378 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1379 uint64_t start
, uint64_t length
)
1381 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1383 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1384 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1386 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1389 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1390 uint64_t start
, uint64_t length
,
1391 gen8_pte_t scratch_pte
,
1394 struct i915_page_directory
*pd
;
1397 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1398 struct i915_page_table
*pt
;
1399 uint64_t pd_len
= length
;
1400 uint64_t pd_start
= start
;
1403 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1406 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1407 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1409 gen8_pte_t
*pt_vaddr
;
1411 if (!test_bit(pde
, pd
->used_pdes
))
1414 pt_vaddr
= kmap_px(pt
);
1415 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1417 (pdpe
<< GEN8_PDPE_SHIFT
) |
1418 (pde
<< GEN8_PDE_SHIFT
) |
1419 (pte
<< GEN8_PTE_SHIFT
);
1423 for (i
= 0; i
< 4; i
++)
1424 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1429 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1430 for (i
= 0; i
< 4; i
++) {
1431 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1432 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1434 seq_puts(m
, " SCRATCH ");
1438 /* don't use kunmap_px, it could trigger
1439 * an unnecessary flush.
1441 kunmap_atomic(pt_vaddr
);
1446 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1448 struct i915_address_space
*vm
= &ppgtt
->base
;
1449 uint64_t start
= ppgtt
->base
.start
;
1450 uint64_t length
= ppgtt
->base
.total
;
1451 gen8_pte_t scratch_pte
= gen8_pte_encode(vm
->scratch_page
.daddr
,
1452 I915_CACHE_LLC
, true);
1454 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1455 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1458 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1459 struct i915_page_directory_pointer
*pdp
;
1461 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1462 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1465 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1466 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1471 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1473 unsigned long *new_page_dirs
, *new_page_tables
;
1474 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1477 /* We allocate temp bitmap for page tables for no gain
1478 * but as this is for init only, lets keep the things simple
1480 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1484 /* Allocate for all pdps regardless of how the ppgtt
1487 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1491 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1493 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1499 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1500 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1501 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1505 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1509 ret
= gen8_init_scratch(&ppgtt
->base
);
1513 ppgtt
->base
.start
= 0;
1514 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1515 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1516 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1517 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1518 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1519 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1520 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1522 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1523 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1527 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1529 ppgtt
->base
.total
= 1ULL << 48;
1530 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1532 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1536 ppgtt
->base
.total
= 1ULL << 32;
1537 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1538 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1542 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
))) {
1543 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1549 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
)))
1550 gen8_ppgtt_notify_vgt(ppgtt
, true);
1555 gen8_free_scratch(&ppgtt
->base
);
1559 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1561 struct i915_address_space
*vm
= &ppgtt
->base
;
1562 struct i915_page_table
*unused
;
1563 gen6_pte_t scratch_pte
;
1566 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1568 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
1569 I915_CACHE_LLC
, true, 0);
1571 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1573 gen6_pte_t
*pt_vaddr
;
1574 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1575 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1576 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1578 if (pd_entry
!= expected
)
1579 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1583 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1585 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1587 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1589 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1593 for (i
= 0; i
< 4; i
++)
1594 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1599 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1600 for (i
= 0; i
< 4; i
++) {
1601 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1602 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1604 seq_puts(m
, " SCRATCH ");
1608 kunmap_px(ppgtt
, pt_vaddr
);
1612 /* Write pde (index) from the page directory @pd to the page table @pt */
1613 static void gen6_write_pde(struct i915_page_directory
*pd
,
1614 const int pde
, struct i915_page_table
*pt
)
1616 /* Caller needs to make sure the write completes if necessary */
1617 struct i915_hw_ppgtt
*ppgtt
=
1618 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1621 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1622 pd_entry
|= GEN6_PDE_VALID
;
1624 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1627 /* Write all the page tables found in the ppgtt structure to incrementing page
1629 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1630 struct i915_page_directory
*pd
,
1631 uint32_t start
, uint32_t length
)
1633 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1634 struct i915_page_table
*pt
;
1637 gen6_for_each_pde(pt
, pd
, start
, length
, pde
)
1638 gen6_write_pde(pd
, pde
, pt
);
1640 /* Make sure write is complete before other code can use this page
1641 * table. Also require for WC mapped PTEs */
1645 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1647 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1649 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1652 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1653 struct drm_i915_gem_request
*req
)
1655 struct intel_ring
*ring
= req
->ring
;
1656 struct intel_engine_cs
*engine
= req
->engine
;
1659 /* NB: TLBs must be flushed and invalidated before a switch */
1660 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1664 ret
= intel_ring_begin(req
, 6);
1668 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1669 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(engine
));
1670 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1671 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(engine
));
1672 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1673 intel_ring_emit(ring
, MI_NOOP
);
1674 intel_ring_advance(ring
);
1679 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1680 struct drm_i915_gem_request
*req
)
1682 struct intel_ring
*ring
= req
->ring
;
1683 struct intel_engine_cs
*engine
= req
->engine
;
1686 /* NB: TLBs must be flushed and invalidated before a switch */
1687 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1691 ret
= intel_ring_begin(req
, 6);
1695 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1696 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(engine
));
1697 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1698 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(engine
));
1699 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1700 intel_ring_emit(ring
, MI_NOOP
);
1701 intel_ring_advance(ring
);
1703 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1704 if (engine
->id
!= RCS
) {
1705 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1713 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1714 struct drm_i915_gem_request
*req
)
1716 struct intel_engine_cs
*engine
= req
->engine
;
1717 struct drm_i915_private
*dev_priv
= req
->i915
;
1719 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1720 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1724 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1726 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1727 struct intel_engine_cs
*engine
;
1729 for_each_engine(engine
, dev_priv
) {
1730 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1731 I915_WRITE(RING_MODE_GEN7(engine
),
1732 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1736 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1739 struct intel_engine_cs
*engine
;
1740 uint32_t ecochk
, ecobits
;
1742 ecobits
= I915_READ(GAC_ECO_BITS
);
1743 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1745 ecochk
= I915_READ(GAM_ECOCHK
);
1746 if (IS_HASWELL(dev
)) {
1747 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1749 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1750 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1752 I915_WRITE(GAM_ECOCHK
, ecochk
);
1754 for_each_engine(engine
, dev_priv
) {
1755 /* GFX_MODE is per-ring on gen7+ */
1756 I915_WRITE(RING_MODE_GEN7(engine
),
1757 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1761 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1763 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1764 uint32_t ecochk
, gab_ctl
, ecobits
;
1766 ecobits
= I915_READ(GAC_ECO_BITS
);
1767 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1768 ECOBITS_PPGTT_CACHE64B
);
1770 gab_ctl
= I915_READ(GAB_CTL
);
1771 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1773 ecochk
= I915_READ(GAM_ECOCHK
);
1774 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1776 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1779 /* PPGTT support for Sandybdrige/Gen6 and later */
1780 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1785 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1786 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1787 unsigned first_entry
= start
>> PAGE_SHIFT
;
1788 unsigned num_entries
= length
>> PAGE_SHIFT
;
1789 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1790 unsigned first_pte
= first_entry
% GEN6_PTES
;
1791 unsigned last_pte
, i
;
1793 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
1794 I915_CACHE_LLC
, true, 0);
1796 while (num_entries
) {
1797 last_pte
= first_pte
+ num_entries
;
1798 if (last_pte
> GEN6_PTES
)
1799 last_pte
= GEN6_PTES
;
1801 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1803 for (i
= first_pte
; i
< last_pte
; i
++)
1804 pt_vaddr
[i
] = scratch_pte
;
1806 kunmap_px(ppgtt
, pt_vaddr
);
1808 num_entries
-= last_pte
- first_pte
;
1814 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1815 struct sg_table
*pages
,
1817 enum i915_cache_level cache_level
, u32 flags
)
1819 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1820 unsigned first_entry
= start
>> PAGE_SHIFT
;
1821 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1822 unsigned act_pte
= first_entry
% GEN6_PTES
;
1823 gen6_pte_t
*pt_vaddr
= NULL
;
1824 struct sgt_iter sgt_iter
;
1827 for_each_sgt_dma(addr
, sgt_iter
, pages
) {
1828 if (pt_vaddr
== NULL
)
1829 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1832 vm
->pte_encode(addr
, cache_level
, true, flags
);
1834 if (++act_pte
== GEN6_PTES
) {
1835 kunmap_px(ppgtt
, pt_vaddr
);
1843 kunmap_px(ppgtt
, pt_vaddr
);
1846 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1847 uint64_t start_in
, uint64_t length_in
)
1849 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1850 struct drm_device
*dev
= vm
->dev
;
1851 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1852 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1853 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1854 struct i915_page_table
*pt
;
1855 uint32_t start
, length
, start_save
, length_save
;
1859 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1862 start
= start_save
= start_in
;
1863 length
= length_save
= length_in
;
1865 bitmap_zero(new_page_tables
, I915_PDES
);
1867 /* The allocation is done in two stages so that we can bail out with
1868 * minimal amount of pain. The first stage finds new page tables that
1869 * need allocation. The second stage marks use ptes within the page
1872 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1873 if (pt
!= vm
->scratch_pt
) {
1874 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1878 /* We've already allocated a page table */
1879 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1887 gen6_initialize_pt(vm
, pt
);
1889 ppgtt
->pd
.page_table
[pde
] = pt
;
1890 __set_bit(pde
, new_page_tables
);
1891 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1895 length
= length_save
;
1897 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1898 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1900 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1901 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1902 gen6_pte_count(start
, length
));
1904 if (__test_and_clear_bit(pde
, new_page_tables
))
1905 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1907 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1908 gen6_pte_index(start
),
1909 gen6_pte_count(start
, length
),
1911 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1915 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1917 /* Make sure write is complete before other code can use this page
1918 * table. Also require for WC mapped PTEs */
1921 mark_tlbs_dirty(ppgtt
);
1925 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1926 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1928 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1929 free_pt(vm
->dev
, pt
);
1932 mark_tlbs_dirty(ppgtt
);
1936 static int gen6_init_scratch(struct i915_address_space
*vm
)
1938 struct drm_device
*dev
= vm
->dev
;
1941 ret
= setup_scratch_page(dev
, &vm
->scratch_page
, I915_GFP_DMA
);
1945 vm
->scratch_pt
= alloc_pt(dev
);
1946 if (IS_ERR(vm
->scratch_pt
)) {
1947 cleanup_scratch_page(dev
, &vm
->scratch_page
);
1948 return PTR_ERR(vm
->scratch_pt
);
1951 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1956 static void gen6_free_scratch(struct i915_address_space
*vm
)
1958 struct drm_device
*dev
= vm
->dev
;
1960 free_pt(dev
, vm
->scratch_pt
);
1961 cleanup_scratch_page(dev
, &vm
->scratch_page
);
1964 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1966 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1967 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1968 struct drm_device
*dev
= vm
->dev
;
1969 struct i915_page_table
*pt
;
1972 drm_mm_remove_node(&ppgtt
->node
);
1974 gen6_for_all_pdes(pt
, pd
, pde
)
1975 if (pt
!= vm
->scratch_pt
)
1978 gen6_free_scratch(vm
);
1981 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1983 struct i915_address_space
*vm
= &ppgtt
->base
;
1984 struct drm_device
*dev
= ppgtt
->base
.dev
;
1985 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1986 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1987 bool retried
= false;
1990 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1991 * allocator works in address space sizes, so it's multiplied by page
1992 * size. We allocate at the top of the GTT to avoid fragmentation.
1994 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
1996 ret
= gen6_init_scratch(vm
);
2001 ret
= drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
,
2002 &ppgtt
->node
, GEN6_PD_SIZE
,
2004 0, ggtt
->base
.total
,
2006 if (ret
== -ENOSPC
&& !retried
) {
2007 ret
= i915_gem_evict_something(&ggtt
->base
,
2008 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2010 0, ggtt
->base
.total
,
2023 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
2024 DRM_DEBUG("Forced to use aperture for PDEs\n");
2029 gen6_free_scratch(vm
);
2033 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2035 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2038 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2039 uint64_t start
, uint64_t length
)
2041 struct i915_page_table
*unused
;
2044 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
2045 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2048 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2050 struct drm_device
*dev
= ppgtt
->base
.dev
;
2051 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2052 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2055 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
2056 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev
))
2057 ppgtt
->switch_mm
= gen6_mm_switch
;
2058 else if (IS_HASWELL(dev
))
2059 ppgtt
->switch_mm
= hsw_mm_switch
;
2060 else if (IS_GEN7(dev
))
2061 ppgtt
->switch_mm
= gen7_mm_switch
;
2065 ret
= gen6_ppgtt_alloc(ppgtt
);
2069 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2070 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2071 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2072 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2073 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2074 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2075 ppgtt
->base
.start
= 0;
2076 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2077 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2079 ppgtt
->pd
.base
.ggtt_offset
=
2080 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2082 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
2083 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2085 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2087 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2089 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2090 ppgtt
->node
.size
>> 20,
2091 ppgtt
->node
.start
/ PAGE_SIZE
);
2093 DRM_DEBUG("Adding PPGTT at offset %x\n",
2094 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2099 static int __hw_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2100 struct drm_i915_private
*dev_priv
)
2102 ppgtt
->base
.dev
= &dev_priv
->drm
;
2104 if (INTEL_INFO(dev_priv
)->gen
< 8)
2105 return gen6_ppgtt_init(ppgtt
);
2107 return gen8_ppgtt_init(ppgtt
);
2110 static void i915_address_space_init(struct i915_address_space
*vm
,
2111 struct drm_i915_private
*dev_priv
)
2113 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2114 INIT_LIST_HEAD(&vm
->active_list
);
2115 INIT_LIST_HEAD(&vm
->inactive_list
);
2116 INIT_LIST_HEAD(&vm
->unbound_list
);
2117 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2120 static void gtt_write_workarounds(struct drm_device
*dev
)
2122 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2124 /* This function is for gtt related workarounds. This function is
2125 * called on driver load and after a GPU reset, so you can place
2126 * workarounds here even if they get overwritten by GPU reset.
2128 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2129 if (IS_BROADWELL(dev
))
2130 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
2131 else if (IS_CHERRYVIEW(dev
))
2132 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
2133 else if (IS_SKYLAKE(dev
))
2134 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
2135 else if (IS_BROXTON(dev
))
2136 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
2139 static int i915_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2140 struct drm_i915_private
*dev_priv
,
2141 struct drm_i915_file_private
*file_priv
)
2145 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2147 kref_init(&ppgtt
->ref
);
2148 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2149 ppgtt
->base
.file
= file_priv
;
2155 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2157 gtt_write_workarounds(dev
);
2159 /* In the case of execlists, PPGTT is enabled by the context descriptor
2160 * and the PDPs are contained within the context itself. We don't
2161 * need to do anything here. */
2162 if (i915
.enable_execlists
)
2165 if (!USES_PPGTT(dev
))
2169 gen6_ppgtt_enable(dev
);
2170 else if (IS_GEN7(dev
))
2171 gen7_ppgtt_enable(dev
);
2172 else if (INTEL_INFO(dev
)->gen
>= 8)
2173 gen8_ppgtt_enable(dev
);
2175 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2180 struct i915_hw_ppgtt
*
2181 i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
2182 struct drm_i915_file_private
*fpriv
)
2184 struct i915_hw_ppgtt
*ppgtt
;
2187 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2189 return ERR_PTR(-ENOMEM
);
2191 ret
= i915_ppgtt_init(ppgtt
, dev_priv
, fpriv
);
2194 return ERR_PTR(ret
);
2197 trace_i915_ppgtt_create(&ppgtt
->base
);
2202 void i915_ppgtt_release(struct kref
*kref
)
2204 struct i915_hw_ppgtt
*ppgtt
=
2205 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2207 trace_i915_ppgtt_release(&ppgtt
->base
);
2209 /* vmas should already be unbound and destroyed */
2210 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2211 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2212 WARN_ON(!list_empty(&ppgtt
->base
.unbound_list
));
2214 list_del(&ppgtt
->base
.global_link
);
2215 drm_mm_takedown(&ppgtt
->base
.mm
);
2217 ppgtt
->base
.cleanup(&ppgtt
->base
);
2221 /* Certain Gen5 chipsets require require idling the GPU before
2222 * unmapping anything from the GTT when VT-d is enabled.
2224 static bool needs_idle_maps(struct drm_i915_private
*dev_priv
)
2226 #ifdef CONFIG_INTEL_IOMMU
2227 /* Query intel_iommu to see if we need the workaround. Presumably that
2230 if (IS_GEN5(dev_priv
) && IS_MOBILE(dev_priv
) && intel_iommu_gfx_mapped
)
2236 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2238 struct intel_engine_cs
*engine
;
2240 if (INTEL_INFO(dev_priv
)->gen
< 6)
2243 for_each_engine(engine
, dev_priv
) {
2245 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2246 if (fault_reg
& RING_FAULT_VALID
) {
2247 DRM_DEBUG_DRIVER("Unexpected fault\n"
2249 "\tAddress space: %s\n"
2252 fault_reg
& PAGE_MASK
,
2253 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2254 RING_FAULT_SRCID(fault_reg
),
2255 RING_FAULT_FAULT_TYPE(fault_reg
));
2256 I915_WRITE(RING_FAULT_REG(engine
),
2257 fault_reg
& ~RING_FAULT_VALID
);
2260 POSTING_READ(RING_FAULT_REG(&dev_priv
->engine
[RCS
]));
2263 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2265 if (INTEL_INFO(dev_priv
)->gen
< 6) {
2266 intel_gtt_chipset_flush();
2268 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2269 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2273 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2275 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2276 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2278 /* Don't bother messing with faults pre GEN6 as we have little
2279 * documentation supporting that it's a good idea.
2281 if (INTEL_INFO(dev
)->gen
< 6)
2284 i915_check_and_clear_faults(dev_priv
);
2286 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
2289 i915_ggtt_flush(dev_priv
);
2292 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2294 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2295 obj
->pages
->sgl
, obj
->pages
->nents
,
2296 PCI_DMA_BIDIRECTIONAL
))
2302 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2307 iowrite32((u32
)pte
, addr
);
2308 iowrite32(pte
>> 32, addr
+ 4);
2312 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2315 enum i915_cache_level level
,
2318 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2319 gen8_pte_t __iomem
*pte
=
2320 (gen8_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2321 (offset
>> PAGE_SHIFT
);
2324 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2326 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
, true));
2328 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2329 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2331 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2334 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2335 struct sg_table
*st
,
2337 enum i915_cache_level level
, u32 unused
)
2339 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2340 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2341 struct sgt_iter sgt_iter
;
2342 gen8_pte_t __iomem
*gtt_entries
;
2343 gen8_pte_t gtt_entry
;
2348 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2350 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2352 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2353 gtt_entry
= gen8_pte_encode(addr
, level
, true);
2354 gen8_set_pte(>t_entries
[i
++], gtt_entry
);
2358 * XXX: This serves as a posting read to make sure that the PTE has
2359 * actually been updated. There is some concern that even though
2360 * registers and PTEs are within the same BAR that they are potentially
2361 * of NUMA access patterns. Therefore, even with the way we assume
2362 * hardware should work, we must keep this posting read for paranoia.
2365 WARN_ON(readq(>t_entries
[i
-1]) != gtt_entry
);
2367 /* This next bit makes the above posting read even more important. We
2368 * want to flush the TLBs only after we're certain all the PTE updates
2371 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2372 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2374 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2377 struct insert_entries
{
2378 struct i915_address_space
*vm
;
2379 struct sg_table
*st
;
2381 enum i915_cache_level level
;
2385 static int gen8_ggtt_insert_entries__cb(void *_arg
)
2387 struct insert_entries
*arg
= _arg
;
2388 gen8_ggtt_insert_entries(arg
->vm
, arg
->st
,
2389 arg
->start
, arg
->level
, arg
->flags
);
2393 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2394 struct sg_table
*st
,
2396 enum i915_cache_level level
,
2399 struct insert_entries arg
= { vm
, st
, start
, level
, flags
};
2400 stop_machine(gen8_ggtt_insert_entries__cb
, &arg
, NULL
);
2403 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2406 enum i915_cache_level level
,
2409 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2410 gen6_pte_t __iomem
*pte
=
2411 (gen6_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2412 (offset
>> PAGE_SHIFT
);
2415 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2417 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), pte
);
2419 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2420 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2422 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2426 * Binds an object into the global gtt with the specified cache level. The object
2427 * will be accessible to the GPU via commands whose operands reference offsets
2428 * within the global GTT as well as accessible by the GPU through the GMADR
2429 * mapped BAR (dev_priv->mm.gtt->gtt).
2431 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2432 struct sg_table
*st
,
2434 enum i915_cache_level level
, u32 flags
)
2436 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2437 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2438 struct sgt_iter sgt_iter
;
2439 gen6_pte_t __iomem
*gtt_entries
;
2440 gen6_pte_t gtt_entry
;
2445 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2447 gtt_entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2449 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2450 gtt_entry
= vm
->pte_encode(addr
, level
, true, flags
);
2451 iowrite32(gtt_entry
, >t_entries
[i
++]);
2454 /* XXX: This serves as a posting read to make sure that the PTE has
2455 * actually been updated. There is some concern that even though
2456 * registers and PTEs are within the same BAR that they are potentially
2457 * of NUMA access patterns. Therefore, even with the way we assume
2458 * hardware should work, we must keep this posting read for paranoia.
2461 WARN_ON(readl(>t_entries
[i
-1]) != gtt_entry
);
2463 /* This next bit makes the above posting read even more important. We
2464 * want to flush the TLBs only after we're certain all the PTE updates
2467 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2468 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2470 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2473 static void nop_clear_range(struct i915_address_space
*vm
,
2480 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2485 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2486 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2487 unsigned first_entry
= start
>> PAGE_SHIFT
;
2488 unsigned num_entries
= length
>> PAGE_SHIFT
;
2489 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2490 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2491 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2495 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2497 if (WARN(num_entries
> max_entries
,
2498 "First entry = %d; Num entries = %d (max=%d)\n",
2499 first_entry
, num_entries
, max_entries
))
2500 num_entries
= max_entries
;
2502 scratch_pte
= gen8_pte_encode(vm
->scratch_page
.daddr
,
2505 for (i
= 0; i
< num_entries
; i
++)
2506 gen8_set_pte(>t_base
[i
], scratch_pte
);
2509 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2512 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2517 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2518 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2519 unsigned first_entry
= start
>> PAGE_SHIFT
;
2520 unsigned num_entries
= length
>> PAGE_SHIFT
;
2521 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2522 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2523 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2527 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2529 if (WARN(num_entries
> max_entries
,
2530 "First entry = %d; Num entries = %d (max=%d)\n",
2531 first_entry
, num_entries
, max_entries
))
2532 num_entries
= max_entries
;
2534 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
2535 I915_CACHE_LLC
, use_scratch
, 0);
2537 for (i
= 0; i
< num_entries
; i
++)
2538 iowrite32(scratch_pte
, >t_base
[i
]);
2541 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2544 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2547 enum i915_cache_level cache_level
,
2550 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2551 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2552 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2555 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2557 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2559 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2562 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2563 struct sg_table
*pages
,
2565 enum i915_cache_level cache_level
, u32 unused
)
2567 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2568 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2569 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2572 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2574 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2576 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2580 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2585 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2586 unsigned first_entry
= start
>> PAGE_SHIFT
;
2587 unsigned num_entries
= length
>> PAGE_SHIFT
;
2590 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2592 intel_gtt_clear_range(first_entry
, num_entries
);
2594 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2597 static int ggtt_bind_vma(struct i915_vma
*vma
,
2598 enum i915_cache_level cache_level
,
2601 struct drm_i915_gem_object
*obj
= vma
->obj
;
2605 ret
= i915_get_ggtt_vma_pages(vma
);
2609 /* Currently applicable only to VLV */
2611 pte_flags
|= PTE_READ_ONLY
;
2613 vma
->vm
->insert_entries(vma
->vm
, vma
->pages
, vma
->node
.start
,
2614 cache_level
, pte_flags
);
2617 * Without aliasing PPGTT there's no difference between
2618 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2619 * upgrade to both bound if we bind either to avoid double-binding.
2621 vma
->flags
|= I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
;
2626 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2627 enum i915_cache_level cache_level
,
2633 ret
= i915_get_ggtt_vma_pages(vma
);
2637 /* Currently applicable only to VLV */
2639 if (vma
->obj
->gt_ro
)
2640 pte_flags
|= PTE_READ_ONLY
;
2643 if (flags
& I915_VMA_GLOBAL_BIND
) {
2644 vma
->vm
->insert_entries(vma
->vm
,
2645 vma
->pages
, vma
->node
.start
,
2646 cache_level
, pte_flags
);
2649 if (flags
& I915_VMA_LOCAL_BIND
) {
2650 struct i915_hw_ppgtt
*appgtt
=
2651 to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2652 appgtt
->base
.insert_entries(&appgtt
->base
,
2653 vma
->pages
, vma
->node
.start
,
2654 cache_level
, pte_flags
);
2660 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2662 struct i915_hw_ppgtt
*appgtt
= to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2663 const u64 size
= min(vma
->size
, vma
->node
.size
);
2665 if (vma
->flags
& I915_VMA_GLOBAL_BIND
)
2666 vma
->vm
->clear_range(vma
->vm
,
2667 vma
->node
.start
, size
,
2670 if (vma
->flags
& I915_VMA_LOCAL_BIND
&& appgtt
)
2671 appgtt
->base
.clear_range(&appgtt
->base
,
2672 vma
->node
.start
, size
,
2676 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2678 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2679 struct device
*kdev
= &dev_priv
->drm
.pdev
->dev
;
2680 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2682 if (unlikely(ggtt
->do_idle_maps
)) {
2683 if (i915_gem_wait_for_idle(dev_priv
, false)) {
2684 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2685 /* Wait a bit, in hopes it avoids the hang */
2690 dma_unmap_sg(kdev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2691 PCI_DMA_BIDIRECTIONAL
);
2694 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2695 unsigned long color
,
2699 if (node
->color
!= color
)
2702 node
= list_first_entry_or_null(&node
->node_list
,
2705 if (node
&& node
->allocated
&& node
->color
!= color
)
2709 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
)
2711 /* Let GEM Manage all of the aperture.
2713 * However, leave one page at the end still bound to the scratch page.
2714 * There are a number of places where the hardware apparently prefetches
2715 * past the end of the object, and we've seen multiple hangs with the
2716 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2717 * aperture. One page should be enough to keep any prefetching inside
2720 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2721 unsigned long hole_start
, hole_end
;
2722 struct drm_mm_node
*entry
;
2725 ret
= intel_vgt_balloon(dev_priv
);
2729 /* Clear any non-preallocated blocks */
2730 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2731 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2732 hole_start
, hole_end
);
2733 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2734 hole_end
- hole_start
, true);
2737 /* And finally clear the reserved guard page */
2738 ggtt
->base
.clear_range(&ggtt
->base
,
2739 ggtt
->base
.total
- PAGE_SIZE
, PAGE_SIZE
,
2742 if (USES_PPGTT(dev_priv
) && !USES_FULL_PPGTT(dev_priv
)) {
2743 struct i915_hw_ppgtt
*ppgtt
;
2745 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2749 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2755 if (ppgtt
->base
.allocate_va_range
)
2756 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2759 ppgtt
->base
.cleanup(&ppgtt
->base
);
2764 ppgtt
->base
.clear_range(&ppgtt
->base
,
2769 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2770 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2771 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2778 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2779 * @dev_priv: i915 device
2781 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
)
2783 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2785 if (dev_priv
->mm
.aliasing_ppgtt
) {
2786 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2787 ppgtt
->base
.cleanup(&ppgtt
->base
);
2791 i915_gem_cleanup_stolen(&dev_priv
->drm
);
2793 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2794 intel_vgt_deballoon(dev_priv
);
2796 drm_mm_takedown(&ggtt
->base
.mm
);
2797 list_del(&ggtt
->base
.global_link
);
2800 ggtt
->base
.cleanup(&ggtt
->base
);
2802 arch_phys_wc_del(ggtt
->mtrr
);
2803 io_mapping_fini(&ggtt
->mappable
);
2806 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2808 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2809 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2810 return snb_gmch_ctl
<< 20;
2813 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2815 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2816 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2818 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2820 #ifdef CONFIG_X86_32
2821 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2822 if (bdw_gmch_ctl
> 4)
2826 return bdw_gmch_ctl
<< 20;
2829 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2831 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2832 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2835 return 1 << (20 + gmch_ctrl
);
2840 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2842 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2843 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2844 return snb_gmch_ctl
<< 25; /* 32 MB units */
2847 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2849 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2850 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2851 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2854 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2856 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2857 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2860 * 0x0 to 0x10: 32MB increments starting at 0MB
2861 * 0x11 to 0x16: 4MB increments starting at 8MB
2862 * 0x17 to 0x1d: 4MB increments start at 36MB
2864 if (gmch_ctrl
< 0x11)
2865 return gmch_ctrl
<< 25;
2866 else if (gmch_ctrl
< 0x17)
2867 return (gmch_ctrl
- 0x11 + 2) << 22;
2869 return (gmch_ctrl
- 0x17 + 9) << 22;
2872 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2874 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2875 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2877 if (gen9_gmch_ctl
< 0xf0)
2878 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2880 /* 4MB increments starting at 0xf0 for 4MB */
2881 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2884 static int ggtt_probe_common(struct i915_ggtt
*ggtt
, u64 size
)
2886 struct pci_dev
*pdev
= ggtt
->base
.dev
->pdev
;
2887 phys_addr_t phys_addr
;
2890 /* For Modern GENs the PTEs and register space are split in the BAR */
2891 phys_addr
= pci_resource_start(pdev
, 0) + pci_resource_len(pdev
, 0) / 2;
2894 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2895 * dropped. For WC mappings in general we have 64 byte burst writes
2896 * when the WC buffer is flushed, so we can't use it, but have to
2897 * resort to an uncached mapping. The WC issue is easily caught by the
2898 * readback check when writing GTT PTE entries.
2900 if (IS_BROXTON(ggtt
->base
.dev
))
2901 ggtt
->gsm
= ioremap_nocache(phys_addr
, size
);
2903 ggtt
->gsm
= ioremap_wc(phys_addr
, size
);
2905 DRM_ERROR("Failed to map the ggtt page table\n");
2909 ret
= setup_scratch_page(ggtt
->base
.dev
,
2910 &ggtt
->base
.scratch_page
,
2913 DRM_ERROR("Scratch setup failed\n");
2914 /* iounmap will also get called at remove, but meh */
2922 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2923 * bits. When using advanced contexts each context stores its own PAT, but
2924 * writing this data shouldn't be harmful even in those cases. */
2925 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2929 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2930 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2931 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2932 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2933 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2934 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2935 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2936 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2938 if (!USES_PPGTT(dev_priv
))
2939 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2940 * so RTL will always use the value corresponding to
2942 * So let's disable cache for GGTT to avoid screen corruptions.
2943 * MOCS still can be used though.
2944 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2945 * before this patch, i.e. the same uncached + snooping access
2946 * like on gen6/7 seems to be in effect.
2947 * - So this just fixes blitter/render access. Again it looks
2948 * like it's not just uncached access, but uncached + snooping.
2949 * So we can still hold onto all our assumptions wrt cpu
2950 * clflushing on LLC machines.
2952 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2954 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2955 * write would work. */
2956 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2957 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2960 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2965 * Map WB on BDW to snooped on CHV.
2967 * Only the snoop bit has meaning for CHV, the rest is
2970 * The hardware will never snoop for certain types of accesses:
2971 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2972 * - PPGTT page tables
2973 * - some other special cycles
2975 * As with BDW, we also need to consider the following for GT accesses:
2976 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2977 * so RTL will always use the value corresponding to
2979 * Which means we must set the snoop bit in PAT entry 0
2980 * in order to keep the global status page working.
2982 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2986 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2987 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2988 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2989 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2991 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2992 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2995 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2997 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
3000 cleanup_scratch_page(vm
->dev
, &vm
->scratch_page
);
3003 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
3005 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3006 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3010 /* TODO: We're not aware of mappable constraints on gen8 yet */
3011 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
3012 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
3014 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(39)))
3015 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(39));
3017 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3019 if (INTEL_GEN(dev_priv
) >= 9) {
3020 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
3021 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3022 } else if (IS_CHERRYVIEW(dev_priv
)) {
3023 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
3024 size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3026 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
3027 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3030 ggtt
->base
.total
= (size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3032 if (IS_CHERRYVIEW(dev_priv
) || IS_BROXTON(dev_priv
))
3033 chv_setup_private_ppat(dev_priv
);
3035 bdw_setup_private_ppat(dev_priv
);
3037 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3038 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3039 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3040 ggtt
->base
.insert_page
= gen8_ggtt_insert_page
;
3041 ggtt
->base
.clear_range
= nop_clear_range
;
3042 if (!USES_FULL_PPGTT(dev_priv
) || intel_scanout_needs_vtd_wa(dev_priv
))
3043 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
3045 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
3046 if (IS_CHERRYVIEW(dev_priv
))
3047 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries__BKL
;
3049 return ggtt_probe_common(ggtt
, size
);
3052 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
3054 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3055 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3059 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
3060 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
3062 /* 64/512MB is the current min/max we actually know of, but this is just
3063 * a coarse sanity check.
3065 if (ggtt
->mappable_end
< (64<<20) || ggtt
->mappable_end
> (512<<20)) {
3066 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
3070 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
3071 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40));
3072 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3074 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
3076 size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3077 ggtt
->base
.total
= (size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3079 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
3080 ggtt
->base
.insert_page
= gen6_ggtt_insert_page
;
3081 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
3082 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3083 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3084 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3086 if (HAS_EDRAM(dev_priv
))
3087 ggtt
->base
.pte_encode
= iris_pte_encode
;
3088 else if (IS_HASWELL(dev_priv
))
3089 ggtt
->base
.pte_encode
= hsw_pte_encode
;
3090 else if (IS_VALLEYVIEW(dev_priv
))
3091 ggtt
->base
.pte_encode
= byt_pte_encode
;
3092 else if (INTEL_GEN(dev_priv
) >= 7)
3093 ggtt
->base
.pte_encode
= ivb_pte_encode
;
3095 ggtt
->base
.pte_encode
= snb_pte_encode
;
3097 return ggtt_probe_common(ggtt
, size
);
3100 static void i915_gmch_remove(struct i915_address_space
*vm
)
3102 intel_gmch_remove();
3105 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
3107 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3110 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
3112 DRM_ERROR("failed to set up gmch\n");
3116 intel_gtt_get(&ggtt
->base
.total
, &ggtt
->stolen_size
,
3117 &ggtt
->mappable_base
, &ggtt
->mappable_end
);
3119 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
);
3120 ggtt
->base
.insert_page
= i915_ggtt_insert_page
;
3121 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
3122 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
3123 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3124 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3125 ggtt
->base
.cleanup
= i915_gmch_remove
;
3127 if (unlikely(ggtt
->do_idle_maps
))
3128 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3134 * i915_ggtt_probe_hw - Probe GGTT hardware location
3135 * @dev_priv: i915 device
3137 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
)
3139 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3142 ggtt
->base
.dev
= &dev_priv
->drm
;
3144 if (INTEL_GEN(dev_priv
) <= 5)
3145 ret
= i915_gmch_probe(ggtt
);
3146 else if (INTEL_GEN(dev_priv
) < 8)
3147 ret
= gen6_gmch_probe(ggtt
);
3149 ret
= gen8_gmch_probe(ggtt
);
3153 if ((ggtt
->base
.total
- 1) >> 32) {
3154 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3155 " of address space! Found %lldM!\n",
3156 ggtt
->base
.total
>> 20);
3157 ggtt
->base
.total
= 1ULL << 32;
3158 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3161 if (ggtt
->mappable_end
> ggtt
->base
.total
) {
3162 DRM_ERROR("mappable aperture extends past end of GGTT,"
3163 " aperture=%llx, total=%llx\n",
3164 ggtt
->mappable_end
, ggtt
->base
.total
);
3165 ggtt
->mappable_end
= ggtt
->base
.total
;
3168 /* GMADR is the PCI mmio aperture into the global GTT. */
3169 DRM_INFO("Memory usable by graphics device = %lluM\n",
3170 ggtt
->base
.total
>> 20);
3171 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
3172 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt
->stolen_size
>> 20);
3173 #ifdef CONFIG_INTEL_IOMMU
3174 if (intel_iommu_gfx_mapped
)
3175 DRM_INFO("VT-d active for gfx access\n");
3182 * i915_ggtt_init_hw - Initialize GGTT hardware
3183 * @dev_priv: i915 device
3185 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
)
3187 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3190 INIT_LIST_HEAD(&dev_priv
->vm_list
);
3192 /* Subtract the guard page before address space initialization to
3193 * shrink the range used by drm_mm.
3195 ggtt
->base
.total
-= PAGE_SIZE
;
3196 i915_address_space_init(&ggtt
->base
, dev_priv
);
3197 ggtt
->base
.total
+= PAGE_SIZE
;
3198 if (!HAS_LLC(dev_priv
))
3199 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
3201 if (!io_mapping_init_wc(&dev_priv
->ggtt
.mappable
,
3202 dev_priv
->ggtt
.mappable_base
,
3203 dev_priv
->ggtt
.mappable_end
)) {
3205 goto out_gtt_cleanup
;
3208 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->mappable_base
, ggtt
->mappable_end
);
3211 * Initialise stolen early so that we may reserve preallocated
3212 * objects for the BIOS to KMS transition.
3214 ret
= i915_gem_init_stolen(&dev_priv
->drm
);
3216 goto out_gtt_cleanup
;
3221 ggtt
->base
.cleanup(&ggtt
->base
);
3225 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
)
3227 if (INTEL_GEN(dev_priv
) < 6 && !intel_enable_gtt())
3233 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3235 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3236 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3237 struct drm_i915_gem_object
*obj
;
3238 struct i915_vma
*vma
;
3240 i915_check_and_clear_faults(dev_priv
);
3242 /* First fill our portion of the GTT with scratch pages */
3243 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
3246 /* Cache flush objects bound into GGTT and rebind them. */
3247 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3248 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3249 if (vma
->vm
!= &ggtt
->base
)
3252 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3256 if (obj
->pin_display
)
3257 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3260 if (INTEL_INFO(dev
)->gen
>= 8) {
3261 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3262 chv_setup_private_ppat(dev_priv
);
3264 bdw_setup_private_ppat(dev_priv
);
3269 if (USES_PPGTT(dev
)) {
3270 struct i915_address_space
*vm
;
3272 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3273 /* TODO: Perhaps it shouldn't be gen6 specific */
3275 struct i915_hw_ppgtt
*ppgtt
;
3277 if (i915_is_ggtt(vm
))
3278 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3280 ppgtt
= i915_vm_to_ppgtt(vm
);
3282 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3283 0, ppgtt
->base
.total
);
3287 i915_ggtt_flush(dev_priv
);
3291 i915_vma_retire(struct i915_gem_active
*active
,
3292 struct drm_i915_gem_request
*rq
)
3294 const unsigned int idx
= rq
->engine
->id
;
3295 struct i915_vma
*vma
=
3296 container_of(active
, struct i915_vma
, last_read
[idx
]);
3298 GEM_BUG_ON(!i915_vma_has_active_engine(vma
, idx
));
3300 i915_vma_clear_active(vma
, idx
);
3301 if (i915_vma_is_active(vma
))
3304 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
3305 if (unlikely(i915_vma_is_closed(vma
) && !i915_vma_is_pinned(vma
)))
3306 WARN_ON(i915_vma_unbind(vma
));
3309 void i915_vma_destroy(struct i915_vma
*vma
)
3311 GEM_BUG_ON(vma
->node
.allocated
);
3312 GEM_BUG_ON(i915_vma_is_active(vma
));
3313 GEM_BUG_ON(!i915_vma_is_closed(vma
));
3314 GEM_BUG_ON(vma
->fence
);
3316 list_del(&vma
->vm_link
);
3317 if (!i915_vma_is_ggtt(vma
))
3318 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
3320 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
3323 void i915_vma_close(struct i915_vma
*vma
)
3325 GEM_BUG_ON(i915_vma_is_closed(vma
));
3326 vma
->flags
|= I915_VMA_CLOSED
;
3328 list_del_init(&vma
->obj_link
);
3329 if (!i915_vma_is_active(vma
) && !i915_vma_is_pinned(vma
))
3330 WARN_ON(i915_vma_unbind(vma
));
3333 static struct i915_vma
*
3334 __i915_vma_create(struct drm_i915_gem_object
*obj
,
3335 struct i915_address_space
*vm
,
3336 const struct i915_ggtt_view
*view
)
3338 struct i915_vma
*vma
;
3341 GEM_BUG_ON(vm
->closed
);
3343 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3345 return ERR_PTR(-ENOMEM
);
3347 INIT_LIST_HEAD(&vma
->exec_list
);
3348 for (i
= 0; i
< ARRAY_SIZE(vma
->last_read
); i
++)
3349 init_request_active(&vma
->last_read
[i
], i915_vma_retire
);
3350 init_request_active(&vma
->last_fence
, NULL
);
3351 list_add(&vma
->vm_link
, &vm
->unbound_list
);
3354 vma
->size
= obj
->base
.size
;
3357 vma
->ggtt_view
= *view
;
3358 if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3359 vma
->size
= view
->params
.partial
.size
;
3360 vma
->size
<<= PAGE_SHIFT
;
3361 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3363 intel_rotation_info_size(&view
->params
.rotated
);
3364 vma
->size
<<= PAGE_SHIFT
;
3368 if (i915_is_ggtt(vm
)) {
3369 vma
->flags
|= I915_VMA_GGTT
;
3371 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3374 list_add_tail(&vma
->obj_link
, &obj
->vma_list
);
3378 static inline bool vma_matches(struct i915_vma
*vma
,
3379 struct i915_address_space
*vm
,
3380 const struct i915_ggtt_view
*view
)
3385 if (!i915_vma_is_ggtt(vma
))
3389 return vma
->ggtt_view
.type
== 0;
3391 if (vma
->ggtt_view
.type
!= view
->type
)
3394 return memcmp(&vma
->ggtt_view
.params
,
3396 sizeof(view
->params
)) == 0;
3400 i915_vma_create(struct drm_i915_gem_object
*obj
,
3401 struct i915_address_space
*vm
,
3402 const struct i915_ggtt_view
*view
)
3404 GEM_BUG_ON(view
&& !i915_is_ggtt(vm
));
3405 GEM_BUG_ON(i915_gem_obj_to_vma(obj
, vm
, view
));
3407 return __i915_vma_create(obj
, vm
, view
);
3411 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3412 struct i915_address_space
*vm
,
3413 const struct i915_ggtt_view
*view
)
3415 struct i915_vma
*vma
;
3417 list_for_each_entry_reverse(vma
, &obj
->vma_list
, obj_link
)
3418 if (vma_matches(vma
, vm
, view
))
3425 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3426 struct i915_address_space
*vm
,
3427 const struct i915_ggtt_view
*view
)
3429 struct i915_vma
*vma
;
3431 GEM_BUG_ON(view
&& !i915_is_ggtt(vm
));
3433 vma
= i915_gem_obj_to_vma(obj
, vm
, view
);
3435 vma
= __i915_vma_create(obj
, vm
, view
);
3437 GEM_BUG_ON(i915_vma_is_closed(vma
));
3441 static struct scatterlist
*
3442 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3443 unsigned int width
, unsigned int height
,
3444 unsigned int stride
,
3445 struct sg_table
*st
, struct scatterlist
*sg
)
3447 unsigned int column
, row
;
3448 unsigned int src_idx
;
3450 for (column
= 0; column
< width
; column
++) {
3451 src_idx
= stride
* (height
- 1) + column
;
3452 for (row
= 0; row
< height
; row
++) {
3454 /* We don't need the pages, but need to initialize
3455 * the entries so the sg list can be happily traversed.
3456 * The only thing we need are DMA addresses.
3458 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3459 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3460 sg_dma_len(sg
) = PAGE_SIZE
;
3469 static struct sg_table
*
3470 intel_rotate_fb_obj_pages(const struct intel_rotation_info
*rot_info
,
3471 struct drm_i915_gem_object
*obj
)
3473 const size_t n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3474 unsigned int size
= intel_rotation_info_size(rot_info
);
3475 struct sgt_iter sgt_iter
;
3476 dma_addr_t dma_addr
;
3478 dma_addr_t
*page_addr_list
;
3479 struct sg_table
*st
;
3480 struct scatterlist
*sg
;
3483 /* Allocate a temporary list of source pages for random access. */
3484 page_addr_list
= drm_malloc_gfp(n_pages
,
3487 if (!page_addr_list
)
3488 return ERR_PTR(ret
);
3490 /* Allocate target SG list. */
3491 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3495 ret
= sg_alloc_table(st
, size
, GFP_KERNEL
);
3499 /* Populate source page list from the object. */
3501 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->pages
)
3502 page_addr_list
[i
++] = dma_addr
;
3504 GEM_BUG_ON(i
!= n_pages
);
3508 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++) {
3509 sg
= rotate_pages(page_addr_list
, rot_info
->plane
[i
].offset
,
3510 rot_info
->plane
[i
].width
, rot_info
->plane
[i
].height
,
3511 rot_info
->plane
[i
].stride
, st
, sg
);
3514 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3515 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3517 drm_free_large(page_addr_list
);
3524 drm_free_large(page_addr_list
);
3526 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3527 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3529 return ERR_PTR(ret
);
3532 static struct sg_table
*
3533 intel_partial_pages(const struct i915_ggtt_view
*view
,
3534 struct drm_i915_gem_object
*obj
)
3536 struct sg_table
*st
;
3537 struct scatterlist
*sg
;
3538 struct sg_page_iter obj_sg_iter
;
3541 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3545 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3551 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3552 view
->params
.partial
.offset
)
3554 if (st
->nents
>= view
->params
.partial
.size
)
3557 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3558 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3559 sg_dma_len(sg
) = PAGE_SIZE
;
3570 return ERR_PTR(ret
);
3574 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3581 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3582 vma
->pages
= vma
->obj
->pages
;
3583 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3585 intel_rotate_fb_obj_pages(&vma
->ggtt_view
.params
.rotated
, vma
->obj
);
3586 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3587 vma
->pages
= intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3589 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3590 vma
->ggtt_view
.type
);
3593 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3594 vma
->ggtt_view
.type
);
3596 } else if (IS_ERR(vma
->pages
)) {
3597 ret
= PTR_ERR(vma
->pages
);
3599 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3600 vma
->ggtt_view
.type
, ret
);
3607 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3609 * @cache_level: mapping cache level
3610 * @flags: flags like global or local mapping
3612 * DMA addresses are taken from the scatter-gather table of this object (or of
3613 * this VMA in case of non-default GGTT views) and PTE entries set up.
3614 * Note that DMA addresses are also the only part of the SG table we care about.
3616 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3623 if (WARN_ON(flags
== 0))
3627 if (flags
& PIN_GLOBAL
)
3628 bind_flags
|= I915_VMA_GLOBAL_BIND
;
3629 if (flags
& PIN_USER
)
3630 bind_flags
|= I915_VMA_LOCAL_BIND
;
3632 vma_flags
= vma
->flags
& (I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
);
3633 if (flags
& PIN_UPDATE
)
3634 bind_flags
|= vma_flags
;
3636 bind_flags
&= ~vma_flags
;
3637 if (bind_flags
== 0)
3640 if (vma_flags
== 0 && vma
->vm
->allocate_va_range
) {
3641 trace_i915_va_alloc(vma
);
3642 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3649 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3653 vma
->flags
|= bind_flags
;
3657 void __iomem
*i915_vma_pin_iomap(struct i915_vma
*vma
)
3661 /* Access through the GTT requires the device to be awake. */
3662 assert_rpm_wakelock_held(to_i915(vma
->vm
->dev
));
3664 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3665 if (WARN_ON(!i915_vma_is_map_and_fenceable(vma
)))
3666 return IO_ERR_PTR(-ENODEV
);
3668 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
3669 GEM_BUG_ON((vma
->flags
& I915_VMA_GLOBAL_BIND
) == 0);
3673 ptr
= io_mapping_map_wc(&i915_vm_to_ggtt(vma
->vm
)->mappable
,
3677 return IO_ERR_PTR(-ENOMEM
);
3682 __i915_vma_pin(vma
);
3686 void i915_vma_unpin_and_release(struct i915_vma
**p_vma
)
3688 struct i915_vma
*vma
;
3690 vma
= fetch_and_zero(p_vma
);
3694 i915_vma_unpin(vma
);