drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 #define GEN6_PPGTT_PD_ENTRIES 512
  32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  33
  34 /* PPGTT stuff */
  35 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  36
  37 #define GEN6_PDE_VALID                  (1 << 0)
  38 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  39 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  40
  41 #define GEN6_PTE_VALID                  (1 << 0)
  42 #define GEN6_PTE_UNCACHED               (1 << 1)
  43 #define HSW_PTE_UNCACHED                (0)
  44 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  45 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  46 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  47
  48 static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
  49                                       enum i915_cache_level level)
  50 {
  51         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 pte |= GEN6_PTE_CACHE_LLC_MLC;
  57                 break;
  58         case I915_CACHE_LLC:
  59                 pte |= GEN6_PTE_CACHE_LLC;
  60                 break;
  61         case I915_CACHE_NONE:
  62                 pte |= GEN6_PTE_UNCACHED;
  63                 break;
  64         default:
  65                 BUG();
  66         }
  67
  68         return pte;
  69 }
  70
  71 #define BYT_PTE_WRITEABLE               (1 << 1)
  72 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
  73
  74 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
  75                                      enum i915_cache_level level)
  76 {
  77         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  78         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  79
  80         /* Mark the page as writeable.  Other platforms don't have a
  81          * setting for read-only/writable, so this matches that behavior.
  82          */
  83         pte |= BYT_PTE_WRITEABLE;
  84
  85         if (level != I915_CACHE_NONE)
  86                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
  87
  88         return pte;
  89 }
  90
  91 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
  92                                      enum i915_cache_level level)
  93 {
  94         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  95         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  96
  97         if (level != I915_CACHE_NONE)
  98                 pte |= GEN6_PTE_CACHE_LLC;
  99
 100         return pte;
 101 }
 102
 103 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 104 {
 105         struct drm_i915_private *dev_priv = ppgtt->dev->dev_private;
 106         gen6_gtt_pte_t __iomem *pd_addr;
 107         uint32_t pd_entry;
 108         int i;
 109
 110         WARN_ON(ppgtt->pd_offset & 0x3f);
 111         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 112                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 113         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 114                 dma_addr_t pt_addr;
 115
 116                 pt_addr = ppgtt->pt_dma_addr[i];
 117                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 118                 pd_entry |= GEN6_PDE_VALID;
 119
 120                 writel(pd_entry, pd_addr + i);
 121         }
 122         readl(pd_addr);
 123 }
 124
 125 static int gen6_ppgtt_enable(struct drm_device *dev)
 126 {
 127         drm_i915_private_t *dev_priv = dev->dev_private;
 128         uint32_t pd_offset;
 129         struct intel_ring_buffer *ring;
 130         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 131         int i;
 132
 133         BUG_ON(ppgtt->pd_offset & 0x3f);
 134
 135         gen6_write_pdes(ppgtt);
 136
 137         pd_offset = ppgtt->pd_offset;
 138         pd_offset /= 64; /* in cachelines, */
 139         pd_offset <<= 16;
 140
 141         if (INTEL_INFO(dev)->gen == 6) {
 142                 uint32_t ecochk, gab_ctl, ecobits;
 143
 144                 ecobits = I915_READ(GAC_ECO_BITS);
 145                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 146                                          ECOBITS_PPGTT_CACHE64B);
 147
 148                 gab_ctl = I915_READ(GAB_CTL);
 149                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 150
 151                 ecochk = I915_READ(GAM_ECOCHK);
 152                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 153                                        ECOCHK_PPGTT_CACHE64B);
 154                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 155         } else if (INTEL_INFO(dev)->gen >= 7) {
 156                 uint32_t ecochk, ecobits;
 157
 158                 ecobits = I915_READ(GAC_ECO_BITS);
 159                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 160
 161                 ecochk = I915_READ(GAM_ECOCHK);
 162                 if (IS_HASWELL(dev)) {
 163                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 164                 } else {
 165                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 166                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 167                 }
 168                 I915_WRITE(GAM_ECOCHK, ecochk);
 169                 /* GFX_MODE is per-ring on gen7+ */
 170         }
 171
 172         for_each_ring(ring, dev_priv, i) {
 173                 if (INTEL_INFO(dev)->gen >= 7)
 174                         I915_WRITE(RING_MODE_GEN7(ring),
 175                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 176
 177                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 178                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 179         }
 180         return 0;
 181 }
 182
 183 /* PPGTT support for Sandybdrige/Gen6 and later */
 184 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 185                                    unsigned first_entry,
 186                                    unsigned num_entries)
 187 {
 188         struct drm_i915_private *dev_priv = ppgtt->dev->dev_private;
 189         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 190         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 191         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 192         unsigned last_pte, i;
 193
 194         scratch_pte = ppgtt->pte_encode(dev_priv->gtt.scratch.addr,
 195                                         I915_CACHE_LLC);
 196
 197         while (num_entries) {
 198                 last_pte = first_pte + num_entries;
 199                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 200                         last_pte = I915_PPGTT_PT_ENTRIES;
 201
 202                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 203
 204                 for (i = first_pte; i < last_pte; i++)
 205                         pt_vaddr[i] = scratch_pte;
 206
 207                 kunmap_atomic(pt_vaddr);
 208
 209                 num_entries -= last_pte - first_pte;
 210                 first_pte = 0;
 211                 act_pt++;
 212         }
 213 }
 214
 215 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 216                                       struct sg_table *pages,
 217                                       unsigned first_entry,
 218                                       enum i915_cache_level cache_level)
 219 {
 220         gen6_gtt_pte_t *pt_vaddr;
 221         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 222         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 223         struct sg_page_iter sg_iter;
 224
 225         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 226         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 227                 dma_addr_t page_addr;
 228
 229                 page_addr = sg_page_iter_dma_address(&sg_iter);
 230                 pt_vaddr[act_pte] = ppgtt->pte_encode(page_addr, cache_level);
 231                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 232                         kunmap_atomic(pt_vaddr);
 233                         act_pt++;
 234                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 235                         act_pte = 0;
 236
 237                 }
 238         }
 239         kunmap_atomic(pt_vaddr);
 240 }
 241
 242 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 243 {
 244         int i;
 245
 246         if (ppgtt->pt_dma_addr) {
 247                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 248                         pci_unmap_page(ppgtt->dev->pdev,
 249                                        ppgtt->pt_dma_addr[i],
 250                                        4096, PCI_DMA_BIDIRECTIONAL);
 251         }
 252
 253         kfree(ppgtt->pt_dma_addr);
 254         for (i = 0; i < ppgtt->num_pd_entries; i++)
 255                 __free_page(ppgtt->pt_pages[i]);
 256         kfree(ppgtt->pt_pages);
 257         kfree(ppgtt);
 258 }
 259
 260 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 261 {
 262         struct drm_device *dev = ppgtt->dev;
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         unsigned first_pd_entry_in_global_pt;
 265         int i;
 266         int ret = -ENOMEM;
 267
 268         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 269          * entries. For aliasing ppgtt support we just steal them at the end for
 270          * now. */
 271         first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 272
 273         if (IS_HASWELL(dev)) {
 274                 ppgtt->pte_encode = hsw_pte_encode;
 275         } else if (IS_VALLEYVIEW(dev)) {
 276                 ppgtt->pte_encode = byt_pte_encode;
 277         } else {
 278                 ppgtt->pte_encode = gen6_pte_encode;
 279         }
 280         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 281         ppgtt->enable = gen6_ppgtt_enable;
 282         ppgtt->clear_range = gen6_ppgtt_clear_range;
 283         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 284         ppgtt->cleanup = gen6_ppgtt_cleanup;
 285         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 286                                   GFP_KERNEL);
 287         if (!ppgtt->pt_pages)
 288                 return -ENOMEM;
 289
 290         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 291                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 292                 if (!ppgtt->pt_pages[i])
 293                         goto err_pt_alloc;
 294         }
 295
 296         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 297                                      GFP_KERNEL);
 298         if (!ppgtt->pt_dma_addr)
 299                 goto err_pt_alloc;
 300
 301         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 302                 dma_addr_t pt_addr;
 303
 304                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 305                                        PCI_DMA_BIDIRECTIONAL);
 306
 307                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 308                         ret = -EIO;
 309                         goto err_pd_pin;
 310
 311                 }
 312                 ppgtt->pt_dma_addr[i] = pt_addr;
 313         }
 314
 315         ppgtt->clear_range(ppgtt, 0,
 316                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 317
 318         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 319
 320         return 0;
 321
 322 err_pd_pin:
 323         if (ppgtt->pt_dma_addr) {
 324                 for (i--; i >= 0; i--)
 325                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 326                                        4096, PCI_DMA_BIDIRECTIONAL);
 327         }
 328 err_pt_alloc:
 329         kfree(ppgtt->pt_dma_addr);
 330         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 331                 if (ppgtt->pt_pages[i])
 332                         __free_page(ppgtt->pt_pages[i]);
 333         }
 334         kfree(ppgtt->pt_pages);
 335
 336         return ret;
 337 }
 338
 339 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 340 {
 341         struct drm_i915_private *dev_priv = dev->dev_private;
 342         struct i915_hw_ppgtt *ppgtt;
 343         int ret;
 344
 345         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 346         if (!ppgtt)
 347                 return -ENOMEM;
 348
 349         ppgtt->dev = dev;
 350
 351         if (INTEL_INFO(dev)->gen < 8)
 352                 ret = gen6_ppgtt_init(ppgtt);
 353         else
 354                 BUG();
 355
 356         if (ret)
 357                 kfree(ppgtt);
 358         else
 359                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 360
 361         return ret;
 362 }
 363
 364 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 365 {
 366         struct drm_i915_private *dev_priv = dev->dev_private;
 367         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 368
 369         if (!ppgtt)
 370                 return;
 371
 372         ppgtt->cleanup(ppgtt);
 373         dev_priv->mm.aliasing_ppgtt = NULL;
 374 }
 375
 376 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 377                             struct drm_i915_gem_object *obj,
 378                             enum i915_cache_level cache_level)
 379 {
 380         ppgtt->insert_entries(ppgtt, obj->pages,
 381                               obj->gtt_space->start >> PAGE_SHIFT,
 382                               cache_level);
 383 }
 384
 385 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 386                               struct drm_i915_gem_object *obj)
 387 {
 388         ppgtt->clear_range(ppgtt,
 389                            obj->gtt_space->start >> PAGE_SHIFT,
 390                            obj->base.size >> PAGE_SHIFT);
 391 }
 392
 393 extern int intel_iommu_gfx_mapped;
 394 /* Certain Gen5 chipsets require require idling the GPU before
 395  * unmapping anything from the GTT when VT-d is enabled.
 396  */
 397 static inline bool needs_idle_maps(struct drm_device *dev)
 398 {
 399 #ifdef CONFIG_INTEL_IOMMU
 400         /* Query intel_iommu to see if we need the workaround. Presumably that
 401          * was loaded first.
 402          */
 403         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 404                 return true;
 405 #endif
 406         return false;
 407 }
 408
 409 static bool do_idling(struct drm_i915_private *dev_priv)
 410 {
 411         bool ret = dev_priv->mm.interruptible;
 412
 413         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 414                 dev_priv->mm.interruptible = false;
 415                 if (i915_gpu_idle(dev_priv->dev)) {
 416                         DRM_ERROR("Couldn't idle GPU\n");
 417                         /* Wait a bit, in hopes it avoids the hang */
 418                         udelay(10);
 419                 }
 420         }
 421
 422         return ret;
 423 }
 424
 425 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 426 {
 427         if (unlikely(dev_priv->gtt.do_idle_maps))
 428                 dev_priv->mm.interruptible = interruptible;
 429 }
 430
 431 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         struct drm_i915_gem_object *obj;
 435
 436         /* First fill our portion of the GTT with scratch pages */
 437         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 438                                       dev_priv->gtt.total / PAGE_SIZE);
 439
 440         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 441                 i915_gem_clflush_object(obj);
 442                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 443         }
 444
 445         i915_gem_chipset_flush(dev);
 446 }
 447
 448 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 449 {
 450         if (obj->has_dma_mapping)
 451                 return 0;
 452
 453         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 454                         obj->pages->sgl, obj->pages->nents,
 455                         PCI_DMA_BIDIRECTIONAL))
 456                 return -ENOSPC;
 457
 458         return 0;
 459 }
 460
 461 /*
 462  * Binds an object into the global gtt with the specified cache level. The object
 463  * will be accessible to the GPU via commands whose operands reference offsets
 464  * within the global GTT as well as accessible by the GPU through the GMADR
 465  * mapped BAR (dev_priv->mm.gtt->gtt).
 466  */
 467 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 468                                      struct sg_table *st,
 469                                      unsigned int first_entry,
 470                                      enum i915_cache_level level)
 471 {
 472         struct drm_i915_private *dev_priv = dev->dev_private;
 473         gen6_gtt_pte_t __iomem *gtt_entries =
 474                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 475         int i = 0;
 476         struct sg_page_iter sg_iter;
 477         dma_addr_t addr;
 478
 479         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 480                 addr = sg_page_iter_dma_address(&sg_iter);
 481                 iowrite32(dev_priv->gtt.pte_encode(addr, level),
 482                           &gtt_entries[i]);
 483                 i++;
 484         }
 485
 486         /* XXX: This serves as a posting read to make sure that the PTE has
 487          * actually been updated. There is some concern that even though
 488          * registers and PTEs are within the same BAR that they are potentially
 489          * of NUMA access patterns. Therefore, even with the way we assume
 490          * hardware should work, we must keep this posting read for paranoia.
 491          */
 492         if (i != 0)
 493                 WARN_ON(readl(&gtt_entries[i-1])
 494                         != dev_priv->gtt.pte_encode(addr, level));
 495
 496         /* This next bit makes the above posting read even more important. We
 497          * want to flush the TLBs only after we're certain all the PTE updates
 498          * have finished.
 499          */
 500         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 501         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 502 }
 503
 504 static void gen6_ggtt_clear_range(struct drm_device *dev,
 505                                   unsigned int first_entry,
 506                                   unsigned int num_entries)
 507 {
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 510                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 511         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 512         int i;
 513
 514         if (WARN(num_entries > max_entries,
 515                  "First entry = %d; Num entries = %d (max=%d)\n",
 516                  first_entry, num_entries, max_entries))
 517                 num_entries = max_entries;
 518
 519         scratch_pte = dev_priv->gtt.pte_encode(dev_priv->gtt.scratch.addr,
 520                                                I915_CACHE_LLC);
 521         for (i = 0; i < num_entries; i++)
 522                 iowrite32(scratch_pte, &gtt_base[i]);
 523         readl(gtt_base);
 524 }
 525
 526
 527 static void i915_ggtt_insert_entries(struct drm_device *dev,
 528                                      struct sg_table *st,
 529                                      unsigned int pg_start,
 530                                      enum i915_cache_level cache_level)
 531 {
 532         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 533                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 534
 535         intel_gtt_insert_sg_entries(st, pg_start, flags);
 536
 537 }
 538
 539 static void i915_ggtt_clear_range(struct drm_device *dev,
 540                                   unsigned int first_entry,
 541                                   unsigned int num_entries)
 542 {
 543         intel_gtt_clear_range(first_entry, num_entries);
 544 }
 545
 546
 547 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 548                               enum i915_cache_level cache_level)
 549 {
 550         struct drm_device *dev = obj->base.dev;
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552
 553         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 554                                          obj->gtt_space->start >> PAGE_SHIFT,
 555                                          cache_level);
 556
 557         obj->has_global_gtt_mapping = 1;
 558 }
 559
 560 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 561 {
 562         struct drm_device *dev = obj->base.dev;
 563         struct drm_i915_private *dev_priv = dev->dev_private;
 564
 565         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 566                                       obj->gtt_space->start >> PAGE_SHIFT,
 567                                       obj->base.size >> PAGE_SHIFT);
 568
 569         obj->has_global_gtt_mapping = 0;
 570 }
 571
 572 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 573 {
 574         struct drm_device *dev = obj->base.dev;
 575         struct drm_i915_private *dev_priv = dev->dev_private;
 576         bool interruptible;
 577
 578         interruptible = do_idling(dev_priv);
 579
 580         if (!obj->has_dma_mapping)
 581                 dma_unmap_sg(&dev->pdev->dev,
 582                              obj->pages->sgl, obj->pages->nents,
 583                              PCI_DMA_BIDIRECTIONAL);
 584
 585         undo_idling(dev_priv, interruptible);
 586 }
 587
 588 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 589                                   unsigned long color,
 590                                   unsigned long *start,
 591                                   unsigned long *end)
 592 {
 593         if (node->color != color)
 594                 *start += 4096;
 595
 596         if (!list_empty(&node->node_list)) {
 597                 node = list_entry(node->node_list.next,
 598                                   struct drm_mm_node,
 599                                   node_list);
 600                 if (node->allocated && node->color != color)
 601                         *end -= 4096;
 602         }
 603 }
 604 void i915_gem_setup_global_gtt(struct drm_device *dev,
 605                                unsigned long start,
 606                                unsigned long mappable_end,
 607                                unsigned long end)
 608 {
 609         /* Let GEM Manage all of the aperture.
 610          *
 611          * However, leave one page at the end still bound to the scratch page.
 612          * There are a number of places where the hardware apparently prefetches
 613          * past the end of the object, and we've seen multiple hangs with the
 614          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 615          * aperture.  One page should be enough to keep any prefetching inside
 616          * of the aperture.
 617          */
 618         drm_i915_private_t *dev_priv = dev->dev_private;
 619         struct drm_mm_node *entry;
 620         struct drm_i915_gem_object *obj;
 621         unsigned long hole_start, hole_end;
 622
 623         BUG_ON(mappable_end > end);
 624
 625         /* Subtract the guard page ... */
 626         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 627         if (!HAS_LLC(dev))
 628                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 629
 630         /* Mark any preallocated objects as occupied */
 631         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 632                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 633                               obj->gtt_offset, obj->base.size);
 634
 635                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 636                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 637                                                      obj->gtt_offset,
 638                                                      obj->base.size,
 639                                                      false);
 640                 obj->has_global_gtt_mapping = 1;
 641         }
 642
 643         dev_priv->gtt.start = start;
 644         dev_priv->gtt.total = end - start;
 645
 646         /* Clear any non-preallocated blocks */
 647         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 648                              hole_start, hole_end) {
 649                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 650                               hole_start, hole_end);
 651                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 652                                               (hole_end-hole_start) / PAGE_SIZE);
 653         }
 654
 655         /* And finally clear the reserved guard page */
 656         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 657 }
 658
 659 static bool
 660 intel_enable_ppgtt(struct drm_device *dev)
 661 {
 662         if (i915_enable_ppgtt >= 0)
 663                 return i915_enable_ppgtt;
 664
 665 #ifdef CONFIG_INTEL_IOMMU
 666         /* Disable ppgtt on SNB if VT-d is on. */
 667         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 668                 return false;
 669 #endif
 670
 671         return true;
 672 }
 673
 674 void i915_gem_init_global_gtt(struct drm_device *dev)
 675 {
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         unsigned long gtt_size, mappable_size;
 678
 679         gtt_size = dev_priv->gtt.total;
 680         mappable_size = dev_priv->gtt.mappable_end;
 681
 682         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 683                 int ret;
 684
 685                 if (INTEL_INFO(dev)->gen <= 7) {
 686                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 687                          * aperture accordingly when using aliasing ppgtt. */
 688                         gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
 689                 }
 690
 691                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 692
 693                 ret = i915_gem_init_aliasing_ppgtt(dev);
 694                 if (!ret)
 695                         return;
 696
 697                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 698                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 699                 gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
 700         }
 701         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 702 }
 703
 704 static int setup_scratch_page(struct drm_device *dev)
 705 {
 706         struct drm_i915_private *dev_priv = dev->dev_private;
 707         struct page *page;
 708         dma_addr_t dma_addr;
 709
 710         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 711         if (page == NULL)
 712                 return -ENOMEM;
 713         get_page(page);
 714         set_pages_uc(page, 1);
 715
 716 #ifdef CONFIG_INTEL_IOMMU
 717         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 718                                 PCI_DMA_BIDIRECTIONAL);
 719         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 720                 return -EINVAL;
 721 #else
 722         dma_addr = page_to_phys(page);
 723 #endif
 724         dev_priv->gtt.scratch.page = page;
 725         dev_priv->gtt.scratch.addr = dma_addr;
 726
 727         return 0;
 728 }
 729
 730 static void teardown_scratch_page(struct drm_device *dev)
 731 {
 732         struct drm_i915_private *dev_priv = dev->dev_private;
 733         set_pages_wb(dev_priv->gtt.scratch.page, 1);
 734         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch.addr,
 735                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 736         put_page(dev_priv->gtt.scratch.page);
 737         __free_page(dev_priv->gtt.scratch.page);
 738 }
 739
 740 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 741 {
 742         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 743         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 744         return snb_gmch_ctl << 20;
 745 }
 746
 747 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 748 {
 749         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 750         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 751         return snb_gmch_ctl << 25; /* 32 MB units */
 752 }
 753
 754 static int gen6_gmch_probe(struct drm_device *dev,
 755                            size_t *gtt_total,
 756                            size_t *stolen,
 757                            phys_addr_t *mappable_base,
 758                            unsigned long *mappable_end)
 759 {
 760         struct drm_i915_private *dev_priv = dev->dev_private;
 761         phys_addr_t gtt_bus_addr;
 762         unsigned int gtt_size;
 763         u16 snb_gmch_ctl;
 764         int ret;
 765
 766         *mappable_base = pci_resource_start(dev->pdev, 2);
 767         *mappable_end = pci_resource_len(dev->pdev, 2);
 768
 769         /* 64/512MB is the current min/max we actually know of, but this is just
 770          * a coarse sanity check.
 771          */
 772         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 773                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 774                           dev_priv->gtt.mappable_end);
 775                 return -ENXIO;
 776         }
 777
 778         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 779                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 780         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 781         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 782
 783         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 784         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 785
 786         /* For Modern GENs the PTEs and register space are split in the BAR */
 787         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 788                 (pci_resource_len(dev->pdev, 0) / 2);
 789
 790         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 791         if (!dev_priv->gtt.gsm) {
 792                 DRM_ERROR("Failed to map the gtt page table\n");
 793                 return -ENOMEM;
 794         }
 795
 796         ret = setup_scratch_page(dev);
 797         if (ret)
 798                 DRM_ERROR("Scratch setup failed\n");
 799
 800         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 801         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 802
 803         return ret;
 804 }
 805
 806 static void gen6_gmch_remove(struct drm_device *dev)
 807 {
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         iounmap(dev_priv->gtt.gsm);
 810         teardown_scratch_page(dev_priv->dev);
 811 }
 812
 813 static int i915_gmch_probe(struct drm_device *dev,
 814                            size_t *gtt_total,
 815                            size_t *stolen,
 816                            phys_addr_t *mappable_base,
 817                            unsigned long *mappable_end)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         int ret;
 821
 822         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 823         if (!ret) {
 824                 DRM_ERROR("failed to set up gmch\n");
 825                 return -EIO;
 826         }
 827
 828         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 829
 830         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 831         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 832         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 833
 834         return 0;
 835 }
 836
 837 static void i915_gmch_remove(struct drm_device *dev)
 838 {
 839         intel_gmch_remove();
 840 }
 841
 842 int i915_gem_gtt_init(struct drm_device *dev)
 843 {
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         struct i915_gtt *gtt = &dev_priv->gtt;
 846         int ret;
 847
 848         if (INTEL_INFO(dev)->gen <= 5) {
 849                 gtt->gtt_probe = i915_gmch_probe;
 850                 gtt->gtt_remove = i915_gmch_remove;
 851         } else {
 852                 gtt->gtt_probe = gen6_gmch_probe;
 853                 gtt->gtt_remove = gen6_gmch_remove;
 854                 if (IS_HASWELL(dev))
 855                         gtt->pte_encode = hsw_pte_encode;
 856                 else if (IS_VALLEYVIEW(dev))
 857                         gtt->pte_encode = byt_pte_encode;
 858                 else
 859                         gtt->pte_encode = gen6_pte_encode;
 860         }
 861
 862         ret = gtt->gtt_probe(dev, &gtt->total, &gtt->stolen_size,
 863                              &gtt->mappable_base, &gtt->mappable_end);
 864         if (ret)
 865                 return ret;
 866
 867         /* GMADR is the PCI mmio aperture into the global GTT. */
 868         DRM_INFO("Memory usable by graphics device = %zdM\n", gtt->total >> 20);
 869         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
 870         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
 871
 872         return 0;
 873 }