2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 #define GEN6_PPGTT_PD_ENTRIES 512
32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
35 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
37 #define GEN6_PDE_VALID (1 << 0)
38 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
39 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
41 #define GEN6_PTE_VALID (1 << 0)
42 #define GEN6_PTE_UNCACHED (1 << 1)
43 #define HSW_PTE_UNCACHED (0)
44 #define GEN6_PTE_CACHE_LLC (2 << 1)
45 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
46 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
48 static gen6_gtt_pte_t
gen6_pte_encode(dma_addr_t addr
,
49 enum i915_cache_level level
)
51 gen6_gtt_pte_t pte
= GEN6_PTE_VALID
;
52 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
55 case I915_CACHE_LLC_MLC
:
56 pte
|= GEN6_PTE_CACHE_LLC_MLC
;
59 pte
|= GEN6_PTE_CACHE_LLC
;
62 pte
|= GEN6_PTE_UNCACHED
;
71 #define BYT_PTE_WRITEABLE (1 << 1)
72 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
74 static gen6_gtt_pte_t
byt_pte_encode(dma_addr_t addr
,
75 enum i915_cache_level level
)
77 gen6_gtt_pte_t pte
= GEN6_PTE_VALID
;
78 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
80 /* Mark the page as writeable. Other platforms don't have a
81 * setting for read-only/writable, so this matches that behavior.
83 pte
|= BYT_PTE_WRITEABLE
;
85 if (level
!= I915_CACHE_NONE
)
86 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
91 static gen6_gtt_pte_t
hsw_pte_encode(dma_addr_t addr
,
92 enum i915_cache_level level
)
94 gen6_gtt_pte_t pte
= GEN6_PTE_VALID
;
95 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
97 if (level
!= I915_CACHE_NONE
)
98 pte
|= GEN6_PTE_CACHE_LLC
;
103 static void gen6_write_pdes(struct i915_hw_ppgtt
*ppgtt
)
105 struct drm_i915_private
*dev_priv
= ppgtt
->dev
->dev_private
;
106 gen6_gtt_pte_t __iomem
*pd_addr
;
110 WARN_ON(ppgtt
->pd_offset
& 0x3f);
111 pd_addr
= (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
112 ppgtt
->pd_offset
/ sizeof(gen6_gtt_pte_t
);
113 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
116 pt_addr
= ppgtt
->pt_dma_addr
[i
];
117 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
118 pd_entry
|= GEN6_PDE_VALID
;
120 writel(pd_entry
, pd_addr
+ i
);
125 static int gen6_ppgtt_enable(struct drm_device
*dev
)
127 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
129 struct intel_ring_buffer
*ring
;
130 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
133 BUG_ON(ppgtt
->pd_offset
& 0x3f);
135 gen6_write_pdes(ppgtt
);
137 pd_offset
= ppgtt
->pd_offset
;
138 pd_offset
/= 64; /* in cachelines, */
141 if (INTEL_INFO(dev
)->gen
== 6) {
142 uint32_t ecochk
, gab_ctl
, ecobits
;
144 ecobits
= I915_READ(GAC_ECO_BITS
);
145 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
146 ECOBITS_PPGTT_CACHE64B
);
148 gab_ctl
= I915_READ(GAB_CTL
);
149 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
151 ecochk
= I915_READ(GAM_ECOCHK
);
152 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
153 ECOCHK_PPGTT_CACHE64B
);
154 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
155 } else if (INTEL_INFO(dev
)->gen
>= 7) {
156 uint32_t ecochk
, ecobits
;
158 ecobits
= I915_READ(GAC_ECO_BITS
);
159 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
161 ecochk
= I915_READ(GAM_ECOCHK
);
162 if (IS_HASWELL(dev
)) {
163 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
165 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
166 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
168 I915_WRITE(GAM_ECOCHK
, ecochk
);
169 /* GFX_MODE is per-ring on gen7+ */
172 for_each_ring(ring
, dev_priv
, i
) {
173 if (INTEL_INFO(dev
)->gen
>= 7)
174 I915_WRITE(RING_MODE_GEN7(ring
),
175 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
177 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
178 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
183 /* PPGTT support for Sandybdrige/Gen6 and later */
184 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt
*ppgtt
,
185 unsigned first_entry
,
186 unsigned num_entries
)
188 struct drm_i915_private
*dev_priv
= ppgtt
->dev
->dev_private
;
189 gen6_gtt_pte_t
*pt_vaddr
, scratch_pte
;
190 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
191 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
192 unsigned last_pte
, i
;
194 scratch_pte
= ppgtt
->pte_encode(dev_priv
->gtt
.scratch
.addr
,
197 while (num_entries
) {
198 last_pte
= first_pte
+ num_entries
;
199 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
200 last_pte
= I915_PPGTT_PT_ENTRIES
;
202 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
204 for (i
= first_pte
; i
< last_pte
; i
++)
205 pt_vaddr
[i
] = scratch_pte
;
207 kunmap_atomic(pt_vaddr
);
209 num_entries
-= last_pte
- first_pte
;
215 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt
*ppgtt
,
216 struct sg_table
*pages
,
217 unsigned first_entry
,
218 enum i915_cache_level cache_level
)
220 gen6_gtt_pte_t
*pt_vaddr
;
221 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
222 unsigned act_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
223 struct sg_page_iter sg_iter
;
225 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
226 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
227 dma_addr_t page_addr
;
229 page_addr
= sg_page_iter_dma_address(&sg_iter
);
230 pt_vaddr
[act_pte
] = ppgtt
->pte_encode(page_addr
, cache_level
);
231 if (++act_pte
== I915_PPGTT_PT_ENTRIES
) {
232 kunmap_atomic(pt_vaddr
);
234 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
239 kunmap_atomic(pt_vaddr
);
242 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt
*ppgtt
)
246 if (ppgtt
->pt_dma_addr
) {
247 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
248 pci_unmap_page(ppgtt
->dev
->pdev
,
249 ppgtt
->pt_dma_addr
[i
],
250 4096, PCI_DMA_BIDIRECTIONAL
);
253 kfree(ppgtt
->pt_dma_addr
);
254 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
255 __free_page(ppgtt
->pt_pages
[i
]);
256 kfree(ppgtt
->pt_pages
);
260 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
262 struct drm_device
*dev
= ppgtt
->dev
;
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 unsigned first_pd_entry_in_global_pt
;
268 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
269 * entries. For aliasing ppgtt support we just steal them at the end for
271 first_pd_entry_in_global_pt
= gtt_total_entries(dev_priv
->gtt
);
273 if (IS_HASWELL(dev
)) {
274 ppgtt
->pte_encode
= hsw_pte_encode
;
275 } else if (IS_VALLEYVIEW(dev
)) {
276 ppgtt
->pte_encode
= byt_pte_encode
;
278 ppgtt
->pte_encode
= gen6_pte_encode
;
280 ppgtt
->num_pd_entries
= GEN6_PPGTT_PD_ENTRIES
;
281 ppgtt
->enable
= gen6_ppgtt_enable
;
282 ppgtt
->clear_range
= gen6_ppgtt_clear_range
;
283 ppgtt
->insert_entries
= gen6_ppgtt_insert_entries
;
284 ppgtt
->cleanup
= gen6_ppgtt_cleanup
;
285 ppgtt
->pt_pages
= kzalloc(sizeof(struct page
*)*ppgtt
->num_pd_entries
,
287 if (!ppgtt
->pt_pages
)
290 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
291 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
292 if (!ppgtt
->pt_pages
[i
])
296 ppgtt
->pt_dma_addr
= kzalloc(sizeof(dma_addr_t
) *ppgtt
->num_pd_entries
,
298 if (!ppgtt
->pt_dma_addr
)
301 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
304 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
305 PCI_DMA_BIDIRECTIONAL
);
307 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
312 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
315 ppgtt
->clear_range(ppgtt
, 0,
316 ppgtt
->num_pd_entries
*I915_PPGTT_PT_ENTRIES
);
318 ppgtt
->pd_offset
= first_pd_entry_in_global_pt
* sizeof(gen6_gtt_pte_t
);
323 if (ppgtt
->pt_dma_addr
) {
324 for (i
--; i
>= 0; i
--)
325 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
326 4096, PCI_DMA_BIDIRECTIONAL
);
329 kfree(ppgtt
->pt_dma_addr
);
330 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
331 if (ppgtt
->pt_pages
[i
])
332 __free_page(ppgtt
->pt_pages
[i
]);
334 kfree(ppgtt
->pt_pages
);
339 static int i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
)
341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 struct i915_hw_ppgtt
*ppgtt
;
345 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
351 if (INTEL_INFO(dev
)->gen
< 8)
352 ret
= gen6_ppgtt_init(ppgtt
);
359 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
364 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
)
366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
367 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
372 ppgtt
->cleanup(ppgtt
);
373 dev_priv
->mm
.aliasing_ppgtt
= NULL
;
376 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
377 struct drm_i915_gem_object
*obj
,
378 enum i915_cache_level cache_level
)
380 ppgtt
->insert_entries(ppgtt
, obj
->pages
,
381 i915_gem_obj_ggtt_offset(obj
) >> PAGE_SHIFT
,
385 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
386 struct drm_i915_gem_object
*obj
)
388 ppgtt
->clear_range(ppgtt
,
389 i915_gem_obj_ggtt_offset(obj
) >> PAGE_SHIFT
,
390 obj
->base
.size
>> PAGE_SHIFT
);
393 extern int intel_iommu_gfx_mapped
;
394 /* Certain Gen5 chipsets require require idling the GPU before
395 * unmapping anything from the GTT when VT-d is enabled.
397 static inline bool needs_idle_maps(struct drm_device
*dev
)
399 #ifdef CONFIG_INTEL_IOMMU
400 /* Query intel_iommu to see if we need the workaround. Presumably that
403 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
409 static bool do_idling(struct drm_i915_private
*dev_priv
)
411 bool ret
= dev_priv
->mm
.interruptible
;
413 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
414 dev_priv
->mm
.interruptible
= false;
415 if (i915_gpu_idle(dev_priv
->dev
)) {
416 DRM_ERROR("Couldn't idle GPU\n");
417 /* Wait a bit, in hopes it avoids the hang */
425 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
427 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
428 dev_priv
->mm
.interruptible
= interruptible
;
431 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
434 struct drm_i915_gem_object
*obj
;
436 /* First fill our portion of the GTT with scratch pages */
437 dev_priv
->gtt
.gtt_clear_range(dev
, dev_priv
->gtt
.start
/ PAGE_SIZE
,
438 dev_priv
->gtt
.total
/ PAGE_SIZE
);
440 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
441 i915_gem_clflush_object(obj
);
442 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
445 i915_gem_chipset_flush(dev
);
448 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
450 if (obj
->has_dma_mapping
)
453 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
454 obj
->pages
->sgl
, obj
->pages
->nents
,
455 PCI_DMA_BIDIRECTIONAL
))
462 * Binds an object into the global gtt with the specified cache level. The object
463 * will be accessible to the GPU via commands whose operands reference offsets
464 * within the global GTT as well as accessible by the GPU through the GMADR
465 * mapped BAR (dev_priv->mm.gtt->gtt).
467 static void gen6_ggtt_insert_entries(struct drm_device
*dev
,
469 unsigned int first_entry
,
470 enum i915_cache_level level
)
472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
473 gen6_gtt_pte_t __iomem
*gtt_entries
=
474 (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
476 struct sg_page_iter sg_iter
;
479 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
480 addr
= sg_page_iter_dma_address(&sg_iter
);
481 iowrite32(dev_priv
->gtt
.pte_encode(addr
, level
),
486 /* XXX: This serves as a posting read to make sure that the PTE has
487 * actually been updated. There is some concern that even though
488 * registers and PTEs are within the same BAR that they are potentially
489 * of NUMA access patterns. Therefore, even with the way we assume
490 * hardware should work, we must keep this posting read for paranoia.
493 WARN_ON(readl(>t_entries
[i
-1])
494 != dev_priv
->gtt
.pte_encode(addr
, level
));
496 /* This next bit makes the above posting read even more important. We
497 * want to flush the TLBs only after we're certain all the PTE updates
500 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
501 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
504 static void gen6_ggtt_clear_range(struct drm_device
*dev
,
505 unsigned int first_entry
,
506 unsigned int num_entries
)
508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
509 gen6_gtt_pte_t scratch_pte
, __iomem
*gtt_base
=
510 (gen6_gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
511 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
514 if (WARN(num_entries
> max_entries
,
515 "First entry = %d; Num entries = %d (max=%d)\n",
516 first_entry
, num_entries
, max_entries
))
517 num_entries
= max_entries
;
519 scratch_pte
= dev_priv
->gtt
.pte_encode(dev_priv
->gtt
.scratch
.addr
,
521 for (i
= 0; i
< num_entries
; i
++)
522 iowrite32(scratch_pte
, >t_base
[i
]);
527 static void i915_ggtt_insert_entries(struct drm_device
*dev
,
529 unsigned int pg_start
,
530 enum i915_cache_level cache_level
)
532 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
533 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
535 intel_gtt_insert_sg_entries(st
, pg_start
, flags
);
539 static void i915_ggtt_clear_range(struct drm_device
*dev
,
540 unsigned int first_entry
,
541 unsigned int num_entries
)
543 intel_gtt_clear_range(first_entry
, num_entries
);
547 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
548 enum i915_cache_level cache_level
)
550 struct drm_device
*dev
= obj
->base
.dev
;
551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
553 dev_priv
->gtt
.gtt_insert_entries(dev
, obj
->pages
,
554 i915_gem_obj_ggtt_offset(obj
) >> PAGE_SHIFT
,
557 obj
->has_global_gtt_mapping
= 1;
560 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
)
562 struct drm_device
*dev
= obj
->base
.dev
;
563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
565 dev_priv
->gtt
.gtt_clear_range(obj
->base
.dev
,
566 i915_gem_obj_ggtt_offset(obj
) >> PAGE_SHIFT
,
567 obj
->base
.size
>> PAGE_SHIFT
);
569 obj
->has_global_gtt_mapping
= 0;
572 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
574 struct drm_device
*dev
= obj
->base
.dev
;
575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
578 interruptible
= do_idling(dev_priv
);
580 if (!obj
->has_dma_mapping
)
581 dma_unmap_sg(&dev
->pdev
->dev
,
582 obj
->pages
->sgl
, obj
->pages
->nents
,
583 PCI_DMA_BIDIRECTIONAL
);
585 undo_idling(dev_priv
, interruptible
);
588 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
590 unsigned long *start
,
593 if (node
->color
!= color
)
596 if (!list_empty(&node
->node_list
)) {
597 node
= list_entry(node
->node_list
.next
,
600 if (node
->allocated
&& node
->color
!= color
)
604 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
606 unsigned long mappable_end
,
609 /* Let GEM Manage all of the aperture.
611 * However, leave one page at the end still bound to the scratch page.
612 * There are a number of places where the hardware apparently prefetches
613 * past the end of the object, and we've seen multiple hangs with the
614 * GPU head pointer stuck in a batchbuffer bound at the last page of the
615 * aperture. One page should be enough to keep any prefetching inside
618 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
619 struct drm_mm_node
*entry
;
620 struct drm_i915_gem_object
*obj
;
621 unsigned long hole_start
, hole_end
;
623 BUG_ON(mappable_end
> end
);
625 /* Subtract the guard page ... */
626 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
- PAGE_SIZE
);
628 dev_priv
->mm
.gtt_space
.color_adjust
= i915_gtt_color_adjust
;
630 /* Mark any preallocated objects as occupied */
631 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
633 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
634 obj
->gtt_offset
, obj
->base
.size
);
636 BUG_ON(obj
->gtt_space
!= I915_GTT_RESERVED
);
637 obj
->gtt_space
= kzalloc(sizeof(*obj
->gtt_space
), GFP_KERNEL
);
638 if (!obj
->gtt_space
) {
639 DRM_ERROR("Failed to preserve object at offset %x\n",
643 obj
->gtt_space
->start
= obj
->gtt_offset
;
644 obj
->gtt_space
->size
= obj
->base
.size
;
645 ret
= drm_mm_reserve_node(&dev_priv
->mm
.gtt_space
,
648 DRM_DEBUG_KMS("Reservation failed\n");
649 kfree(obj
->gtt_space
);
650 obj
->gtt_space
= NULL
;
652 obj
->has_global_gtt_mapping
= 1;
655 dev_priv
->gtt
.start
= start
;
656 dev_priv
->gtt
.total
= end
- start
;
658 /* Clear any non-preallocated blocks */
659 drm_mm_for_each_hole(entry
, &dev_priv
->mm
.gtt_space
,
660 hole_start
, hole_end
) {
661 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
662 hole_start
, hole_end
);
663 dev_priv
->gtt
.gtt_clear_range(dev
, hole_start
/ PAGE_SIZE
,
664 (hole_end
-hole_start
) / PAGE_SIZE
);
667 /* And finally clear the reserved guard page */
668 dev_priv
->gtt
.gtt_clear_range(dev
, end
/ PAGE_SIZE
- 1, 1);
672 intel_enable_ppgtt(struct drm_device
*dev
)
674 if (i915_enable_ppgtt
>= 0)
675 return i915_enable_ppgtt
;
677 #ifdef CONFIG_INTEL_IOMMU
678 /* Disable ppgtt on SNB if VT-d is on. */
679 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
686 void i915_gem_init_global_gtt(struct drm_device
*dev
)
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 unsigned long gtt_size
, mappable_size
;
691 gtt_size
= dev_priv
->gtt
.total
;
692 mappable_size
= dev_priv
->gtt
.mappable_end
;
694 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
697 if (INTEL_INFO(dev
)->gen
<= 7) {
698 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
699 * aperture accordingly when using aliasing ppgtt. */
700 gtt_size
-= GEN6_PPGTT_PD_ENTRIES
* PAGE_SIZE
;
703 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
705 ret
= i915_gem_init_aliasing_ppgtt(dev
);
709 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret
);
710 drm_mm_takedown(&dev_priv
->mm
.gtt_space
);
711 gtt_size
+= GEN6_PPGTT_PD_ENTRIES
* PAGE_SIZE
;
713 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
716 static int setup_scratch_page(struct drm_device
*dev
)
718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
722 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
726 set_pages_uc(page
, 1);
728 #ifdef CONFIG_INTEL_IOMMU
729 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
730 PCI_DMA_BIDIRECTIONAL
);
731 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
734 dma_addr
= page_to_phys(page
);
736 dev_priv
->gtt
.scratch
.page
= page
;
737 dev_priv
->gtt
.scratch
.addr
= dma_addr
;
742 static void teardown_scratch_page(struct drm_device
*dev
)
744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
745 set_pages_wb(dev_priv
->gtt
.scratch
.page
, 1);
746 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.scratch
.addr
,
747 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
748 put_page(dev_priv
->gtt
.scratch
.page
);
749 __free_page(dev_priv
->gtt
.scratch
.page
);
752 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
754 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
755 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
756 return snb_gmch_ctl
<< 20;
759 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
761 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
762 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
763 return snb_gmch_ctl
<< 25; /* 32 MB units */
766 static int gen6_gmch_probe(struct drm_device
*dev
,
769 phys_addr_t
*mappable_base
,
770 unsigned long *mappable_end
)
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
773 phys_addr_t gtt_bus_addr
;
774 unsigned int gtt_size
;
778 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
779 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
781 /* 64/512MB is the current min/max we actually know of, but this is just
782 * a coarse sanity check.
784 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
785 DRM_ERROR("Unknown GMADR size (%lx)\n",
786 dev_priv
->gtt
.mappable_end
);
790 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
791 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
792 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
793 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
795 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
796 *gtt_total
= (gtt_size
/ sizeof(gen6_gtt_pte_t
)) << PAGE_SHIFT
;
798 /* For Modern GENs the PTEs and register space are split in the BAR */
799 gtt_bus_addr
= pci_resource_start(dev
->pdev
, 0) +
800 (pci_resource_len(dev
->pdev
, 0) / 2);
802 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_bus_addr
, gtt_size
);
803 if (!dev_priv
->gtt
.gsm
) {
804 DRM_ERROR("Failed to map the gtt page table\n");
808 ret
= setup_scratch_page(dev
);
810 DRM_ERROR("Scratch setup failed\n");
812 dev_priv
->gtt
.gtt_clear_range
= gen6_ggtt_clear_range
;
813 dev_priv
->gtt
.gtt_insert_entries
= gen6_ggtt_insert_entries
;
818 static void gen6_gmch_remove(struct drm_device
*dev
)
820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
821 iounmap(dev_priv
->gtt
.gsm
);
822 teardown_scratch_page(dev_priv
->dev
);
825 static int i915_gmch_probe(struct drm_device
*dev
,
828 phys_addr_t
*mappable_base
,
829 unsigned long *mappable_end
)
831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
834 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
836 DRM_ERROR("failed to set up gmch\n");
840 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
842 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
843 dev_priv
->gtt
.gtt_clear_range
= i915_ggtt_clear_range
;
844 dev_priv
->gtt
.gtt_insert_entries
= i915_ggtt_insert_entries
;
849 static void i915_gmch_remove(struct drm_device
*dev
)
854 int i915_gem_gtt_init(struct drm_device
*dev
)
856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
857 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
860 if (INTEL_INFO(dev
)->gen
<= 5) {
861 gtt
->gtt_probe
= i915_gmch_probe
;
862 gtt
->gtt_remove
= i915_gmch_remove
;
864 gtt
->gtt_probe
= gen6_gmch_probe
;
865 gtt
->gtt_remove
= gen6_gmch_remove
;
867 gtt
->pte_encode
= hsw_pte_encode
;
868 else if (IS_VALLEYVIEW(dev
))
869 gtt
->pte_encode
= byt_pte_encode
;
871 gtt
->pte_encode
= gen6_pte_encode
;
874 ret
= gtt
->gtt_probe(dev
, >t
->total
, >t
->stolen_size
,
875 >t
->mappable_base
, >t
->mappable_end
);
879 /* GMADR is the PCI mmio aperture into the global GTT. */
880 DRM_INFO("Memory usable by graphics device = %zdM\n", gtt
->total
>> 20);
881 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt
->mappable_end
>> 20);
882 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);