2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
196 const enum i915_cache_level level
)
198 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
200 if (level
!= I915_CACHE_NONE
)
201 pde
|= PPAT_CACHED_PDE_INDEX
;
203 pde
|= PPAT_UNCACHED_INDEX
;
207 #define gen8_pdpe_encode gen8_pde_encode
208 #define gen8_pml4e_encode gen8_pde_encode
210 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
211 enum i915_cache_level level
,
212 bool valid
, u32 unused
)
214 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
215 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
218 case I915_CACHE_L3_LLC
:
220 pte
|= GEN6_PTE_CACHE_LLC
;
222 case I915_CACHE_NONE
:
223 pte
|= GEN6_PTE_UNCACHED
;
232 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
233 enum i915_cache_level level
,
234 bool valid
, u32 unused
)
236 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
237 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
240 case I915_CACHE_L3_LLC
:
241 pte
|= GEN7_PTE_CACHE_L3_LLC
;
244 pte
|= GEN6_PTE_CACHE_LLC
;
246 case I915_CACHE_NONE
:
247 pte
|= GEN6_PTE_UNCACHED
;
256 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
257 enum i915_cache_level level
,
258 bool valid
, u32 flags
)
260 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
261 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
263 if (!(flags
& PTE_READ_ONLY
))
264 pte
|= BYT_PTE_WRITEABLE
;
266 if (level
!= I915_CACHE_NONE
)
267 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
272 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
273 enum i915_cache_level level
,
274 bool valid
, u32 unused
)
276 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
277 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
279 if (level
!= I915_CACHE_NONE
)
280 pte
|= HSW_WB_LLC_AGE3
;
285 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
286 enum i915_cache_level level
,
287 bool valid
, u32 unused
)
289 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
290 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
293 case I915_CACHE_NONE
:
296 pte
|= HSW_WT_ELLC_LLC_AGE3
;
299 pte
|= HSW_WB_ELLC_LLC_AGE3
;
306 static int __setup_page_dma(struct drm_device
*dev
,
307 struct i915_page_dma
*p
, gfp_t flags
)
309 struct device
*device
= &dev
->pdev
->dev
;
311 p
->page
= alloc_page(flags
);
315 p
->daddr
= dma_map_page(device
,
316 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
318 if (dma_mapping_error(device
, p
->daddr
)) {
319 __free_page(p
->page
);
326 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
328 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
331 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
333 if (WARN_ON(!p
->page
))
336 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
337 __free_page(p
->page
);
338 memset(p
, 0, sizeof(*p
));
341 static void *kmap_page_dma(struct i915_page_dma
*p
)
343 return kmap_atomic(p
->page
);
346 /* We use the flushing unmap only with ppgtt structures:
347 * page directories, page tables and scratch pages.
349 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
351 /* There are only few exceptions for gen >=6. chv and bxt.
352 * And we are not sure about the latter so play safe for now.
354 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
355 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
357 kunmap_atomic(vaddr
);
360 #define kmap_px(px) kmap_page_dma(px_base(px))
361 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
363 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
364 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
365 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
366 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
368 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
372 uint64_t * const vaddr
= kmap_page_dma(p
);
374 for (i
= 0; i
< 512; i
++)
377 kunmap_page_dma(dev
, vaddr
);
380 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
381 const uint32_t val32
)
387 fill_page_dma(dev
, p
, v
);
390 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
392 struct i915_page_scratch
*sp
;
395 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
397 return ERR_PTR(-ENOMEM
);
399 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
405 set_pages_uc(px_page(sp
), 1);
410 static void free_scratch_page(struct drm_device
*dev
,
411 struct i915_page_scratch
*sp
)
413 set_pages_wb(px_page(sp
), 1);
419 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
421 struct i915_page_table
*pt
;
422 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
423 GEN8_PTES
: GEN6_PTES
;
426 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
428 return ERR_PTR(-ENOMEM
);
430 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
436 ret
= setup_px(dev
, pt
);
443 kfree(pt
->used_ptes
);
450 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
453 kfree(pt
->used_ptes
);
457 static void gen8_initialize_pt(struct i915_address_space
*vm
,
458 struct i915_page_table
*pt
)
460 gen8_pte_t scratch_pte
;
462 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
463 I915_CACHE_LLC
, true);
465 fill_px(vm
->dev
, pt
, scratch_pte
);
468 static void gen6_initialize_pt(struct i915_address_space
*vm
,
469 struct i915_page_table
*pt
)
471 gen6_pte_t scratch_pte
;
473 WARN_ON(px_dma(vm
->scratch_page
) == 0);
475 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
476 I915_CACHE_LLC
, true, 0);
478 fill32_px(vm
->dev
, pt
, scratch_pte
);
481 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
483 struct i915_page_directory
*pd
;
486 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
488 return ERR_PTR(-ENOMEM
);
490 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
491 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
495 ret
= setup_px(dev
, pd
);
502 kfree(pd
->used_pdes
);
509 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
513 kfree(pd
->used_pdes
);
518 static void gen8_initialize_pd(struct i915_address_space
*vm
,
519 struct i915_page_directory
*pd
)
521 gen8_pde_t scratch_pde
;
523 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
525 fill_px(vm
->dev
, pd
, scratch_pde
);
528 static int __pdp_init(struct drm_device
*dev
,
529 struct i915_page_directory_pointer
*pdp
)
531 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
533 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
534 sizeof(unsigned long),
536 if (!pdp
->used_pdpes
)
539 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
541 if (!pdp
->page_directory
) {
542 kfree(pdp
->used_pdpes
);
543 /* the PDP might be the statically allocated top level. Keep it
544 * as clean as possible */
545 pdp
->used_pdpes
= NULL
;
552 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
554 kfree(pdp
->used_pdpes
);
555 kfree(pdp
->page_directory
);
556 pdp
->page_directory
= NULL
;
560 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
562 struct i915_page_directory_pointer
*pdp
;
565 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
567 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
569 return ERR_PTR(-ENOMEM
);
571 ret
= __pdp_init(dev
, pdp
);
575 ret
= setup_px(dev
, pdp
);
589 static void free_pdp(struct drm_device
*dev
,
590 struct i915_page_directory_pointer
*pdp
)
593 if (USES_FULL_48BIT_PPGTT(dev
)) {
594 cleanup_px(dev
, pdp
);
599 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
600 struct i915_page_directory_pointer
*pdp
)
602 gen8_ppgtt_pdpe_t scratch_pdpe
;
604 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
606 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
609 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
610 struct i915_pml4
*pml4
)
612 gen8_ppgtt_pml4e_t scratch_pml4e
;
614 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
617 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
621 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
622 struct i915_page_directory_pointer
*pdp
,
623 struct i915_page_directory
*pd
,
626 gen8_ppgtt_pdpe_t
*page_directorypo
;
628 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
631 page_directorypo
= kmap_px(pdp
);
632 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
633 kunmap_px(ppgtt
, page_directorypo
);
637 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
638 struct i915_pml4
*pml4
,
639 struct i915_page_directory_pointer
*pdp
,
642 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
644 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
645 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
646 kunmap_px(ppgtt
, pagemap
);
649 /* Broadwell Page Directory Pointer Descriptors */
650 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
654 struct intel_engine_cs
*ring
= req
->ring
;
659 ret
= intel_ring_begin(req
, 6);
663 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
664 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
665 intel_ring_emit(ring
, upper_32_bits(addr
));
666 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
667 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
668 intel_ring_emit(ring
, lower_32_bits(addr
));
669 intel_ring_advance(ring
);
674 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
675 struct drm_i915_gem_request
*req
)
679 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
680 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
682 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
690 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
691 struct drm_i915_gem_request
*req
)
693 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
696 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
697 struct i915_page_directory_pointer
*pdp
,
700 gen8_pte_t scratch_pte
)
702 struct i915_hw_ppgtt
*ppgtt
=
703 container_of(vm
, struct i915_hw_ppgtt
, base
);
704 gen8_pte_t
*pt_vaddr
;
705 unsigned pdpe
= gen8_pdpe_index(start
);
706 unsigned pde
= gen8_pde_index(start
);
707 unsigned pte
= gen8_pte_index(start
);
708 unsigned num_entries
= length
>> PAGE_SHIFT
;
709 unsigned last_pte
, i
;
714 while (num_entries
) {
715 struct i915_page_directory
*pd
;
716 struct i915_page_table
*pt
;
718 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
721 pd
= pdp
->page_directory
[pdpe
];
723 if (WARN_ON(!pd
->page_table
[pde
]))
726 pt
= pd
->page_table
[pde
];
728 if (WARN_ON(!px_page(pt
)))
731 last_pte
= pte
+ num_entries
;
732 if (last_pte
> GEN8_PTES
)
733 last_pte
= GEN8_PTES
;
735 pt_vaddr
= kmap_px(pt
);
737 for (i
= pte
; i
< last_pte
; i
++) {
738 pt_vaddr
[i
] = scratch_pte
;
742 kunmap_px(ppgtt
, pt
);
745 if (++pde
== I915_PDES
) {
746 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
753 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
758 struct i915_hw_ppgtt
*ppgtt
=
759 container_of(vm
, struct i915_hw_ppgtt
, base
);
760 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
761 I915_CACHE_LLC
, use_scratch
);
763 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
764 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
767 uint64_t templ4
, pml4e
;
768 struct i915_page_directory_pointer
*pdp
;
770 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, templ4
, pml4e
) {
771 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
778 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
779 struct i915_page_directory_pointer
*pdp
,
780 struct sg_page_iter
*sg_iter
,
782 enum i915_cache_level cache_level
)
784 struct i915_hw_ppgtt
*ppgtt
=
785 container_of(vm
, struct i915_hw_ppgtt
, base
);
786 gen8_pte_t
*pt_vaddr
;
787 unsigned pdpe
= gen8_pdpe_index(start
);
788 unsigned pde
= gen8_pde_index(start
);
789 unsigned pte
= gen8_pte_index(start
);
793 while (__sg_page_iter_next(sg_iter
)) {
794 if (pt_vaddr
== NULL
) {
795 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
796 struct i915_page_table
*pt
= pd
->page_table
[pde
];
797 pt_vaddr
= kmap_px(pt
);
801 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
803 if (++pte
== GEN8_PTES
) {
804 kunmap_px(ppgtt
, pt_vaddr
);
806 if (++pde
== I915_PDES
) {
807 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
816 kunmap_px(ppgtt
, pt_vaddr
);
819 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
820 struct sg_table
*pages
,
822 enum i915_cache_level cache_level
,
825 struct i915_hw_ppgtt
*ppgtt
=
826 container_of(vm
, struct i915_hw_ppgtt
, base
);
827 struct sg_page_iter sg_iter
;
829 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
831 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
832 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
835 struct i915_page_directory_pointer
*pdp
;
836 uint64_t templ4
, pml4e
;
837 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
839 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, templ4
, pml4e
) {
840 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
846 static void gen8_free_page_tables(struct drm_device
*dev
,
847 struct i915_page_directory
*pd
)
854 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
855 if (WARN_ON(!pd
->page_table
[i
]))
858 free_pt(dev
, pd
->page_table
[i
]);
859 pd
->page_table
[i
] = NULL
;
863 static int gen8_init_scratch(struct i915_address_space
*vm
)
865 struct drm_device
*dev
= vm
->dev
;
867 vm
->scratch_page
= alloc_scratch_page(dev
);
868 if (IS_ERR(vm
->scratch_page
))
869 return PTR_ERR(vm
->scratch_page
);
871 vm
->scratch_pt
= alloc_pt(dev
);
872 if (IS_ERR(vm
->scratch_pt
)) {
873 free_scratch_page(dev
, vm
->scratch_page
);
874 return PTR_ERR(vm
->scratch_pt
);
877 vm
->scratch_pd
= alloc_pd(dev
);
878 if (IS_ERR(vm
->scratch_pd
)) {
879 free_pt(dev
, vm
->scratch_pt
);
880 free_scratch_page(dev
, vm
->scratch_page
);
881 return PTR_ERR(vm
->scratch_pd
);
884 if (USES_FULL_48BIT_PPGTT(dev
)) {
885 vm
->scratch_pdp
= alloc_pdp(dev
);
886 if (IS_ERR(vm
->scratch_pdp
)) {
887 free_pd(dev
, vm
->scratch_pd
);
888 free_pt(dev
, vm
->scratch_pt
);
889 free_scratch_page(dev
, vm
->scratch_page
);
890 return PTR_ERR(vm
->scratch_pdp
);
894 gen8_initialize_pt(vm
, vm
->scratch_pt
);
895 gen8_initialize_pd(vm
, vm
->scratch_pd
);
896 if (USES_FULL_48BIT_PPGTT(dev
))
897 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
902 static void gen8_free_scratch(struct i915_address_space
*vm
)
904 struct drm_device
*dev
= vm
->dev
;
906 if (USES_FULL_48BIT_PPGTT(dev
))
907 free_pdp(dev
, vm
->scratch_pdp
);
908 free_pd(dev
, vm
->scratch_pd
);
909 free_pt(dev
, vm
->scratch_pt
);
910 free_scratch_page(dev
, vm
->scratch_page
);
913 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
914 struct i915_page_directory_pointer
*pdp
)
918 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
919 if (WARN_ON(!pdp
->page_directory
[i
]))
922 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
923 free_pd(dev
, pdp
->page_directory
[i
]);
929 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
933 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
934 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
937 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
940 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
943 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
945 struct i915_hw_ppgtt
*ppgtt
=
946 container_of(vm
, struct i915_hw_ppgtt
, base
);
948 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
949 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
951 gen8_ppgtt_cleanup_4lvl(ppgtt
);
953 gen8_free_scratch(vm
);
957 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
958 * @vm: Master vm structure.
959 * @pd: Page directory for this address range.
960 * @start: Starting virtual address to begin allocations.
961 * @length: Size of the allocations.
962 * @new_pts: Bitmap set by function with new allocations. Likely used by the
963 * caller to free on error.
965 * Allocate the required number of page tables. Extremely similar to
966 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
967 * the page directory boundary (instead of the page directory pointer). That
968 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
969 * possible, and likely that the caller will need to use multiple calls of this
970 * function to achieve the appropriate allocation.
972 * Return: 0 if success; negative error code otherwise.
974 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
975 struct i915_page_directory
*pd
,
978 unsigned long *new_pts
)
980 struct drm_device
*dev
= vm
->dev
;
981 struct i915_page_table
*pt
;
985 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
986 /* Don't reallocate page tables */
987 if (test_bit(pde
, pd
->used_pdes
)) {
988 /* Scratch is never allocated this way */
989 WARN_ON(pt
== vm
->scratch_pt
);
997 gen8_initialize_pt(vm
, pt
);
998 pd
->page_table
[pde
] = pt
;
999 __set_bit(pde
, new_pts
);
1000 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1006 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1007 free_pt(dev
, pd
->page_table
[pde
]);
1013 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1014 * @vm: Master vm structure.
1015 * @pdp: Page directory pointer for this address range.
1016 * @start: Starting virtual address to begin allocations.
1017 * @length: Size of the allocations.
1018 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1019 * caller to free on error.
1021 * Allocate the required number of page directories starting at the pde index of
1022 * @start, and ending at the pde index @start + @length. This function will skip
1023 * over already allocated page directories within the range, and only allocate
1024 * new ones, setting the appropriate pointer within the pdp as well as the
1025 * correct position in the bitmap @new_pds.
1027 * The function will only allocate the pages within the range for a give page
1028 * directory pointer. In other words, if @start + @length straddles a virtually
1029 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1030 * required by the caller, This is not currently possible, and the BUG in the
1031 * code will prevent it.
1033 * Return: 0 if success; negative error code otherwise.
1036 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1037 struct i915_page_directory_pointer
*pdp
,
1040 unsigned long *new_pds
)
1042 struct drm_device
*dev
= vm
->dev
;
1043 struct i915_page_directory
*pd
;
1046 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1048 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1050 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1051 if (test_bit(pdpe
, pdp
->used_pdpes
))
1058 gen8_initialize_pd(vm
, pd
);
1059 pdp
->page_directory
[pdpe
] = pd
;
1060 __set_bit(pdpe
, new_pds
);
1061 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1067 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1068 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1074 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1075 * @vm: Master vm structure.
1076 * @pml4: Page map level 4 for this address range.
1077 * @start: Starting virtual address to begin allocations.
1078 * @length: Size of the allocations.
1079 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1080 * caller to free on error.
1082 * Allocate the required number of page directory pointers. Extremely similar to
1083 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1084 * The main difference is here we are limited by the pml4 boundary (instead of
1085 * the page directory pointer).
1087 * Return: 0 if success; negative error code otherwise.
1090 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1091 struct i915_pml4
*pml4
,
1094 unsigned long *new_pdps
)
1096 struct drm_device
*dev
= vm
->dev
;
1097 struct i915_page_directory_pointer
*pdp
;
1101 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1103 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1104 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1105 pdp
= alloc_pdp(dev
);
1109 gen8_initialize_pdp(vm
, pdp
);
1110 pml4
->pdps
[pml4e
] = pdp
;
1111 __set_bit(pml4e
, new_pdps
);
1112 trace_i915_page_directory_pointer_entry_alloc(vm
,
1122 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1123 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1129 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
,
1134 for (i
= 0; i
< pdpes
; i
++)
1140 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1141 * of these are based on the number of PDPEs in the system.
1144 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1145 unsigned long ***new_pts
,
1150 unsigned long **pts
;
1152 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_KERNEL
);
1156 pts
= kcalloc(pdpes
, sizeof(unsigned long *), GFP_KERNEL
);
1162 for (i
= 0; i
< pdpes
; i
++) {
1163 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
1164 sizeof(unsigned long), GFP_KERNEL
);
1175 free_gen8_temp_bitmaps(pds
, pts
, pdpes
);
1179 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1180 * the page table structures, we mark them dirty so that
1181 * context switching/execlist queuing code takes extra steps
1182 * to ensure that tlbs are flushed.
1184 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1186 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1189 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1190 struct i915_page_directory_pointer
*pdp
,
1194 struct i915_hw_ppgtt
*ppgtt
=
1195 container_of(vm
, struct i915_hw_ppgtt
, base
);
1196 unsigned long *new_page_dirs
, **new_page_tables
;
1197 struct drm_device
*dev
= vm
->dev
;
1198 struct i915_page_directory
*pd
;
1199 const uint64_t orig_start
= start
;
1200 const uint64_t orig_length
= length
;
1203 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1206 /* Wrap is never okay since we can only represent 48b, and we don't
1207 * actually use the other side of the canonical address space.
1209 if (WARN_ON(start
+ length
< start
))
1212 if (WARN_ON(start
+ length
> vm
->total
))
1215 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1219 /* Do the allocations first so we can easily bail out */
1220 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1223 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1227 /* For every page directory referenced, allocate page tables */
1228 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1229 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1230 new_page_tables
[pdpe
]);
1236 length
= orig_length
;
1238 /* Allocations have completed successfully, so set the bitmaps, and do
1240 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1241 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1242 struct i915_page_table
*pt
;
1243 uint64_t pd_len
= length
;
1244 uint64_t pd_start
= start
;
1247 /* Every pd should be allocated, we just did that above. */
1250 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1251 /* Same reasoning as pd */
1254 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1256 /* Set our used ptes within the page table */
1257 bitmap_set(pt
->used_ptes
,
1258 gen8_pte_index(pd_start
),
1259 gen8_pte_count(pd_start
, pd_len
));
1261 /* Our pde is now pointing to the pagetable, pt */
1262 __set_bit(pde
, pd
->used_pdes
);
1264 /* Map the PDE to the page table */
1265 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1267 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1268 gen8_pte_index(start
),
1269 gen8_pte_count(start
, length
),
1272 /* NB: We haven't yet mapped ptes to pages. At this
1273 * point we're still relying on insert_entries() */
1276 kunmap_px(ppgtt
, page_directory
);
1277 __set_bit(pdpe
, pdp
->used_pdpes
);
1278 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1281 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1282 mark_tlbs_dirty(ppgtt
);
1287 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
1288 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1291 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1292 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1294 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1295 mark_tlbs_dirty(ppgtt
);
1299 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1300 struct i915_pml4
*pml4
,
1304 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1305 struct i915_hw_ppgtt
*ppgtt
=
1306 container_of(vm
, struct i915_hw_ppgtt
, base
);
1307 struct i915_page_directory_pointer
*pdp
;
1308 uint64_t temp
, pml4e
;
1311 /* Do the pml4 allocations first, so we don't need to track the newly
1312 * allocated tables below the pdp */
1313 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1315 /* The pagedirectory and pagetable allocations are done in the shared 3
1316 * and 4 level code. Just allocate the pdps.
1318 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1323 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1324 "The allocation has spanned more than 512GB. "
1325 "It is highly likely this is incorrect.");
1327 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1330 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1334 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1337 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1338 GEN8_PML4ES_PER_PML4
);
1343 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1344 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1349 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1350 uint64_t start
, uint64_t length
)
1352 struct i915_hw_ppgtt
*ppgtt
=
1353 container_of(vm
, struct i915_hw_ppgtt
, base
);
1355 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1356 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1358 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1361 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1362 uint64_t start
, uint64_t length
,
1363 gen8_pte_t scratch_pte
,
1366 struct i915_page_directory
*pd
;
1370 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1371 struct i915_page_table
*pt
;
1372 uint64_t pd_len
= length
;
1373 uint64_t pd_start
= start
;
1376 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1379 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1380 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1382 gen8_pte_t
*pt_vaddr
;
1384 if (!test_bit(pde
, pd
->used_pdes
))
1387 pt_vaddr
= kmap_px(pt
);
1388 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1390 (pdpe
<< GEN8_PDPE_SHIFT
) |
1391 (pde
<< GEN8_PDE_SHIFT
) |
1392 (pte
<< GEN8_PTE_SHIFT
);
1396 for (i
= 0; i
< 4; i
++)
1397 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1402 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1403 for (i
= 0; i
< 4; i
++) {
1404 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1405 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1407 seq_puts(m
, " SCRATCH ");
1411 /* don't use kunmap_px, it could trigger
1412 * an unnecessary flush.
1414 kunmap_atomic(pt_vaddr
);
1419 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1421 struct i915_address_space
*vm
= &ppgtt
->base
;
1422 uint64_t start
= ppgtt
->base
.start
;
1423 uint64_t length
= ppgtt
->base
.total
;
1424 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1425 I915_CACHE_LLC
, true);
1427 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1428 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1430 uint64_t templ4
, pml4e
;
1431 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1432 struct i915_page_directory_pointer
*pdp
;
1434 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, templ4
, pml4e
) {
1435 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1438 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1439 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1445 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1446 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1447 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1451 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1455 ret
= gen8_init_scratch(&ppgtt
->base
);
1459 ppgtt
->base
.start
= 0;
1460 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1461 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1462 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1463 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1464 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1465 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1466 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1468 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1469 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1473 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1475 ppgtt
->base
.total
= 1ULL << 48;
1476 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1478 ret
= __pdp_init(false, &ppgtt
->pdp
);
1482 ppgtt
->base
.total
= 1ULL << 32;
1483 if (IS_ENABLED(CONFIG_X86_32
))
1484 /* While we have a proliferation of size_t variables
1485 * we cannot represent the full ppgtt size on 32bit,
1486 * so limit it to the same size as the GGTT (currently
1489 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
1491 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1492 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1500 gen8_free_scratch(&ppgtt
->base
);
1504 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1506 struct i915_address_space
*vm
= &ppgtt
->base
;
1507 struct i915_page_table
*unused
;
1508 gen6_pte_t scratch_pte
;
1510 uint32_t pte
, pde
, temp
;
1511 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1513 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1514 I915_CACHE_LLC
, true, 0);
1516 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1518 gen6_pte_t
*pt_vaddr
;
1519 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1520 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1521 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1523 if (pd_entry
!= expected
)
1524 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1528 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1530 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1532 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1534 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1538 for (i
= 0; i
< 4; i
++)
1539 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1544 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1545 for (i
= 0; i
< 4; i
++) {
1546 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1547 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1549 seq_puts(m
, " SCRATCH ");
1553 kunmap_px(ppgtt
, pt_vaddr
);
1557 /* Write pde (index) from the page directory @pd to the page table @pt */
1558 static void gen6_write_pde(struct i915_page_directory
*pd
,
1559 const int pde
, struct i915_page_table
*pt
)
1561 /* Caller needs to make sure the write completes if necessary */
1562 struct i915_hw_ppgtt
*ppgtt
=
1563 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1566 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1567 pd_entry
|= GEN6_PDE_VALID
;
1569 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1572 /* Write all the page tables found in the ppgtt structure to incrementing page
1574 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1575 struct i915_page_directory
*pd
,
1576 uint32_t start
, uint32_t length
)
1578 struct i915_page_table
*pt
;
1581 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1582 gen6_write_pde(pd
, pde
, pt
);
1584 /* Make sure write is complete before other code can use this page
1585 * table. Also require for WC mapped PTEs */
1586 readl(dev_priv
->gtt
.gsm
);
1589 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1591 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1593 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1596 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1597 struct drm_i915_gem_request
*req
)
1599 struct intel_engine_cs
*ring
= req
->ring
;
1602 /* NB: TLBs must be flushed and invalidated before a switch */
1603 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1607 ret
= intel_ring_begin(req
, 6);
1611 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1612 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1613 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1614 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1615 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1616 intel_ring_emit(ring
, MI_NOOP
);
1617 intel_ring_advance(ring
);
1622 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1623 struct drm_i915_gem_request
*req
)
1625 struct intel_engine_cs
*ring
= req
->ring
;
1626 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1628 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1629 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1633 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1634 struct drm_i915_gem_request
*req
)
1636 struct intel_engine_cs
*ring
= req
->ring
;
1639 /* NB: TLBs must be flushed and invalidated before a switch */
1640 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1644 ret
= intel_ring_begin(req
, 6);
1648 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1649 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1650 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1651 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1652 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1653 intel_ring_emit(ring
, MI_NOOP
);
1654 intel_ring_advance(ring
);
1656 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1657 if (ring
->id
!= RCS
) {
1658 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1666 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1667 struct drm_i915_gem_request
*req
)
1669 struct intel_engine_cs
*ring
= req
->ring
;
1670 struct drm_device
*dev
= ppgtt
->base
.dev
;
1671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1675 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1677 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1682 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1685 struct intel_engine_cs
*ring
;
1688 for_each_ring(ring
, dev_priv
, j
) {
1689 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1690 I915_WRITE(RING_MODE_GEN7(ring
),
1691 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1695 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1698 struct intel_engine_cs
*ring
;
1699 uint32_t ecochk
, ecobits
;
1702 ecobits
= I915_READ(GAC_ECO_BITS
);
1703 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1705 ecochk
= I915_READ(GAM_ECOCHK
);
1706 if (IS_HASWELL(dev
)) {
1707 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1709 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1710 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1712 I915_WRITE(GAM_ECOCHK
, ecochk
);
1714 for_each_ring(ring
, dev_priv
, i
) {
1715 /* GFX_MODE is per-ring on gen7+ */
1716 I915_WRITE(RING_MODE_GEN7(ring
),
1717 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1721 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1724 uint32_t ecochk
, gab_ctl
, ecobits
;
1726 ecobits
= I915_READ(GAC_ECO_BITS
);
1727 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1728 ECOBITS_PPGTT_CACHE64B
);
1730 gab_ctl
= I915_READ(GAB_CTL
);
1731 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1733 ecochk
= I915_READ(GAM_ECOCHK
);
1734 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1736 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1739 /* PPGTT support for Sandybdrige/Gen6 and later */
1740 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1745 struct i915_hw_ppgtt
*ppgtt
=
1746 container_of(vm
, struct i915_hw_ppgtt
, base
);
1747 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1748 unsigned first_entry
= start
>> PAGE_SHIFT
;
1749 unsigned num_entries
= length
>> PAGE_SHIFT
;
1750 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1751 unsigned first_pte
= first_entry
% GEN6_PTES
;
1752 unsigned last_pte
, i
;
1754 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1755 I915_CACHE_LLC
, true, 0);
1757 while (num_entries
) {
1758 last_pte
= first_pte
+ num_entries
;
1759 if (last_pte
> GEN6_PTES
)
1760 last_pte
= GEN6_PTES
;
1762 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1764 for (i
= first_pte
; i
< last_pte
; i
++)
1765 pt_vaddr
[i
] = scratch_pte
;
1767 kunmap_px(ppgtt
, pt_vaddr
);
1769 num_entries
-= last_pte
- first_pte
;
1775 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1776 struct sg_table
*pages
,
1778 enum i915_cache_level cache_level
, u32 flags
)
1780 struct i915_hw_ppgtt
*ppgtt
=
1781 container_of(vm
, struct i915_hw_ppgtt
, base
);
1782 gen6_pte_t
*pt_vaddr
;
1783 unsigned first_entry
= start
>> PAGE_SHIFT
;
1784 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1785 unsigned act_pte
= first_entry
% GEN6_PTES
;
1786 struct sg_page_iter sg_iter
;
1789 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1790 if (pt_vaddr
== NULL
)
1791 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1794 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1795 cache_level
, true, flags
);
1797 if (++act_pte
== GEN6_PTES
) {
1798 kunmap_px(ppgtt
, pt_vaddr
);
1805 kunmap_px(ppgtt
, pt_vaddr
);
1808 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1809 uint64_t start_in
, uint64_t length_in
)
1811 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1812 struct drm_device
*dev
= vm
->dev
;
1813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1814 struct i915_hw_ppgtt
*ppgtt
=
1815 container_of(vm
, struct i915_hw_ppgtt
, base
);
1816 struct i915_page_table
*pt
;
1817 uint32_t start
, length
, start_save
, length_save
;
1821 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1824 start
= start_save
= start_in
;
1825 length
= length_save
= length_in
;
1827 bitmap_zero(new_page_tables
, I915_PDES
);
1829 /* The allocation is done in two stages so that we can bail out with
1830 * minimal amount of pain. The first stage finds new page tables that
1831 * need allocation. The second stage marks use ptes within the page
1834 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1835 if (pt
!= vm
->scratch_pt
) {
1836 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1840 /* We've already allocated a page table */
1841 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1849 gen6_initialize_pt(vm
, pt
);
1851 ppgtt
->pd
.page_table
[pde
] = pt
;
1852 __set_bit(pde
, new_page_tables
);
1853 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1857 length
= length_save
;
1859 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1860 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1862 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1863 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1864 gen6_pte_count(start
, length
));
1866 if (__test_and_clear_bit(pde
, new_page_tables
))
1867 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1869 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1870 gen6_pte_index(start
),
1871 gen6_pte_count(start
, length
),
1873 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1877 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1879 /* Make sure write is complete before other code can use this page
1880 * table. Also require for WC mapped PTEs */
1881 readl(dev_priv
->gtt
.gsm
);
1883 mark_tlbs_dirty(ppgtt
);
1887 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1888 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1890 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1891 free_pt(vm
->dev
, pt
);
1894 mark_tlbs_dirty(ppgtt
);
1898 static int gen6_init_scratch(struct i915_address_space
*vm
)
1900 struct drm_device
*dev
= vm
->dev
;
1902 vm
->scratch_page
= alloc_scratch_page(dev
);
1903 if (IS_ERR(vm
->scratch_page
))
1904 return PTR_ERR(vm
->scratch_page
);
1906 vm
->scratch_pt
= alloc_pt(dev
);
1907 if (IS_ERR(vm
->scratch_pt
)) {
1908 free_scratch_page(dev
, vm
->scratch_page
);
1909 return PTR_ERR(vm
->scratch_pt
);
1912 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1917 static void gen6_free_scratch(struct i915_address_space
*vm
)
1919 struct drm_device
*dev
= vm
->dev
;
1921 free_pt(dev
, vm
->scratch_pt
);
1922 free_scratch_page(dev
, vm
->scratch_page
);
1925 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1927 struct i915_hw_ppgtt
*ppgtt
=
1928 container_of(vm
, struct i915_hw_ppgtt
, base
);
1929 struct i915_page_table
*pt
;
1932 drm_mm_remove_node(&ppgtt
->node
);
1934 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1935 if (pt
!= vm
->scratch_pt
)
1936 free_pt(ppgtt
->base
.dev
, pt
);
1939 gen6_free_scratch(vm
);
1942 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1944 struct i915_address_space
*vm
= &ppgtt
->base
;
1945 struct drm_device
*dev
= ppgtt
->base
.dev
;
1946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 bool retried
= false;
1950 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1951 * allocator works in address space sizes, so it's multiplied by page
1952 * size. We allocate at the top of the GTT to avoid fragmentation.
1954 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1956 ret
= gen6_init_scratch(vm
);
1961 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1962 &ppgtt
->node
, GEN6_PD_SIZE
,
1964 0, dev_priv
->gtt
.base
.total
,
1966 if (ret
== -ENOSPC
&& !retried
) {
1967 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1968 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1970 0, dev_priv
->gtt
.base
.total
,
1983 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1984 DRM_DEBUG("Forced to use aperture for PDEs\n");
1989 gen6_free_scratch(vm
);
1993 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1995 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1998 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1999 uint64_t start
, uint64_t length
)
2001 struct i915_page_table
*unused
;
2004 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
2005 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2008 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2010 struct drm_device
*dev
= ppgtt
->base
.dev
;
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2014 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
2016 ppgtt
->switch_mm
= gen6_mm_switch
;
2017 } else if (IS_HASWELL(dev
)) {
2018 ppgtt
->switch_mm
= hsw_mm_switch
;
2019 } else if (IS_GEN7(dev
)) {
2020 ppgtt
->switch_mm
= gen7_mm_switch
;
2024 if (intel_vgpu_active(dev
))
2025 ppgtt
->switch_mm
= vgpu_mm_switch
;
2027 ret
= gen6_ppgtt_alloc(ppgtt
);
2031 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2032 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2033 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2034 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2035 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2036 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2037 ppgtt
->base
.start
= 0;
2038 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2039 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2041 ppgtt
->pd
.base
.ggtt_offset
=
2042 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2044 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
2045 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2047 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2049 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2051 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2052 ppgtt
->node
.size
>> 20,
2053 ppgtt
->node
.start
/ PAGE_SIZE
);
2055 DRM_DEBUG("Adding PPGTT at offset %x\n",
2056 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2061 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2063 ppgtt
->base
.dev
= dev
;
2065 if (INTEL_INFO(dev
)->gen
< 8)
2066 return gen6_ppgtt_init(ppgtt
);
2068 return gen8_ppgtt_init(ppgtt
);
2071 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2076 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2078 kref_init(&ppgtt
->ref
);
2079 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
2081 i915_init_vm(dev_priv
, &ppgtt
->base
);
2087 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2089 /* In the case of execlists, PPGTT is enabled by the context descriptor
2090 * and the PDPs are contained within the context itself. We don't
2091 * need to do anything here. */
2092 if (i915
.enable_execlists
)
2095 if (!USES_PPGTT(dev
))
2099 gen6_ppgtt_enable(dev
);
2100 else if (IS_GEN7(dev
))
2101 gen7_ppgtt_enable(dev
);
2102 else if (INTEL_INFO(dev
)->gen
>= 8)
2103 gen8_ppgtt_enable(dev
);
2105 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2110 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
2112 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
2113 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2115 if (i915
.enable_execlists
)
2121 return ppgtt
->switch_mm(ppgtt
, req
);
2124 struct i915_hw_ppgtt
*
2125 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
2127 struct i915_hw_ppgtt
*ppgtt
;
2130 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2132 return ERR_PTR(-ENOMEM
);
2134 ret
= i915_ppgtt_init(dev
, ppgtt
);
2137 return ERR_PTR(ret
);
2140 ppgtt
->file_priv
= fpriv
;
2142 trace_i915_ppgtt_create(&ppgtt
->base
);
2147 void i915_ppgtt_release(struct kref
*kref
)
2149 struct i915_hw_ppgtt
*ppgtt
=
2150 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2152 trace_i915_ppgtt_release(&ppgtt
->base
);
2154 /* vmas should already be unbound */
2155 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2156 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2158 list_del(&ppgtt
->base
.global_link
);
2159 drm_mm_takedown(&ppgtt
->base
.mm
);
2161 ppgtt
->base
.cleanup(&ppgtt
->base
);
2165 extern int intel_iommu_gfx_mapped
;
2166 /* Certain Gen5 chipsets require require idling the GPU before
2167 * unmapping anything from the GTT when VT-d is enabled.
2169 static bool needs_idle_maps(struct drm_device
*dev
)
2171 #ifdef CONFIG_INTEL_IOMMU
2172 /* Query intel_iommu to see if we need the workaround. Presumably that
2175 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
2181 static bool do_idling(struct drm_i915_private
*dev_priv
)
2183 bool ret
= dev_priv
->mm
.interruptible
;
2185 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
2186 dev_priv
->mm
.interruptible
= false;
2187 if (i915_gpu_idle(dev_priv
->dev
)) {
2188 DRM_ERROR("Couldn't idle GPU\n");
2189 /* Wait a bit, in hopes it avoids the hang */
2197 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
2199 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2200 dev_priv
->mm
.interruptible
= interruptible
;
2203 void i915_check_and_clear_faults(struct drm_device
*dev
)
2205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 struct intel_engine_cs
*ring
;
2209 if (INTEL_INFO(dev
)->gen
< 6)
2212 for_each_ring(ring
, dev_priv
, i
) {
2214 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
2215 if (fault_reg
& RING_FAULT_VALID
) {
2216 DRM_DEBUG_DRIVER("Unexpected fault\n"
2218 "\tAddress space: %s\n"
2221 fault_reg
& PAGE_MASK
,
2222 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2223 RING_FAULT_SRCID(fault_reg
),
2224 RING_FAULT_FAULT_TYPE(fault_reg
));
2225 I915_WRITE(RING_FAULT_REG(ring
),
2226 fault_reg
& ~RING_FAULT_VALID
);
2229 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
2232 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2234 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
2235 intel_gtt_chipset_flush();
2237 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2238 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2242 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2246 /* Don't bother messing with faults pre GEN6 as we have little
2247 * documentation supporting that it's a good idea.
2249 if (INTEL_INFO(dev
)->gen
< 6)
2252 i915_check_and_clear_faults(dev
);
2254 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2255 dev_priv
->gtt
.base
.start
,
2256 dev_priv
->gtt
.base
.total
,
2259 i915_ggtt_flush(dev_priv
);
2262 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2264 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2265 obj
->pages
->sgl
, obj
->pages
->nents
,
2266 PCI_DMA_BIDIRECTIONAL
))
2272 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2277 iowrite32((u32
)pte
, addr
);
2278 iowrite32(pte
>> 32, addr
+ 4);
2282 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2283 struct sg_table
*st
,
2285 enum i915_cache_level level
, u32 unused
)
2287 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2288 unsigned first_entry
= start
>> PAGE_SHIFT
;
2289 gen8_pte_t __iomem
*gtt_entries
=
2290 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2292 struct sg_page_iter sg_iter
;
2293 dma_addr_t addr
= 0; /* shut up gcc */
2295 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2296 addr
= sg_dma_address(sg_iter
.sg
) +
2297 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
2298 gen8_set_pte(>t_entries
[i
],
2299 gen8_pte_encode(addr
, level
, true));
2304 * XXX: This serves as a posting read to make sure that the PTE has
2305 * actually been updated. There is some concern that even though
2306 * registers and PTEs are within the same BAR that they are potentially
2307 * of NUMA access patterns. Therefore, even with the way we assume
2308 * hardware should work, we must keep this posting read for paranoia.
2311 WARN_ON(readq(>t_entries
[i
-1])
2312 != gen8_pte_encode(addr
, level
, true));
2314 /* This next bit makes the above posting read even more important. We
2315 * want to flush the TLBs only after we're certain all the PTE updates
2318 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2319 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2323 * Binds an object into the global gtt with the specified cache level. The object
2324 * will be accessible to the GPU via commands whose operands reference offsets
2325 * within the global GTT as well as accessible by the GPU through the GMADR
2326 * mapped BAR (dev_priv->mm.gtt->gtt).
2328 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2329 struct sg_table
*st
,
2331 enum i915_cache_level level
, u32 flags
)
2333 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2334 unsigned first_entry
= start
>> PAGE_SHIFT
;
2335 gen6_pte_t __iomem
*gtt_entries
=
2336 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2338 struct sg_page_iter sg_iter
;
2339 dma_addr_t addr
= 0;
2341 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2342 addr
= sg_page_iter_dma_address(&sg_iter
);
2343 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
2347 /* XXX: This serves as a posting read to make sure that the PTE has
2348 * actually been updated. There is some concern that even though
2349 * registers and PTEs are within the same BAR that they are potentially
2350 * of NUMA access patterns. Therefore, even with the way we assume
2351 * hardware should work, we must keep this posting read for paranoia.
2354 unsigned long gtt
= readl(>t_entries
[i
-1]);
2355 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
2358 /* This next bit makes the above posting read even more important. We
2359 * want to flush the TLBs only after we're certain all the PTE updates
2362 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2363 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2366 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2371 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2372 unsigned first_entry
= start
>> PAGE_SHIFT
;
2373 unsigned num_entries
= length
>> PAGE_SHIFT
;
2374 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2375 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2376 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2379 if (WARN(num_entries
> max_entries
,
2380 "First entry = %d; Num entries = %d (max=%d)\n",
2381 first_entry
, num_entries
, max_entries
))
2382 num_entries
= max_entries
;
2384 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2387 for (i
= 0; i
< num_entries
; i
++)
2388 gen8_set_pte(>t_base
[i
], scratch_pte
);
2392 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2397 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2398 unsigned first_entry
= start
>> PAGE_SHIFT
;
2399 unsigned num_entries
= length
>> PAGE_SHIFT
;
2400 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2401 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2402 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2405 if (WARN(num_entries
> max_entries
,
2406 "First entry = %d; Num entries = %d (max=%d)\n",
2407 first_entry
, num_entries
, max_entries
))
2408 num_entries
= max_entries
;
2410 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2411 I915_CACHE_LLC
, use_scratch
, 0);
2413 for (i
= 0; i
< num_entries
; i
++)
2414 iowrite32(scratch_pte
, >t_base
[i
]);
2418 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2419 struct sg_table
*pages
,
2421 enum i915_cache_level cache_level
, u32 unused
)
2423 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2424 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2426 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2430 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2435 unsigned first_entry
= start
>> PAGE_SHIFT
;
2436 unsigned num_entries
= length
>> PAGE_SHIFT
;
2437 intel_gtt_clear_range(first_entry
, num_entries
);
2440 static int ggtt_bind_vma(struct i915_vma
*vma
,
2441 enum i915_cache_level cache_level
,
2444 struct drm_device
*dev
= vma
->vm
->dev
;
2445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2446 struct drm_i915_gem_object
*obj
= vma
->obj
;
2447 struct sg_table
*pages
= obj
->pages
;
2451 ret
= i915_get_ggtt_vma_pages(vma
);
2454 pages
= vma
->ggtt_view
.pages
;
2456 /* Currently applicable only to VLV */
2458 pte_flags
|= PTE_READ_ONLY
;
2461 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
2462 vma
->vm
->insert_entries(vma
->vm
, pages
,
2464 cache_level
, pte_flags
);
2466 /* Note the inconsistency here is due to absence of the
2467 * aliasing ppgtt on gen4 and earlier. Though we always
2468 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2469 * without the appgtt, we cannot honour that request and so
2470 * must substitute it with a global binding. Since we do this
2471 * behind the upper layers back, we need to explicitly set
2472 * the bound flag ourselves.
2474 vma
->bound
|= GLOBAL_BIND
;
2478 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
2479 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2480 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2482 cache_level
, pte_flags
);
2488 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2490 struct drm_device
*dev
= vma
->vm
->dev
;
2491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2492 struct drm_i915_gem_object
*obj
= vma
->obj
;
2493 const uint64_t size
= min_t(uint64_t,
2497 if (vma
->bound
& GLOBAL_BIND
) {
2498 vma
->vm
->clear_range(vma
->vm
,
2504 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2505 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2507 appgtt
->base
.clear_range(&appgtt
->base
,
2514 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2516 struct drm_device
*dev
= obj
->base
.dev
;
2517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2520 interruptible
= do_idling(dev_priv
);
2522 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2523 PCI_DMA_BIDIRECTIONAL
);
2525 undo_idling(dev_priv
, interruptible
);
2528 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2529 unsigned long color
,
2533 if (node
->color
!= color
)
2536 if (!list_empty(&node
->node_list
)) {
2537 node
= list_entry(node
->node_list
.next
,
2540 if (node
->allocated
&& node
->color
!= color
)
2545 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2550 /* Let GEM Manage all of the aperture.
2552 * However, leave one page at the end still bound to the scratch page.
2553 * There are a number of places where the hardware apparently prefetches
2554 * past the end of the object, and we've seen multiple hangs with the
2555 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2556 * aperture. One page should be enough to keep any prefetching inside
2559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2560 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2561 struct drm_mm_node
*entry
;
2562 struct drm_i915_gem_object
*obj
;
2563 unsigned long hole_start
, hole_end
;
2566 BUG_ON(mappable_end
> end
);
2568 /* Subtract the guard page ... */
2569 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2571 dev_priv
->gtt
.base
.start
= start
;
2572 dev_priv
->gtt
.base
.total
= end
- start
;
2574 if (intel_vgpu_active(dev
)) {
2575 ret
= intel_vgt_balloon(dev
);
2581 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2583 /* Mark any preallocated objects as occupied */
2584 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2585 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2587 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2588 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2590 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2591 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2593 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2596 vma
->bound
|= GLOBAL_BIND
;
2599 /* Clear any non-preallocated blocks */
2600 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2601 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2602 hole_start
, hole_end
);
2603 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2604 hole_end
- hole_start
, true);
2607 /* And finally clear the reserved guard page */
2608 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2610 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2611 struct i915_hw_ppgtt
*ppgtt
;
2613 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2617 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2619 ppgtt
->base
.cleanup(&ppgtt
->base
);
2624 if (ppgtt
->base
.allocate_va_range
)
2625 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2628 ppgtt
->base
.cleanup(&ppgtt
->base
);
2633 ppgtt
->base
.clear_range(&ppgtt
->base
,
2638 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2644 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2647 u64 gtt_size
, mappable_size
;
2649 gtt_size
= dev_priv
->gtt
.base
.total
;
2650 mappable_size
= dev_priv
->gtt
.mappable_end
;
2652 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2655 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2658 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2660 if (dev_priv
->mm
.aliasing_ppgtt
) {
2661 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2663 ppgtt
->base
.cleanup(&ppgtt
->base
);
2666 if (drm_mm_initialized(&vm
->mm
)) {
2667 if (intel_vgpu_active(dev
))
2668 intel_vgt_deballoon();
2670 drm_mm_takedown(&vm
->mm
);
2671 list_del(&vm
->global_link
);
2677 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2679 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2680 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2681 return snb_gmch_ctl
<< 20;
2684 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2686 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2687 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2689 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2691 #ifdef CONFIG_X86_32
2692 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2693 if (bdw_gmch_ctl
> 4)
2697 return bdw_gmch_ctl
<< 20;
2700 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2702 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2703 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2706 return 1 << (20 + gmch_ctrl
);
2711 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2713 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2714 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2715 return snb_gmch_ctl
<< 25; /* 32 MB units */
2718 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2720 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2721 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2722 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2725 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2727 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2728 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2731 * 0x0 to 0x10: 32MB increments starting at 0MB
2732 * 0x11 to 0x16: 4MB increments starting at 8MB
2733 * 0x17 to 0x1d: 4MB increments start at 36MB
2735 if (gmch_ctrl
< 0x11)
2736 return gmch_ctrl
<< 25;
2737 else if (gmch_ctrl
< 0x17)
2738 return (gmch_ctrl
- 0x11 + 2) << 22;
2740 return (gmch_ctrl
- 0x17 + 9) << 22;
2743 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2745 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2746 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2748 if (gen9_gmch_ctl
< 0xf0)
2749 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2751 /* 4MB increments starting at 0xf0 for 4MB */
2752 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2755 static int ggtt_probe_common(struct drm_device
*dev
,
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2759 struct i915_page_scratch
*scratch_page
;
2760 phys_addr_t gtt_phys_addr
;
2762 /* For Modern GENs the PTEs and register space are split in the BAR */
2763 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2764 (pci_resource_len(dev
->pdev
, 0) / 2);
2767 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2768 * dropped. For WC mappings in general we have 64 byte burst writes
2769 * when the WC buffer is flushed, so we can't use it, but have to
2770 * resort to an uncached mapping. The WC issue is easily caught by the
2771 * readback check when writing GTT PTE entries.
2773 if (IS_BROXTON(dev
))
2774 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2776 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2777 if (!dev_priv
->gtt
.gsm
) {
2778 DRM_ERROR("Failed to map the gtt page table\n");
2782 scratch_page
= alloc_scratch_page(dev
);
2783 if (IS_ERR(scratch_page
)) {
2784 DRM_ERROR("Scratch setup failed\n");
2785 /* iounmap will also get called at remove, but meh */
2786 iounmap(dev_priv
->gtt
.gsm
);
2787 return PTR_ERR(scratch_page
);
2790 dev_priv
->gtt
.base
.scratch_page
= scratch_page
;
2795 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2796 * bits. When using advanced contexts each context stores its own PAT, but
2797 * writing this data shouldn't be harmful even in those cases. */
2798 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2802 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2803 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2804 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2805 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2806 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2807 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2808 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2809 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2811 if (!USES_PPGTT(dev_priv
->dev
))
2812 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2813 * so RTL will always use the value corresponding to
2815 * So let's disable cache for GGTT to avoid screen corruptions.
2816 * MOCS still can be used though.
2817 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2818 * before this patch, i.e. the same uncached + snooping access
2819 * like on gen6/7 seems to be in effect.
2820 * - So this just fixes blitter/render access. Again it looks
2821 * like it's not just uncached access, but uncached + snooping.
2822 * So we can still hold onto all our assumptions wrt cpu
2823 * clflushing on LLC machines.
2825 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2827 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2828 * write would work. */
2829 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2830 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2833 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2838 * Map WB on BDW to snooped on CHV.
2840 * Only the snoop bit has meaning for CHV, the rest is
2843 * The hardware will never snoop for certain types of accesses:
2844 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2845 * - PPGTT page tables
2846 * - some other special cycles
2848 * As with BDW, we also need to consider the following for GT accesses:
2849 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2850 * so RTL will always use the value corresponding to
2852 * Which means we must set the snoop bit in PAT entry 0
2853 * in order to keep the global status page working.
2855 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2859 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2860 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2861 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2862 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2864 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2865 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2868 static int gen8_gmch_probe(struct drm_device
*dev
,
2871 phys_addr_t
*mappable_base
,
2874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2879 /* TODO: We're not aware of mappable constraints on gen8 yet */
2880 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2881 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2883 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2884 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2886 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2888 if (INTEL_INFO(dev
)->gen
>= 9) {
2889 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2890 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2891 } else if (IS_CHERRYVIEW(dev
)) {
2892 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2893 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2895 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2896 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2899 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2901 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2902 chv_setup_private_ppat(dev_priv
);
2904 bdw_setup_private_ppat(dev_priv
);
2906 ret
= ggtt_probe_common(dev
, gtt_size
);
2908 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2909 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2910 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2911 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2916 static int gen6_gmch_probe(struct drm_device
*dev
,
2919 phys_addr_t
*mappable_base
,
2922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2923 unsigned int gtt_size
;
2927 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2928 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2930 /* 64/512MB is the current min/max we actually know of, but this is just
2931 * a coarse sanity check.
2933 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2934 DRM_ERROR("Unknown GMADR size (%llx)\n",
2935 dev_priv
->gtt
.mappable_end
);
2939 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2940 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2941 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2943 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2945 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2946 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2948 ret
= ggtt_probe_common(dev
, gtt_size
);
2950 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2951 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2952 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2953 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2958 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2961 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2964 free_scratch_page(vm
->dev
, vm
->scratch_page
);
2967 static int i915_gmch_probe(struct drm_device
*dev
,
2970 phys_addr_t
*mappable_base
,
2973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2976 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2978 DRM_ERROR("failed to set up gmch\n");
2982 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2984 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2985 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2986 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2987 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2988 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2990 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2991 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2996 static void i915_gmch_remove(struct i915_address_space
*vm
)
2998 intel_gmch_remove();
3001 int i915_gem_gtt_init(struct drm_device
*dev
)
3003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3004 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3007 if (INTEL_INFO(dev
)->gen
<= 5) {
3008 gtt
->gtt_probe
= i915_gmch_probe
;
3009 gtt
->base
.cleanup
= i915_gmch_remove
;
3010 } else if (INTEL_INFO(dev
)->gen
< 8) {
3011 gtt
->gtt_probe
= gen6_gmch_probe
;
3012 gtt
->base
.cleanup
= gen6_gmch_remove
;
3013 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
3014 gtt
->base
.pte_encode
= iris_pte_encode
;
3015 else if (IS_HASWELL(dev
))
3016 gtt
->base
.pte_encode
= hsw_pte_encode
;
3017 else if (IS_VALLEYVIEW(dev
))
3018 gtt
->base
.pte_encode
= byt_pte_encode
;
3019 else if (INTEL_INFO(dev
)->gen
>= 7)
3020 gtt
->base
.pte_encode
= ivb_pte_encode
;
3022 gtt
->base
.pte_encode
= snb_pte_encode
;
3024 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
3025 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
3028 gtt
->base
.dev
= dev
;
3030 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
3031 >t
->mappable_base
, >t
->mappable_end
);
3035 /* GMADR is the PCI mmio aperture into the global GTT. */
3036 DRM_INFO("Memory usable by graphics device = %lluM\n",
3037 gtt
->base
.total
>> 20);
3038 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
3039 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
3040 #ifdef CONFIG_INTEL_IOMMU
3041 if (intel_iommu_gfx_mapped
)
3042 DRM_INFO("VT-d active for gfx access\n");
3045 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3046 * user's requested state against the hardware/driver capabilities. We
3047 * do this now so that we can print out any log messages once rather
3048 * than every time we check intel_enable_ppgtt().
3050 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
3051 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
3056 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3059 struct drm_i915_gem_object
*obj
;
3060 struct i915_address_space
*vm
;
3061 struct i915_vma
*vma
;
3064 i915_check_and_clear_faults(dev
);
3066 /* First fill our portion of the GTT with scratch pages */
3067 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
3068 dev_priv
->gtt
.base
.start
,
3069 dev_priv
->gtt
.base
.total
,
3072 /* Cache flush objects bound into GGTT and rebind them. */
3073 vm
= &dev_priv
->gtt
.base
;
3074 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3076 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3080 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3087 i915_gem_clflush_object(obj
, obj
->pin_display
);
3090 if (INTEL_INFO(dev
)->gen
>= 8) {
3091 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3092 chv_setup_private_ppat(dev_priv
);
3094 bdw_setup_private_ppat(dev_priv
);
3099 if (USES_PPGTT(dev
)) {
3100 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3101 /* TODO: Perhaps it shouldn't be gen6 specific */
3103 struct i915_hw_ppgtt
*ppgtt
=
3104 container_of(vm
, struct i915_hw_ppgtt
,
3107 if (i915_is_ggtt(vm
))
3108 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3110 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3111 0, ppgtt
->base
.total
);
3115 i915_ggtt_flush(dev_priv
);
3118 static struct i915_vma
*
3119 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
3120 struct i915_address_space
*vm
,
3121 const struct i915_ggtt_view
*ggtt_view
)
3123 struct i915_vma
*vma
;
3125 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3126 return ERR_PTR(-EINVAL
);
3128 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3130 return ERR_PTR(-ENOMEM
);
3132 INIT_LIST_HEAD(&vma
->vma_link
);
3133 INIT_LIST_HEAD(&vma
->mm_list
);
3134 INIT_LIST_HEAD(&vma
->exec_list
);
3138 if (i915_is_ggtt(vm
))
3139 vma
->ggtt_view
= *ggtt_view
;
3141 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
3142 if (!i915_is_ggtt(vm
))
3143 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3149 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3150 struct i915_address_space
*vm
)
3152 struct i915_vma
*vma
;
3154 vma
= i915_gem_obj_to_vma(obj
, vm
);
3156 vma
= __i915_gem_vma_create(obj
, vm
,
3157 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3163 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3164 const struct i915_ggtt_view
*view
)
3166 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
3167 struct i915_vma
*vma
;
3170 return ERR_PTR(-EINVAL
);
3172 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3178 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
3185 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
3186 struct sg_table
*st
)
3188 unsigned int column
, row
;
3189 unsigned int src_idx
;
3190 struct scatterlist
*sg
= st
->sgl
;
3194 for (column
= 0; column
< width
; column
++) {
3195 src_idx
= width
* (height
- 1) + column
;
3196 for (row
= 0; row
< height
; row
++) {
3198 /* We don't need the pages, but need to initialize
3199 * the entries so the sg list can be happily traversed.
3200 * The only thing we need are DMA addresses.
3202 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3203 sg_dma_address(sg
) = in
[src_idx
];
3204 sg_dma_len(sg
) = PAGE_SIZE
;
3211 static struct sg_table
*
3212 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
3213 struct drm_i915_gem_object
*obj
)
3215 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
3216 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
3217 struct sg_page_iter sg_iter
;
3219 dma_addr_t
*page_addr_list
;
3220 struct sg_table
*st
;
3223 /* Allocate a temporary list of source pages for random access. */
3224 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
3225 sizeof(dma_addr_t
));
3226 if (!page_addr_list
)
3227 return ERR_PTR(ret
);
3229 /* Allocate target SG list. */
3230 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3234 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
3238 /* Populate source page list from the object. */
3240 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
3241 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
3245 /* Rotate the pages. */
3246 rotate_pages(page_addr_list
,
3247 rot_info
->width_pages
, rot_info
->height_pages
,
3251 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
3252 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
3253 rot_info
->pixel_format
, rot_info
->width_pages
,
3254 rot_info
->height_pages
, size_pages
);
3256 drm_free_large(page_addr_list
);
3263 drm_free_large(page_addr_list
);
3266 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
3267 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
3268 rot_info
->pixel_format
, rot_info
->width_pages
,
3269 rot_info
->height_pages
, size_pages
);
3270 return ERR_PTR(ret
);
3273 static struct sg_table
*
3274 intel_partial_pages(const struct i915_ggtt_view
*view
,
3275 struct drm_i915_gem_object
*obj
)
3277 struct sg_table
*st
;
3278 struct scatterlist
*sg
;
3279 struct sg_page_iter obj_sg_iter
;
3282 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3286 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3292 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3293 view
->params
.partial
.offset
)
3295 if (st
->nents
>= view
->params
.partial
.size
)
3298 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3299 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3300 sg_dma_len(sg
) = PAGE_SIZE
;
3311 return ERR_PTR(ret
);
3315 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3319 if (vma
->ggtt_view
.pages
)
3322 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3323 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3324 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3325 vma
->ggtt_view
.pages
=
3326 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
3327 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3328 vma
->ggtt_view
.pages
=
3329 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3331 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3332 vma
->ggtt_view
.type
);
3334 if (!vma
->ggtt_view
.pages
) {
3335 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3336 vma
->ggtt_view
.type
);
3338 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3339 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3340 vma
->ggtt_view
.pages
= NULL
;
3341 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3342 vma
->ggtt_view
.type
, ret
);
3349 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3351 * @cache_level: mapping cache level
3352 * @flags: flags like global or local mapping
3354 * DMA addresses are taken from the scatter-gather table of this object (or of
3355 * this VMA in case of non-default GGTT views) and PTE entries set up.
3356 * Note that DMA addresses are also the only part of the SG table we care about.
3358 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3364 if (WARN_ON(flags
== 0))
3368 if (flags
& PIN_GLOBAL
)
3369 bind_flags
|= GLOBAL_BIND
;
3370 if (flags
& PIN_USER
)
3371 bind_flags
|= LOCAL_BIND
;
3373 if (flags
& PIN_UPDATE
)
3374 bind_flags
|= vma
->bound
;
3376 bind_flags
&= ~vma
->bound
;
3378 if (bind_flags
== 0)
3381 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3382 trace_i915_va_alloc(vma
->vm
,
3385 VM_TO_TRACE_NAME(vma
->vm
));
3387 /* XXX: i915_vma_pin() will fix this +- hack */
3389 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3397 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3401 vma
->bound
|= bind_flags
;
3407 * i915_ggtt_view_size - Get the size of a GGTT view.
3408 * @obj: Object the view is of.
3409 * @view: The view in question.
3411 * @return The size of the GGTT view in bytes.
3414 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3415 const struct i915_ggtt_view
*view
)
3417 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3418 return obj
->base
.size
;
3419 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3420 return view
->rotation_info
.size
;
3421 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3422 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3424 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3425 return obj
->base
.size
;