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drm/i915: Inline feature detection into sanitize_enable_ppgtt
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
35
36 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
37 {
38 bool has_aliasing_ppgtt;
39 bool has_full_ppgtt;
40
41 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
42 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
43 if (IS_GEN8(dev))
44 has_full_ppgtt = false; /* XXX why? */
45
46 if (enable_ppgtt == 0 || !has_aliasing_ppgtt)
47 return 0;
48
49 if (enable_ppgtt == 1)
50 return 1;
51
52 if (enable_ppgtt == 2 && has_full_ppgtt)
53 return 2;
54
55 #ifdef CONFIG_INTEL_IOMMU
56 /* Disable ppgtt on SNB if VT-d is on. */
57 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
58 DRM_INFO("Disabling PPGTT because VT-d is on\n");
59 return 0;
60 }
61 #endif
62
63 /* Early VLV doesn't have this */
64 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
65 dev->pdev->revision < 0xb) {
66 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
67 return 0;
68 }
69
70 return has_full_ppgtt ? 2 : has_aliasing_ppgtt ? 1 : 0;
71 }
72
73
74 static void ppgtt_bind_vma(struct i915_vma *vma,
75 enum i915_cache_level cache_level,
76 u32 flags);
77 static void ppgtt_unbind_vma(struct i915_vma *vma);
78
79 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
80 enum i915_cache_level level,
81 bool valid)
82 {
83 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
84 pte |= addr;
85
86 switch (level) {
87 case I915_CACHE_NONE:
88 pte |= PPAT_UNCACHED_INDEX;
89 break;
90 case I915_CACHE_WT:
91 pte |= PPAT_DISPLAY_ELLC_INDEX;
92 break;
93 default:
94 pte |= PPAT_CACHED_INDEX;
95 break;
96 }
97
98 return pte;
99 }
100
101 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
102 dma_addr_t addr,
103 enum i915_cache_level level)
104 {
105 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
106 pde |= addr;
107 if (level != I915_CACHE_NONE)
108 pde |= PPAT_CACHED_PDE_INDEX;
109 else
110 pde |= PPAT_UNCACHED_INDEX;
111 return pde;
112 }
113
114 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
115 enum i915_cache_level level,
116 bool valid, u32 unused)
117 {
118 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
119 pte |= GEN6_PTE_ADDR_ENCODE(addr);
120
121 switch (level) {
122 case I915_CACHE_L3_LLC:
123 case I915_CACHE_LLC:
124 pte |= GEN6_PTE_CACHE_LLC;
125 break;
126 case I915_CACHE_NONE:
127 pte |= GEN6_PTE_UNCACHED;
128 break;
129 default:
130 WARN_ON(1);
131 }
132
133 return pte;
134 }
135
136 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
137 enum i915_cache_level level,
138 bool valid, u32 unused)
139 {
140 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
141 pte |= GEN6_PTE_ADDR_ENCODE(addr);
142
143 switch (level) {
144 case I915_CACHE_L3_LLC:
145 pte |= GEN7_PTE_CACHE_L3_LLC;
146 break;
147 case I915_CACHE_LLC:
148 pte |= GEN6_PTE_CACHE_LLC;
149 break;
150 case I915_CACHE_NONE:
151 pte |= GEN6_PTE_UNCACHED;
152 break;
153 default:
154 WARN_ON(1);
155 }
156
157 return pte;
158 }
159
160 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
161 enum i915_cache_level level,
162 bool valid, u32 flags)
163 {
164 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
165 pte |= GEN6_PTE_ADDR_ENCODE(addr);
166
167 /* Mark the page as writeable. Other platforms don't have a
168 * setting for read-only/writable, so this matches that behavior.
169 */
170 if (!(flags & PTE_READ_ONLY))
171 pte |= BYT_PTE_WRITEABLE;
172
173 if (level != I915_CACHE_NONE)
174 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
175
176 return pte;
177 }
178
179 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
180 enum i915_cache_level level,
181 bool valid, u32 unused)
182 {
183 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
184 pte |= HSW_PTE_ADDR_ENCODE(addr);
185
186 if (level != I915_CACHE_NONE)
187 pte |= HSW_WB_LLC_AGE3;
188
189 return pte;
190 }
191
192 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
193 enum i915_cache_level level,
194 bool valid, u32 unused)
195 {
196 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
197 pte |= HSW_PTE_ADDR_ENCODE(addr);
198
199 switch (level) {
200 case I915_CACHE_NONE:
201 break;
202 case I915_CACHE_WT:
203 pte |= HSW_WT_ELLC_LLC_AGE3;
204 break;
205 default:
206 pte |= HSW_WB_ELLC_LLC_AGE3;
207 break;
208 }
209
210 return pte;
211 }
212
213 /* Broadwell Page Directory Pointer Descriptors */
214 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
215 uint64_t val)
216 {
217 int ret;
218
219 BUG_ON(entry >= 4);
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
226 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
227 intel_ring_emit(ring, (u32)(val >> 32));
228 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
229 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
230 intel_ring_emit(ring, (u32)(val));
231 intel_ring_advance(ring);
232
233 return 0;
234 }
235
236 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
237 struct intel_engine_cs *ring)
238 {
239 int i, ret;
240
241 /* bit of a hack to find the actual last used pd */
242 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
243
244 for (i = used_pd - 1; i >= 0; i--) {
245 dma_addr_t addr = ppgtt->pd_dma_addr[i];
246 ret = gen8_write_pdp(ring, i, addr);
247 if (ret)
248 return ret;
249 }
250
251 return 0;
252 }
253
254 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
255 uint64_t start,
256 uint64_t length,
257 bool use_scratch)
258 {
259 struct i915_hw_ppgtt *ppgtt =
260 container_of(vm, struct i915_hw_ppgtt, base);
261 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
262 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
263 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
264 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
265 unsigned num_entries = length >> PAGE_SHIFT;
266 unsigned last_pte, i;
267
268 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
269 I915_CACHE_LLC, use_scratch);
270
271 while (num_entries) {
272 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
273
274 last_pte = pte + num_entries;
275 if (last_pte > GEN8_PTES_PER_PAGE)
276 last_pte = GEN8_PTES_PER_PAGE;
277
278 pt_vaddr = kmap_atomic(page_table);
279
280 for (i = pte; i < last_pte; i++) {
281 pt_vaddr[i] = scratch_pte;
282 num_entries--;
283 }
284
285 if (!HAS_LLC(ppgtt->base.dev))
286 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
287 kunmap_atomic(pt_vaddr);
288
289 pte = 0;
290 if (++pde == GEN8_PDES_PER_PAGE) {
291 pdpe++;
292 pde = 0;
293 }
294 }
295 }
296
297 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
298 struct sg_table *pages,
299 uint64_t start,
300 enum i915_cache_level cache_level, u32 unused)
301 {
302 struct i915_hw_ppgtt *ppgtt =
303 container_of(vm, struct i915_hw_ppgtt, base);
304 gen8_gtt_pte_t *pt_vaddr;
305 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
306 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
307 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
308 struct sg_page_iter sg_iter;
309
310 pt_vaddr = NULL;
311
312 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
313 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
314 break;
315
316 if (pt_vaddr == NULL)
317 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
318
319 pt_vaddr[pte] =
320 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
321 cache_level, true);
322 if (++pte == GEN8_PTES_PER_PAGE) {
323 if (!HAS_LLC(ppgtt->base.dev))
324 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
325 kunmap_atomic(pt_vaddr);
326 pt_vaddr = NULL;
327 if (++pde == GEN8_PDES_PER_PAGE) {
328 pdpe++;
329 pde = 0;
330 }
331 pte = 0;
332 }
333 }
334 if (pt_vaddr) {
335 if (!HAS_LLC(ppgtt->base.dev))
336 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
337 kunmap_atomic(pt_vaddr);
338 }
339 }
340
341 static void gen8_free_page_tables(struct page **pt_pages)
342 {
343 int i;
344
345 if (pt_pages == NULL)
346 return;
347
348 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
349 if (pt_pages[i])
350 __free_pages(pt_pages[i], 0);
351 }
352
353 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
354 {
355 int i;
356
357 for (i = 0; i < ppgtt->num_pd_pages; i++) {
358 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
359 kfree(ppgtt->gen8_pt_pages[i]);
360 kfree(ppgtt->gen8_pt_dma_addr[i]);
361 }
362
363 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
364 }
365
366 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
367 {
368 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
369 int i, j;
370
371 for (i = 0; i < ppgtt->num_pd_pages; i++) {
372 /* TODO: In the future we'll support sparse mappings, so this
373 * will have to change. */
374 if (!ppgtt->pd_dma_addr[i])
375 continue;
376
377 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
378 PCI_DMA_BIDIRECTIONAL);
379
380 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
381 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
382 if (addr)
383 pci_unmap_page(hwdev, addr, PAGE_SIZE,
384 PCI_DMA_BIDIRECTIONAL);
385 }
386 }
387 }
388
389 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
390 {
391 struct i915_hw_ppgtt *ppgtt =
392 container_of(vm, struct i915_hw_ppgtt, base);
393
394 gen8_ppgtt_unmap_pages(ppgtt);
395 gen8_ppgtt_free(ppgtt);
396 }
397
398 static struct page **__gen8_alloc_page_tables(void)
399 {
400 struct page **pt_pages;
401 int i;
402
403 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
404 if (!pt_pages)
405 return ERR_PTR(-ENOMEM);
406
407 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
408 pt_pages[i] = alloc_page(GFP_KERNEL);
409 if (!pt_pages[i])
410 goto bail;
411 }
412
413 return pt_pages;
414
415 bail:
416 gen8_free_page_tables(pt_pages);
417 kfree(pt_pages);
418 return ERR_PTR(-ENOMEM);
419 }
420
421 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
422 const int max_pdp)
423 {
424 struct page **pt_pages[GEN8_LEGACY_PDPS];
425 int i, ret;
426
427 for (i = 0; i < max_pdp; i++) {
428 pt_pages[i] = __gen8_alloc_page_tables();
429 if (IS_ERR(pt_pages[i])) {
430 ret = PTR_ERR(pt_pages[i]);
431 goto unwind_out;
432 }
433 }
434
435 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
436 * "atomic" - for cleanup purposes.
437 */
438 for (i = 0; i < max_pdp; i++)
439 ppgtt->gen8_pt_pages[i] = pt_pages[i];
440
441 return 0;
442
443 unwind_out:
444 while (i--) {
445 gen8_free_page_tables(pt_pages[i]);
446 kfree(pt_pages[i]);
447 }
448
449 return ret;
450 }
451
452 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
453 {
454 int i;
455
456 for (i = 0; i < ppgtt->num_pd_pages; i++) {
457 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
458 sizeof(dma_addr_t),
459 GFP_KERNEL);
460 if (!ppgtt->gen8_pt_dma_addr[i])
461 return -ENOMEM;
462 }
463
464 return 0;
465 }
466
467 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
468 const int max_pdp)
469 {
470 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
471 if (!ppgtt->pd_pages)
472 return -ENOMEM;
473
474 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
475 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
476
477 return 0;
478 }
479
480 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
481 const int max_pdp)
482 {
483 int ret;
484
485 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
486 if (ret)
487 return ret;
488
489 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
490 if (ret) {
491 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
492 return ret;
493 }
494
495 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
496
497 ret = gen8_ppgtt_allocate_dma(ppgtt);
498 if (ret)
499 gen8_ppgtt_free(ppgtt);
500
501 return ret;
502 }
503
504 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
505 const int pd)
506 {
507 dma_addr_t pd_addr;
508 int ret;
509
510 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
511 &ppgtt->pd_pages[pd], 0,
512 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
513
514 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
515 if (ret)
516 return ret;
517
518 ppgtt->pd_dma_addr[pd] = pd_addr;
519
520 return 0;
521 }
522
523 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
524 const int pd,
525 const int pt)
526 {
527 dma_addr_t pt_addr;
528 struct page *p;
529 int ret;
530
531 p = ppgtt->gen8_pt_pages[pd][pt];
532 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
533 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
534 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
535 if (ret)
536 return ret;
537
538 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
539
540 return 0;
541 }
542
543 /**
544 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
545 * with a net effect resembling a 2-level page table in normal x86 terms. Each
546 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
547 * space.
548 *
549 * FIXME: split allocation into smaller pieces. For now we only ever do this
550 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
551 * TODO: Do something with the size parameter
552 */
553 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
554 {
555 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
556 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
557 int i, j, ret;
558
559 if (size % (1<<30))
560 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
561
562 /* 1. Do all our allocations for page directories and page tables. */
563 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
564 if (ret)
565 return ret;
566
567 /*
568 * 2. Create DMA mappings for the page directories and page tables.
569 */
570 for (i = 0; i < max_pdp; i++) {
571 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
572 if (ret)
573 goto bail;
574
575 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
576 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
577 if (ret)
578 goto bail;
579 }
580 }
581
582 /*
583 * 3. Map all the page directory entires to point to the page tables
584 * we've allocated.
585 *
586 * For now, the PPGTT helper functions all require that the PDEs are
587 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
588 * will never need to touch the PDEs again.
589 */
590 for (i = 0; i < max_pdp; i++) {
591 gen8_ppgtt_pde_t *pd_vaddr;
592 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
593 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
594 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
595 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
596 I915_CACHE_LLC);
597 }
598 if (!HAS_LLC(ppgtt->base.dev))
599 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
600 kunmap_atomic(pd_vaddr);
601 }
602
603 ppgtt->switch_mm = gen8_mm_switch;
604 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
605 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
606 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
607 ppgtt->base.start = 0;
608 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
609
610 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
611
612 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
613 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
614 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
615 ppgtt->num_pd_entries,
616 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
617 return 0;
618
619 bail:
620 gen8_ppgtt_unmap_pages(ppgtt);
621 gen8_ppgtt_free(ppgtt);
622 return ret;
623 }
624
625 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
626 {
627 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
628 struct i915_address_space *vm = &ppgtt->base;
629 gen6_gtt_pte_t __iomem *pd_addr;
630 gen6_gtt_pte_t scratch_pte;
631 uint32_t pd_entry;
632 int pte, pde;
633
634 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
635
636 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
637 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
638
639 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
640 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
641 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
642 u32 expected;
643 gen6_gtt_pte_t *pt_vaddr;
644 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
645 pd_entry = readl(pd_addr + pde);
646 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
647
648 if (pd_entry != expected)
649 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
650 pde,
651 pd_entry,
652 expected);
653 seq_printf(m, "\tPDE: %x\n", pd_entry);
654
655 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
656 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
657 unsigned long va =
658 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
659 (pte * PAGE_SIZE);
660 int i;
661 bool found = false;
662 for (i = 0; i < 4; i++)
663 if (pt_vaddr[pte + i] != scratch_pte)
664 found = true;
665 if (!found)
666 continue;
667
668 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
669 for (i = 0; i < 4; i++) {
670 if (pt_vaddr[pte + i] != scratch_pte)
671 seq_printf(m, " %08x", pt_vaddr[pte + i]);
672 else
673 seq_puts(m, " SCRATCH ");
674 }
675 seq_puts(m, "\n");
676 }
677 kunmap_atomic(pt_vaddr);
678 }
679 }
680
681 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
682 {
683 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
684 gen6_gtt_pte_t __iomem *pd_addr;
685 uint32_t pd_entry;
686 int i;
687
688 WARN_ON(ppgtt->pd_offset & 0x3f);
689 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
690 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
691 for (i = 0; i < ppgtt->num_pd_entries; i++) {
692 dma_addr_t pt_addr;
693
694 pt_addr = ppgtt->pt_dma_addr[i];
695 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
696 pd_entry |= GEN6_PDE_VALID;
697
698 writel(pd_entry, pd_addr + i);
699 }
700 readl(pd_addr);
701 }
702
703 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
704 {
705 BUG_ON(ppgtt->pd_offset & 0x3f);
706
707 return (ppgtt->pd_offset / 64) << 16;
708 }
709
710 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
711 struct intel_engine_cs *ring)
712 {
713 int ret;
714
715 /* NB: TLBs must be flushed and invalidated before a switch */
716 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
717 if (ret)
718 return ret;
719
720 ret = intel_ring_begin(ring, 6);
721 if (ret)
722 return ret;
723
724 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
725 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
726 intel_ring_emit(ring, PP_DIR_DCLV_2G);
727 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
728 intel_ring_emit(ring, get_pd_offset(ppgtt));
729 intel_ring_emit(ring, MI_NOOP);
730 intel_ring_advance(ring);
731
732 return 0;
733 }
734
735 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
736 struct intel_engine_cs *ring)
737 {
738 int ret;
739
740 /* NB: TLBs must be flushed and invalidated before a switch */
741 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
742 if (ret)
743 return ret;
744
745 ret = intel_ring_begin(ring, 6);
746 if (ret)
747 return ret;
748
749 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
750 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
751 intel_ring_emit(ring, PP_DIR_DCLV_2G);
752 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
753 intel_ring_emit(ring, get_pd_offset(ppgtt));
754 intel_ring_emit(ring, MI_NOOP);
755 intel_ring_advance(ring);
756
757 /* XXX: RCS is the only one to auto invalidate the TLBs? */
758 if (ring->id != RCS) {
759 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
760 if (ret)
761 return ret;
762 }
763
764 return 0;
765 }
766
767 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
768 struct intel_engine_cs *ring)
769 {
770 struct drm_device *dev = ppgtt->base.dev;
771 struct drm_i915_private *dev_priv = dev->dev_private;
772
773
774 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
775 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
776
777 POSTING_READ(RING_PP_DIR_DCLV(ring));
778
779 return 0;
780 }
781
782 static void gen8_ppgtt_enable(struct drm_device *dev)
783 {
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 struct intel_engine_cs *ring;
786 int j;
787
788 for_each_ring(ring, dev_priv, j) {
789 I915_WRITE(RING_MODE_GEN7(ring),
790 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
791 }
792 }
793
794 static void gen7_ppgtt_enable(struct drm_device *dev)
795 {
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct intel_engine_cs *ring;
798 uint32_t ecochk, ecobits;
799 int i;
800
801 ecobits = I915_READ(GAC_ECO_BITS);
802 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
803
804 ecochk = I915_READ(GAM_ECOCHK);
805 if (IS_HASWELL(dev)) {
806 ecochk |= ECOCHK_PPGTT_WB_HSW;
807 } else {
808 ecochk |= ECOCHK_PPGTT_LLC_IVB;
809 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
810 }
811 I915_WRITE(GAM_ECOCHK, ecochk);
812
813 for_each_ring(ring, dev_priv, i) {
814 /* GFX_MODE is per-ring on gen7+ */
815 I915_WRITE(RING_MODE_GEN7(ring),
816 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
817 }
818 }
819
820 static void gen6_ppgtt_enable(struct drm_device *dev)
821 {
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t ecochk, gab_ctl, ecobits;
824
825 ecobits = I915_READ(GAC_ECO_BITS);
826 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
827 ECOBITS_PPGTT_CACHE64B);
828
829 gab_ctl = I915_READ(GAB_CTL);
830 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
831
832 ecochk = I915_READ(GAM_ECOCHK);
833 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
834
835 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
836 }
837
838 /* PPGTT support for Sandybdrige/Gen6 and later */
839 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
840 uint64_t start,
841 uint64_t length,
842 bool use_scratch)
843 {
844 struct i915_hw_ppgtt *ppgtt =
845 container_of(vm, struct i915_hw_ppgtt, base);
846 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
847 unsigned first_entry = start >> PAGE_SHIFT;
848 unsigned num_entries = length >> PAGE_SHIFT;
849 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
850 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
851 unsigned last_pte, i;
852
853 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
854
855 while (num_entries) {
856 last_pte = first_pte + num_entries;
857 if (last_pte > I915_PPGTT_PT_ENTRIES)
858 last_pte = I915_PPGTT_PT_ENTRIES;
859
860 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
861
862 for (i = first_pte; i < last_pte; i++)
863 pt_vaddr[i] = scratch_pte;
864
865 kunmap_atomic(pt_vaddr);
866
867 num_entries -= last_pte - first_pte;
868 first_pte = 0;
869 act_pt++;
870 }
871 }
872
873 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
874 struct sg_table *pages,
875 uint64_t start,
876 enum i915_cache_level cache_level, u32 flags)
877 {
878 struct i915_hw_ppgtt *ppgtt =
879 container_of(vm, struct i915_hw_ppgtt, base);
880 gen6_gtt_pte_t *pt_vaddr;
881 unsigned first_entry = start >> PAGE_SHIFT;
882 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
883 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
884 struct sg_page_iter sg_iter;
885
886 pt_vaddr = NULL;
887 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
888 if (pt_vaddr == NULL)
889 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
890
891 pt_vaddr[act_pte] =
892 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
893 cache_level, true, flags);
894
895 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
896 kunmap_atomic(pt_vaddr);
897 pt_vaddr = NULL;
898 act_pt++;
899 act_pte = 0;
900 }
901 }
902 if (pt_vaddr)
903 kunmap_atomic(pt_vaddr);
904 }
905
906 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
907 {
908 int i;
909
910 if (ppgtt->pt_dma_addr) {
911 for (i = 0; i < ppgtt->num_pd_entries; i++)
912 pci_unmap_page(ppgtt->base.dev->pdev,
913 ppgtt->pt_dma_addr[i],
914 4096, PCI_DMA_BIDIRECTIONAL);
915 }
916 }
917
918 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
919 {
920 int i;
921
922 kfree(ppgtt->pt_dma_addr);
923 for (i = 0; i < ppgtt->num_pd_entries; i++)
924 __free_page(ppgtt->pt_pages[i]);
925 kfree(ppgtt->pt_pages);
926 }
927
928 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
929 {
930 struct i915_hw_ppgtt *ppgtt =
931 container_of(vm, struct i915_hw_ppgtt, base);
932
933 drm_mm_remove_node(&ppgtt->node);
934
935 gen6_ppgtt_unmap_pages(ppgtt);
936 gen6_ppgtt_free(ppgtt);
937 }
938
939 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
940 {
941 struct drm_device *dev = ppgtt->base.dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
943 bool retried = false;
944 int ret;
945
946 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
947 * allocator works in address space sizes, so it's multiplied by page
948 * size. We allocate at the top of the GTT to avoid fragmentation.
949 */
950 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
951 alloc:
952 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
953 &ppgtt->node, GEN6_PD_SIZE,
954 GEN6_PD_ALIGN, 0,
955 0, dev_priv->gtt.base.total,
956 DRM_MM_TOPDOWN);
957 if (ret == -ENOSPC && !retried) {
958 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
959 GEN6_PD_SIZE, GEN6_PD_ALIGN,
960 I915_CACHE_NONE,
961 0, dev_priv->gtt.base.total,
962 0);
963 if (ret)
964 return ret;
965
966 retried = true;
967 goto alloc;
968 }
969
970 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
971 DRM_DEBUG("Forced to use aperture for PDEs\n");
972
973 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
974 return ret;
975 }
976
977 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
978 {
979 int i;
980
981 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
982 GFP_KERNEL);
983
984 if (!ppgtt->pt_pages)
985 return -ENOMEM;
986
987 for (i = 0; i < ppgtt->num_pd_entries; i++) {
988 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
989 if (!ppgtt->pt_pages[i]) {
990 gen6_ppgtt_free(ppgtt);
991 return -ENOMEM;
992 }
993 }
994
995 return 0;
996 }
997
998 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
999 {
1000 int ret;
1001
1002 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1003 if (ret)
1004 return ret;
1005
1006 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1007 if (ret) {
1008 drm_mm_remove_node(&ppgtt->node);
1009 return ret;
1010 }
1011
1012 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1013 GFP_KERNEL);
1014 if (!ppgtt->pt_dma_addr) {
1015 drm_mm_remove_node(&ppgtt->node);
1016 gen6_ppgtt_free(ppgtt);
1017 return -ENOMEM;
1018 }
1019
1020 return 0;
1021 }
1022
1023 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1024 {
1025 struct drm_device *dev = ppgtt->base.dev;
1026 int i;
1027
1028 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1029 dma_addr_t pt_addr;
1030
1031 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1032 PCI_DMA_BIDIRECTIONAL);
1033
1034 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1035 gen6_ppgtt_unmap_pages(ppgtt);
1036 return -EIO;
1037 }
1038
1039 ppgtt->pt_dma_addr[i] = pt_addr;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1046 {
1047 struct drm_device *dev = ppgtt->base.dev;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 int ret;
1050
1051 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1052 if (IS_GEN6(dev)) {
1053 ppgtt->switch_mm = gen6_mm_switch;
1054 } else if (IS_HASWELL(dev)) {
1055 ppgtt->switch_mm = hsw_mm_switch;
1056 } else if (IS_GEN7(dev)) {
1057 ppgtt->switch_mm = gen7_mm_switch;
1058 } else
1059 BUG();
1060
1061 ret = gen6_ppgtt_alloc(ppgtt);
1062 if (ret)
1063 return ret;
1064
1065 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1066 if (ret) {
1067 gen6_ppgtt_free(ppgtt);
1068 return ret;
1069 }
1070
1071 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1072 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1073 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1074 ppgtt->base.start = 0;
1075 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1076 ppgtt->debug_dump = gen6_dump_ppgtt;
1077
1078 ppgtt->pd_offset =
1079 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1080
1081 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1082
1083 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1084 ppgtt->node.size >> 20,
1085 ppgtt->node.start / PAGE_SIZE);
1086
1087 gen6_write_pdes(ppgtt);
1088 DRM_DEBUG("Adding PPGTT at offset %x\n",
1089 ppgtt->pd_offset << 10);
1090
1091 return 0;
1092 }
1093
1094 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1095 {
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097
1098 ppgtt->base.dev = dev;
1099 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1100
1101 if (INTEL_INFO(dev)->gen < 8)
1102 return gen6_ppgtt_init(ppgtt);
1103 else if (IS_GEN8(dev))
1104 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1105 else
1106 BUG();
1107 }
1108 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1109 {
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 int ret = 0;
1112
1113 ret = __hw_ppgtt_init(dev, ppgtt);
1114 if (ret == 0) {
1115 kref_init(&ppgtt->ref);
1116 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1117 ppgtt->base.total);
1118 i915_init_vm(dev_priv, &ppgtt->base);
1119 }
1120
1121 return ret;
1122 }
1123
1124 int i915_ppgtt_init_hw(struct drm_device *dev)
1125 {
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127 struct intel_engine_cs *ring;
1128 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1129 int i, ret = 0;
1130
1131 /* In the case of execlists, PPGTT is enabled by the context descriptor
1132 * and the PDPs are contained within the context itself. We don't
1133 * need to do anything here. */
1134 if (i915.enable_execlists)
1135 return 0;
1136
1137 if (!USES_PPGTT(dev))
1138 return 0;
1139
1140 if (IS_GEN6(dev))
1141 gen6_ppgtt_enable(dev);
1142 else if (IS_GEN7(dev))
1143 gen7_ppgtt_enable(dev);
1144 else if (INTEL_INFO(dev)->gen >= 8)
1145 gen8_ppgtt_enable(dev);
1146 else
1147 WARN_ON(1);
1148
1149 if (ppgtt) {
1150 for_each_ring(ring, dev_priv, i) {
1151 ret = ppgtt->switch_mm(ppgtt, ring);
1152 if (ret != 0)
1153 return ret;
1154 }
1155 }
1156
1157 return ret;
1158 }
1159 struct i915_hw_ppgtt *
1160 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1161 {
1162 struct i915_hw_ppgtt *ppgtt;
1163 int ret;
1164
1165 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1166 if (!ppgtt)
1167 return ERR_PTR(-ENOMEM);
1168
1169 ret = i915_ppgtt_init(dev, ppgtt);
1170 if (ret) {
1171 kfree(ppgtt);
1172 return ERR_PTR(ret);
1173 }
1174
1175 ppgtt->file_priv = fpriv;
1176
1177 return ppgtt;
1178 }
1179
1180 void i915_ppgtt_release(struct kref *kref)
1181 {
1182 struct i915_hw_ppgtt *ppgtt =
1183 container_of(kref, struct i915_hw_ppgtt, ref);
1184
1185 /* vmas should already be unbound */
1186 WARN_ON(!list_empty(&ppgtt->base.active_list));
1187 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1188
1189 list_del(&ppgtt->base.global_link);
1190 drm_mm_takedown(&ppgtt->base.mm);
1191
1192 ppgtt->base.cleanup(&ppgtt->base);
1193 kfree(ppgtt);
1194 }
1195
1196 static void
1197 ppgtt_bind_vma(struct i915_vma *vma,
1198 enum i915_cache_level cache_level,
1199 u32 flags)
1200 {
1201 /* Currently applicable only to VLV */
1202 if (vma->obj->gt_ro)
1203 flags |= PTE_READ_ONLY;
1204
1205 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1206 cache_level, flags);
1207 }
1208
1209 static void ppgtt_unbind_vma(struct i915_vma *vma)
1210 {
1211 vma->vm->clear_range(vma->vm,
1212 vma->node.start,
1213 vma->obj->base.size,
1214 true);
1215 }
1216
1217 extern int intel_iommu_gfx_mapped;
1218 /* Certain Gen5 chipsets require require idling the GPU before
1219 * unmapping anything from the GTT when VT-d is enabled.
1220 */
1221 static inline bool needs_idle_maps(struct drm_device *dev)
1222 {
1223 #ifdef CONFIG_INTEL_IOMMU
1224 /* Query intel_iommu to see if we need the workaround. Presumably that
1225 * was loaded first.
1226 */
1227 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1228 return true;
1229 #endif
1230 return false;
1231 }
1232
1233 static bool do_idling(struct drm_i915_private *dev_priv)
1234 {
1235 bool ret = dev_priv->mm.interruptible;
1236
1237 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1238 dev_priv->mm.interruptible = false;
1239 if (i915_gpu_idle(dev_priv->dev)) {
1240 DRM_ERROR("Couldn't idle GPU\n");
1241 /* Wait a bit, in hopes it avoids the hang */
1242 udelay(10);
1243 }
1244 }
1245
1246 return ret;
1247 }
1248
1249 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1250 {
1251 if (unlikely(dev_priv->gtt.do_idle_maps))
1252 dev_priv->mm.interruptible = interruptible;
1253 }
1254
1255 void i915_check_and_clear_faults(struct drm_device *dev)
1256 {
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 struct intel_engine_cs *ring;
1259 int i;
1260
1261 if (INTEL_INFO(dev)->gen < 6)
1262 return;
1263
1264 for_each_ring(ring, dev_priv, i) {
1265 u32 fault_reg;
1266 fault_reg = I915_READ(RING_FAULT_REG(ring));
1267 if (fault_reg & RING_FAULT_VALID) {
1268 DRM_DEBUG_DRIVER("Unexpected fault\n"
1269 "\tAddr: 0x%08lx\\n"
1270 "\tAddress space: %s\n"
1271 "\tSource ID: %d\n"
1272 "\tType: %d\n",
1273 fault_reg & PAGE_MASK,
1274 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1275 RING_FAULT_SRCID(fault_reg),
1276 RING_FAULT_FAULT_TYPE(fault_reg));
1277 I915_WRITE(RING_FAULT_REG(ring),
1278 fault_reg & ~RING_FAULT_VALID);
1279 }
1280 }
1281 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1282 }
1283
1284 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1285 {
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287
1288 /* Don't bother messing with faults pre GEN6 as we have little
1289 * documentation supporting that it's a good idea.
1290 */
1291 if (INTEL_INFO(dev)->gen < 6)
1292 return;
1293
1294 i915_check_and_clear_faults(dev);
1295
1296 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1297 dev_priv->gtt.base.start,
1298 dev_priv->gtt.base.total,
1299 true);
1300 }
1301
1302 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1303 {
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct drm_i915_gem_object *obj;
1306 struct i915_address_space *vm;
1307
1308 i915_check_and_clear_faults(dev);
1309
1310 /* First fill our portion of the GTT with scratch pages */
1311 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1312 dev_priv->gtt.base.start,
1313 dev_priv->gtt.base.total,
1314 true);
1315
1316 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1317 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1318 &dev_priv->gtt.base);
1319 if (!vma)
1320 continue;
1321
1322 i915_gem_clflush_object(obj, obj->pin_display);
1323 /* The bind_vma code tries to be smart about tracking mappings.
1324 * Unfortunately above, we've just wiped out the mappings
1325 * without telling our object about it. So we need to fake it.
1326 */
1327 obj->has_global_gtt_mapping = 0;
1328 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1329 }
1330
1331
1332 if (INTEL_INFO(dev)->gen >= 8) {
1333 if (IS_CHERRYVIEW(dev))
1334 chv_setup_private_ppat(dev_priv);
1335 else
1336 bdw_setup_private_ppat(dev_priv);
1337
1338 return;
1339 }
1340
1341 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1342 /* TODO: Perhaps it shouldn't be gen6 specific */
1343 if (i915_is_ggtt(vm)) {
1344 if (dev_priv->mm.aliasing_ppgtt)
1345 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1346 continue;
1347 }
1348
1349 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1350 }
1351
1352 i915_gem_chipset_flush(dev);
1353 }
1354
1355 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1356 {
1357 if (obj->has_dma_mapping)
1358 return 0;
1359
1360 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1361 obj->pages->sgl, obj->pages->nents,
1362 PCI_DMA_BIDIRECTIONAL))
1363 return -ENOSPC;
1364
1365 return 0;
1366 }
1367
1368 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1369 {
1370 #ifdef writeq
1371 writeq(pte, addr);
1372 #else
1373 iowrite32((u32)pte, addr);
1374 iowrite32(pte >> 32, addr + 4);
1375 #endif
1376 }
1377
1378 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1379 struct sg_table *st,
1380 uint64_t start,
1381 enum i915_cache_level level, u32 unused)
1382 {
1383 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1384 unsigned first_entry = start >> PAGE_SHIFT;
1385 gen8_gtt_pte_t __iomem *gtt_entries =
1386 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1387 int i = 0;
1388 struct sg_page_iter sg_iter;
1389 dma_addr_t addr = 0; /* shut up gcc */
1390
1391 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1392 addr = sg_dma_address(sg_iter.sg) +
1393 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1394 gen8_set_pte(&gtt_entries[i],
1395 gen8_pte_encode(addr, level, true));
1396 i++;
1397 }
1398
1399 /*
1400 * XXX: This serves as a posting read to make sure that the PTE has
1401 * actually been updated. There is some concern that even though
1402 * registers and PTEs are within the same BAR that they are potentially
1403 * of NUMA access patterns. Therefore, even with the way we assume
1404 * hardware should work, we must keep this posting read for paranoia.
1405 */
1406 if (i != 0)
1407 WARN_ON(readq(&gtt_entries[i-1])
1408 != gen8_pte_encode(addr, level, true));
1409
1410 /* This next bit makes the above posting read even more important. We
1411 * want to flush the TLBs only after we're certain all the PTE updates
1412 * have finished.
1413 */
1414 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1415 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1416 }
1417
1418 /*
1419 * Binds an object into the global gtt with the specified cache level. The object
1420 * will be accessible to the GPU via commands whose operands reference offsets
1421 * within the global GTT as well as accessible by the GPU through the GMADR
1422 * mapped BAR (dev_priv->mm.gtt->gtt).
1423 */
1424 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1425 struct sg_table *st,
1426 uint64_t start,
1427 enum i915_cache_level level, u32 flags)
1428 {
1429 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1430 unsigned first_entry = start >> PAGE_SHIFT;
1431 gen6_gtt_pte_t __iomem *gtt_entries =
1432 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1433 int i = 0;
1434 struct sg_page_iter sg_iter;
1435 dma_addr_t addr = 0;
1436
1437 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1438 addr = sg_page_iter_dma_address(&sg_iter);
1439 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1440 i++;
1441 }
1442
1443 /* XXX: This serves as a posting read to make sure that the PTE has
1444 * actually been updated. There is some concern that even though
1445 * registers and PTEs are within the same BAR that they are potentially
1446 * of NUMA access patterns. Therefore, even with the way we assume
1447 * hardware should work, we must keep this posting read for paranoia.
1448 */
1449 if (i != 0) {
1450 unsigned long gtt = readl(&gtt_entries[i-1]);
1451 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1452 }
1453
1454 /* This next bit makes the above posting read even more important. We
1455 * want to flush the TLBs only after we're certain all the PTE updates
1456 * have finished.
1457 */
1458 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1459 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1460 }
1461
1462 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1463 uint64_t start,
1464 uint64_t length,
1465 bool use_scratch)
1466 {
1467 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1468 unsigned first_entry = start >> PAGE_SHIFT;
1469 unsigned num_entries = length >> PAGE_SHIFT;
1470 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1471 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1472 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1473 int i;
1474
1475 if (WARN(num_entries > max_entries,
1476 "First entry = %d; Num entries = %d (max=%d)\n",
1477 first_entry, num_entries, max_entries))
1478 num_entries = max_entries;
1479
1480 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1481 I915_CACHE_LLC,
1482 use_scratch);
1483 for (i = 0; i < num_entries; i++)
1484 gen8_set_pte(&gtt_base[i], scratch_pte);
1485 readl(gtt_base);
1486 }
1487
1488 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1489 uint64_t start,
1490 uint64_t length,
1491 bool use_scratch)
1492 {
1493 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1494 unsigned first_entry = start >> PAGE_SHIFT;
1495 unsigned num_entries = length >> PAGE_SHIFT;
1496 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1497 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1498 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1499 int i;
1500
1501 if (WARN(num_entries > max_entries,
1502 "First entry = %d; Num entries = %d (max=%d)\n",
1503 first_entry, num_entries, max_entries))
1504 num_entries = max_entries;
1505
1506 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1507
1508 for (i = 0; i < num_entries; i++)
1509 iowrite32(scratch_pte, &gtt_base[i]);
1510 readl(gtt_base);
1511 }
1512
1513
1514 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1515 enum i915_cache_level cache_level,
1516 u32 unused)
1517 {
1518 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1519 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1520 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1521
1522 BUG_ON(!i915_is_ggtt(vma->vm));
1523 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1524 vma->obj->has_global_gtt_mapping = 1;
1525 }
1526
1527 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1528 uint64_t start,
1529 uint64_t length,
1530 bool unused)
1531 {
1532 unsigned first_entry = start >> PAGE_SHIFT;
1533 unsigned num_entries = length >> PAGE_SHIFT;
1534 intel_gtt_clear_range(first_entry, num_entries);
1535 }
1536
1537 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1538 {
1539 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1540 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1541
1542 BUG_ON(!i915_is_ggtt(vma->vm));
1543 vma->obj->has_global_gtt_mapping = 0;
1544 intel_gtt_clear_range(first, size);
1545 }
1546
1547 static void ggtt_bind_vma(struct i915_vma *vma,
1548 enum i915_cache_level cache_level,
1549 u32 flags)
1550 {
1551 struct drm_device *dev = vma->vm->dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 struct drm_i915_gem_object *obj = vma->obj;
1554
1555 /* Currently applicable only to VLV */
1556 if (obj->gt_ro)
1557 flags |= PTE_READ_ONLY;
1558
1559 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1560 * or we have a global mapping already but the cacheability flags have
1561 * changed, set the global PTEs.
1562 *
1563 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1564 * instead if none of the above hold true.
1565 *
1566 * NB: A global mapping should only be needed for special regions like
1567 * "gtt mappable", SNB errata, or if specified via special execbuf
1568 * flags. At all other times, the GPU will use the aliasing PPGTT.
1569 */
1570 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1571 if (!obj->has_global_gtt_mapping ||
1572 (cache_level != obj->cache_level)) {
1573 vma->vm->insert_entries(vma->vm, obj->pages,
1574 vma->node.start,
1575 cache_level, flags);
1576 obj->has_global_gtt_mapping = 1;
1577 }
1578 }
1579
1580 if (dev_priv->mm.aliasing_ppgtt &&
1581 (!obj->has_aliasing_ppgtt_mapping ||
1582 (cache_level != obj->cache_level))) {
1583 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1584 appgtt->base.insert_entries(&appgtt->base,
1585 vma->obj->pages,
1586 vma->node.start,
1587 cache_level, flags);
1588 vma->obj->has_aliasing_ppgtt_mapping = 1;
1589 }
1590 }
1591
1592 static void ggtt_unbind_vma(struct i915_vma *vma)
1593 {
1594 struct drm_device *dev = vma->vm->dev;
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 struct drm_i915_gem_object *obj = vma->obj;
1597
1598 if (obj->has_global_gtt_mapping) {
1599 vma->vm->clear_range(vma->vm,
1600 vma->node.start,
1601 obj->base.size,
1602 true);
1603 obj->has_global_gtt_mapping = 0;
1604 }
1605
1606 if (obj->has_aliasing_ppgtt_mapping) {
1607 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1608 appgtt->base.clear_range(&appgtt->base,
1609 vma->node.start,
1610 obj->base.size,
1611 true);
1612 obj->has_aliasing_ppgtt_mapping = 0;
1613 }
1614 }
1615
1616 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1617 {
1618 struct drm_device *dev = obj->base.dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 bool interruptible;
1621
1622 interruptible = do_idling(dev_priv);
1623
1624 if (!obj->has_dma_mapping)
1625 dma_unmap_sg(&dev->pdev->dev,
1626 obj->pages->sgl, obj->pages->nents,
1627 PCI_DMA_BIDIRECTIONAL);
1628
1629 undo_idling(dev_priv, interruptible);
1630 }
1631
1632 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1633 unsigned long color,
1634 unsigned long *start,
1635 unsigned long *end)
1636 {
1637 if (node->color != color)
1638 *start += 4096;
1639
1640 if (!list_empty(&node->node_list)) {
1641 node = list_entry(node->node_list.next,
1642 struct drm_mm_node,
1643 node_list);
1644 if (node->allocated && node->color != color)
1645 *end -= 4096;
1646 }
1647 }
1648
1649 int i915_gem_setup_global_gtt(struct drm_device *dev,
1650 unsigned long start,
1651 unsigned long mappable_end,
1652 unsigned long end)
1653 {
1654 /* Let GEM Manage all of the aperture.
1655 *
1656 * However, leave one page at the end still bound to the scratch page.
1657 * There are a number of places where the hardware apparently prefetches
1658 * past the end of the object, and we've seen multiple hangs with the
1659 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1660 * aperture. One page should be enough to keep any prefetching inside
1661 * of the aperture.
1662 */
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1665 struct drm_mm_node *entry;
1666 struct drm_i915_gem_object *obj;
1667 unsigned long hole_start, hole_end;
1668 int ret;
1669
1670 BUG_ON(mappable_end > end);
1671
1672 /* Subtract the guard page ... */
1673 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1674 if (!HAS_LLC(dev))
1675 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1676
1677 /* Mark any preallocated objects as occupied */
1678 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1679 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1680
1681 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1682 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1683
1684 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1685 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1686 if (ret) {
1687 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1688 return ret;
1689 }
1690 obj->has_global_gtt_mapping = 1;
1691 }
1692
1693 dev_priv->gtt.base.start = start;
1694 dev_priv->gtt.base.total = end - start;
1695
1696 /* Clear any non-preallocated blocks */
1697 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1698 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1699 hole_start, hole_end);
1700 ggtt_vm->clear_range(ggtt_vm, hole_start,
1701 hole_end - hole_start, true);
1702 }
1703
1704 /* And finally clear the reserved guard page */
1705 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1706
1707 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1708 struct i915_hw_ppgtt *ppgtt;
1709
1710 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1711 if (!ppgtt)
1712 return -ENOMEM;
1713
1714 ret = __hw_ppgtt_init(dev, ppgtt);
1715 if (ret != 0)
1716 return ret;
1717
1718 dev_priv->mm.aliasing_ppgtt = ppgtt;
1719 }
1720
1721 return 0;
1722 }
1723
1724 void i915_gem_init_global_gtt(struct drm_device *dev)
1725 {
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727 unsigned long gtt_size, mappable_size;
1728
1729 gtt_size = dev_priv->gtt.base.total;
1730 mappable_size = dev_priv->gtt.mappable_end;
1731
1732 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1733 }
1734
1735 void i915_global_gtt_cleanup(struct drm_device *dev)
1736 {
1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 struct i915_address_space *vm = &dev_priv->gtt.base;
1739
1740 if (dev_priv->mm.aliasing_ppgtt) {
1741 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1742
1743 ppgtt->base.cleanup(&ppgtt->base);
1744 }
1745
1746 if (drm_mm_initialized(&vm->mm)) {
1747 drm_mm_takedown(&vm->mm);
1748 list_del(&vm->global_link);
1749 }
1750
1751 vm->cleanup(vm);
1752 }
1753
1754 static int setup_scratch_page(struct drm_device *dev)
1755 {
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 struct page *page;
1758 dma_addr_t dma_addr;
1759
1760 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1761 if (page == NULL)
1762 return -ENOMEM;
1763 set_pages_uc(page, 1);
1764
1765 #ifdef CONFIG_INTEL_IOMMU
1766 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1767 PCI_DMA_BIDIRECTIONAL);
1768 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1769 return -EINVAL;
1770 #else
1771 dma_addr = page_to_phys(page);
1772 #endif
1773 dev_priv->gtt.base.scratch.page = page;
1774 dev_priv->gtt.base.scratch.addr = dma_addr;
1775
1776 return 0;
1777 }
1778
1779 static void teardown_scratch_page(struct drm_device *dev)
1780 {
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 struct page *page = dev_priv->gtt.base.scratch.page;
1783
1784 set_pages_wb(page, 1);
1785 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1786 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1787 __free_page(page);
1788 }
1789
1790 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1791 {
1792 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1793 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1794 return snb_gmch_ctl << 20;
1795 }
1796
1797 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1798 {
1799 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1800 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1801 if (bdw_gmch_ctl)
1802 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1803
1804 #ifdef CONFIG_X86_32
1805 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1806 if (bdw_gmch_ctl > 4)
1807 bdw_gmch_ctl = 4;
1808 #endif
1809
1810 return bdw_gmch_ctl << 20;
1811 }
1812
1813 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1814 {
1815 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1816 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1817
1818 if (gmch_ctrl)
1819 return 1 << (20 + gmch_ctrl);
1820
1821 return 0;
1822 }
1823
1824 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1825 {
1826 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1827 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1828 return snb_gmch_ctl << 25; /* 32 MB units */
1829 }
1830
1831 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1832 {
1833 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1834 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1835 return bdw_gmch_ctl << 25; /* 32 MB units */
1836 }
1837
1838 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1839 {
1840 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1841 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1842
1843 /*
1844 * 0x0 to 0x10: 32MB increments starting at 0MB
1845 * 0x11 to 0x16: 4MB increments starting at 8MB
1846 * 0x17 to 0x1d: 4MB increments start at 36MB
1847 */
1848 if (gmch_ctrl < 0x11)
1849 return gmch_ctrl << 25;
1850 else if (gmch_ctrl < 0x17)
1851 return (gmch_ctrl - 0x11 + 2) << 22;
1852 else
1853 return (gmch_ctrl - 0x17 + 9) << 22;
1854 }
1855
1856 static int ggtt_probe_common(struct drm_device *dev,
1857 size_t gtt_size)
1858 {
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 phys_addr_t gtt_phys_addr;
1861 int ret;
1862
1863 /* For Modern GENs the PTEs and register space are split in the BAR */
1864 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1865 (pci_resource_len(dev->pdev, 0) / 2);
1866
1867 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1868 if (!dev_priv->gtt.gsm) {
1869 DRM_ERROR("Failed to map the gtt page table\n");
1870 return -ENOMEM;
1871 }
1872
1873 ret = setup_scratch_page(dev);
1874 if (ret) {
1875 DRM_ERROR("Scratch setup failed\n");
1876 /* iounmap will also get called at remove, but meh */
1877 iounmap(dev_priv->gtt.gsm);
1878 }
1879
1880 return ret;
1881 }
1882
1883 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1884 * bits. When using advanced contexts each context stores its own PAT, but
1885 * writing this data shouldn't be harmful even in those cases. */
1886 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1887 {
1888 uint64_t pat;
1889
1890 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1891 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1892 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1893 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1894 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1895 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1896 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1897 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1898
1899 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1900 * write would work. */
1901 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1902 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1903 }
1904
1905 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1906 {
1907 uint64_t pat;
1908
1909 /*
1910 * Map WB on BDW to snooped on CHV.
1911 *
1912 * Only the snoop bit has meaning for CHV, the rest is
1913 * ignored.
1914 *
1915 * Note that the harware enforces snooping for all page
1916 * table accesses. The snoop bit is actually ignored for
1917 * PDEs.
1918 */
1919 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1920 GEN8_PPAT(1, 0) |
1921 GEN8_PPAT(2, 0) |
1922 GEN8_PPAT(3, 0) |
1923 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1924 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1925 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1926 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1927
1928 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1929 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1930 }
1931
1932 static int gen8_gmch_probe(struct drm_device *dev,
1933 size_t *gtt_total,
1934 size_t *stolen,
1935 phys_addr_t *mappable_base,
1936 unsigned long *mappable_end)
1937 {
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 unsigned int gtt_size;
1940 u16 snb_gmch_ctl;
1941 int ret;
1942
1943 /* TODO: We're not aware of mappable constraints on gen8 yet */
1944 *mappable_base = pci_resource_start(dev->pdev, 2);
1945 *mappable_end = pci_resource_len(dev->pdev, 2);
1946
1947 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1948 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1949
1950 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1951
1952 if (IS_CHERRYVIEW(dev)) {
1953 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1954 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1955 } else {
1956 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1957 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1958 }
1959
1960 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1961
1962 if (IS_CHERRYVIEW(dev))
1963 chv_setup_private_ppat(dev_priv);
1964 else
1965 bdw_setup_private_ppat(dev_priv);
1966
1967 ret = ggtt_probe_common(dev, gtt_size);
1968
1969 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1970 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1971
1972 return ret;
1973 }
1974
1975 static int gen6_gmch_probe(struct drm_device *dev,
1976 size_t *gtt_total,
1977 size_t *stolen,
1978 phys_addr_t *mappable_base,
1979 unsigned long *mappable_end)
1980 {
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 unsigned int gtt_size;
1983 u16 snb_gmch_ctl;
1984 int ret;
1985
1986 *mappable_base = pci_resource_start(dev->pdev, 2);
1987 *mappable_end = pci_resource_len(dev->pdev, 2);
1988
1989 /* 64/512MB is the current min/max we actually know of, but this is just
1990 * a coarse sanity check.
1991 */
1992 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1993 DRM_ERROR("Unknown GMADR size (%lx)\n",
1994 dev_priv->gtt.mappable_end);
1995 return -ENXIO;
1996 }
1997
1998 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1999 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2000 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2001
2002 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2003
2004 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2005 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2006
2007 ret = ggtt_probe_common(dev, gtt_size);
2008
2009 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2010 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2011
2012 return ret;
2013 }
2014
2015 static void gen6_gmch_remove(struct i915_address_space *vm)
2016 {
2017
2018 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2019
2020 iounmap(gtt->gsm);
2021 teardown_scratch_page(vm->dev);
2022 }
2023
2024 static int i915_gmch_probe(struct drm_device *dev,
2025 size_t *gtt_total,
2026 size_t *stolen,
2027 phys_addr_t *mappable_base,
2028 unsigned long *mappable_end)
2029 {
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 int ret;
2032
2033 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2034 if (!ret) {
2035 DRM_ERROR("failed to set up gmch\n");
2036 return -EIO;
2037 }
2038
2039 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2040
2041 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2042 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2043
2044 if (unlikely(dev_priv->gtt.do_idle_maps))
2045 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2046
2047 return 0;
2048 }
2049
2050 static void i915_gmch_remove(struct i915_address_space *vm)
2051 {
2052 intel_gmch_remove();
2053 }
2054
2055 int i915_gem_gtt_init(struct drm_device *dev)
2056 {
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058 struct i915_gtt *gtt = &dev_priv->gtt;
2059 int ret;
2060
2061 if (INTEL_INFO(dev)->gen <= 5) {
2062 gtt->gtt_probe = i915_gmch_probe;
2063 gtt->base.cleanup = i915_gmch_remove;
2064 } else if (INTEL_INFO(dev)->gen < 8) {
2065 gtt->gtt_probe = gen6_gmch_probe;
2066 gtt->base.cleanup = gen6_gmch_remove;
2067 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2068 gtt->base.pte_encode = iris_pte_encode;
2069 else if (IS_HASWELL(dev))
2070 gtt->base.pte_encode = hsw_pte_encode;
2071 else if (IS_VALLEYVIEW(dev))
2072 gtt->base.pte_encode = byt_pte_encode;
2073 else if (INTEL_INFO(dev)->gen >= 7)
2074 gtt->base.pte_encode = ivb_pte_encode;
2075 else
2076 gtt->base.pte_encode = snb_pte_encode;
2077 } else {
2078 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2079 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2080 }
2081
2082 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2083 &gtt->mappable_base, &gtt->mappable_end);
2084 if (ret)
2085 return ret;
2086
2087 gtt->base.dev = dev;
2088
2089 /* GMADR is the PCI mmio aperture into the global GTT. */
2090 DRM_INFO("Memory usable by graphics device = %zdM\n",
2091 gtt->base.total >> 20);
2092 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2093 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2094 #ifdef CONFIG_INTEL_IOMMU
2095 if (intel_iommu_gfx_mapped)
2096 DRM_INFO("VT-d active for gfx access\n");
2097 #endif
2098 /*
2099 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2100 * user's requested state against the hardware/driver capabilities. We
2101 * do this now so that we can print out any log messages once rather
2102 * than every time we check intel_enable_ppgtt().
2103 */
2104 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2105 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2106
2107 return 0;
2108 }
2109
2110 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2111 struct i915_address_space *vm)
2112 {
2113 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2114 if (vma == NULL)
2115 return ERR_PTR(-ENOMEM);
2116
2117 INIT_LIST_HEAD(&vma->vma_link);
2118 INIT_LIST_HEAD(&vma->mm_list);
2119 INIT_LIST_HEAD(&vma->exec_list);
2120 vma->vm = vm;
2121 vma->obj = obj;
2122
2123 switch (INTEL_INFO(vm->dev)->gen) {
2124 case 8:
2125 case 7:
2126 case 6:
2127 if (i915_is_ggtt(vm)) {
2128 vma->unbind_vma = ggtt_unbind_vma;
2129 vma->bind_vma = ggtt_bind_vma;
2130 } else {
2131 vma->unbind_vma = ppgtt_unbind_vma;
2132 vma->bind_vma = ppgtt_bind_vma;
2133 }
2134 break;
2135 case 5:
2136 case 4:
2137 case 3:
2138 case 2:
2139 BUG_ON(!i915_is_ggtt(vm));
2140 vma->unbind_vma = i915_ggtt_unbind_vma;
2141 vma->bind_vma = i915_ggtt_bind_vma;
2142 break;
2143 default:
2144 BUG();
2145 }
2146
2147 /* Keep GGTT vmas first to make debug easier */
2148 if (i915_is_ggtt(vm))
2149 list_add(&vma->vma_link, &obj->vma_list);
2150 else {
2151 list_add_tail(&vma->vma_link, &obj->vma_list);
2152 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2153 }
2154
2155 return vma;
2156 }
2157
2158 struct i915_vma *
2159 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2160 struct i915_address_space *vm)
2161 {
2162 struct i915_vma *vma;
2163
2164 vma = i915_gem_obj_to_vma(obj, vm);
2165 if (!vma)
2166 vma = __i915_gem_vma_create(obj, vm);
2167
2168 return vma;
2169 }
Linux kernel - Deliverables
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