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drm/i915: Infrastructure for supporting different GGTT views per object
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 const struct i915_ggtt_view i915_ggtt_view_normal;
34
35 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
36 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
37
38 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
39 {
40 bool has_aliasing_ppgtt;
41 bool has_full_ppgtt;
42
43 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
44 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
45 if (IS_GEN8(dev))
46 has_full_ppgtt = false; /* XXX why? */
47
48 /*
49 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
50 * execlists, the sole mechanism available to submit work.
51 */
52 if (INTEL_INFO(dev)->gen < 9 &&
53 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
54 return 0;
55
56 if (enable_ppgtt == 1)
57 return 1;
58
59 if (enable_ppgtt == 2 && has_full_ppgtt)
60 return 2;
61
62 #ifdef CONFIG_INTEL_IOMMU
63 /* Disable ppgtt on SNB if VT-d is on. */
64 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
65 DRM_INFO("Disabling PPGTT because VT-d is on\n");
66 return 0;
67 }
68 #endif
69
70 /* Early VLV doesn't have this */
71 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
72 dev->pdev->revision < 0xb) {
73 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
74 return 0;
75 }
76
77 return has_aliasing_ppgtt ? 1 : 0;
78 }
79
80
81 static void ppgtt_bind_vma(struct i915_vma *vma,
82 enum i915_cache_level cache_level,
83 u32 flags);
84 static void ppgtt_unbind_vma(struct i915_vma *vma);
85
86 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
87 enum i915_cache_level level,
88 bool valid)
89 {
90 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
91 pte |= addr;
92
93 switch (level) {
94 case I915_CACHE_NONE:
95 pte |= PPAT_UNCACHED_INDEX;
96 break;
97 case I915_CACHE_WT:
98 pte |= PPAT_DISPLAY_ELLC_INDEX;
99 break;
100 default:
101 pte |= PPAT_CACHED_INDEX;
102 break;
103 }
104
105 return pte;
106 }
107
108 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
109 dma_addr_t addr,
110 enum i915_cache_level level)
111 {
112 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
113 pde |= addr;
114 if (level != I915_CACHE_NONE)
115 pde |= PPAT_CACHED_PDE_INDEX;
116 else
117 pde |= PPAT_UNCACHED_INDEX;
118 return pde;
119 }
120
121 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
122 enum i915_cache_level level,
123 bool valid, u32 unused)
124 {
125 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
126 pte |= GEN6_PTE_ADDR_ENCODE(addr);
127
128 switch (level) {
129 case I915_CACHE_L3_LLC:
130 case I915_CACHE_LLC:
131 pte |= GEN6_PTE_CACHE_LLC;
132 break;
133 case I915_CACHE_NONE:
134 pte |= GEN6_PTE_UNCACHED;
135 break;
136 default:
137 MISSING_CASE(level);
138 }
139
140 return pte;
141 }
142
143 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
144 enum i915_cache_level level,
145 bool valid, u32 unused)
146 {
147 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
148 pte |= GEN6_PTE_ADDR_ENCODE(addr);
149
150 switch (level) {
151 case I915_CACHE_L3_LLC:
152 pte |= GEN7_PTE_CACHE_L3_LLC;
153 break;
154 case I915_CACHE_LLC:
155 pte |= GEN6_PTE_CACHE_LLC;
156 break;
157 case I915_CACHE_NONE:
158 pte |= GEN6_PTE_UNCACHED;
159 break;
160 default:
161 MISSING_CASE(level);
162 }
163
164 return pte;
165 }
166
167 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
168 enum i915_cache_level level,
169 bool valid, u32 flags)
170 {
171 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
172 pte |= GEN6_PTE_ADDR_ENCODE(addr);
173
174 if (!(flags & PTE_READ_ONLY))
175 pte |= BYT_PTE_WRITEABLE;
176
177 if (level != I915_CACHE_NONE)
178 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
179
180 return pte;
181 }
182
183 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
184 enum i915_cache_level level,
185 bool valid, u32 unused)
186 {
187 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
188 pte |= HSW_PTE_ADDR_ENCODE(addr);
189
190 if (level != I915_CACHE_NONE)
191 pte |= HSW_WB_LLC_AGE3;
192
193 return pte;
194 }
195
196 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
197 enum i915_cache_level level,
198 bool valid, u32 unused)
199 {
200 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
201 pte |= HSW_PTE_ADDR_ENCODE(addr);
202
203 switch (level) {
204 case I915_CACHE_NONE:
205 break;
206 case I915_CACHE_WT:
207 pte |= HSW_WT_ELLC_LLC_AGE3;
208 break;
209 default:
210 pte |= HSW_WB_ELLC_LLC_AGE3;
211 break;
212 }
213
214 return pte;
215 }
216
217 /* Broadwell Page Directory Pointer Descriptors */
218 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
219 uint64_t val)
220 {
221 int ret;
222
223 BUG_ON(entry >= 4);
224
225 ret = intel_ring_begin(ring, 6);
226 if (ret)
227 return ret;
228
229 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
230 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
231 intel_ring_emit(ring, (u32)(val >> 32));
232 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
233 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
234 intel_ring_emit(ring, (u32)(val));
235 intel_ring_advance(ring);
236
237 return 0;
238 }
239
240 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
241 struct intel_engine_cs *ring)
242 {
243 int i, ret;
244
245 /* bit of a hack to find the actual last used pd */
246 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
247
248 for (i = used_pd - 1; i >= 0; i--) {
249 dma_addr_t addr = ppgtt->pd_dma_addr[i];
250 ret = gen8_write_pdp(ring, i, addr);
251 if (ret)
252 return ret;
253 }
254
255 return 0;
256 }
257
258 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
259 uint64_t start,
260 uint64_t length,
261 bool use_scratch)
262 {
263 struct i915_hw_ppgtt *ppgtt =
264 container_of(vm, struct i915_hw_ppgtt, base);
265 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
266 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
267 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
268 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
269 unsigned num_entries = length >> PAGE_SHIFT;
270 unsigned last_pte, i;
271
272 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
273 I915_CACHE_LLC, use_scratch);
274
275 while (num_entries) {
276 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
277
278 last_pte = pte + num_entries;
279 if (last_pte > GEN8_PTES_PER_PAGE)
280 last_pte = GEN8_PTES_PER_PAGE;
281
282 pt_vaddr = kmap_atomic(page_table);
283
284 for (i = pte; i < last_pte; i++) {
285 pt_vaddr[i] = scratch_pte;
286 num_entries--;
287 }
288
289 if (!HAS_LLC(ppgtt->base.dev))
290 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
291 kunmap_atomic(pt_vaddr);
292
293 pte = 0;
294 if (++pde == GEN8_PDES_PER_PAGE) {
295 pdpe++;
296 pde = 0;
297 }
298 }
299 }
300
301 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
302 struct sg_table *pages,
303 uint64_t start,
304 enum i915_cache_level cache_level, u32 unused)
305 {
306 struct i915_hw_ppgtt *ppgtt =
307 container_of(vm, struct i915_hw_ppgtt, base);
308 gen8_gtt_pte_t *pt_vaddr;
309 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
310 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
311 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
312 struct sg_page_iter sg_iter;
313
314 pt_vaddr = NULL;
315
316 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
317 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
318 break;
319
320 if (pt_vaddr == NULL)
321 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
322
323 pt_vaddr[pte] =
324 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
325 cache_level, true);
326 if (++pte == GEN8_PTES_PER_PAGE) {
327 if (!HAS_LLC(ppgtt->base.dev))
328 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
329 kunmap_atomic(pt_vaddr);
330 pt_vaddr = NULL;
331 if (++pde == GEN8_PDES_PER_PAGE) {
332 pdpe++;
333 pde = 0;
334 }
335 pte = 0;
336 }
337 }
338 if (pt_vaddr) {
339 if (!HAS_LLC(ppgtt->base.dev))
340 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
341 kunmap_atomic(pt_vaddr);
342 }
343 }
344
345 static void gen8_free_page_tables(struct page **pt_pages)
346 {
347 int i;
348
349 if (pt_pages == NULL)
350 return;
351
352 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
353 if (pt_pages[i])
354 __free_pages(pt_pages[i], 0);
355 }
356
357 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
358 {
359 int i;
360
361 for (i = 0; i < ppgtt->num_pd_pages; i++) {
362 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
363 kfree(ppgtt->gen8_pt_pages[i]);
364 kfree(ppgtt->gen8_pt_dma_addr[i]);
365 }
366
367 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
368 }
369
370 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
371 {
372 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
373 int i, j;
374
375 for (i = 0; i < ppgtt->num_pd_pages; i++) {
376 /* TODO: In the future we'll support sparse mappings, so this
377 * will have to change. */
378 if (!ppgtt->pd_dma_addr[i])
379 continue;
380
381 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
382 PCI_DMA_BIDIRECTIONAL);
383
384 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
385 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
386 if (addr)
387 pci_unmap_page(hwdev, addr, PAGE_SIZE,
388 PCI_DMA_BIDIRECTIONAL);
389 }
390 }
391 }
392
393 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
394 {
395 struct i915_hw_ppgtt *ppgtt =
396 container_of(vm, struct i915_hw_ppgtt, base);
397
398 gen8_ppgtt_unmap_pages(ppgtt);
399 gen8_ppgtt_free(ppgtt);
400 }
401
402 static struct page **__gen8_alloc_page_tables(void)
403 {
404 struct page **pt_pages;
405 int i;
406
407 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
408 if (!pt_pages)
409 return ERR_PTR(-ENOMEM);
410
411 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
412 pt_pages[i] = alloc_page(GFP_KERNEL);
413 if (!pt_pages[i])
414 goto bail;
415 }
416
417 return pt_pages;
418
419 bail:
420 gen8_free_page_tables(pt_pages);
421 kfree(pt_pages);
422 return ERR_PTR(-ENOMEM);
423 }
424
425 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
426 const int max_pdp)
427 {
428 struct page **pt_pages[GEN8_LEGACY_PDPS];
429 int i, ret;
430
431 for (i = 0; i < max_pdp; i++) {
432 pt_pages[i] = __gen8_alloc_page_tables();
433 if (IS_ERR(pt_pages[i])) {
434 ret = PTR_ERR(pt_pages[i]);
435 goto unwind_out;
436 }
437 }
438
439 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
440 * "atomic" - for cleanup purposes.
441 */
442 for (i = 0; i < max_pdp; i++)
443 ppgtt->gen8_pt_pages[i] = pt_pages[i];
444
445 return 0;
446
447 unwind_out:
448 while (i--) {
449 gen8_free_page_tables(pt_pages[i]);
450 kfree(pt_pages[i]);
451 }
452
453 return ret;
454 }
455
456 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
457 {
458 int i;
459
460 for (i = 0; i < ppgtt->num_pd_pages; i++) {
461 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
462 sizeof(dma_addr_t),
463 GFP_KERNEL);
464 if (!ppgtt->gen8_pt_dma_addr[i])
465 return -ENOMEM;
466 }
467
468 return 0;
469 }
470
471 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
472 const int max_pdp)
473 {
474 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
475 if (!ppgtt->pd_pages)
476 return -ENOMEM;
477
478 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
479 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
480
481 return 0;
482 }
483
484 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
485 const int max_pdp)
486 {
487 int ret;
488
489 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
490 if (ret)
491 return ret;
492
493 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
494 if (ret) {
495 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
496 return ret;
497 }
498
499 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
500
501 ret = gen8_ppgtt_allocate_dma(ppgtt);
502 if (ret)
503 gen8_ppgtt_free(ppgtt);
504
505 return ret;
506 }
507
508 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
509 const int pd)
510 {
511 dma_addr_t pd_addr;
512 int ret;
513
514 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
515 &ppgtt->pd_pages[pd], 0,
516 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
517
518 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
519 if (ret)
520 return ret;
521
522 ppgtt->pd_dma_addr[pd] = pd_addr;
523
524 return 0;
525 }
526
527 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
528 const int pd,
529 const int pt)
530 {
531 dma_addr_t pt_addr;
532 struct page *p;
533 int ret;
534
535 p = ppgtt->gen8_pt_pages[pd][pt];
536 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
537 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
538 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
539 if (ret)
540 return ret;
541
542 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
543
544 return 0;
545 }
546
547 /**
548 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
549 * with a net effect resembling a 2-level page table in normal x86 terms. Each
550 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
551 * space.
552 *
553 * FIXME: split allocation into smaller pieces. For now we only ever do this
554 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
555 * TODO: Do something with the size parameter
556 */
557 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
558 {
559 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
560 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
561 int i, j, ret;
562
563 if (size % (1<<30))
564 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
565
566 /* 1. Do all our allocations for page directories and page tables. */
567 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
568 if (ret)
569 return ret;
570
571 /*
572 * 2. Create DMA mappings for the page directories and page tables.
573 */
574 for (i = 0; i < max_pdp; i++) {
575 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
576 if (ret)
577 goto bail;
578
579 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
580 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
581 if (ret)
582 goto bail;
583 }
584 }
585
586 /*
587 * 3. Map all the page directory entires to point to the page tables
588 * we've allocated.
589 *
590 * For now, the PPGTT helper functions all require that the PDEs are
591 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
592 * will never need to touch the PDEs again.
593 */
594 for (i = 0; i < max_pdp; i++) {
595 gen8_ppgtt_pde_t *pd_vaddr;
596 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
597 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
598 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
599 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
600 I915_CACHE_LLC);
601 }
602 if (!HAS_LLC(ppgtt->base.dev))
603 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
604 kunmap_atomic(pd_vaddr);
605 }
606
607 ppgtt->switch_mm = gen8_mm_switch;
608 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
609 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
610 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
611 ppgtt->base.start = 0;
612 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
613
614 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
615
616 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
617 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
618 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
619 ppgtt->num_pd_entries,
620 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
621 return 0;
622
623 bail:
624 gen8_ppgtt_unmap_pages(ppgtt);
625 gen8_ppgtt_free(ppgtt);
626 return ret;
627 }
628
629 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
630 {
631 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
632 struct i915_address_space *vm = &ppgtt->base;
633 gen6_gtt_pte_t __iomem *pd_addr;
634 gen6_gtt_pte_t scratch_pte;
635 uint32_t pd_entry;
636 int pte, pde;
637
638 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
639
640 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
641 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
642
643 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
644 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
645 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
646 u32 expected;
647 gen6_gtt_pte_t *pt_vaddr;
648 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
649 pd_entry = readl(pd_addr + pde);
650 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
651
652 if (pd_entry != expected)
653 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
654 pde,
655 pd_entry,
656 expected);
657 seq_printf(m, "\tPDE: %x\n", pd_entry);
658
659 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
660 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
661 unsigned long va =
662 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
663 (pte * PAGE_SIZE);
664 int i;
665 bool found = false;
666 for (i = 0; i < 4; i++)
667 if (pt_vaddr[pte + i] != scratch_pte)
668 found = true;
669 if (!found)
670 continue;
671
672 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
673 for (i = 0; i < 4; i++) {
674 if (pt_vaddr[pte + i] != scratch_pte)
675 seq_printf(m, " %08x", pt_vaddr[pte + i]);
676 else
677 seq_puts(m, " SCRATCH ");
678 }
679 seq_puts(m, "\n");
680 }
681 kunmap_atomic(pt_vaddr);
682 }
683 }
684
685 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
686 {
687 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
688 gen6_gtt_pte_t __iomem *pd_addr;
689 uint32_t pd_entry;
690 int i;
691
692 WARN_ON(ppgtt->pd_offset & 0x3f);
693 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
694 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
695 for (i = 0; i < ppgtt->num_pd_entries; i++) {
696 dma_addr_t pt_addr;
697
698 pt_addr = ppgtt->pt_dma_addr[i];
699 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
700 pd_entry |= GEN6_PDE_VALID;
701
702 writel(pd_entry, pd_addr + i);
703 }
704 readl(pd_addr);
705 }
706
707 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
708 {
709 BUG_ON(ppgtt->pd_offset & 0x3f);
710
711 return (ppgtt->pd_offset / 64) << 16;
712 }
713
714 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
715 struct intel_engine_cs *ring)
716 {
717 int ret;
718
719 /* NB: TLBs must be flushed and invalidated before a switch */
720 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
721 if (ret)
722 return ret;
723
724 ret = intel_ring_begin(ring, 6);
725 if (ret)
726 return ret;
727
728 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
729 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
730 intel_ring_emit(ring, PP_DIR_DCLV_2G);
731 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
732 intel_ring_emit(ring, get_pd_offset(ppgtt));
733 intel_ring_emit(ring, MI_NOOP);
734 intel_ring_advance(ring);
735
736 return 0;
737 }
738
739 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
740 struct intel_engine_cs *ring)
741 {
742 int ret;
743
744 /* NB: TLBs must be flushed and invalidated before a switch */
745 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
746 if (ret)
747 return ret;
748
749 ret = intel_ring_begin(ring, 6);
750 if (ret)
751 return ret;
752
753 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
754 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
755 intel_ring_emit(ring, PP_DIR_DCLV_2G);
756 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
757 intel_ring_emit(ring, get_pd_offset(ppgtt));
758 intel_ring_emit(ring, MI_NOOP);
759 intel_ring_advance(ring);
760
761 /* XXX: RCS is the only one to auto invalidate the TLBs? */
762 if (ring->id != RCS) {
763 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
764 if (ret)
765 return ret;
766 }
767
768 return 0;
769 }
770
771 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
772 struct intel_engine_cs *ring)
773 {
774 struct drm_device *dev = ppgtt->base.dev;
775 struct drm_i915_private *dev_priv = dev->dev_private;
776
777
778 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
779 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
780
781 POSTING_READ(RING_PP_DIR_DCLV(ring));
782
783 return 0;
784 }
785
786 static void gen8_ppgtt_enable(struct drm_device *dev)
787 {
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 struct intel_engine_cs *ring;
790 int j;
791
792 for_each_ring(ring, dev_priv, j) {
793 I915_WRITE(RING_MODE_GEN7(ring),
794 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
795 }
796 }
797
798 static void gen7_ppgtt_enable(struct drm_device *dev)
799 {
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 struct intel_engine_cs *ring;
802 uint32_t ecochk, ecobits;
803 int i;
804
805 ecobits = I915_READ(GAC_ECO_BITS);
806 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
807
808 ecochk = I915_READ(GAM_ECOCHK);
809 if (IS_HASWELL(dev)) {
810 ecochk |= ECOCHK_PPGTT_WB_HSW;
811 } else {
812 ecochk |= ECOCHK_PPGTT_LLC_IVB;
813 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
814 }
815 I915_WRITE(GAM_ECOCHK, ecochk);
816
817 for_each_ring(ring, dev_priv, i) {
818 /* GFX_MODE is per-ring on gen7+ */
819 I915_WRITE(RING_MODE_GEN7(ring),
820 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
821 }
822 }
823
824 static void gen6_ppgtt_enable(struct drm_device *dev)
825 {
826 struct drm_i915_private *dev_priv = dev->dev_private;
827 uint32_t ecochk, gab_ctl, ecobits;
828
829 ecobits = I915_READ(GAC_ECO_BITS);
830 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
831 ECOBITS_PPGTT_CACHE64B);
832
833 gab_ctl = I915_READ(GAB_CTL);
834 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
835
836 ecochk = I915_READ(GAM_ECOCHK);
837 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
838
839 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
840 }
841
842 /* PPGTT support for Sandybdrige/Gen6 and later */
843 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
844 uint64_t start,
845 uint64_t length,
846 bool use_scratch)
847 {
848 struct i915_hw_ppgtt *ppgtt =
849 container_of(vm, struct i915_hw_ppgtt, base);
850 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
851 unsigned first_entry = start >> PAGE_SHIFT;
852 unsigned num_entries = length >> PAGE_SHIFT;
853 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
854 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
855 unsigned last_pte, i;
856
857 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
858
859 while (num_entries) {
860 last_pte = first_pte + num_entries;
861 if (last_pte > I915_PPGTT_PT_ENTRIES)
862 last_pte = I915_PPGTT_PT_ENTRIES;
863
864 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
865
866 for (i = first_pte; i < last_pte; i++)
867 pt_vaddr[i] = scratch_pte;
868
869 kunmap_atomic(pt_vaddr);
870
871 num_entries -= last_pte - first_pte;
872 first_pte = 0;
873 act_pt++;
874 }
875 }
876
877 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
878 struct sg_table *pages,
879 uint64_t start,
880 enum i915_cache_level cache_level, u32 flags)
881 {
882 struct i915_hw_ppgtt *ppgtt =
883 container_of(vm, struct i915_hw_ppgtt, base);
884 gen6_gtt_pte_t *pt_vaddr;
885 unsigned first_entry = start >> PAGE_SHIFT;
886 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
887 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
888 struct sg_page_iter sg_iter;
889
890 pt_vaddr = NULL;
891 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
892 if (pt_vaddr == NULL)
893 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
894
895 pt_vaddr[act_pte] =
896 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
897 cache_level, true, flags);
898
899 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
900 kunmap_atomic(pt_vaddr);
901 pt_vaddr = NULL;
902 act_pt++;
903 act_pte = 0;
904 }
905 }
906 if (pt_vaddr)
907 kunmap_atomic(pt_vaddr);
908 }
909
910 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
911 {
912 int i;
913
914 if (ppgtt->pt_dma_addr) {
915 for (i = 0; i < ppgtt->num_pd_entries; i++)
916 pci_unmap_page(ppgtt->base.dev->pdev,
917 ppgtt->pt_dma_addr[i],
918 4096, PCI_DMA_BIDIRECTIONAL);
919 }
920 }
921
922 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
923 {
924 int i;
925
926 kfree(ppgtt->pt_dma_addr);
927 for (i = 0; i < ppgtt->num_pd_entries; i++)
928 __free_page(ppgtt->pt_pages[i]);
929 kfree(ppgtt->pt_pages);
930 }
931
932 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
933 {
934 struct i915_hw_ppgtt *ppgtt =
935 container_of(vm, struct i915_hw_ppgtt, base);
936
937 drm_mm_remove_node(&ppgtt->node);
938
939 gen6_ppgtt_unmap_pages(ppgtt);
940 gen6_ppgtt_free(ppgtt);
941 }
942
943 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
944 {
945 struct drm_device *dev = ppgtt->base.dev;
946 struct drm_i915_private *dev_priv = dev->dev_private;
947 bool retried = false;
948 int ret;
949
950 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
951 * allocator works in address space sizes, so it's multiplied by page
952 * size. We allocate at the top of the GTT to avoid fragmentation.
953 */
954 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
955 alloc:
956 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
957 &ppgtt->node, GEN6_PD_SIZE,
958 GEN6_PD_ALIGN, 0,
959 0, dev_priv->gtt.base.total,
960 DRM_MM_TOPDOWN);
961 if (ret == -ENOSPC && !retried) {
962 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
963 GEN6_PD_SIZE, GEN6_PD_ALIGN,
964 I915_CACHE_NONE,
965 0, dev_priv->gtt.base.total,
966 0);
967 if (ret)
968 return ret;
969
970 retried = true;
971 goto alloc;
972 }
973
974 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
975 DRM_DEBUG("Forced to use aperture for PDEs\n");
976
977 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
978 return ret;
979 }
980
981 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
982 {
983 int i;
984
985 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
986 GFP_KERNEL);
987
988 if (!ppgtt->pt_pages)
989 return -ENOMEM;
990
991 for (i = 0; i < ppgtt->num_pd_entries; i++) {
992 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
993 if (!ppgtt->pt_pages[i]) {
994 gen6_ppgtt_free(ppgtt);
995 return -ENOMEM;
996 }
997 }
998
999 return 0;
1000 }
1001
1002 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1003 {
1004 int ret;
1005
1006 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1007 if (ret)
1008 return ret;
1009
1010 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1011 if (ret) {
1012 drm_mm_remove_node(&ppgtt->node);
1013 return ret;
1014 }
1015
1016 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1017 GFP_KERNEL);
1018 if (!ppgtt->pt_dma_addr) {
1019 drm_mm_remove_node(&ppgtt->node);
1020 gen6_ppgtt_free(ppgtt);
1021 return -ENOMEM;
1022 }
1023
1024 return 0;
1025 }
1026
1027 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1028 {
1029 struct drm_device *dev = ppgtt->base.dev;
1030 int i;
1031
1032 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1033 dma_addr_t pt_addr;
1034
1035 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1036 PCI_DMA_BIDIRECTIONAL);
1037
1038 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1039 gen6_ppgtt_unmap_pages(ppgtt);
1040 return -EIO;
1041 }
1042
1043 ppgtt->pt_dma_addr[i] = pt_addr;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1050 {
1051 struct drm_device *dev = ppgtt->base.dev;
1052 struct drm_i915_private *dev_priv = dev->dev_private;
1053 int ret;
1054
1055 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1056 if (IS_GEN6(dev)) {
1057 ppgtt->switch_mm = gen6_mm_switch;
1058 } else if (IS_HASWELL(dev)) {
1059 ppgtt->switch_mm = hsw_mm_switch;
1060 } else if (IS_GEN7(dev)) {
1061 ppgtt->switch_mm = gen7_mm_switch;
1062 } else
1063 BUG();
1064
1065 ret = gen6_ppgtt_alloc(ppgtt);
1066 if (ret)
1067 return ret;
1068
1069 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1070 if (ret) {
1071 gen6_ppgtt_free(ppgtt);
1072 return ret;
1073 }
1074
1075 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1076 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1077 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1078 ppgtt->base.start = 0;
1079 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1080 ppgtt->debug_dump = gen6_dump_ppgtt;
1081
1082 ppgtt->pd_offset =
1083 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1084
1085 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1086
1087 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1088 ppgtt->node.size >> 20,
1089 ppgtt->node.start / PAGE_SIZE);
1090
1091 gen6_write_pdes(ppgtt);
1092 DRM_DEBUG("Adding PPGTT at offset %x\n",
1093 ppgtt->pd_offset << 10);
1094
1095 return 0;
1096 }
1097
1098 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1099 {
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1101
1102 ppgtt->base.dev = dev;
1103 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1104
1105 if (INTEL_INFO(dev)->gen < 8)
1106 return gen6_ppgtt_init(ppgtt);
1107 else if (IS_GEN8(dev) || IS_GEN9(dev))
1108 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1109 else
1110 BUG();
1111 }
1112 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1113 {
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 int ret = 0;
1116
1117 ret = __hw_ppgtt_init(dev, ppgtt);
1118 if (ret == 0) {
1119 kref_init(&ppgtt->ref);
1120 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1121 ppgtt->base.total);
1122 i915_init_vm(dev_priv, &ppgtt->base);
1123 }
1124
1125 return ret;
1126 }
1127
1128 int i915_ppgtt_init_hw(struct drm_device *dev)
1129 {
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 struct intel_engine_cs *ring;
1132 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1133 int i, ret = 0;
1134
1135 /* In the case of execlists, PPGTT is enabled by the context descriptor
1136 * and the PDPs are contained within the context itself. We don't
1137 * need to do anything here. */
1138 if (i915.enable_execlists)
1139 return 0;
1140
1141 if (!USES_PPGTT(dev))
1142 return 0;
1143
1144 if (IS_GEN6(dev))
1145 gen6_ppgtt_enable(dev);
1146 else if (IS_GEN7(dev))
1147 gen7_ppgtt_enable(dev);
1148 else if (INTEL_INFO(dev)->gen >= 8)
1149 gen8_ppgtt_enable(dev);
1150 else
1151 MISSING_CASE(INTEL_INFO(dev)->gen);
1152
1153 if (ppgtt) {
1154 for_each_ring(ring, dev_priv, i) {
1155 ret = ppgtt->switch_mm(ppgtt, ring);
1156 if (ret != 0)
1157 return ret;
1158 }
1159 }
1160
1161 return ret;
1162 }
1163 struct i915_hw_ppgtt *
1164 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1165 {
1166 struct i915_hw_ppgtt *ppgtt;
1167 int ret;
1168
1169 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1170 if (!ppgtt)
1171 return ERR_PTR(-ENOMEM);
1172
1173 ret = i915_ppgtt_init(dev, ppgtt);
1174 if (ret) {
1175 kfree(ppgtt);
1176 return ERR_PTR(ret);
1177 }
1178
1179 ppgtt->file_priv = fpriv;
1180
1181 trace_i915_ppgtt_create(&ppgtt->base);
1182
1183 return ppgtt;
1184 }
1185
1186 void i915_ppgtt_release(struct kref *kref)
1187 {
1188 struct i915_hw_ppgtt *ppgtt =
1189 container_of(kref, struct i915_hw_ppgtt, ref);
1190
1191 trace_i915_ppgtt_release(&ppgtt->base);
1192
1193 /* vmas should already be unbound */
1194 WARN_ON(!list_empty(&ppgtt->base.active_list));
1195 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1196
1197 list_del(&ppgtt->base.global_link);
1198 drm_mm_takedown(&ppgtt->base.mm);
1199
1200 ppgtt->base.cleanup(&ppgtt->base);
1201 kfree(ppgtt);
1202 }
1203
1204 static void
1205 ppgtt_bind_vma(struct i915_vma *vma,
1206 enum i915_cache_level cache_level,
1207 u32 flags)
1208 {
1209 /* Currently applicable only to VLV */
1210 if (vma->obj->gt_ro)
1211 flags |= PTE_READ_ONLY;
1212
1213 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1214 cache_level, flags);
1215 }
1216
1217 static void ppgtt_unbind_vma(struct i915_vma *vma)
1218 {
1219 vma->vm->clear_range(vma->vm,
1220 vma->node.start,
1221 vma->obj->base.size,
1222 true);
1223 }
1224
1225 extern int intel_iommu_gfx_mapped;
1226 /* Certain Gen5 chipsets require require idling the GPU before
1227 * unmapping anything from the GTT when VT-d is enabled.
1228 */
1229 static inline bool needs_idle_maps(struct drm_device *dev)
1230 {
1231 #ifdef CONFIG_INTEL_IOMMU
1232 /* Query intel_iommu to see if we need the workaround. Presumably that
1233 * was loaded first.
1234 */
1235 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1236 return true;
1237 #endif
1238 return false;
1239 }
1240
1241 static bool do_idling(struct drm_i915_private *dev_priv)
1242 {
1243 bool ret = dev_priv->mm.interruptible;
1244
1245 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1246 dev_priv->mm.interruptible = false;
1247 if (i915_gpu_idle(dev_priv->dev)) {
1248 DRM_ERROR("Couldn't idle GPU\n");
1249 /* Wait a bit, in hopes it avoids the hang */
1250 udelay(10);
1251 }
1252 }
1253
1254 return ret;
1255 }
1256
1257 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1258 {
1259 if (unlikely(dev_priv->gtt.do_idle_maps))
1260 dev_priv->mm.interruptible = interruptible;
1261 }
1262
1263 void i915_check_and_clear_faults(struct drm_device *dev)
1264 {
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 struct intel_engine_cs *ring;
1267 int i;
1268
1269 if (INTEL_INFO(dev)->gen < 6)
1270 return;
1271
1272 for_each_ring(ring, dev_priv, i) {
1273 u32 fault_reg;
1274 fault_reg = I915_READ(RING_FAULT_REG(ring));
1275 if (fault_reg & RING_FAULT_VALID) {
1276 DRM_DEBUG_DRIVER("Unexpected fault\n"
1277 "\tAddr: 0x%08lx\n"
1278 "\tAddress space: %s\n"
1279 "\tSource ID: %d\n"
1280 "\tType: %d\n",
1281 fault_reg & PAGE_MASK,
1282 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1283 RING_FAULT_SRCID(fault_reg),
1284 RING_FAULT_FAULT_TYPE(fault_reg));
1285 I915_WRITE(RING_FAULT_REG(ring),
1286 fault_reg & ~RING_FAULT_VALID);
1287 }
1288 }
1289 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1290 }
1291
1292 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1293 {
1294 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1295 intel_gtt_chipset_flush();
1296 } else {
1297 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1298 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1299 }
1300 }
1301
1302 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1303 {
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305
1306 /* Don't bother messing with faults pre GEN6 as we have little
1307 * documentation supporting that it's a good idea.
1308 */
1309 if (INTEL_INFO(dev)->gen < 6)
1310 return;
1311
1312 i915_check_and_clear_faults(dev);
1313
1314 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1315 dev_priv->gtt.base.start,
1316 dev_priv->gtt.base.total,
1317 true);
1318
1319 i915_ggtt_flush(dev_priv);
1320 }
1321
1322 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1323 {
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct drm_i915_gem_object *obj;
1326 struct i915_address_space *vm;
1327
1328 i915_check_and_clear_faults(dev);
1329
1330 /* First fill our portion of the GTT with scratch pages */
1331 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1332 dev_priv->gtt.base.start,
1333 dev_priv->gtt.base.total,
1334 true);
1335
1336 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1337 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1338 &dev_priv->gtt.base);
1339 if (!vma)
1340 continue;
1341
1342 i915_gem_clflush_object(obj, obj->pin_display);
1343 /* The bind_vma code tries to be smart about tracking mappings.
1344 * Unfortunately above, we've just wiped out the mappings
1345 * without telling our object about it. So we need to fake it.
1346 *
1347 * Bind is not expected to fail since this is only called on
1348 * resume and assumption is all requirements exist already.
1349 */
1350 vma->bound &= ~GLOBAL_BIND;
1351 WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND));
1352 }
1353
1354
1355 if (INTEL_INFO(dev)->gen >= 8) {
1356 if (IS_CHERRYVIEW(dev))
1357 chv_setup_private_ppat(dev_priv);
1358 else
1359 bdw_setup_private_ppat(dev_priv);
1360
1361 return;
1362 }
1363
1364 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1365 /* TODO: Perhaps it shouldn't be gen6 specific */
1366 if (i915_is_ggtt(vm)) {
1367 if (dev_priv->mm.aliasing_ppgtt)
1368 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1369 continue;
1370 }
1371
1372 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1373 }
1374
1375 i915_ggtt_flush(dev_priv);
1376 }
1377
1378 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1379 {
1380 if (obj->has_dma_mapping)
1381 return 0;
1382
1383 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1384 obj->pages->sgl, obj->pages->nents,
1385 PCI_DMA_BIDIRECTIONAL))
1386 return -ENOSPC;
1387
1388 return 0;
1389 }
1390
1391 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1392 {
1393 #ifdef writeq
1394 writeq(pte, addr);
1395 #else
1396 iowrite32((u32)pte, addr);
1397 iowrite32(pte >> 32, addr + 4);
1398 #endif
1399 }
1400
1401 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1402 struct sg_table *st,
1403 uint64_t start,
1404 enum i915_cache_level level, u32 unused)
1405 {
1406 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1407 unsigned first_entry = start >> PAGE_SHIFT;
1408 gen8_gtt_pte_t __iomem *gtt_entries =
1409 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1410 int i = 0;
1411 struct sg_page_iter sg_iter;
1412 dma_addr_t addr = 0; /* shut up gcc */
1413
1414 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1415 addr = sg_dma_address(sg_iter.sg) +
1416 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1417 gen8_set_pte(&gtt_entries[i],
1418 gen8_pte_encode(addr, level, true));
1419 i++;
1420 }
1421
1422 /*
1423 * XXX: This serves as a posting read to make sure that the PTE has
1424 * actually been updated. There is some concern that even though
1425 * registers and PTEs are within the same BAR that they are potentially
1426 * of NUMA access patterns. Therefore, even with the way we assume
1427 * hardware should work, we must keep this posting read for paranoia.
1428 */
1429 if (i != 0)
1430 WARN_ON(readq(&gtt_entries[i-1])
1431 != gen8_pte_encode(addr, level, true));
1432
1433 /* This next bit makes the above posting read even more important. We
1434 * want to flush the TLBs only after we're certain all the PTE updates
1435 * have finished.
1436 */
1437 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1438 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1439 }
1440
1441 /*
1442 * Binds an object into the global gtt with the specified cache level. The object
1443 * will be accessible to the GPU via commands whose operands reference offsets
1444 * within the global GTT as well as accessible by the GPU through the GMADR
1445 * mapped BAR (dev_priv->mm.gtt->gtt).
1446 */
1447 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1448 struct sg_table *st,
1449 uint64_t start,
1450 enum i915_cache_level level, u32 flags)
1451 {
1452 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1453 unsigned first_entry = start >> PAGE_SHIFT;
1454 gen6_gtt_pte_t __iomem *gtt_entries =
1455 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1456 int i = 0;
1457 struct sg_page_iter sg_iter;
1458 dma_addr_t addr = 0;
1459
1460 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1461 addr = sg_page_iter_dma_address(&sg_iter);
1462 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1463 i++;
1464 }
1465
1466 /* XXX: This serves as a posting read to make sure that the PTE has
1467 * actually been updated. There is some concern that even though
1468 * registers and PTEs are within the same BAR that they are potentially
1469 * of NUMA access patterns. Therefore, even with the way we assume
1470 * hardware should work, we must keep this posting read for paranoia.
1471 */
1472 if (i != 0) {
1473 unsigned long gtt = readl(&gtt_entries[i-1]);
1474 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1475 }
1476
1477 /* This next bit makes the above posting read even more important. We
1478 * want to flush the TLBs only after we're certain all the PTE updates
1479 * have finished.
1480 */
1481 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1482 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1483 }
1484
1485 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1486 uint64_t start,
1487 uint64_t length,
1488 bool use_scratch)
1489 {
1490 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1491 unsigned first_entry = start >> PAGE_SHIFT;
1492 unsigned num_entries = length >> PAGE_SHIFT;
1493 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1494 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1495 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1496 int i;
1497
1498 if (WARN(num_entries > max_entries,
1499 "First entry = %d; Num entries = %d (max=%d)\n",
1500 first_entry, num_entries, max_entries))
1501 num_entries = max_entries;
1502
1503 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1504 I915_CACHE_LLC,
1505 use_scratch);
1506 for (i = 0; i < num_entries; i++)
1507 gen8_set_pte(&gtt_base[i], scratch_pte);
1508 readl(gtt_base);
1509 }
1510
1511 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1512 uint64_t start,
1513 uint64_t length,
1514 bool use_scratch)
1515 {
1516 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1517 unsigned first_entry = start >> PAGE_SHIFT;
1518 unsigned num_entries = length >> PAGE_SHIFT;
1519 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1520 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1521 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1522 int i;
1523
1524 if (WARN(num_entries > max_entries,
1525 "First entry = %d; Num entries = %d (max=%d)\n",
1526 first_entry, num_entries, max_entries))
1527 num_entries = max_entries;
1528
1529 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1530
1531 for (i = 0; i < num_entries; i++)
1532 iowrite32(scratch_pte, &gtt_base[i]);
1533 readl(gtt_base);
1534 }
1535
1536
1537 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1538 enum i915_cache_level cache_level,
1539 u32 unused)
1540 {
1541 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1542 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1543 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1544
1545 BUG_ON(!i915_is_ggtt(vma->vm));
1546 intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags);
1547 vma->bound = GLOBAL_BIND;
1548 }
1549
1550 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1551 uint64_t start,
1552 uint64_t length,
1553 bool unused)
1554 {
1555 unsigned first_entry = start >> PAGE_SHIFT;
1556 unsigned num_entries = length >> PAGE_SHIFT;
1557 intel_gtt_clear_range(first_entry, num_entries);
1558 }
1559
1560 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1561 {
1562 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1563 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1564
1565 BUG_ON(!i915_is_ggtt(vma->vm));
1566 vma->bound = 0;
1567 intel_gtt_clear_range(first, size);
1568 }
1569
1570 static void ggtt_bind_vma(struct i915_vma *vma,
1571 enum i915_cache_level cache_level,
1572 u32 flags)
1573 {
1574 struct drm_device *dev = vma->vm->dev;
1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576 struct drm_i915_gem_object *obj = vma->obj;
1577
1578 /* Currently applicable only to VLV */
1579 if (obj->gt_ro)
1580 flags |= PTE_READ_ONLY;
1581
1582 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1583 * or we have a global mapping already but the cacheability flags have
1584 * changed, set the global PTEs.
1585 *
1586 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1587 * instead if none of the above hold true.
1588 *
1589 * NB: A global mapping should only be needed for special regions like
1590 * "gtt mappable", SNB errata, or if specified via special execbuf
1591 * flags. At all other times, the GPU will use the aliasing PPGTT.
1592 */
1593 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1594 if (!(vma->bound & GLOBAL_BIND) ||
1595 (cache_level != obj->cache_level)) {
1596 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
1597 vma->node.start,
1598 cache_level, flags);
1599 vma->bound |= GLOBAL_BIND;
1600 }
1601 }
1602
1603 if (dev_priv->mm.aliasing_ppgtt &&
1604 (!(vma->bound & LOCAL_BIND) ||
1605 (cache_level != obj->cache_level))) {
1606 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1607 appgtt->base.insert_entries(&appgtt->base,
1608 vma->ggtt_view.pages,
1609 vma->node.start,
1610 cache_level, flags);
1611 vma->bound |= LOCAL_BIND;
1612 }
1613 }
1614
1615 static void ggtt_unbind_vma(struct i915_vma *vma)
1616 {
1617 struct drm_device *dev = vma->vm->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 struct drm_i915_gem_object *obj = vma->obj;
1620
1621 if (vma->bound & GLOBAL_BIND) {
1622 vma->vm->clear_range(vma->vm,
1623 vma->node.start,
1624 obj->base.size,
1625 true);
1626 vma->bound &= ~GLOBAL_BIND;
1627 }
1628
1629 if (vma->bound & LOCAL_BIND) {
1630 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1631 appgtt->base.clear_range(&appgtt->base,
1632 vma->node.start,
1633 obj->base.size,
1634 true);
1635 vma->bound &= ~LOCAL_BIND;
1636 }
1637 }
1638
1639 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1640 {
1641 struct drm_device *dev = obj->base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 bool interruptible;
1644
1645 interruptible = do_idling(dev_priv);
1646
1647 if (!obj->has_dma_mapping)
1648 dma_unmap_sg(&dev->pdev->dev,
1649 obj->pages->sgl, obj->pages->nents,
1650 PCI_DMA_BIDIRECTIONAL);
1651
1652 undo_idling(dev_priv, interruptible);
1653 }
1654
1655 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1656 unsigned long color,
1657 unsigned long *start,
1658 unsigned long *end)
1659 {
1660 if (node->color != color)
1661 *start += 4096;
1662
1663 if (!list_empty(&node->node_list)) {
1664 node = list_entry(node->node_list.next,
1665 struct drm_mm_node,
1666 node_list);
1667 if (node->allocated && node->color != color)
1668 *end -= 4096;
1669 }
1670 }
1671
1672 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1673 unsigned long start,
1674 unsigned long mappable_end,
1675 unsigned long end)
1676 {
1677 /* Let GEM Manage all of the aperture.
1678 *
1679 * However, leave one page at the end still bound to the scratch page.
1680 * There are a number of places where the hardware apparently prefetches
1681 * past the end of the object, and we've seen multiple hangs with the
1682 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1683 * aperture. One page should be enough to keep any prefetching inside
1684 * of the aperture.
1685 */
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1688 struct drm_mm_node *entry;
1689 struct drm_i915_gem_object *obj;
1690 unsigned long hole_start, hole_end;
1691 int ret;
1692
1693 BUG_ON(mappable_end > end);
1694
1695 /* Subtract the guard page ... */
1696 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1697 if (!HAS_LLC(dev))
1698 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1699
1700 /* Mark any preallocated objects as occupied */
1701 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1702 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1703
1704 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1705 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1706
1707 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1708 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1709 if (ret) {
1710 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1711 return ret;
1712 }
1713 vma->bound |= GLOBAL_BIND;
1714 }
1715
1716 dev_priv->gtt.base.start = start;
1717 dev_priv->gtt.base.total = end - start;
1718
1719 /* Clear any non-preallocated blocks */
1720 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1721 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1722 hole_start, hole_end);
1723 ggtt_vm->clear_range(ggtt_vm, hole_start,
1724 hole_end - hole_start, true);
1725 }
1726
1727 /* And finally clear the reserved guard page */
1728 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1729
1730 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1731 struct i915_hw_ppgtt *ppgtt;
1732
1733 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1734 if (!ppgtt)
1735 return -ENOMEM;
1736
1737 ret = __hw_ppgtt_init(dev, ppgtt);
1738 if (ret != 0)
1739 return ret;
1740
1741 dev_priv->mm.aliasing_ppgtt = ppgtt;
1742 }
1743
1744 return 0;
1745 }
1746
1747 void i915_gem_init_global_gtt(struct drm_device *dev)
1748 {
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 unsigned long gtt_size, mappable_size;
1751
1752 gtt_size = dev_priv->gtt.base.total;
1753 mappable_size = dev_priv->gtt.mappable_end;
1754
1755 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1756 }
1757
1758 void i915_global_gtt_cleanup(struct drm_device *dev)
1759 {
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 struct i915_address_space *vm = &dev_priv->gtt.base;
1762
1763 if (dev_priv->mm.aliasing_ppgtt) {
1764 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1765
1766 ppgtt->base.cleanup(&ppgtt->base);
1767 }
1768
1769 if (drm_mm_initialized(&vm->mm)) {
1770 drm_mm_takedown(&vm->mm);
1771 list_del(&vm->global_link);
1772 }
1773
1774 vm->cleanup(vm);
1775 }
1776
1777 static int setup_scratch_page(struct drm_device *dev)
1778 {
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct page *page;
1781 dma_addr_t dma_addr;
1782
1783 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1784 if (page == NULL)
1785 return -ENOMEM;
1786 set_pages_uc(page, 1);
1787
1788 #ifdef CONFIG_INTEL_IOMMU
1789 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1790 PCI_DMA_BIDIRECTIONAL);
1791 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1792 return -EINVAL;
1793 #else
1794 dma_addr = page_to_phys(page);
1795 #endif
1796 dev_priv->gtt.base.scratch.page = page;
1797 dev_priv->gtt.base.scratch.addr = dma_addr;
1798
1799 return 0;
1800 }
1801
1802 static void teardown_scratch_page(struct drm_device *dev)
1803 {
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 struct page *page = dev_priv->gtt.base.scratch.page;
1806
1807 set_pages_wb(page, 1);
1808 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1809 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1810 __free_page(page);
1811 }
1812
1813 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1814 {
1815 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1816 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1817 return snb_gmch_ctl << 20;
1818 }
1819
1820 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1821 {
1822 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1823 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1824 if (bdw_gmch_ctl)
1825 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1826
1827 #ifdef CONFIG_X86_32
1828 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1829 if (bdw_gmch_ctl > 4)
1830 bdw_gmch_ctl = 4;
1831 #endif
1832
1833 return bdw_gmch_ctl << 20;
1834 }
1835
1836 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1837 {
1838 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1839 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1840
1841 if (gmch_ctrl)
1842 return 1 << (20 + gmch_ctrl);
1843
1844 return 0;
1845 }
1846
1847 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1848 {
1849 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1850 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1851 return snb_gmch_ctl << 25; /* 32 MB units */
1852 }
1853
1854 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1855 {
1856 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1857 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1858 return bdw_gmch_ctl << 25; /* 32 MB units */
1859 }
1860
1861 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1862 {
1863 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1864 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1865
1866 /*
1867 * 0x0 to 0x10: 32MB increments starting at 0MB
1868 * 0x11 to 0x16: 4MB increments starting at 8MB
1869 * 0x17 to 0x1d: 4MB increments start at 36MB
1870 */
1871 if (gmch_ctrl < 0x11)
1872 return gmch_ctrl << 25;
1873 else if (gmch_ctrl < 0x17)
1874 return (gmch_ctrl - 0x11 + 2) << 22;
1875 else
1876 return (gmch_ctrl - 0x17 + 9) << 22;
1877 }
1878
1879 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
1880 {
1881 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1882 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
1883
1884 if (gen9_gmch_ctl < 0xf0)
1885 return gen9_gmch_ctl << 25; /* 32 MB units */
1886 else
1887 /* 4MB increments starting at 0xf0 for 4MB */
1888 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
1889 }
1890
1891 static int ggtt_probe_common(struct drm_device *dev,
1892 size_t gtt_size)
1893 {
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 phys_addr_t gtt_phys_addr;
1896 int ret;
1897
1898 /* For Modern GENs the PTEs and register space are split in the BAR */
1899 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1900 (pci_resource_len(dev->pdev, 0) / 2);
1901
1902 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1903 if (!dev_priv->gtt.gsm) {
1904 DRM_ERROR("Failed to map the gtt page table\n");
1905 return -ENOMEM;
1906 }
1907
1908 ret = setup_scratch_page(dev);
1909 if (ret) {
1910 DRM_ERROR("Scratch setup failed\n");
1911 /* iounmap will also get called at remove, but meh */
1912 iounmap(dev_priv->gtt.gsm);
1913 }
1914
1915 return ret;
1916 }
1917
1918 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1919 * bits. When using advanced contexts each context stores its own PAT, but
1920 * writing this data shouldn't be harmful even in those cases. */
1921 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1922 {
1923 uint64_t pat;
1924
1925 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1926 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1927 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1928 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1929 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1930 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1931 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1932 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1933
1934 if (!USES_PPGTT(dev_priv->dev))
1935 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
1936 * so RTL will always use the value corresponding to
1937 * pat_sel = 000".
1938 * So let's disable cache for GGTT to avoid screen corruptions.
1939 * MOCS still can be used though.
1940 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
1941 * before this patch, i.e. the same uncached + snooping access
1942 * like on gen6/7 seems to be in effect.
1943 * - So this just fixes blitter/render access. Again it looks
1944 * like it's not just uncached access, but uncached + snooping.
1945 * So we can still hold onto all our assumptions wrt cpu
1946 * clflushing on LLC machines.
1947 */
1948 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
1949
1950 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1951 * write would work. */
1952 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1953 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1954 }
1955
1956 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1957 {
1958 uint64_t pat;
1959
1960 /*
1961 * Map WB on BDW to snooped on CHV.
1962 *
1963 * Only the snoop bit has meaning for CHV, the rest is
1964 * ignored.
1965 *
1966 * The hardware will never snoop for certain types of accesses:
1967 * - CPU GTT (GMADR->GGTT->no snoop->memory)
1968 * - PPGTT page tables
1969 * - some other special cycles
1970 *
1971 * As with BDW, we also need to consider the following for GT accesses:
1972 * "For GGTT, there is NO pat_sel[2:0] from the entry,
1973 * so RTL will always use the value corresponding to
1974 * pat_sel = 000".
1975 * Which means we must set the snoop bit in PAT entry 0
1976 * in order to keep the global status page working.
1977 */
1978 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1979 GEN8_PPAT(1, 0) |
1980 GEN8_PPAT(2, 0) |
1981 GEN8_PPAT(3, 0) |
1982 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1983 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1984 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1985 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1986
1987 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1988 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1989 }
1990
1991 static int gen8_gmch_probe(struct drm_device *dev,
1992 size_t *gtt_total,
1993 size_t *stolen,
1994 phys_addr_t *mappable_base,
1995 unsigned long *mappable_end)
1996 {
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 unsigned int gtt_size;
1999 u16 snb_gmch_ctl;
2000 int ret;
2001
2002 /* TODO: We're not aware of mappable constraints on gen8 yet */
2003 *mappable_base = pci_resource_start(dev->pdev, 2);
2004 *mappable_end = pci_resource_len(dev->pdev, 2);
2005
2006 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2007 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2008
2009 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2010
2011 if (INTEL_INFO(dev)->gen >= 9) {
2012 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2013 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2014 } else if (IS_CHERRYVIEW(dev)) {
2015 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2016 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2017 } else {
2018 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2019 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2020 }
2021
2022 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
2023
2024 if (IS_CHERRYVIEW(dev))
2025 chv_setup_private_ppat(dev_priv);
2026 else
2027 bdw_setup_private_ppat(dev_priv);
2028
2029 ret = ggtt_probe_common(dev, gtt_size);
2030
2031 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2032 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2033
2034 return ret;
2035 }
2036
2037 static int gen6_gmch_probe(struct drm_device *dev,
2038 size_t *gtt_total,
2039 size_t *stolen,
2040 phys_addr_t *mappable_base,
2041 unsigned long *mappable_end)
2042 {
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 unsigned int gtt_size;
2045 u16 snb_gmch_ctl;
2046 int ret;
2047
2048 *mappable_base = pci_resource_start(dev->pdev, 2);
2049 *mappable_end = pci_resource_len(dev->pdev, 2);
2050
2051 /* 64/512MB is the current min/max we actually know of, but this is just
2052 * a coarse sanity check.
2053 */
2054 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2055 DRM_ERROR("Unknown GMADR size (%lx)\n",
2056 dev_priv->gtt.mappable_end);
2057 return -ENXIO;
2058 }
2059
2060 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2061 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2062 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2063
2064 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2065
2066 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2067 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2068
2069 ret = ggtt_probe_common(dev, gtt_size);
2070
2071 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2072 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2073
2074 return ret;
2075 }
2076
2077 static void gen6_gmch_remove(struct i915_address_space *vm)
2078 {
2079
2080 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2081
2082 iounmap(gtt->gsm);
2083 teardown_scratch_page(vm->dev);
2084 }
2085
2086 static int i915_gmch_probe(struct drm_device *dev,
2087 size_t *gtt_total,
2088 size_t *stolen,
2089 phys_addr_t *mappable_base,
2090 unsigned long *mappable_end)
2091 {
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 int ret;
2094
2095 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2096 if (!ret) {
2097 DRM_ERROR("failed to set up gmch\n");
2098 return -EIO;
2099 }
2100
2101 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2102
2103 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2104 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2105
2106 if (unlikely(dev_priv->gtt.do_idle_maps))
2107 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2108
2109 return 0;
2110 }
2111
2112 static void i915_gmch_remove(struct i915_address_space *vm)
2113 {
2114 intel_gmch_remove();
2115 }
2116
2117 int i915_gem_gtt_init(struct drm_device *dev)
2118 {
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct i915_gtt *gtt = &dev_priv->gtt;
2121 int ret;
2122
2123 if (INTEL_INFO(dev)->gen <= 5) {
2124 gtt->gtt_probe = i915_gmch_probe;
2125 gtt->base.cleanup = i915_gmch_remove;
2126 } else if (INTEL_INFO(dev)->gen < 8) {
2127 gtt->gtt_probe = gen6_gmch_probe;
2128 gtt->base.cleanup = gen6_gmch_remove;
2129 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2130 gtt->base.pte_encode = iris_pte_encode;
2131 else if (IS_HASWELL(dev))
2132 gtt->base.pte_encode = hsw_pte_encode;
2133 else if (IS_VALLEYVIEW(dev))
2134 gtt->base.pte_encode = byt_pte_encode;
2135 else if (INTEL_INFO(dev)->gen >= 7)
2136 gtt->base.pte_encode = ivb_pte_encode;
2137 else
2138 gtt->base.pte_encode = snb_pte_encode;
2139 } else {
2140 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2141 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2142 }
2143
2144 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2145 &gtt->mappable_base, &gtt->mappable_end);
2146 if (ret)
2147 return ret;
2148
2149 gtt->base.dev = dev;
2150
2151 /* GMADR is the PCI mmio aperture into the global GTT. */
2152 DRM_INFO("Memory usable by graphics device = %zdM\n",
2153 gtt->base.total >> 20);
2154 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2155 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2156 #ifdef CONFIG_INTEL_IOMMU
2157 if (intel_iommu_gfx_mapped)
2158 DRM_INFO("VT-d active for gfx access\n");
2159 #endif
2160 /*
2161 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2162 * user's requested state against the hardware/driver capabilities. We
2163 * do this now so that we can print out any log messages once rather
2164 * than every time we check intel_enable_ppgtt().
2165 */
2166 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2167 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2168
2169 return 0;
2170 }
2171
2172 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2173 struct i915_address_space *vm,
2174 const struct i915_ggtt_view *view)
2175 {
2176 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2177 if (vma == NULL)
2178 return ERR_PTR(-ENOMEM);
2179
2180 INIT_LIST_HEAD(&vma->vma_link);
2181 INIT_LIST_HEAD(&vma->mm_list);
2182 INIT_LIST_HEAD(&vma->exec_list);
2183 vma->vm = vm;
2184 vma->obj = obj;
2185 vma->ggtt_view = *view;
2186
2187 switch (INTEL_INFO(vm->dev)->gen) {
2188 case 9:
2189 case 8:
2190 case 7:
2191 case 6:
2192 if (i915_is_ggtt(vm)) {
2193 vma->unbind_vma = ggtt_unbind_vma;
2194 vma->bind_vma = ggtt_bind_vma;
2195 } else {
2196 vma->unbind_vma = ppgtt_unbind_vma;
2197 vma->bind_vma = ppgtt_bind_vma;
2198 }
2199 break;
2200 case 5:
2201 case 4:
2202 case 3:
2203 case 2:
2204 BUG_ON(!i915_is_ggtt(vm));
2205 vma->unbind_vma = i915_ggtt_unbind_vma;
2206 vma->bind_vma = i915_ggtt_bind_vma;
2207 break;
2208 default:
2209 BUG();
2210 }
2211
2212 list_add_tail(&vma->vma_link, &obj->vma_list);
2213 if (!i915_is_ggtt(vm))
2214 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2215
2216 return vma;
2217 }
2218
2219 struct i915_vma *
2220 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2221 struct i915_address_space *vm,
2222 const struct i915_ggtt_view *view)
2223 {
2224 struct i915_vma *vma;
2225
2226 vma = i915_gem_obj_to_vma_view(obj, vm, view);
2227 if (!vma)
2228 vma = __i915_gem_vma_create(obj, vm, view);
2229
2230 return vma;
2231 }
2232
2233 static inline
2234 int i915_get_vma_pages(struct i915_vma *vma)
2235 {
2236 if (vma->ggtt_view.pages)
2237 return 0;
2238
2239 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2240 vma->ggtt_view.pages = vma->obj->pages;
2241 else
2242 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2243 vma->ggtt_view.type);
2244
2245 if (!vma->ggtt_view.pages) {
2246 DRM_ERROR("Failed to get pages for VMA view type %u!\n",
2247 vma->ggtt_view.type);
2248 return -EINVAL;
2249 }
2250
2251 return 0;
2252 }
2253
2254 /**
2255 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2256 * @vma: VMA to map
2257 * @cache_level: mapping cache level
2258 * @flags: flags like global or local mapping
2259 *
2260 * DMA addresses are taken from the scatter-gather table of this object (or of
2261 * this VMA in case of non-default GGTT views) and PTE entries set up.
2262 * Note that DMA addresses are also the only part of the SG table we care about.
2263 */
2264 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2265 u32 flags)
2266 {
2267 int ret = i915_get_vma_pages(vma);
2268
2269 if (ret)
2270 return ret;
2271
2272 vma->bind_vma(vma, cache_level, flags);
2273
2274 return 0;
2275 }
Linux kernel - Deliverables
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