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a4153eef48c20c02f444e53b4de144e5414987fc
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
35
36 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
37 {
38 if (i915.enable_ppgtt == 0)
39 return false;
40
41 if (i915.enable_ppgtt == 1 && full)
42 return false;
43
44 return true;
45 }
46
47 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
48 {
49 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
50 return 0;
51
52 if (enable_ppgtt == 1)
53 return 1;
54
55 if (enable_ppgtt == 2 && HAS_PPGTT(dev))
56 return 2;
57
58 #ifdef CONFIG_INTEL_IOMMU
59 /* Disable ppgtt on SNB if VT-d is on. */
60 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
61 DRM_INFO("Disabling PPGTT because VT-d is on\n");
62 return 0;
63 }
64 #endif
65
66 /* Early VLV doesn't have this */
67 if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
68 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
69 return 0;
70 }
71
72 return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
73 }
74
75
76 static void ppgtt_bind_vma(struct i915_vma *vma,
77 enum i915_cache_level cache_level,
78 u32 flags);
79 static void ppgtt_unbind_vma(struct i915_vma *vma);
80 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
81
82 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
83 enum i915_cache_level level,
84 bool valid)
85 {
86 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
87 pte |= addr;
88
89 switch (level) {
90 case I915_CACHE_NONE:
91 pte |= PPAT_UNCACHED_INDEX;
92 break;
93 case I915_CACHE_WT:
94 pte |= PPAT_DISPLAY_ELLC_INDEX;
95 break;
96 default:
97 pte |= PPAT_CACHED_INDEX;
98 break;
99 }
100
101 return pte;
102 }
103
104 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
105 dma_addr_t addr,
106 enum i915_cache_level level)
107 {
108 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
109 pde |= addr;
110 if (level != I915_CACHE_NONE)
111 pde |= PPAT_CACHED_PDE_INDEX;
112 else
113 pde |= PPAT_UNCACHED_INDEX;
114 return pde;
115 }
116
117 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
118 enum i915_cache_level level,
119 bool valid, u32 unused)
120 {
121 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
122 pte |= GEN6_PTE_ADDR_ENCODE(addr);
123
124 switch (level) {
125 case I915_CACHE_L3_LLC:
126 case I915_CACHE_LLC:
127 pte |= GEN6_PTE_CACHE_LLC;
128 break;
129 case I915_CACHE_NONE:
130 pte |= GEN6_PTE_UNCACHED;
131 break;
132 default:
133 WARN_ON(1);
134 }
135
136 return pte;
137 }
138
139 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
140 enum i915_cache_level level,
141 bool valid, u32 unused)
142 {
143 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
144 pte |= GEN6_PTE_ADDR_ENCODE(addr);
145
146 switch (level) {
147 case I915_CACHE_L3_LLC:
148 pte |= GEN7_PTE_CACHE_L3_LLC;
149 break;
150 case I915_CACHE_LLC:
151 pte |= GEN6_PTE_CACHE_LLC;
152 break;
153 case I915_CACHE_NONE:
154 pte |= GEN6_PTE_UNCACHED;
155 break;
156 default:
157 WARN_ON(1);
158 }
159
160 return pte;
161 }
162
163 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
164 enum i915_cache_level level,
165 bool valid, u32 flags)
166 {
167 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
168 pte |= GEN6_PTE_ADDR_ENCODE(addr);
169
170 /* Mark the page as writeable. Other platforms don't have a
171 * setting for read-only/writable, so this matches that behavior.
172 */
173 if (!(flags & PTE_READ_ONLY))
174 pte |= BYT_PTE_WRITEABLE;
175
176 if (level != I915_CACHE_NONE)
177 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
178
179 return pte;
180 }
181
182 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
183 enum i915_cache_level level,
184 bool valid, u32 unused)
185 {
186 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
187 pte |= HSW_PTE_ADDR_ENCODE(addr);
188
189 if (level != I915_CACHE_NONE)
190 pte |= HSW_WB_LLC_AGE3;
191
192 return pte;
193 }
194
195 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
196 enum i915_cache_level level,
197 bool valid, u32 unused)
198 {
199 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
200 pte |= HSW_PTE_ADDR_ENCODE(addr);
201
202 switch (level) {
203 case I915_CACHE_NONE:
204 break;
205 case I915_CACHE_WT:
206 pte |= HSW_WT_ELLC_LLC_AGE3;
207 break;
208 default:
209 pte |= HSW_WB_ELLC_LLC_AGE3;
210 break;
211 }
212
213 return pte;
214 }
215
216 /* Broadwell Page Directory Pointer Descriptors */
217 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
218 uint64_t val, bool synchronous)
219 {
220 struct drm_i915_private *dev_priv = ring->dev->dev_private;
221 int ret;
222
223 BUG_ON(entry >= 4);
224
225 if (synchronous) {
226 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
227 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
228 return 0;
229 }
230
231 ret = intel_ring_begin(ring, 6);
232 if (ret)
233 return ret;
234
235 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
236 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
237 intel_ring_emit(ring, (u32)(val >> 32));
238 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
239 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
240 intel_ring_emit(ring, (u32)(val));
241 intel_ring_advance(ring);
242
243 return 0;
244 }
245
246 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
247 struct intel_engine_cs *ring,
248 bool synchronous)
249 {
250 int i, ret;
251
252 /* bit of a hack to find the actual last used pd */
253 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
254
255 for (i = used_pd - 1; i >= 0; i--) {
256 dma_addr_t addr = ppgtt->pd_dma_addr[i];
257 ret = gen8_write_pdp(ring, i, addr, synchronous);
258 if (ret)
259 return ret;
260 }
261
262 return 0;
263 }
264
265 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
266 uint64_t start,
267 uint64_t length,
268 bool use_scratch)
269 {
270 struct i915_hw_ppgtt *ppgtt =
271 container_of(vm, struct i915_hw_ppgtt, base);
272 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
273 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
274 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
275 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
276 unsigned num_entries = length >> PAGE_SHIFT;
277 unsigned last_pte, i;
278
279 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
280 I915_CACHE_LLC, use_scratch);
281
282 while (num_entries) {
283 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
284
285 last_pte = pte + num_entries;
286 if (last_pte > GEN8_PTES_PER_PAGE)
287 last_pte = GEN8_PTES_PER_PAGE;
288
289 pt_vaddr = kmap_atomic(page_table);
290
291 for (i = pte; i < last_pte; i++) {
292 pt_vaddr[i] = scratch_pte;
293 num_entries--;
294 }
295
296 if (!HAS_LLC(ppgtt->base.dev))
297 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
298 kunmap_atomic(pt_vaddr);
299
300 pte = 0;
301 if (++pde == GEN8_PDES_PER_PAGE) {
302 pdpe++;
303 pde = 0;
304 }
305 }
306 }
307
308 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
309 struct sg_table *pages,
310 uint64_t start,
311 enum i915_cache_level cache_level, u32 unused)
312 {
313 struct i915_hw_ppgtt *ppgtt =
314 container_of(vm, struct i915_hw_ppgtt, base);
315 gen8_gtt_pte_t *pt_vaddr;
316 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
317 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
318 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
319 struct sg_page_iter sg_iter;
320
321 pt_vaddr = NULL;
322
323 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
324 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
325 break;
326
327 if (pt_vaddr == NULL)
328 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
329
330 pt_vaddr[pte] =
331 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
332 cache_level, true);
333 if (++pte == GEN8_PTES_PER_PAGE) {
334 if (!HAS_LLC(ppgtt->base.dev))
335 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
336 kunmap_atomic(pt_vaddr);
337 pt_vaddr = NULL;
338 if (++pde == GEN8_PDES_PER_PAGE) {
339 pdpe++;
340 pde = 0;
341 }
342 pte = 0;
343 }
344 }
345 if (pt_vaddr) {
346 if (!HAS_LLC(ppgtt->base.dev))
347 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
348 kunmap_atomic(pt_vaddr);
349 }
350 }
351
352 static void gen8_free_page_tables(struct page **pt_pages)
353 {
354 int i;
355
356 if (pt_pages == NULL)
357 return;
358
359 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
360 if (pt_pages[i])
361 __free_pages(pt_pages[i], 0);
362 }
363
364 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
365 {
366 int i;
367
368 for (i = 0; i < ppgtt->num_pd_pages; i++) {
369 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
370 kfree(ppgtt->gen8_pt_pages[i]);
371 kfree(ppgtt->gen8_pt_dma_addr[i]);
372 }
373
374 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
375 }
376
377 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
378 {
379 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
380 int i, j;
381
382 for (i = 0; i < ppgtt->num_pd_pages; i++) {
383 /* TODO: In the future we'll support sparse mappings, so this
384 * will have to change. */
385 if (!ppgtt->pd_dma_addr[i])
386 continue;
387
388 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
389 PCI_DMA_BIDIRECTIONAL);
390
391 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
392 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
393 if (addr)
394 pci_unmap_page(hwdev, addr, PAGE_SIZE,
395 PCI_DMA_BIDIRECTIONAL);
396 }
397 }
398 }
399
400 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
401 {
402 struct i915_hw_ppgtt *ppgtt =
403 container_of(vm, struct i915_hw_ppgtt, base);
404
405 list_del(&vm->global_link);
406 drm_mm_takedown(&vm->mm);
407
408 gen8_ppgtt_unmap_pages(ppgtt);
409 gen8_ppgtt_free(ppgtt);
410 }
411
412 static struct page **__gen8_alloc_page_tables(void)
413 {
414 struct page **pt_pages;
415 int i;
416
417 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
418 if (!pt_pages)
419 return ERR_PTR(-ENOMEM);
420
421 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
422 pt_pages[i] = alloc_page(GFP_KERNEL);
423 if (!pt_pages[i])
424 goto bail;
425 }
426
427 return pt_pages;
428
429 bail:
430 gen8_free_page_tables(pt_pages);
431 kfree(pt_pages);
432 return ERR_PTR(-ENOMEM);
433 }
434
435 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
436 const int max_pdp)
437 {
438 struct page **pt_pages[GEN8_LEGACY_PDPS];
439 int i, ret;
440
441 for (i = 0; i < max_pdp; i++) {
442 pt_pages[i] = __gen8_alloc_page_tables();
443 if (IS_ERR(pt_pages[i])) {
444 ret = PTR_ERR(pt_pages[i]);
445 goto unwind_out;
446 }
447 }
448
449 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
450 * "atomic" - for cleanup purposes.
451 */
452 for (i = 0; i < max_pdp; i++)
453 ppgtt->gen8_pt_pages[i] = pt_pages[i];
454
455 return 0;
456
457 unwind_out:
458 while (i--) {
459 gen8_free_page_tables(pt_pages[i]);
460 kfree(pt_pages[i]);
461 }
462
463 return ret;
464 }
465
466 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
467 {
468 int i;
469
470 for (i = 0; i < ppgtt->num_pd_pages; i++) {
471 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
472 sizeof(dma_addr_t),
473 GFP_KERNEL);
474 if (!ppgtt->gen8_pt_dma_addr[i])
475 return -ENOMEM;
476 }
477
478 return 0;
479 }
480
481 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
482 const int max_pdp)
483 {
484 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
485 if (!ppgtt->pd_pages)
486 return -ENOMEM;
487
488 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
489 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
490
491 return 0;
492 }
493
494 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
495 const int max_pdp)
496 {
497 int ret;
498
499 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
500 if (ret)
501 return ret;
502
503 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
504 if (ret) {
505 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
506 return ret;
507 }
508
509 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
510
511 ret = gen8_ppgtt_allocate_dma(ppgtt);
512 if (ret)
513 gen8_ppgtt_free(ppgtt);
514
515 return ret;
516 }
517
518 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
519 const int pd)
520 {
521 dma_addr_t pd_addr;
522 int ret;
523
524 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
525 &ppgtt->pd_pages[pd], 0,
526 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
527
528 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
529 if (ret)
530 return ret;
531
532 ppgtt->pd_dma_addr[pd] = pd_addr;
533
534 return 0;
535 }
536
537 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
538 const int pd,
539 const int pt)
540 {
541 dma_addr_t pt_addr;
542 struct page *p;
543 int ret;
544
545 p = ppgtt->gen8_pt_pages[pd][pt];
546 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
547 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
548 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
549 if (ret)
550 return ret;
551
552 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
553
554 return 0;
555 }
556
557 /**
558 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
559 * with a net effect resembling a 2-level page table in normal x86 terms. Each
560 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
561 * space.
562 *
563 * FIXME: split allocation into smaller pieces. For now we only ever do this
564 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
565 * TODO: Do something with the size parameter
566 */
567 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
568 {
569 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
570 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
571 int i, j, ret;
572
573 if (size % (1<<30))
574 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
575
576 /* 1. Do all our allocations for page directories and page tables. */
577 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
578 if (ret)
579 return ret;
580
581 /*
582 * 2. Create DMA mappings for the page directories and page tables.
583 */
584 for (i = 0; i < max_pdp; i++) {
585 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
586 if (ret)
587 goto bail;
588
589 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
590 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
591 if (ret)
592 goto bail;
593 }
594 }
595
596 /*
597 * 3. Map all the page directory entires to point to the page tables
598 * we've allocated.
599 *
600 * For now, the PPGTT helper functions all require that the PDEs are
601 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
602 * will never need to touch the PDEs again.
603 */
604 for (i = 0; i < max_pdp; i++) {
605 gen8_ppgtt_pde_t *pd_vaddr;
606 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
607 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
608 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
609 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
610 I915_CACHE_LLC);
611 }
612 if (!HAS_LLC(ppgtt->base.dev))
613 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
614 kunmap_atomic(pd_vaddr);
615 }
616
617 ppgtt->enable = gen8_ppgtt_enable;
618 ppgtt->switch_mm = gen8_mm_switch;
619 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
620 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
621 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
622 ppgtt->base.start = 0;
623 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
624
625 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
626
627 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
628 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
629 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
630 ppgtt->num_pd_entries,
631 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
632 return 0;
633
634 bail:
635 gen8_ppgtt_unmap_pages(ppgtt);
636 gen8_ppgtt_free(ppgtt);
637 return ret;
638 }
639
640 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
641 {
642 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
643 struct i915_address_space *vm = &ppgtt->base;
644 gen6_gtt_pte_t __iomem *pd_addr;
645 gen6_gtt_pte_t scratch_pte;
646 uint32_t pd_entry;
647 int pte, pde;
648
649 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
650
651 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
652 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
653
654 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
655 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
656 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
657 u32 expected;
658 gen6_gtt_pte_t *pt_vaddr;
659 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
660 pd_entry = readl(pd_addr + pde);
661 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
662
663 if (pd_entry != expected)
664 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
665 pde,
666 pd_entry,
667 expected);
668 seq_printf(m, "\tPDE: %x\n", pd_entry);
669
670 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
671 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
672 unsigned long va =
673 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
674 (pte * PAGE_SIZE);
675 int i;
676 bool found = false;
677 for (i = 0; i < 4; i++)
678 if (pt_vaddr[pte + i] != scratch_pte)
679 found = true;
680 if (!found)
681 continue;
682
683 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
684 for (i = 0; i < 4; i++) {
685 if (pt_vaddr[pte + i] != scratch_pte)
686 seq_printf(m, " %08x", pt_vaddr[pte + i]);
687 else
688 seq_puts(m, " SCRATCH ");
689 }
690 seq_puts(m, "\n");
691 }
692 kunmap_atomic(pt_vaddr);
693 }
694 }
695
696 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
697 {
698 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
699 gen6_gtt_pte_t __iomem *pd_addr;
700 uint32_t pd_entry;
701 int i;
702
703 WARN_ON(ppgtt->pd_offset & 0x3f);
704 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
705 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
706 for (i = 0; i < ppgtt->num_pd_entries; i++) {
707 dma_addr_t pt_addr;
708
709 pt_addr = ppgtt->pt_dma_addr[i];
710 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
711 pd_entry |= GEN6_PDE_VALID;
712
713 writel(pd_entry, pd_addr + i);
714 }
715 readl(pd_addr);
716 }
717
718 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
719 {
720 BUG_ON(ppgtt->pd_offset & 0x3f);
721
722 return (ppgtt->pd_offset / 64) << 16;
723 }
724
725 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
726 struct intel_engine_cs *ring,
727 bool synchronous)
728 {
729 struct drm_device *dev = ppgtt->base.dev;
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 int ret;
732
733 /* If we're in reset, we can assume the GPU is sufficiently idle to
734 * manually frob these bits. Ideally we could use the ring functions,
735 * except our error handling makes it quite difficult (can't use
736 * intel_ring_begin, ring->flush, or intel_ring_advance)
737 *
738 * FIXME: We should try not to special case reset
739 */
740 if (synchronous ||
741 i915_reset_in_progress(&dev_priv->gpu_error)) {
742 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
743 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
744 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
745 POSTING_READ(RING_PP_DIR_BASE(ring));
746 return 0;
747 }
748
749 /* NB: TLBs must be flushed and invalidated before a switch */
750 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
751 if (ret)
752 return ret;
753
754 ret = intel_ring_begin(ring, 6);
755 if (ret)
756 return ret;
757
758 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
759 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
760 intel_ring_emit(ring, PP_DIR_DCLV_2G);
761 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
762 intel_ring_emit(ring, get_pd_offset(ppgtt));
763 intel_ring_emit(ring, MI_NOOP);
764 intel_ring_advance(ring);
765
766 return 0;
767 }
768
769 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
770 struct intel_engine_cs *ring,
771 bool synchronous)
772 {
773 struct drm_device *dev = ppgtt->base.dev;
774 struct drm_i915_private *dev_priv = dev->dev_private;
775 int ret;
776
777 /* If we're in reset, we can assume the GPU is sufficiently idle to
778 * manually frob these bits. Ideally we could use the ring functions,
779 * except our error handling makes it quite difficult (can't use
780 * intel_ring_begin, ring->flush, or intel_ring_advance)
781 *
782 * FIXME: We should try not to special case reset
783 */
784 if (synchronous ||
785 i915_reset_in_progress(&dev_priv->gpu_error)) {
786 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
787 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
788 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
789 POSTING_READ(RING_PP_DIR_BASE(ring));
790 return 0;
791 }
792
793 /* NB: TLBs must be flushed and invalidated before a switch */
794 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
795 if (ret)
796 return ret;
797
798 ret = intel_ring_begin(ring, 6);
799 if (ret)
800 return ret;
801
802 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
803 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
804 intel_ring_emit(ring, PP_DIR_DCLV_2G);
805 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
806 intel_ring_emit(ring, get_pd_offset(ppgtt));
807 intel_ring_emit(ring, MI_NOOP);
808 intel_ring_advance(ring);
809
810 /* XXX: RCS is the only one to auto invalidate the TLBs? */
811 if (ring->id != RCS) {
812 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
813 if (ret)
814 return ret;
815 }
816
817 return 0;
818 }
819
820 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
821 struct intel_engine_cs *ring,
822 bool synchronous)
823 {
824 struct drm_device *dev = ppgtt->base.dev;
825 struct drm_i915_private *dev_priv = dev->dev_private;
826
827 if (!synchronous)
828 return 0;
829
830 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
831 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
832
833 POSTING_READ(RING_PP_DIR_DCLV(ring));
834
835 return 0;
836 }
837
838 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
839 {
840 struct drm_device *dev = ppgtt->base.dev;
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 struct intel_engine_cs *ring;
843 int j, ret;
844
845 for_each_ring(ring, dev_priv, j) {
846 I915_WRITE(RING_MODE_GEN7(ring),
847 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
848
849 /* We promise to do a switch later with FULL PPGTT. If this is
850 * aliasing, this is the one and only switch we'll do */
851 if (USES_FULL_PPGTT(dev))
852 continue;
853
854 ret = ppgtt->switch_mm(ppgtt, ring, true);
855 if (ret)
856 goto err_out;
857 }
858
859 return 0;
860
861 err_out:
862 for_each_ring(ring, dev_priv, j)
863 I915_WRITE(RING_MODE_GEN7(ring),
864 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
865 return ret;
866 }
867
868 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
869 {
870 struct drm_device *dev = ppgtt->base.dev;
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 struct intel_engine_cs *ring;
873 uint32_t ecochk, ecobits;
874 int i;
875
876 ecobits = I915_READ(GAC_ECO_BITS);
877 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
878
879 ecochk = I915_READ(GAM_ECOCHK);
880 if (IS_HASWELL(dev)) {
881 ecochk |= ECOCHK_PPGTT_WB_HSW;
882 } else {
883 ecochk |= ECOCHK_PPGTT_LLC_IVB;
884 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
885 }
886 I915_WRITE(GAM_ECOCHK, ecochk);
887
888 for_each_ring(ring, dev_priv, i) {
889 int ret;
890 /* GFX_MODE is per-ring on gen7+ */
891 I915_WRITE(RING_MODE_GEN7(ring),
892 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
893
894 /* We promise to do a switch later with FULL PPGTT. If this is
895 * aliasing, this is the one and only switch we'll do */
896 if (USES_FULL_PPGTT(dev))
897 continue;
898
899 ret = ppgtt->switch_mm(ppgtt, ring, true);
900 if (ret)
901 return ret;
902 }
903
904 return 0;
905 }
906
907 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
908 {
909 struct drm_device *dev = ppgtt->base.dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
911 struct intel_engine_cs *ring;
912 uint32_t ecochk, gab_ctl, ecobits;
913 int i;
914
915 ecobits = I915_READ(GAC_ECO_BITS);
916 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
917 ECOBITS_PPGTT_CACHE64B);
918
919 gab_ctl = I915_READ(GAB_CTL);
920 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
921
922 ecochk = I915_READ(GAM_ECOCHK);
923 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
924
925 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
926
927 for_each_ring(ring, dev_priv, i) {
928 int ret = ppgtt->switch_mm(ppgtt, ring, true);
929 if (ret)
930 return ret;
931 }
932
933 return 0;
934 }
935
936 /* PPGTT support for Sandybdrige/Gen6 and later */
937 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
938 uint64_t start,
939 uint64_t length,
940 bool use_scratch)
941 {
942 struct i915_hw_ppgtt *ppgtt =
943 container_of(vm, struct i915_hw_ppgtt, base);
944 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
945 unsigned first_entry = start >> PAGE_SHIFT;
946 unsigned num_entries = length >> PAGE_SHIFT;
947 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
948 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
949 unsigned last_pte, i;
950
951 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
952
953 while (num_entries) {
954 last_pte = first_pte + num_entries;
955 if (last_pte > I915_PPGTT_PT_ENTRIES)
956 last_pte = I915_PPGTT_PT_ENTRIES;
957
958 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
959
960 for (i = first_pte; i < last_pte; i++)
961 pt_vaddr[i] = scratch_pte;
962
963 kunmap_atomic(pt_vaddr);
964
965 num_entries -= last_pte - first_pte;
966 first_pte = 0;
967 act_pt++;
968 }
969 }
970
971 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
972 struct sg_table *pages,
973 uint64_t start,
974 enum i915_cache_level cache_level, u32 flags)
975 {
976 struct i915_hw_ppgtt *ppgtt =
977 container_of(vm, struct i915_hw_ppgtt, base);
978 gen6_gtt_pte_t *pt_vaddr;
979 unsigned first_entry = start >> PAGE_SHIFT;
980 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
981 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
982 struct sg_page_iter sg_iter;
983
984 pt_vaddr = NULL;
985 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
986 if (pt_vaddr == NULL)
987 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
988
989 pt_vaddr[act_pte] =
990 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
991 cache_level, true, flags);
992
993 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
994 kunmap_atomic(pt_vaddr);
995 pt_vaddr = NULL;
996 act_pt++;
997 act_pte = 0;
998 }
999 }
1000 if (pt_vaddr)
1001 kunmap_atomic(pt_vaddr);
1002 }
1003
1004 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
1005 {
1006 int i;
1007
1008 if (ppgtt->pt_dma_addr) {
1009 for (i = 0; i < ppgtt->num_pd_entries; i++)
1010 pci_unmap_page(ppgtt->base.dev->pdev,
1011 ppgtt->pt_dma_addr[i],
1012 4096, PCI_DMA_BIDIRECTIONAL);
1013 }
1014 }
1015
1016 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1017 {
1018 int i;
1019
1020 kfree(ppgtt->pt_dma_addr);
1021 for (i = 0; i < ppgtt->num_pd_entries; i++)
1022 __free_page(ppgtt->pt_pages[i]);
1023 kfree(ppgtt->pt_pages);
1024 }
1025
1026 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1027 {
1028 struct i915_hw_ppgtt *ppgtt =
1029 container_of(vm, struct i915_hw_ppgtt, base);
1030
1031 list_del(&vm->global_link);
1032 drm_mm_takedown(&ppgtt->base.mm);
1033 drm_mm_remove_node(&ppgtt->node);
1034
1035 gen6_ppgtt_unmap_pages(ppgtt);
1036 gen6_ppgtt_free(ppgtt);
1037 }
1038
1039 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1040 {
1041 struct drm_device *dev = ppgtt->base.dev;
1042 struct drm_i915_private *dev_priv = dev->dev_private;
1043 bool retried = false;
1044 int ret;
1045
1046 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1047 * allocator works in address space sizes, so it's multiplied by page
1048 * size. We allocate at the top of the GTT to avoid fragmentation.
1049 */
1050 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1051 alloc:
1052 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1053 &ppgtt->node, GEN6_PD_SIZE,
1054 GEN6_PD_ALIGN, 0,
1055 0, dev_priv->gtt.base.total,
1056 DRM_MM_TOPDOWN);
1057 if (ret == -ENOSPC && !retried) {
1058 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1059 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1060 I915_CACHE_NONE,
1061 0, dev_priv->gtt.base.total,
1062 0);
1063 if (ret)
1064 return ret;
1065
1066 retried = true;
1067 goto alloc;
1068 }
1069
1070 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1071 DRM_DEBUG("Forced to use aperture for PDEs\n");
1072
1073 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1074 return ret;
1075 }
1076
1077 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1078 {
1079 int i;
1080
1081 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1082 GFP_KERNEL);
1083
1084 if (!ppgtt->pt_pages)
1085 return -ENOMEM;
1086
1087 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1088 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1089 if (!ppgtt->pt_pages[i]) {
1090 gen6_ppgtt_free(ppgtt);
1091 return -ENOMEM;
1092 }
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1099 {
1100 int ret;
1101
1102 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1103 if (ret)
1104 return ret;
1105
1106 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1107 if (ret) {
1108 drm_mm_remove_node(&ppgtt->node);
1109 return ret;
1110 }
1111
1112 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1113 GFP_KERNEL);
1114 if (!ppgtt->pt_dma_addr) {
1115 drm_mm_remove_node(&ppgtt->node);
1116 gen6_ppgtt_free(ppgtt);
1117 return -ENOMEM;
1118 }
1119
1120 return 0;
1121 }
1122
1123 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1124 {
1125 struct drm_device *dev = ppgtt->base.dev;
1126 int i;
1127
1128 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1129 dma_addr_t pt_addr;
1130
1131 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1132 PCI_DMA_BIDIRECTIONAL);
1133
1134 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1135 gen6_ppgtt_unmap_pages(ppgtt);
1136 return -EIO;
1137 }
1138
1139 ppgtt->pt_dma_addr[i] = pt_addr;
1140 }
1141
1142 return 0;
1143 }
1144
1145 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1146 {
1147 struct drm_device *dev = ppgtt->base.dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 int ret;
1150
1151 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1152 if (IS_GEN6(dev)) {
1153 ppgtt->enable = gen6_ppgtt_enable;
1154 ppgtt->switch_mm = gen6_mm_switch;
1155 } else if (IS_HASWELL(dev)) {
1156 ppgtt->enable = gen7_ppgtt_enable;
1157 ppgtt->switch_mm = hsw_mm_switch;
1158 } else if (IS_GEN7(dev)) {
1159 ppgtt->enable = gen7_ppgtt_enable;
1160 ppgtt->switch_mm = gen7_mm_switch;
1161 } else
1162 BUG();
1163
1164 ret = gen6_ppgtt_alloc(ppgtt);
1165 if (ret)
1166 return ret;
1167
1168 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1169 if (ret) {
1170 gen6_ppgtt_free(ppgtt);
1171 return ret;
1172 }
1173
1174 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1175 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1176 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1177 ppgtt->base.start = 0;
1178 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1179 ppgtt->debug_dump = gen6_dump_ppgtt;
1180
1181 ppgtt->pd_offset =
1182 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1183
1184 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1185
1186 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1187 ppgtt->node.size >> 20,
1188 ppgtt->node.start / PAGE_SIZE);
1189
1190 return 0;
1191 }
1192
1193 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1194 {
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 int ret = 0;
1197
1198 ppgtt->base.dev = dev;
1199 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1200
1201 if (INTEL_INFO(dev)->gen < 8)
1202 ret = gen6_ppgtt_init(ppgtt);
1203 else if (IS_GEN8(dev))
1204 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1205 else
1206 BUG();
1207
1208 if (!ret) {
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 kref_init(&ppgtt->ref);
1211 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1212 ppgtt->base.total);
1213 i915_init_vm(dev_priv, &ppgtt->base);
1214 if (INTEL_INFO(dev)->gen < 8) {
1215 gen6_write_pdes(ppgtt);
1216 DRM_DEBUG("Adding PPGTT at offset %x\n",
1217 ppgtt->pd_offset << 10);
1218 }
1219 }
1220
1221 return ret;
1222 }
1223
1224 static void
1225 ppgtt_bind_vma(struct i915_vma *vma,
1226 enum i915_cache_level cache_level,
1227 u32 flags)
1228 {
1229 /* Currently applicable only to VLV */
1230 if (vma->obj->gt_ro)
1231 flags |= PTE_READ_ONLY;
1232
1233 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1234 cache_level, flags);
1235 }
1236
1237 static void ppgtt_unbind_vma(struct i915_vma *vma)
1238 {
1239 vma->vm->clear_range(vma->vm,
1240 vma->node.start,
1241 vma->obj->base.size,
1242 true);
1243 }
1244
1245 extern int intel_iommu_gfx_mapped;
1246 /* Certain Gen5 chipsets require require idling the GPU before
1247 * unmapping anything from the GTT when VT-d is enabled.
1248 */
1249 static inline bool needs_idle_maps(struct drm_device *dev)
1250 {
1251 #ifdef CONFIG_INTEL_IOMMU
1252 /* Query intel_iommu to see if we need the workaround. Presumably that
1253 * was loaded first.
1254 */
1255 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1256 return true;
1257 #endif
1258 return false;
1259 }
1260
1261 static bool do_idling(struct drm_i915_private *dev_priv)
1262 {
1263 bool ret = dev_priv->mm.interruptible;
1264
1265 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1266 dev_priv->mm.interruptible = false;
1267 if (i915_gpu_idle(dev_priv->dev)) {
1268 DRM_ERROR("Couldn't idle GPU\n");
1269 /* Wait a bit, in hopes it avoids the hang */
1270 udelay(10);
1271 }
1272 }
1273
1274 return ret;
1275 }
1276
1277 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1278 {
1279 if (unlikely(dev_priv->gtt.do_idle_maps))
1280 dev_priv->mm.interruptible = interruptible;
1281 }
1282
1283 void i915_check_and_clear_faults(struct drm_device *dev)
1284 {
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 struct intel_engine_cs *ring;
1287 int i;
1288
1289 if (INTEL_INFO(dev)->gen < 6)
1290 return;
1291
1292 for_each_ring(ring, dev_priv, i) {
1293 u32 fault_reg;
1294 fault_reg = I915_READ(RING_FAULT_REG(ring));
1295 if (fault_reg & RING_FAULT_VALID) {
1296 DRM_DEBUG_DRIVER("Unexpected fault\n"
1297 "\tAddr: 0x%08lx\\n"
1298 "\tAddress space: %s\n"
1299 "\tSource ID: %d\n"
1300 "\tType: %d\n",
1301 fault_reg & PAGE_MASK,
1302 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1303 RING_FAULT_SRCID(fault_reg),
1304 RING_FAULT_FAULT_TYPE(fault_reg));
1305 I915_WRITE(RING_FAULT_REG(ring),
1306 fault_reg & ~RING_FAULT_VALID);
1307 }
1308 }
1309 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1310 }
1311
1312 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1313 {
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316 /* Don't bother messing with faults pre GEN6 as we have little
1317 * documentation supporting that it's a good idea.
1318 */
1319 if (INTEL_INFO(dev)->gen < 6)
1320 return;
1321
1322 i915_check_and_clear_faults(dev);
1323
1324 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1325 dev_priv->gtt.base.start,
1326 dev_priv->gtt.base.total,
1327 true);
1328 }
1329
1330 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1331 {
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 struct drm_i915_gem_object *obj;
1334 struct i915_address_space *vm;
1335
1336 i915_check_and_clear_faults(dev);
1337
1338 /* First fill our portion of the GTT with scratch pages */
1339 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1340 dev_priv->gtt.base.start,
1341 dev_priv->gtt.base.total,
1342 true);
1343
1344 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1345 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1346 &dev_priv->gtt.base);
1347 if (!vma)
1348 continue;
1349
1350 i915_gem_clflush_object(obj, obj->pin_display);
1351 /* The bind_vma code tries to be smart about tracking mappings.
1352 * Unfortunately above, we've just wiped out the mappings
1353 * without telling our object about it. So we need to fake it.
1354 */
1355 obj->has_global_gtt_mapping = 0;
1356 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1357 }
1358
1359
1360 if (INTEL_INFO(dev)->gen >= 8) {
1361 if (IS_CHERRYVIEW(dev))
1362 chv_setup_private_ppat(dev_priv);
1363 else
1364 bdw_setup_private_ppat(dev_priv);
1365
1366 return;
1367 }
1368
1369 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1370 /* TODO: Perhaps it shouldn't be gen6 specific */
1371 if (i915_is_ggtt(vm)) {
1372 if (dev_priv->mm.aliasing_ppgtt)
1373 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1374 continue;
1375 }
1376
1377 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1378 }
1379
1380 i915_gem_chipset_flush(dev);
1381 }
1382
1383 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1384 {
1385 if (obj->has_dma_mapping)
1386 return 0;
1387
1388 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1389 obj->pages->sgl, obj->pages->nents,
1390 PCI_DMA_BIDIRECTIONAL))
1391 return -ENOSPC;
1392
1393 return 0;
1394 }
1395
1396 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1397 {
1398 #ifdef writeq
1399 writeq(pte, addr);
1400 #else
1401 iowrite32((u32)pte, addr);
1402 iowrite32(pte >> 32, addr + 4);
1403 #endif
1404 }
1405
1406 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1407 struct sg_table *st,
1408 uint64_t start,
1409 enum i915_cache_level level, u32 unused)
1410 {
1411 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1412 unsigned first_entry = start >> PAGE_SHIFT;
1413 gen8_gtt_pte_t __iomem *gtt_entries =
1414 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1415 int i = 0;
1416 struct sg_page_iter sg_iter;
1417 dma_addr_t addr = 0;
1418
1419 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1420 addr = sg_dma_address(sg_iter.sg) +
1421 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1422 gen8_set_pte(&gtt_entries[i],
1423 gen8_pte_encode(addr, level, true));
1424 i++;
1425 }
1426
1427 /*
1428 * XXX: This serves as a posting read to make sure that the PTE has
1429 * actually been updated. There is some concern that even though
1430 * registers and PTEs are within the same BAR that they are potentially
1431 * of NUMA access patterns. Therefore, even with the way we assume
1432 * hardware should work, we must keep this posting read for paranoia.
1433 */
1434 if (i != 0)
1435 WARN_ON(readq(&gtt_entries[i-1])
1436 != gen8_pte_encode(addr, level, true));
1437
1438 /* This next bit makes the above posting read even more important. We
1439 * want to flush the TLBs only after we're certain all the PTE updates
1440 * have finished.
1441 */
1442 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1443 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1444 }
1445
1446 /*
1447 * Binds an object into the global gtt with the specified cache level. The object
1448 * will be accessible to the GPU via commands whose operands reference offsets
1449 * within the global GTT as well as accessible by the GPU through the GMADR
1450 * mapped BAR (dev_priv->mm.gtt->gtt).
1451 */
1452 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1453 struct sg_table *st,
1454 uint64_t start,
1455 enum i915_cache_level level, u32 flags)
1456 {
1457 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1458 unsigned first_entry = start >> PAGE_SHIFT;
1459 gen6_gtt_pte_t __iomem *gtt_entries =
1460 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1461 int i = 0;
1462 struct sg_page_iter sg_iter;
1463 dma_addr_t addr;
1464
1465 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1466 addr = sg_page_iter_dma_address(&sg_iter);
1467 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1468 i++;
1469 }
1470
1471 /* XXX: This serves as a posting read to make sure that the PTE has
1472 * actually been updated. There is some concern that even though
1473 * registers and PTEs are within the same BAR that they are potentially
1474 * of NUMA access patterns. Therefore, even with the way we assume
1475 * hardware should work, we must keep this posting read for paranoia.
1476 */
1477 if (i != 0)
1478 WARN_ON(readl(&gtt_entries[i-1]) !=
1479 vm->pte_encode(addr, level, true, flags));
1480
1481 /* This next bit makes the above posting read even more important. We
1482 * want to flush the TLBs only after we're certain all the PTE updates
1483 * have finished.
1484 */
1485 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1486 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1487 }
1488
1489 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1490 uint64_t start,
1491 uint64_t length,
1492 bool use_scratch)
1493 {
1494 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1495 unsigned first_entry = start >> PAGE_SHIFT;
1496 unsigned num_entries = length >> PAGE_SHIFT;
1497 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1498 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1499 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1500 int i;
1501
1502 if (WARN(num_entries > max_entries,
1503 "First entry = %d; Num entries = %d (max=%d)\n",
1504 first_entry, num_entries, max_entries))
1505 num_entries = max_entries;
1506
1507 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1508 I915_CACHE_LLC,
1509 use_scratch);
1510 for (i = 0; i < num_entries; i++)
1511 gen8_set_pte(&gtt_base[i], scratch_pte);
1512 readl(gtt_base);
1513 }
1514
1515 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1516 uint64_t start,
1517 uint64_t length,
1518 bool use_scratch)
1519 {
1520 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1521 unsigned first_entry = start >> PAGE_SHIFT;
1522 unsigned num_entries = length >> PAGE_SHIFT;
1523 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1524 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1525 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1526 int i;
1527
1528 if (WARN(num_entries > max_entries,
1529 "First entry = %d; Num entries = %d (max=%d)\n",
1530 first_entry, num_entries, max_entries))
1531 num_entries = max_entries;
1532
1533 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1534
1535 for (i = 0; i < num_entries; i++)
1536 iowrite32(scratch_pte, &gtt_base[i]);
1537 readl(gtt_base);
1538 }
1539
1540
1541 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1542 enum i915_cache_level cache_level,
1543 u32 unused)
1544 {
1545 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1546 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1547 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1548
1549 BUG_ON(!i915_is_ggtt(vma->vm));
1550 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1551 vma->obj->has_global_gtt_mapping = 1;
1552 }
1553
1554 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1555 uint64_t start,
1556 uint64_t length,
1557 bool unused)
1558 {
1559 unsigned first_entry = start >> PAGE_SHIFT;
1560 unsigned num_entries = length >> PAGE_SHIFT;
1561 intel_gtt_clear_range(first_entry, num_entries);
1562 }
1563
1564 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1565 {
1566 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1567 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1568
1569 BUG_ON(!i915_is_ggtt(vma->vm));
1570 vma->obj->has_global_gtt_mapping = 0;
1571 intel_gtt_clear_range(first, size);
1572 }
1573
1574 static void ggtt_bind_vma(struct i915_vma *vma,
1575 enum i915_cache_level cache_level,
1576 u32 flags)
1577 {
1578 struct drm_device *dev = vma->vm->dev;
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 struct drm_i915_gem_object *obj = vma->obj;
1581
1582 /* Currently applicable only to VLV */
1583 if (obj->gt_ro)
1584 flags |= PTE_READ_ONLY;
1585
1586 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1587 * or we have a global mapping already but the cacheability flags have
1588 * changed, set the global PTEs.
1589 *
1590 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1591 * instead if none of the above hold true.
1592 *
1593 * NB: A global mapping should only be needed for special regions like
1594 * "gtt mappable", SNB errata, or if specified via special execbuf
1595 * flags. At all other times, the GPU will use the aliasing PPGTT.
1596 */
1597 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1598 if (!obj->has_global_gtt_mapping ||
1599 (cache_level != obj->cache_level)) {
1600 vma->vm->insert_entries(vma->vm, obj->pages,
1601 vma->node.start,
1602 cache_level, flags);
1603 obj->has_global_gtt_mapping = 1;
1604 }
1605 }
1606
1607 if (dev_priv->mm.aliasing_ppgtt &&
1608 (!obj->has_aliasing_ppgtt_mapping ||
1609 (cache_level != obj->cache_level))) {
1610 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1611 appgtt->base.insert_entries(&appgtt->base,
1612 vma->obj->pages,
1613 vma->node.start,
1614 cache_level, flags);
1615 vma->obj->has_aliasing_ppgtt_mapping = 1;
1616 }
1617 }
1618
1619 static void ggtt_unbind_vma(struct i915_vma *vma)
1620 {
1621 struct drm_device *dev = vma->vm->dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 struct drm_i915_gem_object *obj = vma->obj;
1624
1625 if (obj->has_global_gtt_mapping) {
1626 vma->vm->clear_range(vma->vm,
1627 vma->node.start,
1628 obj->base.size,
1629 true);
1630 obj->has_global_gtt_mapping = 0;
1631 }
1632
1633 if (obj->has_aliasing_ppgtt_mapping) {
1634 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1635 appgtt->base.clear_range(&appgtt->base,
1636 vma->node.start,
1637 obj->base.size,
1638 true);
1639 obj->has_aliasing_ppgtt_mapping = 0;
1640 }
1641 }
1642
1643 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1644 {
1645 struct drm_device *dev = obj->base.dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 bool interruptible;
1648
1649 interruptible = do_idling(dev_priv);
1650
1651 if (!obj->has_dma_mapping)
1652 dma_unmap_sg(&dev->pdev->dev,
1653 obj->pages->sgl, obj->pages->nents,
1654 PCI_DMA_BIDIRECTIONAL);
1655
1656 undo_idling(dev_priv, interruptible);
1657 }
1658
1659 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1660 unsigned long color,
1661 unsigned long *start,
1662 unsigned long *end)
1663 {
1664 if (node->color != color)
1665 *start += 4096;
1666
1667 if (!list_empty(&node->node_list)) {
1668 node = list_entry(node->node_list.next,
1669 struct drm_mm_node,
1670 node_list);
1671 if (node->allocated && node->color != color)
1672 *end -= 4096;
1673 }
1674 }
1675
1676 void i915_gem_setup_global_gtt(struct drm_device *dev,
1677 unsigned long start,
1678 unsigned long mappable_end,
1679 unsigned long end)
1680 {
1681 /* Let GEM Manage all of the aperture.
1682 *
1683 * However, leave one page at the end still bound to the scratch page.
1684 * There are a number of places where the hardware apparently prefetches
1685 * past the end of the object, and we've seen multiple hangs with the
1686 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1687 * aperture. One page should be enough to keep any prefetching inside
1688 * of the aperture.
1689 */
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1692 struct drm_mm_node *entry;
1693 struct drm_i915_gem_object *obj;
1694 unsigned long hole_start, hole_end;
1695
1696 BUG_ON(mappable_end > end);
1697
1698 /* Subtract the guard page ... */
1699 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1700 if (!HAS_LLC(dev))
1701 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1702
1703 /* Mark any preallocated objects as occupied */
1704 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1705 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1706 int ret;
1707 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1708 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1709
1710 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1711 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1712 if (ret)
1713 DRM_DEBUG_KMS("Reservation failed\n");
1714 obj->has_global_gtt_mapping = 1;
1715 }
1716
1717 dev_priv->gtt.base.start = start;
1718 dev_priv->gtt.base.total = end - start;
1719
1720 /* Clear any non-preallocated blocks */
1721 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1722 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1723 hole_start, hole_end);
1724 ggtt_vm->clear_range(ggtt_vm, hole_start,
1725 hole_end - hole_start, true);
1726 }
1727
1728 /* And finally clear the reserved guard page */
1729 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1730 }
1731
1732 void i915_gem_init_global_gtt(struct drm_device *dev)
1733 {
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 unsigned long gtt_size, mappable_size;
1736
1737 gtt_size = dev_priv->gtt.base.total;
1738 mappable_size = dev_priv->gtt.mappable_end;
1739
1740 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1741 }
1742
1743 static int setup_scratch_page(struct drm_device *dev)
1744 {
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 struct page *page;
1747 dma_addr_t dma_addr;
1748
1749 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1750 if (page == NULL)
1751 return -ENOMEM;
1752 get_page(page);
1753 set_pages_uc(page, 1);
1754
1755 #ifdef CONFIG_INTEL_IOMMU
1756 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1757 PCI_DMA_BIDIRECTIONAL);
1758 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1759 return -EINVAL;
1760 #else
1761 dma_addr = page_to_phys(page);
1762 #endif
1763 dev_priv->gtt.base.scratch.page = page;
1764 dev_priv->gtt.base.scratch.addr = dma_addr;
1765
1766 return 0;
1767 }
1768
1769 static void teardown_scratch_page(struct drm_device *dev)
1770 {
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 struct page *page = dev_priv->gtt.base.scratch.page;
1773
1774 set_pages_wb(page, 1);
1775 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1776 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1777 put_page(page);
1778 __free_page(page);
1779 }
1780
1781 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1782 {
1783 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1784 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1785 return snb_gmch_ctl << 20;
1786 }
1787
1788 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1789 {
1790 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1791 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1792 if (bdw_gmch_ctl)
1793 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1794
1795 #ifdef CONFIG_X86_32
1796 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1797 if (bdw_gmch_ctl > 4)
1798 bdw_gmch_ctl = 4;
1799 #endif
1800
1801 return bdw_gmch_ctl << 20;
1802 }
1803
1804 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1805 {
1806 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1807 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1808
1809 if (gmch_ctrl)
1810 return 1 << (20 + gmch_ctrl);
1811
1812 return 0;
1813 }
1814
1815 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1816 {
1817 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1818 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1819 return snb_gmch_ctl << 25; /* 32 MB units */
1820 }
1821
1822 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1823 {
1824 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1825 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1826 return bdw_gmch_ctl << 25; /* 32 MB units */
1827 }
1828
1829 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1830 {
1831 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1832 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1833
1834 /*
1835 * 0x0 to 0x10: 32MB increments starting at 0MB
1836 * 0x11 to 0x16: 4MB increments starting at 8MB
1837 * 0x17 to 0x1d: 4MB increments start at 36MB
1838 */
1839 if (gmch_ctrl < 0x11)
1840 return gmch_ctrl << 25;
1841 else if (gmch_ctrl < 0x17)
1842 return (gmch_ctrl - 0x11 + 2) << 22;
1843 else
1844 return (gmch_ctrl - 0x17 + 9) << 22;
1845 }
1846
1847 static int ggtt_probe_common(struct drm_device *dev,
1848 size_t gtt_size)
1849 {
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 phys_addr_t gtt_phys_addr;
1852 int ret;
1853
1854 /* For Modern GENs the PTEs and register space are split in the BAR */
1855 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1856 (pci_resource_len(dev->pdev, 0) / 2);
1857
1858 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1859 if (!dev_priv->gtt.gsm) {
1860 DRM_ERROR("Failed to map the gtt page table\n");
1861 return -ENOMEM;
1862 }
1863
1864 ret = setup_scratch_page(dev);
1865 if (ret) {
1866 DRM_ERROR("Scratch setup failed\n");
1867 /* iounmap will also get called at remove, but meh */
1868 iounmap(dev_priv->gtt.gsm);
1869 }
1870
1871 return ret;
1872 }
1873
1874 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1875 * bits. When using advanced contexts each context stores its own PAT, but
1876 * writing this data shouldn't be harmful even in those cases. */
1877 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1878 {
1879 uint64_t pat;
1880
1881 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1882 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1883 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1884 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1885 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1886 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1887 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1888 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1889
1890 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1891 * write would work. */
1892 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1893 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1894 }
1895
1896 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1897 {
1898 uint64_t pat;
1899
1900 /*
1901 * Map WB on BDW to snooped on CHV.
1902 *
1903 * Only the snoop bit has meaning for CHV, the rest is
1904 * ignored.
1905 *
1906 * Note that the harware enforces snooping for all page
1907 * table accesses. The snoop bit is actually ignored for
1908 * PDEs.
1909 */
1910 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1911 GEN8_PPAT(1, 0) |
1912 GEN8_PPAT(2, 0) |
1913 GEN8_PPAT(3, 0) |
1914 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1915 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1916 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1917 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1918
1919 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1920 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1921 }
1922
1923 static int gen8_gmch_probe(struct drm_device *dev,
1924 size_t *gtt_total,
1925 size_t *stolen,
1926 phys_addr_t *mappable_base,
1927 unsigned long *mappable_end)
1928 {
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 unsigned int gtt_size;
1931 u16 snb_gmch_ctl;
1932 int ret;
1933
1934 /* TODO: We're not aware of mappable constraints on gen8 yet */
1935 *mappable_base = pci_resource_start(dev->pdev, 2);
1936 *mappable_end = pci_resource_len(dev->pdev, 2);
1937
1938 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1939 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1940
1941 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1942
1943 if (IS_CHERRYVIEW(dev)) {
1944 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1945 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1946 } else {
1947 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1948 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1949 }
1950
1951 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1952
1953 if (IS_CHERRYVIEW(dev))
1954 chv_setup_private_ppat(dev_priv);
1955 else
1956 bdw_setup_private_ppat(dev_priv);
1957
1958 ret = ggtt_probe_common(dev, gtt_size);
1959
1960 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1961 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1962
1963 return ret;
1964 }
1965
1966 static int gen6_gmch_probe(struct drm_device *dev,
1967 size_t *gtt_total,
1968 size_t *stolen,
1969 phys_addr_t *mappable_base,
1970 unsigned long *mappable_end)
1971 {
1972 struct drm_i915_private *dev_priv = dev->dev_private;
1973 unsigned int gtt_size;
1974 u16 snb_gmch_ctl;
1975 int ret;
1976
1977 *mappable_base = pci_resource_start(dev->pdev, 2);
1978 *mappable_end = pci_resource_len(dev->pdev, 2);
1979
1980 /* 64/512MB is the current min/max we actually know of, but this is just
1981 * a coarse sanity check.
1982 */
1983 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1984 DRM_ERROR("Unknown GMADR size (%lx)\n",
1985 dev_priv->gtt.mappable_end);
1986 return -ENXIO;
1987 }
1988
1989 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1990 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1991 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1992
1993 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1994
1995 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1996 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1997
1998 ret = ggtt_probe_common(dev, gtt_size);
1999
2000 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2001 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2002
2003 return ret;
2004 }
2005
2006 static void gen6_gmch_remove(struct i915_address_space *vm)
2007 {
2008
2009 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2010
2011 if (drm_mm_initialized(&vm->mm)) {
2012 drm_mm_takedown(&vm->mm);
2013 list_del(&vm->global_link);
2014 }
2015 iounmap(gtt->gsm);
2016 teardown_scratch_page(vm->dev);
2017 }
2018
2019 static int i915_gmch_probe(struct drm_device *dev,
2020 size_t *gtt_total,
2021 size_t *stolen,
2022 phys_addr_t *mappable_base,
2023 unsigned long *mappable_end)
2024 {
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 int ret;
2027
2028 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2029 if (!ret) {
2030 DRM_ERROR("failed to set up gmch\n");
2031 return -EIO;
2032 }
2033
2034 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2035
2036 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2037 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2038
2039 if (unlikely(dev_priv->gtt.do_idle_maps))
2040 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2041
2042 return 0;
2043 }
2044
2045 static void i915_gmch_remove(struct i915_address_space *vm)
2046 {
2047 if (drm_mm_initialized(&vm->mm)) {
2048 drm_mm_takedown(&vm->mm);
2049 list_del(&vm->global_link);
2050 }
2051 intel_gmch_remove();
2052 }
2053
2054 int i915_gem_gtt_init(struct drm_device *dev)
2055 {
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct i915_gtt *gtt = &dev_priv->gtt;
2058 int ret;
2059
2060 if (INTEL_INFO(dev)->gen <= 5) {
2061 gtt->gtt_probe = i915_gmch_probe;
2062 gtt->base.cleanup = i915_gmch_remove;
2063 } else if (INTEL_INFO(dev)->gen < 8) {
2064 gtt->gtt_probe = gen6_gmch_probe;
2065 gtt->base.cleanup = gen6_gmch_remove;
2066 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2067 gtt->base.pte_encode = iris_pte_encode;
2068 else if (IS_HASWELL(dev))
2069 gtt->base.pte_encode = hsw_pte_encode;
2070 else if (IS_VALLEYVIEW(dev))
2071 gtt->base.pte_encode = byt_pte_encode;
2072 else if (INTEL_INFO(dev)->gen >= 7)
2073 gtt->base.pte_encode = ivb_pte_encode;
2074 else
2075 gtt->base.pte_encode = snb_pte_encode;
2076 } else {
2077 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2078 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2079 }
2080
2081 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2082 &gtt->mappable_base, &gtt->mappable_end);
2083 if (ret)
2084 return ret;
2085
2086 gtt->base.dev = dev;
2087
2088 /* GMADR is the PCI mmio aperture into the global GTT. */
2089 DRM_INFO("Memory usable by graphics device = %zdM\n",
2090 gtt->base.total >> 20);
2091 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2092 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2093 #ifdef CONFIG_INTEL_IOMMU
2094 if (intel_iommu_gfx_mapped)
2095 DRM_INFO("VT-d active for gfx access\n");
2096 #endif
2097 /*
2098 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2099 * user's requested state against the hardware/driver capabilities. We
2100 * do this now so that we can print out any log messages once rather
2101 * than every time we check intel_enable_ppgtt().
2102 */
2103 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2104 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2105
2106 return 0;
2107 }
2108
2109 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2110 struct i915_address_space *vm)
2111 {
2112 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2113 if (vma == NULL)
2114 return ERR_PTR(-ENOMEM);
2115
2116 INIT_LIST_HEAD(&vma->vma_link);
2117 INIT_LIST_HEAD(&vma->mm_list);
2118 INIT_LIST_HEAD(&vma->exec_list);
2119 vma->vm = vm;
2120 vma->obj = obj;
2121
2122 switch (INTEL_INFO(vm->dev)->gen) {
2123 case 8:
2124 case 7:
2125 case 6:
2126 if (i915_is_ggtt(vm)) {
2127 vma->unbind_vma = ggtt_unbind_vma;
2128 vma->bind_vma = ggtt_bind_vma;
2129 } else {
2130 vma->unbind_vma = ppgtt_unbind_vma;
2131 vma->bind_vma = ppgtt_bind_vma;
2132 }
2133 break;
2134 case 5:
2135 case 4:
2136 case 3:
2137 case 2:
2138 BUG_ON(!i915_is_ggtt(vm));
2139 vma->unbind_vma = i915_ggtt_unbind_vma;
2140 vma->bind_vma = i915_ggtt_bind_vma;
2141 break;
2142 default:
2143 BUG();
2144 }
2145
2146 /* Keep GGTT vmas first to make debug easier */
2147 if (i915_is_ggtt(vm))
2148 list_add(&vma->vma_link, &obj->vma_list);
2149 else
2150 list_add_tail(&vma->vma_link, &obj->vma_list);
2151
2152 return vma;
2153 }
2154
2155 struct i915_vma *
2156 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2157 struct i915_address_space *vm)
2158 {
2159 struct i915_vma *vma;
2160
2161 vma = i915_gem_obj_to_vma(obj, vm);
2162 if (!vma)
2163 vma = __i915_gem_vma_create(obj, vm);
2164
2165 return vma;
2166 }
Linux kernel - Deliverables
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