2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(struct drm_device
*dev
,
197 enum i915_cache_level level
)
199 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
201 if (level
!= I915_CACHE_NONE
)
202 pde
|= PPAT_CACHED_PDE_INDEX
;
204 pde
|= PPAT_UNCACHED_INDEX
;
208 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
209 enum i915_cache_level level
,
210 bool valid
, u32 unused
)
212 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
213 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
216 case I915_CACHE_L3_LLC
:
218 pte
|= GEN6_PTE_CACHE_LLC
;
220 case I915_CACHE_NONE
:
221 pte
|= GEN6_PTE_UNCACHED
;
230 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
231 enum i915_cache_level level
,
232 bool valid
, u32 unused
)
234 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
235 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
238 case I915_CACHE_L3_LLC
:
239 pte
|= GEN7_PTE_CACHE_L3_LLC
;
242 pte
|= GEN6_PTE_CACHE_LLC
;
244 case I915_CACHE_NONE
:
245 pte
|= GEN6_PTE_UNCACHED
;
254 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
255 enum i915_cache_level level
,
256 bool valid
, u32 flags
)
258 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
259 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
261 if (!(flags
& PTE_READ_ONLY
))
262 pte
|= BYT_PTE_WRITEABLE
;
264 if (level
!= I915_CACHE_NONE
)
265 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
270 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
271 enum i915_cache_level level
,
272 bool valid
, u32 unused
)
274 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
275 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
277 if (level
!= I915_CACHE_NONE
)
278 pte
|= HSW_WB_LLC_AGE3
;
283 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
284 enum i915_cache_level level
,
285 bool valid
, u32 unused
)
287 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
288 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
291 case I915_CACHE_NONE
:
294 pte
|= HSW_WT_ELLC_LLC_AGE3
;
297 pte
|= HSW_WB_ELLC_LLC_AGE3
;
304 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
306 struct device
*device
= &dev
->pdev
->dev
;
308 p
->page
= alloc_page(GFP_KERNEL
);
312 p
->daddr
= dma_map_page(device
,
313 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
315 if (dma_mapping_error(device
, p
->daddr
)) {
316 __free_page(p
->page
);
323 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
325 if (WARN_ON(!p
->page
))
328 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
329 __free_page(p
->page
);
330 memset(p
, 0, sizeof(*p
));
333 static void unmap_and_free_pt(struct i915_page_table
*pt
,
334 struct drm_device
*dev
)
336 cleanup_page_dma(dev
, &pt
->base
);
337 kfree(pt
->used_ptes
);
341 static void gen8_initialize_pt(struct i915_address_space
*vm
,
342 struct i915_page_table
*pt
)
344 gen8_pte_t
*pt_vaddr
, scratch_pte
;
347 pt_vaddr
= kmap_atomic(pt
->base
.page
);
348 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
349 I915_CACHE_LLC
, true);
351 for (i
= 0; i
< GEN8_PTES
; i
++)
352 pt_vaddr
[i
] = scratch_pte
;
354 if (!HAS_LLC(vm
->dev
))
355 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
356 kunmap_atomic(pt_vaddr
);
359 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
361 struct i915_page_table
*pt
;
362 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
363 GEN8_PTES
: GEN6_PTES
;
366 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
368 return ERR_PTR(-ENOMEM
);
370 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
376 ret
= setup_page_dma(dev
, &pt
->base
);
383 kfree(pt
->used_ptes
);
390 static void unmap_and_free_pd(struct i915_page_directory
*pd
,
391 struct drm_device
*dev
)
394 cleanup_page_dma(dev
, &pd
->base
);
395 kfree(pd
->used_pdes
);
400 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
402 struct i915_page_directory
*pd
;
405 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
407 return ERR_PTR(-ENOMEM
);
409 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
410 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
414 ret
= setup_page_dma(dev
, &pd
->base
);
421 kfree(pd
->used_pdes
);
428 /* Broadwell Page Directory Pointer Descriptors */
429 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
433 struct intel_engine_cs
*ring
= req
->ring
;
438 ret
= intel_ring_begin(req
, 6);
442 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
443 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
444 intel_ring_emit(ring
, upper_32_bits(addr
));
445 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
446 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
447 intel_ring_emit(ring
, lower_32_bits(addr
));
448 intel_ring_advance(ring
);
453 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
454 struct drm_i915_gem_request
*req
)
458 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
459 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
461 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
469 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
474 struct i915_hw_ppgtt
*ppgtt
=
475 container_of(vm
, struct i915_hw_ppgtt
, base
);
476 gen8_pte_t
*pt_vaddr
, scratch_pte
;
477 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
478 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
479 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
480 unsigned num_entries
= length
>> PAGE_SHIFT
;
481 unsigned last_pte
, i
;
483 scratch_pte
= gen8_pte_encode(ppgtt
->base
.scratch
.addr
,
484 I915_CACHE_LLC
, use_scratch
);
486 while (num_entries
) {
487 struct i915_page_directory
*pd
;
488 struct i915_page_table
*pt
;
489 struct page
*page_table
;
491 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
494 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
496 if (WARN_ON(!pd
->page_table
[pde
]))
499 pt
= pd
->page_table
[pde
];
501 if (WARN_ON(!pt
->base
.page
))
504 page_table
= pt
->base
.page
;
506 last_pte
= pte
+ num_entries
;
507 if (last_pte
> GEN8_PTES
)
508 last_pte
= GEN8_PTES
;
510 pt_vaddr
= kmap_atomic(page_table
);
512 for (i
= pte
; i
< last_pte
; i
++) {
513 pt_vaddr
[i
] = scratch_pte
;
517 if (!HAS_LLC(ppgtt
->base
.dev
))
518 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
519 kunmap_atomic(pt_vaddr
);
522 if (++pde
== I915_PDES
) {
529 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
530 struct sg_table
*pages
,
532 enum i915_cache_level cache_level
, u32 unused
)
534 struct i915_hw_ppgtt
*ppgtt
=
535 container_of(vm
, struct i915_hw_ppgtt
, base
);
536 gen8_pte_t
*pt_vaddr
;
537 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
538 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
539 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
540 struct sg_page_iter sg_iter
;
544 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
545 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
548 if (pt_vaddr
== NULL
) {
549 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
550 struct i915_page_table
*pt
= pd
->page_table
[pde
];
551 struct page
*page_table
= pt
->base
.page
;
553 pt_vaddr
= kmap_atomic(page_table
);
557 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
559 if (++pte
== GEN8_PTES
) {
560 if (!HAS_LLC(ppgtt
->base
.dev
))
561 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
562 kunmap_atomic(pt_vaddr
);
564 if (++pde
== I915_PDES
) {
572 if (!HAS_LLC(ppgtt
->base
.dev
))
573 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
574 kunmap_atomic(pt_vaddr
);
578 static void __gen8_do_map_pt(gen8_pde_t
* const pde
,
579 struct i915_page_table
*pt
,
580 struct drm_device
*dev
)
583 gen8_pde_encode(dev
, pt
->base
.daddr
, I915_CACHE_LLC
);
587 static void gen8_initialize_pd(struct i915_address_space
*vm
,
588 struct i915_page_directory
*pd
)
590 struct i915_hw_ppgtt
*ppgtt
=
591 container_of(vm
, struct i915_hw_ppgtt
, base
);
592 gen8_pde_t
*page_directory
;
593 struct i915_page_table
*pt
;
596 page_directory
= kmap_atomic(pd
->base
.page
);
597 pt
= ppgtt
->scratch_pt
;
598 for (i
= 0; i
< I915_PDES
; i
++)
599 /* Map the PDE to the page table */
600 __gen8_do_map_pt(page_directory
+ i
, pt
, vm
->dev
);
602 if (!HAS_LLC(vm
->dev
))
603 drm_clflush_virt_range(page_directory
, PAGE_SIZE
);
604 kunmap_atomic(page_directory
);
607 static void gen8_free_page_tables(struct i915_page_directory
*pd
, struct drm_device
*dev
)
614 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
615 if (WARN_ON(!pd
->page_table
[i
]))
618 unmap_and_free_pt(pd
->page_table
[i
], dev
);
619 pd
->page_table
[i
] = NULL
;
623 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
625 struct i915_hw_ppgtt
*ppgtt
=
626 container_of(vm
, struct i915_hw_ppgtt
, base
);
629 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
, GEN8_LEGACY_PDPES
) {
630 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
633 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
634 unmap_and_free_pd(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
637 unmap_and_free_pd(ppgtt
->scratch_pd
, ppgtt
->base
.dev
);
638 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
642 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
643 * @ppgtt: Master ppgtt structure.
644 * @pd: Page directory for this address range.
645 * @start: Starting virtual address to begin allocations.
646 * @length Size of the allocations.
647 * @new_pts: Bitmap set by function with new allocations. Likely used by the
648 * caller to free on error.
650 * Allocate the required number of page tables. Extremely similar to
651 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
652 * the page directory boundary (instead of the page directory pointer). That
653 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
654 * possible, and likely that the caller will need to use multiple calls of this
655 * function to achieve the appropriate allocation.
657 * Return: 0 if success; negative error code otherwise.
659 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
660 struct i915_page_directory
*pd
,
663 unsigned long *new_pts
)
665 struct drm_device
*dev
= ppgtt
->base
.dev
;
666 struct i915_page_table
*pt
;
670 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
671 /* Don't reallocate page tables */
673 /* Scratch is never allocated this way */
674 WARN_ON(pt
== ppgtt
->scratch_pt
);
682 gen8_initialize_pt(&ppgtt
->base
, pt
);
683 pd
->page_table
[pde
] = pt
;
684 set_bit(pde
, new_pts
);
690 for_each_set_bit(pde
, new_pts
, I915_PDES
)
691 unmap_and_free_pt(pd
->page_table
[pde
], dev
);
697 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
698 * @ppgtt: Master ppgtt structure.
699 * @pdp: Page directory pointer for this address range.
700 * @start: Starting virtual address to begin allocations.
701 * @length Size of the allocations.
702 * @new_pds Bitmap set by function with new allocations. Likely used by the
703 * caller to free on error.
705 * Allocate the required number of page directories starting at the pde index of
706 * @start, and ending at the pde index @start + @length. This function will skip
707 * over already allocated page directories within the range, and only allocate
708 * new ones, setting the appropriate pointer within the pdp as well as the
709 * correct position in the bitmap @new_pds.
711 * The function will only allocate the pages within the range for a give page
712 * directory pointer. In other words, if @start + @length straddles a virtually
713 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
714 * required by the caller, This is not currently possible, and the BUG in the
715 * code will prevent it.
717 * Return: 0 if success; negative error code otherwise.
719 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
720 struct i915_page_directory_pointer
*pdp
,
723 unsigned long *new_pds
)
725 struct drm_device
*dev
= ppgtt
->base
.dev
;
726 struct i915_page_directory
*pd
;
730 WARN_ON(!bitmap_empty(new_pds
, GEN8_LEGACY_PDPES
));
732 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
740 gen8_initialize_pd(&ppgtt
->base
, pd
);
741 pdp
->page_directory
[pdpe
] = pd
;
742 set_bit(pdpe
, new_pds
);
748 for_each_set_bit(pdpe
, new_pds
, GEN8_LEGACY_PDPES
)
749 unmap_and_free_pd(pdp
->page_directory
[pdpe
], dev
);
755 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
)
759 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++)
765 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
766 * of these are based on the number of PDPEs in the system.
769 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
770 unsigned long ***new_pts
)
776 pds
= kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES
), sizeof(unsigned long), GFP_KERNEL
);
780 pts
= kcalloc(GEN8_LEGACY_PDPES
, sizeof(unsigned long *), GFP_KERNEL
);
786 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
787 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
788 sizeof(unsigned long), GFP_KERNEL
);
799 free_gen8_temp_bitmaps(pds
, pts
);
803 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
804 * the page table structures, we mark them dirty so that
805 * context switching/execlist queuing code takes extra steps
806 * to ensure that tlbs are flushed.
808 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
810 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
813 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
817 struct i915_hw_ppgtt
*ppgtt
=
818 container_of(vm
, struct i915_hw_ppgtt
, base
);
819 unsigned long *new_page_dirs
, **new_page_tables
;
820 struct i915_page_directory
*pd
;
821 const uint64_t orig_start
= start
;
822 const uint64_t orig_length
= length
;
827 /* Wrap is never okay since we can only represent 48b, and we don't
828 * actually use the other side of the canonical address space.
830 if (WARN_ON(start
+ length
< start
))
833 if (WARN_ON(start
+ length
> ppgtt
->base
.total
))
836 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
);
840 /* Do the allocations first so we can easily bail out */
841 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
844 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
848 /* For every page directory referenced, allocate page tables */
849 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
850 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
851 new_page_tables
[pdpe
]);
857 length
= orig_length
;
859 /* Allocations have completed successfully, so set the bitmaps, and do
861 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
862 gen8_pde_t
*const page_directory
= kmap_atomic(pd
->base
.page
);
863 struct i915_page_table
*pt
;
864 uint64_t pd_len
= gen8_clamp_pd(start
, length
);
865 uint64_t pd_start
= start
;
868 /* Every pd should be allocated, we just did that above. */
871 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
872 /* Same reasoning as pd */
875 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
877 /* Set our used ptes within the page table */
878 bitmap_set(pt
->used_ptes
,
879 gen8_pte_index(pd_start
),
880 gen8_pte_count(pd_start
, pd_len
));
882 /* Our pde is now pointing to the pagetable, pt */
883 set_bit(pde
, pd
->used_pdes
);
885 /* Map the PDE to the page table */
886 __gen8_do_map_pt(page_directory
+ pde
, pt
, vm
->dev
);
888 /* NB: We haven't yet mapped ptes to pages. At this
889 * point we're still relying on insert_entries() */
892 if (!HAS_LLC(vm
->dev
))
893 drm_clflush_virt_range(page_directory
, PAGE_SIZE
);
895 kunmap_atomic(page_directory
);
897 set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
900 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
901 mark_tlbs_dirty(ppgtt
);
906 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
907 unmap_and_free_pt(ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
], vm
->dev
);
910 for_each_set_bit(pdpe
, new_page_dirs
, GEN8_LEGACY_PDPES
)
911 unmap_and_free_pd(ppgtt
->pdp
.page_directory
[pdpe
], vm
->dev
);
913 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
914 mark_tlbs_dirty(ppgtt
);
919 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
920 * with a net effect resembling a 2-level page table in normal x86 terms. Each
921 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
925 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
927 ppgtt
->scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
928 if (IS_ERR(ppgtt
->scratch_pt
))
929 return PTR_ERR(ppgtt
->scratch_pt
);
931 ppgtt
->scratch_pd
= alloc_pd(ppgtt
->base
.dev
);
932 if (IS_ERR(ppgtt
->scratch_pd
))
933 return PTR_ERR(ppgtt
->scratch_pd
);
935 gen8_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
936 gen8_initialize_pd(&ppgtt
->base
, ppgtt
->scratch_pd
);
938 ppgtt
->base
.start
= 0;
939 ppgtt
->base
.total
= 1ULL << 32;
940 if (IS_ENABLED(CONFIG_X86_32
))
941 /* While we have a proliferation of size_t variables
942 * we cannot represent the full ppgtt size on 32bit,
943 * so limit it to the same size as the GGTT (currently
946 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
947 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
948 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
949 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
950 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
951 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
952 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
954 ppgtt
->switch_mm
= gen8_mm_switch
;
959 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
961 struct i915_address_space
*vm
= &ppgtt
->base
;
962 struct i915_page_table
*unused
;
963 gen6_pte_t scratch_pte
;
965 uint32_t pte
, pde
, temp
;
966 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
968 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
970 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
972 gen6_pte_t
*pt_vaddr
;
973 dma_addr_t pt_addr
= ppgtt
->pd
.page_table
[pde
]->base
.daddr
;
974 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
975 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
977 if (pd_entry
!= expected
)
978 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
982 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
984 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[pde
]->base
.page
);
985 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
987 (pde
* PAGE_SIZE
* GEN6_PTES
) +
991 for (i
= 0; i
< 4; i
++)
992 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
997 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
998 for (i
= 0; i
< 4; i
++) {
999 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1000 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1002 seq_puts(m
, " SCRATCH ");
1006 kunmap_atomic(pt_vaddr
);
1010 /* Write pde (index) from the page directory @pd to the page table @pt */
1011 static void gen6_write_pde(struct i915_page_directory
*pd
,
1012 const int pde
, struct i915_page_table
*pt
)
1014 /* Caller needs to make sure the write completes if necessary */
1015 struct i915_hw_ppgtt
*ppgtt
=
1016 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1019 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt
->base
.daddr
);
1020 pd_entry
|= GEN6_PDE_VALID
;
1022 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1025 /* Write all the page tables found in the ppgtt structure to incrementing page
1027 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1028 struct i915_page_directory
*pd
,
1029 uint32_t start
, uint32_t length
)
1031 struct i915_page_table
*pt
;
1034 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1035 gen6_write_pde(pd
, pde
, pt
);
1037 /* Make sure write is complete before other code can use this page
1038 * table. Also require for WC mapped PTEs */
1039 readl(dev_priv
->gtt
.gsm
);
1042 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1044 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1046 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1049 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1050 struct drm_i915_gem_request
*req
)
1052 struct intel_engine_cs
*ring
= req
->ring
;
1055 /* NB: TLBs must be flushed and invalidated before a switch */
1056 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1060 ret
= intel_ring_begin(req
, 6);
1064 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1065 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1066 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1067 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1068 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1069 intel_ring_emit(ring
, MI_NOOP
);
1070 intel_ring_advance(ring
);
1075 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1076 struct drm_i915_gem_request
*req
)
1078 struct intel_engine_cs
*ring
= req
->ring
;
1079 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1081 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1082 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1086 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1087 struct drm_i915_gem_request
*req
)
1089 struct intel_engine_cs
*ring
= req
->ring
;
1092 /* NB: TLBs must be flushed and invalidated before a switch */
1093 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1097 ret
= intel_ring_begin(req
, 6);
1101 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1102 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1103 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1104 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1105 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1106 intel_ring_emit(ring
, MI_NOOP
);
1107 intel_ring_advance(ring
);
1109 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1110 if (ring
->id
!= RCS
) {
1111 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1119 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1120 struct drm_i915_gem_request
*req
)
1122 struct intel_engine_cs
*ring
= req
->ring
;
1123 struct drm_device
*dev
= ppgtt
->base
.dev
;
1124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1127 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1128 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1130 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1135 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1138 struct intel_engine_cs
*ring
;
1141 for_each_ring(ring
, dev_priv
, j
) {
1142 I915_WRITE(RING_MODE_GEN7(ring
),
1143 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1147 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1150 struct intel_engine_cs
*ring
;
1151 uint32_t ecochk
, ecobits
;
1154 ecobits
= I915_READ(GAC_ECO_BITS
);
1155 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1157 ecochk
= I915_READ(GAM_ECOCHK
);
1158 if (IS_HASWELL(dev
)) {
1159 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1161 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1162 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1164 I915_WRITE(GAM_ECOCHK
, ecochk
);
1166 for_each_ring(ring
, dev_priv
, i
) {
1167 /* GFX_MODE is per-ring on gen7+ */
1168 I915_WRITE(RING_MODE_GEN7(ring
),
1169 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1173 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 uint32_t ecochk
, gab_ctl
, ecobits
;
1178 ecobits
= I915_READ(GAC_ECO_BITS
);
1179 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1180 ECOBITS_PPGTT_CACHE64B
);
1182 gab_ctl
= I915_READ(GAB_CTL
);
1183 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1185 ecochk
= I915_READ(GAM_ECOCHK
);
1186 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1188 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1191 /* PPGTT support for Sandybdrige/Gen6 and later */
1192 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1197 struct i915_hw_ppgtt
*ppgtt
=
1198 container_of(vm
, struct i915_hw_ppgtt
, base
);
1199 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1200 unsigned first_entry
= start
>> PAGE_SHIFT
;
1201 unsigned num_entries
= length
>> PAGE_SHIFT
;
1202 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1203 unsigned first_pte
= first_entry
% GEN6_PTES
;
1204 unsigned last_pte
, i
;
1206 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
1208 while (num_entries
) {
1209 last_pte
= first_pte
+ num_entries
;
1210 if (last_pte
> GEN6_PTES
)
1211 last_pte
= GEN6_PTES
;
1213 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[act_pt
]->base
.page
);
1215 for (i
= first_pte
; i
< last_pte
; i
++)
1216 pt_vaddr
[i
] = scratch_pte
;
1218 kunmap_atomic(pt_vaddr
);
1220 num_entries
-= last_pte
- first_pte
;
1226 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1227 struct sg_table
*pages
,
1229 enum i915_cache_level cache_level
, u32 flags
)
1231 struct i915_hw_ppgtt
*ppgtt
=
1232 container_of(vm
, struct i915_hw_ppgtt
, base
);
1233 gen6_pte_t
*pt_vaddr
;
1234 unsigned first_entry
= start
>> PAGE_SHIFT
;
1235 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1236 unsigned act_pte
= first_entry
% GEN6_PTES
;
1237 struct sg_page_iter sg_iter
;
1240 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1241 if (pt_vaddr
== NULL
)
1242 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[act_pt
]->base
.page
);
1245 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1246 cache_level
, true, flags
);
1248 if (++act_pte
== GEN6_PTES
) {
1249 kunmap_atomic(pt_vaddr
);
1256 kunmap_atomic(pt_vaddr
);
1259 static void gen6_initialize_pt(struct i915_address_space
*vm
,
1260 struct i915_page_table
*pt
)
1262 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1265 WARN_ON(vm
->scratch
.addr
== 0);
1267 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
,
1268 I915_CACHE_LLC
, true, 0);
1270 pt_vaddr
= kmap_atomic(pt
->base
.page
);
1272 for (i
= 0; i
< GEN6_PTES
; i
++)
1273 pt_vaddr
[i
] = scratch_pte
;
1275 kunmap_atomic(pt_vaddr
);
1278 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1279 uint64_t start_in
, uint64_t length_in
)
1281 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1282 struct drm_device
*dev
= vm
->dev
;
1283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1284 struct i915_hw_ppgtt
*ppgtt
=
1285 container_of(vm
, struct i915_hw_ppgtt
, base
);
1286 struct i915_page_table
*pt
;
1287 uint32_t start
, length
, start_save
, length_save
;
1291 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1294 start
= start_save
= start_in
;
1295 length
= length_save
= length_in
;
1297 bitmap_zero(new_page_tables
, I915_PDES
);
1299 /* The allocation is done in two stages so that we can bail out with
1300 * minimal amount of pain. The first stage finds new page tables that
1301 * need allocation. The second stage marks use ptes within the page
1304 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1305 if (pt
!= ppgtt
->scratch_pt
) {
1306 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1310 /* We've already allocated a page table */
1311 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1319 gen6_initialize_pt(vm
, pt
);
1321 ppgtt
->pd
.page_table
[pde
] = pt
;
1322 set_bit(pde
, new_page_tables
);
1323 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1327 length
= length_save
;
1329 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1330 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1332 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1333 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1334 gen6_pte_count(start
, length
));
1336 if (test_and_clear_bit(pde
, new_page_tables
))
1337 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1339 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1340 gen6_pte_index(start
),
1341 gen6_pte_count(start
, length
),
1343 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1347 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1349 /* Make sure write is complete before other code can use this page
1350 * table. Also require for WC mapped PTEs */
1351 readl(dev_priv
->gtt
.gsm
);
1353 mark_tlbs_dirty(ppgtt
);
1357 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1358 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1360 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1361 unmap_and_free_pt(pt
, vm
->dev
);
1364 mark_tlbs_dirty(ppgtt
);
1368 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1370 struct i915_hw_ppgtt
*ppgtt
=
1371 container_of(vm
, struct i915_hw_ppgtt
, base
);
1372 struct i915_page_table
*pt
;
1376 drm_mm_remove_node(&ppgtt
->node
);
1378 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1379 if (pt
!= ppgtt
->scratch_pt
)
1380 unmap_and_free_pt(pt
, ppgtt
->base
.dev
);
1383 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1384 unmap_and_free_pd(&ppgtt
->pd
, ppgtt
->base
.dev
);
1387 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1389 struct drm_device
*dev
= ppgtt
->base
.dev
;
1390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1391 bool retried
= false;
1394 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1395 * allocator works in address space sizes, so it's multiplied by page
1396 * size. We allocate at the top of the GTT to avoid fragmentation.
1398 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1399 ppgtt
->scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
1400 if (IS_ERR(ppgtt
->scratch_pt
))
1401 return PTR_ERR(ppgtt
->scratch_pt
);
1403 gen6_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1406 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1407 &ppgtt
->node
, GEN6_PD_SIZE
,
1409 0, dev_priv
->gtt
.base
.total
,
1411 if (ret
== -ENOSPC
&& !retried
) {
1412 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1413 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1415 0, dev_priv
->gtt
.base
.total
,
1428 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1429 DRM_DEBUG("Forced to use aperture for PDEs\n");
1434 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1438 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1440 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1443 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1444 uint64_t start
, uint64_t length
)
1446 struct i915_page_table
*unused
;
1449 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1450 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1453 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1455 struct drm_device
*dev
= ppgtt
->base
.dev
;
1456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1459 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1461 ppgtt
->switch_mm
= gen6_mm_switch
;
1462 } else if (IS_HASWELL(dev
)) {
1463 ppgtt
->switch_mm
= hsw_mm_switch
;
1464 } else if (IS_GEN7(dev
)) {
1465 ppgtt
->switch_mm
= gen7_mm_switch
;
1469 if (intel_vgpu_active(dev
))
1470 ppgtt
->switch_mm
= vgpu_mm_switch
;
1472 ret
= gen6_ppgtt_alloc(ppgtt
);
1476 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1477 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1478 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1479 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1480 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1481 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1482 ppgtt
->base
.start
= 0;
1483 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1484 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1486 ppgtt
->pd
.base
.ggtt_offset
=
1487 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1489 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1490 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1492 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1494 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1496 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1497 ppgtt
->node
.size
>> 20,
1498 ppgtt
->node
.start
/ PAGE_SIZE
);
1500 DRM_DEBUG("Adding PPGTT at offset %x\n",
1501 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1506 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 ppgtt
->base
.dev
= dev
;
1511 ppgtt
->base
.scratch
= dev_priv
->gtt
.base
.scratch
;
1513 if (INTEL_INFO(dev
)->gen
< 8)
1514 return gen6_ppgtt_init(ppgtt
);
1516 return gen8_ppgtt_init(ppgtt
);
1518 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 ret
= __hw_ppgtt_init(dev
, ppgtt
);
1525 kref_init(&ppgtt
->ref
);
1526 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1528 i915_init_vm(dev_priv
, &ppgtt
->base
);
1534 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1536 /* In the case of execlists, PPGTT is enabled by the context descriptor
1537 * and the PDPs are contained within the context itself. We don't
1538 * need to do anything here. */
1539 if (i915
.enable_execlists
)
1542 if (!USES_PPGTT(dev
))
1546 gen6_ppgtt_enable(dev
);
1547 else if (IS_GEN7(dev
))
1548 gen7_ppgtt_enable(dev
);
1549 else if (INTEL_INFO(dev
)->gen
>= 8)
1550 gen8_ppgtt_enable(dev
);
1552 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1557 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1559 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1560 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1562 if (i915
.enable_execlists
)
1568 return ppgtt
->switch_mm(ppgtt
, req
);
1571 struct i915_hw_ppgtt
*
1572 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1574 struct i915_hw_ppgtt
*ppgtt
;
1577 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1579 return ERR_PTR(-ENOMEM
);
1581 ret
= i915_ppgtt_init(dev
, ppgtt
);
1584 return ERR_PTR(ret
);
1587 ppgtt
->file_priv
= fpriv
;
1589 trace_i915_ppgtt_create(&ppgtt
->base
);
1594 void i915_ppgtt_release(struct kref
*kref
)
1596 struct i915_hw_ppgtt
*ppgtt
=
1597 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1599 trace_i915_ppgtt_release(&ppgtt
->base
);
1601 /* vmas should already be unbound */
1602 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1603 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1605 list_del(&ppgtt
->base
.global_link
);
1606 drm_mm_takedown(&ppgtt
->base
.mm
);
1608 ppgtt
->base
.cleanup(&ppgtt
->base
);
1612 extern int intel_iommu_gfx_mapped
;
1613 /* Certain Gen5 chipsets require require idling the GPU before
1614 * unmapping anything from the GTT when VT-d is enabled.
1616 static bool needs_idle_maps(struct drm_device
*dev
)
1618 #ifdef CONFIG_INTEL_IOMMU
1619 /* Query intel_iommu to see if we need the workaround. Presumably that
1622 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1628 static bool do_idling(struct drm_i915_private
*dev_priv
)
1630 bool ret
= dev_priv
->mm
.interruptible
;
1632 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1633 dev_priv
->mm
.interruptible
= false;
1634 if (i915_gpu_idle(dev_priv
->dev
)) {
1635 DRM_ERROR("Couldn't idle GPU\n");
1636 /* Wait a bit, in hopes it avoids the hang */
1644 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1646 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1647 dev_priv
->mm
.interruptible
= interruptible
;
1650 void i915_check_and_clear_faults(struct drm_device
*dev
)
1652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 struct intel_engine_cs
*ring
;
1656 if (INTEL_INFO(dev
)->gen
< 6)
1659 for_each_ring(ring
, dev_priv
, i
) {
1661 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1662 if (fault_reg
& RING_FAULT_VALID
) {
1663 DRM_DEBUG_DRIVER("Unexpected fault\n"
1665 "\tAddress space: %s\n"
1668 fault_reg
& PAGE_MASK
,
1669 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1670 RING_FAULT_SRCID(fault_reg
),
1671 RING_FAULT_FAULT_TYPE(fault_reg
));
1672 I915_WRITE(RING_FAULT_REG(ring
),
1673 fault_reg
& ~RING_FAULT_VALID
);
1676 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1679 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1681 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1682 intel_gtt_chipset_flush();
1684 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1685 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1689 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1693 /* Don't bother messing with faults pre GEN6 as we have little
1694 * documentation supporting that it's a good idea.
1696 if (INTEL_INFO(dev
)->gen
< 6)
1699 i915_check_and_clear_faults(dev
);
1701 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1702 dev_priv
->gtt
.base
.start
,
1703 dev_priv
->gtt
.base
.total
,
1706 i915_ggtt_flush(dev_priv
);
1709 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1711 if (obj
->has_dma_mapping
)
1714 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1715 obj
->pages
->sgl
, obj
->pages
->nents
,
1716 PCI_DMA_BIDIRECTIONAL
))
1722 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1727 iowrite32((u32
)pte
, addr
);
1728 iowrite32(pte
>> 32, addr
+ 4);
1732 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1733 struct sg_table
*st
,
1735 enum i915_cache_level level
, u32 unused
)
1737 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1738 unsigned first_entry
= start
>> PAGE_SHIFT
;
1739 gen8_pte_t __iomem
*gtt_entries
=
1740 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1742 struct sg_page_iter sg_iter
;
1743 dma_addr_t addr
= 0; /* shut up gcc */
1745 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1746 addr
= sg_dma_address(sg_iter
.sg
) +
1747 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1748 gen8_set_pte(>t_entries
[i
],
1749 gen8_pte_encode(addr
, level
, true));
1754 * XXX: This serves as a posting read to make sure that the PTE has
1755 * actually been updated. There is some concern that even though
1756 * registers and PTEs are within the same BAR that they are potentially
1757 * of NUMA access patterns. Therefore, even with the way we assume
1758 * hardware should work, we must keep this posting read for paranoia.
1761 WARN_ON(readq(>t_entries
[i
-1])
1762 != gen8_pte_encode(addr
, level
, true));
1764 /* This next bit makes the above posting read even more important. We
1765 * want to flush the TLBs only after we're certain all the PTE updates
1768 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1769 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1773 * Binds an object into the global gtt with the specified cache level. The object
1774 * will be accessible to the GPU via commands whose operands reference offsets
1775 * within the global GTT as well as accessible by the GPU through the GMADR
1776 * mapped BAR (dev_priv->mm.gtt->gtt).
1778 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1779 struct sg_table
*st
,
1781 enum i915_cache_level level
, u32 flags
)
1783 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1784 unsigned first_entry
= start
>> PAGE_SHIFT
;
1785 gen6_pte_t __iomem
*gtt_entries
=
1786 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1788 struct sg_page_iter sg_iter
;
1789 dma_addr_t addr
= 0;
1791 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1792 addr
= sg_page_iter_dma_address(&sg_iter
);
1793 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1797 /* XXX: This serves as a posting read to make sure that the PTE has
1798 * actually been updated. There is some concern that even though
1799 * registers and PTEs are within the same BAR that they are potentially
1800 * of NUMA access patterns. Therefore, even with the way we assume
1801 * hardware should work, we must keep this posting read for paranoia.
1804 unsigned long gtt
= readl(>t_entries
[i
-1]);
1805 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1808 /* This next bit makes the above posting read even more important. We
1809 * want to flush the TLBs only after we're certain all the PTE updates
1812 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1813 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1816 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1821 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1822 unsigned first_entry
= start
>> PAGE_SHIFT
;
1823 unsigned num_entries
= length
>> PAGE_SHIFT
;
1824 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1825 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1826 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1829 if (WARN(num_entries
> max_entries
,
1830 "First entry = %d; Num entries = %d (max=%d)\n",
1831 first_entry
, num_entries
, max_entries
))
1832 num_entries
= max_entries
;
1834 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
1837 for (i
= 0; i
< num_entries
; i
++)
1838 gen8_set_pte(>t_base
[i
], scratch_pte
);
1842 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1847 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1848 unsigned first_entry
= start
>> PAGE_SHIFT
;
1849 unsigned num_entries
= length
>> PAGE_SHIFT
;
1850 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1851 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1852 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1855 if (WARN(num_entries
> max_entries
,
1856 "First entry = %d; Num entries = %d (max=%d)\n",
1857 first_entry
, num_entries
, max_entries
))
1858 num_entries
= max_entries
;
1860 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, use_scratch
, 0);
1862 for (i
= 0; i
< num_entries
; i
++)
1863 iowrite32(scratch_pte
, >t_base
[i
]);
1867 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
1868 struct sg_table
*pages
,
1870 enum i915_cache_level cache_level
, u32 unused
)
1872 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1873 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1875 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
1879 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1884 unsigned first_entry
= start
>> PAGE_SHIFT
;
1885 unsigned num_entries
= length
>> PAGE_SHIFT
;
1886 intel_gtt_clear_range(first_entry
, num_entries
);
1889 static int ggtt_bind_vma(struct i915_vma
*vma
,
1890 enum i915_cache_level cache_level
,
1893 struct drm_device
*dev
= vma
->vm
->dev
;
1894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1895 struct drm_i915_gem_object
*obj
= vma
->obj
;
1896 struct sg_table
*pages
= obj
->pages
;
1900 ret
= i915_get_ggtt_vma_pages(vma
);
1903 pages
= vma
->ggtt_view
.pages
;
1905 /* Currently applicable only to VLV */
1907 pte_flags
|= PTE_READ_ONLY
;
1910 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1911 vma
->vm
->insert_entries(vma
->vm
, pages
,
1913 cache_level
, pte_flags
);
1916 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
1917 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1918 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
1920 cache_level
, pte_flags
);
1926 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1928 struct drm_device
*dev
= vma
->vm
->dev
;
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1930 struct drm_i915_gem_object
*obj
= vma
->obj
;
1931 const uint64_t size
= min_t(uint64_t,
1935 if (vma
->bound
& GLOBAL_BIND
) {
1936 vma
->vm
->clear_range(vma
->vm
,
1942 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
1943 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1945 appgtt
->base
.clear_range(&appgtt
->base
,
1952 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1954 struct drm_device
*dev
= obj
->base
.dev
;
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1958 interruptible
= do_idling(dev_priv
);
1960 if (!obj
->has_dma_mapping
)
1961 dma_unmap_sg(&dev
->pdev
->dev
,
1962 obj
->pages
->sgl
, obj
->pages
->nents
,
1963 PCI_DMA_BIDIRECTIONAL
);
1965 undo_idling(dev_priv
, interruptible
);
1968 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1969 unsigned long color
,
1973 if (node
->color
!= color
)
1976 if (!list_empty(&node
->node_list
)) {
1977 node
= list_entry(node
->node_list
.next
,
1980 if (node
->allocated
&& node
->color
!= color
)
1985 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
1986 unsigned long start
,
1987 unsigned long mappable_end
,
1990 /* Let GEM Manage all of the aperture.
1992 * However, leave one page at the end still bound to the scratch page.
1993 * There are a number of places where the hardware apparently prefetches
1994 * past the end of the object, and we've seen multiple hangs with the
1995 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1996 * aperture. One page should be enough to keep any prefetching inside
1999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2000 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2001 struct drm_mm_node
*entry
;
2002 struct drm_i915_gem_object
*obj
;
2003 unsigned long hole_start
, hole_end
;
2006 BUG_ON(mappable_end
> end
);
2008 /* Subtract the guard page ... */
2009 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2011 dev_priv
->gtt
.base
.start
= start
;
2012 dev_priv
->gtt
.base
.total
= end
- start
;
2014 if (intel_vgpu_active(dev
)) {
2015 ret
= intel_vgt_balloon(dev
);
2021 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2023 /* Mark any preallocated objects as occupied */
2024 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2025 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2027 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2028 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2030 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2031 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2033 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2036 vma
->bound
|= GLOBAL_BIND
;
2039 /* Clear any non-preallocated blocks */
2040 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2041 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2042 hole_start
, hole_end
);
2043 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2044 hole_end
- hole_start
, true);
2047 /* And finally clear the reserved guard page */
2048 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2050 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2051 struct i915_hw_ppgtt
*ppgtt
;
2053 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2057 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2059 ppgtt
->base
.cleanup(&ppgtt
->base
);
2064 if (ppgtt
->base
.allocate_va_range
)
2065 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2068 ppgtt
->base
.cleanup(&ppgtt
->base
);
2073 ppgtt
->base
.clear_range(&ppgtt
->base
,
2078 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2084 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2087 u64 gtt_size
, mappable_size
;
2089 gtt_size
= dev_priv
->gtt
.base
.total
;
2090 mappable_size
= dev_priv
->gtt
.mappable_end
;
2092 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2095 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2098 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2100 if (dev_priv
->mm
.aliasing_ppgtt
) {
2101 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2103 ppgtt
->base
.cleanup(&ppgtt
->base
);
2106 if (drm_mm_initialized(&vm
->mm
)) {
2107 if (intel_vgpu_active(dev
))
2108 intel_vgt_deballoon();
2110 drm_mm_takedown(&vm
->mm
);
2111 list_del(&vm
->global_link
);
2117 static int setup_scratch_page(struct drm_device
*dev
)
2119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2121 dma_addr_t dma_addr
;
2123 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
2126 set_pages_uc(page
, 1);
2128 #ifdef CONFIG_INTEL_IOMMU
2129 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
2130 PCI_DMA_BIDIRECTIONAL
);
2131 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
)) {
2136 dma_addr
= page_to_phys(page
);
2138 dev_priv
->gtt
.base
.scratch
.page
= page
;
2139 dev_priv
->gtt
.base
.scratch
.addr
= dma_addr
;
2144 static void teardown_scratch_page(struct drm_device
*dev
)
2146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2147 struct page
*page
= dev_priv
->gtt
.base
.scratch
.page
;
2149 set_pages_wb(page
, 1);
2150 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.base
.scratch
.addr
,
2151 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
2155 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2157 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2158 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2159 return snb_gmch_ctl
<< 20;
2162 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2164 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2165 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2167 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2169 #ifdef CONFIG_X86_32
2170 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2171 if (bdw_gmch_ctl
> 4)
2175 return bdw_gmch_ctl
<< 20;
2178 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2180 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2181 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2184 return 1 << (20 + gmch_ctrl
);
2189 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2191 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2192 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2193 return snb_gmch_ctl
<< 25; /* 32 MB units */
2196 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2198 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2199 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2200 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2203 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2205 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2206 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2209 * 0x0 to 0x10: 32MB increments starting at 0MB
2210 * 0x11 to 0x16: 4MB increments starting at 8MB
2211 * 0x17 to 0x1d: 4MB increments start at 36MB
2213 if (gmch_ctrl
< 0x11)
2214 return gmch_ctrl
<< 25;
2215 else if (gmch_ctrl
< 0x17)
2216 return (gmch_ctrl
- 0x11 + 2) << 22;
2218 return (gmch_ctrl
- 0x17 + 9) << 22;
2221 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2223 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2224 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2226 if (gen9_gmch_ctl
< 0xf0)
2227 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2229 /* 4MB increments starting at 0xf0 for 4MB */
2230 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2233 static int ggtt_probe_common(struct drm_device
*dev
,
2236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2237 phys_addr_t gtt_phys_addr
;
2240 /* For Modern GENs the PTEs and register space are split in the BAR */
2241 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2242 (pci_resource_len(dev
->pdev
, 0) / 2);
2245 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2246 * dropped. For WC mappings in general we have 64 byte burst writes
2247 * when the WC buffer is flushed, so we can't use it, but have to
2248 * resort to an uncached mapping. The WC issue is easily caught by the
2249 * readback check when writing GTT PTE entries.
2251 if (IS_BROXTON(dev
))
2252 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2254 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2255 if (!dev_priv
->gtt
.gsm
) {
2256 DRM_ERROR("Failed to map the gtt page table\n");
2260 ret
= setup_scratch_page(dev
);
2262 DRM_ERROR("Scratch setup failed\n");
2263 /* iounmap will also get called at remove, but meh */
2264 iounmap(dev_priv
->gtt
.gsm
);
2270 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2271 * bits. When using advanced contexts each context stores its own PAT, but
2272 * writing this data shouldn't be harmful even in those cases. */
2273 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2277 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2278 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2279 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2280 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2281 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2282 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2283 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2284 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2286 if (!USES_PPGTT(dev_priv
->dev
))
2287 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2288 * so RTL will always use the value corresponding to
2290 * So let's disable cache for GGTT to avoid screen corruptions.
2291 * MOCS still can be used though.
2292 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2293 * before this patch, i.e. the same uncached + snooping access
2294 * like on gen6/7 seems to be in effect.
2295 * - So this just fixes blitter/render access. Again it looks
2296 * like it's not just uncached access, but uncached + snooping.
2297 * So we can still hold onto all our assumptions wrt cpu
2298 * clflushing on LLC machines.
2300 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2302 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2303 * write would work. */
2304 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2305 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2308 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2313 * Map WB on BDW to snooped on CHV.
2315 * Only the snoop bit has meaning for CHV, the rest is
2318 * The hardware will never snoop for certain types of accesses:
2319 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2320 * - PPGTT page tables
2321 * - some other special cycles
2323 * As with BDW, we also need to consider the following for GT accesses:
2324 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2325 * so RTL will always use the value corresponding to
2327 * Which means we must set the snoop bit in PAT entry 0
2328 * in order to keep the global status page working.
2330 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2334 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2335 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2336 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2337 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2339 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2340 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2343 static int gen8_gmch_probe(struct drm_device
*dev
,
2346 phys_addr_t
*mappable_base
,
2349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2354 /* TODO: We're not aware of mappable constraints on gen8 yet */
2355 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2356 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2358 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2359 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2361 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2363 if (INTEL_INFO(dev
)->gen
>= 9) {
2364 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2365 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2366 } else if (IS_CHERRYVIEW(dev
)) {
2367 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2368 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2370 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2371 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2374 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2376 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2377 chv_setup_private_ppat(dev_priv
);
2379 bdw_setup_private_ppat(dev_priv
);
2381 ret
= ggtt_probe_common(dev
, gtt_size
);
2383 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2384 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2385 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2386 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2391 static int gen6_gmch_probe(struct drm_device
*dev
,
2394 phys_addr_t
*mappable_base
,
2397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2398 unsigned int gtt_size
;
2402 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2403 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2405 /* 64/512MB is the current min/max we actually know of, but this is just
2406 * a coarse sanity check.
2408 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2409 DRM_ERROR("Unknown GMADR size (%llx)\n",
2410 dev_priv
->gtt
.mappable_end
);
2414 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2415 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2416 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2418 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2420 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2421 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2423 ret
= ggtt_probe_common(dev
, gtt_size
);
2425 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2426 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2427 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2428 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2433 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2436 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2439 teardown_scratch_page(vm
->dev
);
2442 static int i915_gmch_probe(struct drm_device
*dev
,
2445 phys_addr_t
*mappable_base
,
2448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2451 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2453 DRM_ERROR("failed to set up gmch\n");
2457 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2459 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2460 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2461 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2462 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2463 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2465 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2466 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2471 static void i915_gmch_remove(struct i915_address_space
*vm
)
2473 intel_gmch_remove();
2476 int i915_gem_gtt_init(struct drm_device
*dev
)
2478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2479 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2482 if (INTEL_INFO(dev
)->gen
<= 5) {
2483 gtt
->gtt_probe
= i915_gmch_probe
;
2484 gtt
->base
.cleanup
= i915_gmch_remove
;
2485 } else if (INTEL_INFO(dev
)->gen
< 8) {
2486 gtt
->gtt_probe
= gen6_gmch_probe
;
2487 gtt
->base
.cleanup
= gen6_gmch_remove
;
2488 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2489 gtt
->base
.pte_encode
= iris_pte_encode
;
2490 else if (IS_HASWELL(dev
))
2491 gtt
->base
.pte_encode
= hsw_pte_encode
;
2492 else if (IS_VALLEYVIEW(dev
))
2493 gtt
->base
.pte_encode
= byt_pte_encode
;
2494 else if (INTEL_INFO(dev
)->gen
>= 7)
2495 gtt
->base
.pte_encode
= ivb_pte_encode
;
2497 gtt
->base
.pte_encode
= snb_pte_encode
;
2499 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2500 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2503 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2504 >t
->mappable_base
, >t
->mappable_end
);
2508 gtt
->base
.dev
= dev
;
2510 /* GMADR is the PCI mmio aperture into the global GTT. */
2511 DRM_INFO("Memory usable by graphics device = %lluM\n",
2512 gtt
->base
.total
>> 20);
2513 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
2514 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2515 #ifdef CONFIG_INTEL_IOMMU
2516 if (intel_iommu_gfx_mapped
)
2517 DRM_INFO("VT-d active for gfx access\n");
2520 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2521 * user's requested state against the hardware/driver capabilities. We
2522 * do this now so that we can print out any log messages once rather
2523 * than every time we check intel_enable_ppgtt().
2525 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2526 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2531 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2534 struct drm_i915_gem_object
*obj
;
2535 struct i915_address_space
*vm
;
2537 i915_check_and_clear_faults(dev
);
2539 /* First fill our portion of the GTT with scratch pages */
2540 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2541 dev_priv
->gtt
.base
.start
,
2542 dev_priv
->gtt
.base
.total
,
2545 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2546 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
2547 &dev_priv
->gtt
.base
);
2551 i915_gem_clflush_object(obj
, obj
->pin_display
);
2552 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, PIN_UPDATE
));
2556 if (INTEL_INFO(dev
)->gen
>= 8) {
2557 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2558 chv_setup_private_ppat(dev_priv
);
2560 bdw_setup_private_ppat(dev_priv
);
2565 if (USES_PPGTT(dev
)) {
2566 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2567 /* TODO: Perhaps it shouldn't be gen6 specific */
2569 struct i915_hw_ppgtt
*ppgtt
=
2570 container_of(vm
, struct i915_hw_ppgtt
,
2573 if (i915_is_ggtt(vm
))
2574 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2576 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2577 0, ppgtt
->base
.total
);
2581 i915_ggtt_flush(dev_priv
);
2584 static struct i915_vma
*
2585 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2586 struct i915_address_space
*vm
,
2587 const struct i915_ggtt_view
*ggtt_view
)
2589 struct i915_vma
*vma
;
2591 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2592 return ERR_PTR(-EINVAL
);
2594 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
2596 return ERR_PTR(-ENOMEM
);
2598 INIT_LIST_HEAD(&vma
->vma_link
);
2599 INIT_LIST_HEAD(&vma
->mm_list
);
2600 INIT_LIST_HEAD(&vma
->exec_list
);
2604 if (i915_is_ggtt(vm
))
2605 vma
->ggtt_view
= *ggtt_view
;
2607 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2608 if (!i915_is_ggtt(vm
))
2609 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2615 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2616 struct i915_address_space
*vm
)
2618 struct i915_vma
*vma
;
2620 vma
= i915_gem_obj_to_vma(obj
, vm
);
2622 vma
= __i915_gem_vma_create(obj
, vm
,
2623 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2629 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2630 const struct i915_ggtt_view
*view
)
2632 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2633 struct i915_vma
*vma
;
2636 return ERR_PTR(-EINVAL
);
2638 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2644 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2651 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2652 struct sg_table
*st
)
2654 unsigned int column
, row
;
2655 unsigned int src_idx
;
2656 struct scatterlist
*sg
= st
->sgl
;
2660 for (column
= 0; column
< width
; column
++) {
2661 src_idx
= width
* (height
- 1) + column
;
2662 for (row
= 0; row
< height
; row
++) {
2664 /* We don't need the pages, but need to initialize
2665 * the entries so the sg list can be happily traversed.
2666 * The only thing we need are DMA addresses.
2668 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2669 sg_dma_address(sg
) = in
[src_idx
];
2670 sg_dma_len(sg
) = PAGE_SIZE
;
2677 static struct sg_table
*
2678 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2679 struct drm_i915_gem_object
*obj
)
2681 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2682 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
2683 struct sg_page_iter sg_iter
;
2685 dma_addr_t
*page_addr_list
;
2686 struct sg_table
*st
;
2689 /* Allocate a temporary list of source pages for random access. */
2690 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
2691 sizeof(dma_addr_t
));
2692 if (!page_addr_list
)
2693 return ERR_PTR(ret
);
2695 /* Allocate target SG list. */
2696 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2700 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
2704 /* Populate source page list from the object. */
2706 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2707 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2711 /* Rotate the pages. */
2712 rotate_pages(page_addr_list
,
2713 rot_info
->width_pages
, rot_info
->height_pages
,
2717 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2718 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
2719 rot_info
->pixel_format
, rot_info
->width_pages
,
2720 rot_info
->height_pages
, size_pages
);
2722 drm_free_large(page_addr_list
);
2729 drm_free_large(page_addr_list
);
2732 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2733 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
2734 rot_info
->pixel_format
, rot_info
->width_pages
,
2735 rot_info
->height_pages
, size_pages
);
2736 return ERR_PTR(ret
);
2739 static struct sg_table
*
2740 intel_partial_pages(const struct i915_ggtt_view
*view
,
2741 struct drm_i915_gem_object
*obj
)
2743 struct sg_table
*st
;
2744 struct scatterlist
*sg
;
2745 struct sg_page_iter obj_sg_iter
;
2748 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2752 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2758 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2759 view
->params
.partial
.offset
)
2761 if (st
->nents
>= view
->params
.partial
.size
)
2764 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2765 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2766 sg_dma_len(sg
) = PAGE_SIZE
;
2777 return ERR_PTR(ret
);
2781 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2785 if (vma
->ggtt_view
.pages
)
2788 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2789 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2790 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2791 vma
->ggtt_view
.pages
=
2792 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2793 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2794 vma
->ggtt_view
.pages
=
2795 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2797 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2798 vma
->ggtt_view
.type
);
2800 if (!vma
->ggtt_view
.pages
) {
2801 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2802 vma
->ggtt_view
.type
);
2804 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2805 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2806 vma
->ggtt_view
.pages
= NULL
;
2807 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2808 vma
->ggtt_view
.type
, ret
);
2815 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2817 * @cache_level: mapping cache level
2818 * @flags: flags like global or local mapping
2820 * DMA addresses are taken from the scatter-gather table of this object (or of
2821 * this VMA in case of non-default GGTT views) and PTE entries set up.
2822 * Note that DMA addresses are also the only part of the SG table we care about.
2824 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2830 if (WARN_ON(flags
== 0))
2834 if (flags
& PIN_GLOBAL
)
2835 bind_flags
|= GLOBAL_BIND
;
2836 if (flags
& PIN_USER
)
2837 bind_flags
|= LOCAL_BIND
;
2839 if (flags
& PIN_UPDATE
)
2840 bind_flags
|= vma
->bound
;
2842 bind_flags
&= ~vma
->bound
;
2844 if (bind_flags
== 0)
2847 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
2848 trace_i915_va_alloc(vma
->vm
,
2851 VM_TO_TRACE_NAME(vma
->vm
));
2853 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
2860 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
2864 vma
->bound
|= bind_flags
;
2870 * i915_ggtt_view_size - Get the size of a GGTT view.
2871 * @obj: Object the view is of.
2872 * @view: The view in question.
2874 * @return The size of the GGTT view in bytes.
2877 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
2878 const struct i915_ggtt_view
*view
)
2880 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
2881 return obj
->base
.size
;
2882 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
2883 return view
->rotation_info
.size
;
2884 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
2885 return view
->params
.partial
.size
<< PAGE_SHIFT
;
2887 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
2888 return obj
->base
.size
;