2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 typedef uint32_t gen6_gtt_pte_t
;
34 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
36 #define GEN6_PDE_VALID (1 << 0)
37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
38 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
40 #define GEN6_PTE_VALID (1 << 0)
41 #define GEN6_PTE_UNCACHED (1 << 1)
42 #define HSW_PTE_UNCACHED (0)
43 #define GEN6_PTE_CACHE_LLC (2 << 1)
44 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
45 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
47 static inline gen6_gtt_pte_t
gen6_pte_encode(struct drm_device
*dev
,
49 enum i915_cache_level level
)
51 gen6_gtt_pte_t pte
= GEN6_PTE_VALID
;
52 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
55 case I915_CACHE_LLC_MLC
:
56 /* Haswell doesn't set L3 this way */
58 pte
|= GEN6_PTE_CACHE_LLC
;
60 pte
|= GEN6_PTE_CACHE_LLC_MLC
;
63 pte
|= GEN6_PTE_CACHE_LLC
;
67 pte
|= HSW_PTE_UNCACHED
;
69 pte
|= GEN6_PTE_UNCACHED
;
78 static int gen6_ppgtt_enable(struct drm_device
*dev
)
80 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
82 struct intel_ring_buffer
*ring
;
83 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
84 gen6_gtt_pte_t __iomem
*pd_addr
;
88 pd_addr
= (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
89 ppgtt
->pd_offset
/ sizeof(gen6_gtt_pte_t
);
90 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
93 pt_addr
= ppgtt
->pt_dma_addr
[i
];
94 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
95 pd_entry
|= GEN6_PDE_VALID
;
97 writel(pd_entry
, pd_addr
+ i
);
101 pd_offset
= ppgtt
->pd_offset
;
102 pd_offset
/= 64; /* in cachelines, */
105 if (INTEL_INFO(dev
)->gen
== 6) {
106 uint32_t ecochk
, gab_ctl
, ecobits
;
108 ecobits
= I915_READ(GAC_ECO_BITS
);
109 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
110 ECOBITS_PPGTT_CACHE64B
);
112 gab_ctl
= I915_READ(GAB_CTL
);
113 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
115 ecochk
= I915_READ(GAM_ECOCHK
);
116 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
117 ECOCHK_PPGTT_CACHE64B
);
118 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
119 } else if (INTEL_INFO(dev
)->gen
>= 7) {
120 uint32_t ecochk
, ecobits
;
122 ecobits
= I915_READ(GAC_ECO_BITS
);
123 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
125 ecochk
= I915_READ(GAM_ECOCHK
);
126 if (IS_HASWELL(dev
)) {
127 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
129 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
130 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
132 I915_WRITE(GAM_ECOCHK
, ecochk
);
133 /* GFX_MODE is per-ring on gen7+ */
136 for_each_ring(ring
, dev_priv
, i
) {
137 if (INTEL_INFO(dev
)->gen
>= 7)
138 I915_WRITE(RING_MODE_GEN7(ring
),
139 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
141 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
142 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
147 /* PPGTT support for Sandybdrige/Gen6 and later */
148 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt
*ppgtt
,
149 unsigned first_entry
,
150 unsigned num_entries
)
152 gen6_gtt_pte_t
*pt_vaddr
, scratch_pte
;
153 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
154 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
155 unsigned last_pte
, i
;
157 scratch_pte
= gen6_pte_encode(ppgtt
->dev
,
158 ppgtt
->scratch_page_dma_addr
,
161 while (num_entries
) {
162 last_pte
= first_pte
+ num_entries
;
163 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
164 last_pte
= I915_PPGTT_PT_ENTRIES
;
166 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
168 for (i
= first_pte
; i
< last_pte
; i
++)
169 pt_vaddr
[i
] = scratch_pte
;
171 kunmap_atomic(pt_vaddr
);
173 num_entries
-= last_pte
- first_pte
;
179 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt
*ppgtt
,
180 struct sg_table
*pages
,
181 unsigned first_entry
,
182 enum i915_cache_level cache_level
)
184 gen6_gtt_pte_t
*pt_vaddr
;
185 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
186 unsigned act_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
187 struct sg_page_iter sg_iter
;
189 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
190 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
191 dma_addr_t page_addr
;
193 page_addr
= sg_page_iter_dma_address(&sg_iter
);
194 pt_vaddr
[act_pte
] = gen6_pte_encode(ppgtt
->dev
, page_addr
,
196 if (++act_pte
== I915_PPGTT_PT_ENTRIES
) {
197 kunmap_atomic(pt_vaddr
);
199 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
204 kunmap_atomic(pt_vaddr
);
207 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt
*ppgtt
)
211 if (ppgtt
->pt_dma_addr
) {
212 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
213 pci_unmap_page(ppgtt
->dev
->pdev
,
214 ppgtt
->pt_dma_addr
[i
],
215 4096, PCI_DMA_BIDIRECTIONAL
);
218 kfree(ppgtt
->pt_dma_addr
);
219 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
220 __free_page(ppgtt
->pt_pages
[i
]);
221 kfree(ppgtt
->pt_pages
);
225 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
227 struct drm_device
*dev
= ppgtt
->dev
;
228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
229 unsigned first_pd_entry_in_global_pt
;
233 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
234 * entries. For aliasing ppgtt support we just steal them at the end for
236 first_pd_entry_in_global_pt
=
237 gtt_total_entries(dev_priv
->gtt
) - I915_PPGTT_PD_ENTRIES
;
239 ppgtt
->num_pd_entries
= I915_PPGTT_PD_ENTRIES
;
240 ppgtt
->enable
= gen6_ppgtt_enable
;
241 ppgtt
->clear_range
= gen6_ppgtt_clear_range
;
242 ppgtt
->insert_entries
= gen6_ppgtt_insert_entries
;
243 ppgtt
->cleanup
= gen6_ppgtt_cleanup
;
244 ppgtt
->pt_pages
= kzalloc(sizeof(struct page
*)*ppgtt
->num_pd_entries
,
246 if (!ppgtt
->pt_pages
)
249 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
250 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
251 if (!ppgtt
->pt_pages
[i
])
255 ppgtt
->pt_dma_addr
= kzalloc(sizeof(dma_addr_t
) *ppgtt
->num_pd_entries
,
257 if (!ppgtt
->pt_dma_addr
)
260 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
263 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
264 PCI_DMA_BIDIRECTIONAL
);
266 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
271 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
274 ppgtt
->clear_range(ppgtt
, 0,
275 ppgtt
->num_pd_entries
*I915_PPGTT_PT_ENTRIES
);
277 ppgtt
->pd_offset
= first_pd_entry_in_global_pt
* sizeof(gen6_gtt_pte_t
);
282 if (ppgtt
->pt_dma_addr
) {
283 for (i
--; i
>= 0; i
--)
284 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
285 4096, PCI_DMA_BIDIRECTIONAL
);
288 kfree(ppgtt
->pt_dma_addr
);
289 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
290 if (ppgtt
->pt_pages
[i
])
291 __free_page(ppgtt
->pt_pages
[i
]);
293 kfree(ppgtt
->pt_pages
);
298 static int i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
)
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
301 struct i915_hw_ppgtt
*ppgtt
;
304 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
309 ppgtt
->scratch_page_dma_addr
= dev_priv
->gtt
.scratch_page_dma
;
311 if (INTEL_INFO(dev
)->gen
< 8)
312 ret
= gen6_ppgtt_init(ppgtt
);
319 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
324 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
)
326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
332 ppgtt
->cleanup(ppgtt
);
333 dev_priv
->mm
.aliasing_ppgtt
= NULL
;
336 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
337 struct drm_i915_gem_object
*obj
,
338 enum i915_cache_level cache_level
)
340 ppgtt
->insert_entries(ppgtt
, obj
->pages
,
341 obj
->gtt_space
->start
>> PAGE_SHIFT
,
345 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
346 struct drm_i915_gem_object
*obj
)
348 ppgtt
->clear_range(ppgtt
,
349 obj
->gtt_space
->start
>> PAGE_SHIFT
,
350 obj
->base
.size
>> PAGE_SHIFT
);
353 extern int intel_iommu_gfx_mapped
;
354 /* Certain Gen5 chipsets require require idling the GPU before
355 * unmapping anything from the GTT when VT-d is enabled.
357 static inline bool needs_idle_maps(struct drm_device
*dev
)
359 #ifdef CONFIG_INTEL_IOMMU
360 /* Query intel_iommu to see if we need the workaround. Presumably that
363 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
369 static bool do_idling(struct drm_i915_private
*dev_priv
)
371 bool ret
= dev_priv
->mm
.interruptible
;
373 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
374 dev_priv
->mm
.interruptible
= false;
375 if (i915_gpu_idle(dev_priv
->dev
)) {
376 DRM_ERROR("Couldn't idle GPU\n");
377 /* Wait a bit, in hopes it avoids the hang */
385 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
387 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
388 dev_priv
->mm
.interruptible
= interruptible
;
391 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
394 struct drm_i915_gem_object
*obj
;
396 /* First fill our portion of the GTT with scratch pages */
397 dev_priv
->gtt
.gtt_clear_range(dev
, dev_priv
->gtt
.start
/ PAGE_SIZE
,
398 dev_priv
->gtt
.total
/ PAGE_SIZE
);
400 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
401 i915_gem_clflush_object(obj
);
402 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
405 i915_gem_chipset_flush(dev
);
408 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
410 if (obj
->has_dma_mapping
)
413 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
414 obj
->pages
->sgl
, obj
->pages
->nents
,
415 PCI_DMA_BIDIRECTIONAL
))
422 * Binds an object into the global gtt with the specified cache level. The object
423 * will be accessible to the GPU via commands whose operands reference offsets
424 * within the global GTT as well as accessible by the GPU through the GMADR
425 * mapped BAR (dev_priv->mm.gtt->gtt).
427 static void gen6_ggtt_insert_entries(struct drm_device
*dev
,
429 unsigned int first_entry
,
430 enum i915_cache_level level
)
432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
433 gen6_gtt_pte_t __iomem
*gtt_entries
=
434 (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
436 struct sg_page_iter sg_iter
;
439 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
440 addr
= sg_page_iter_dma_address(&sg_iter
);
441 iowrite32(gen6_pte_encode(dev
, addr
, level
), >t_entries
[i
]);
445 /* XXX: This serves as a posting read to make sure that the PTE has
446 * actually been updated. There is some concern that even though
447 * registers and PTEs are within the same BAR that they are potentially
448 * of NUMA access patterns. Therefore, even with the way we assume
449 * hardware should work, we must keep this posting read for paranoia.
452 WARN_ON(readl(>t_entries
[i
-1])
453 != gen6_pte_encode(dev
, addr
, level
));
455 /* This next bit makes the above posting read even more important. We
456 * want to flush the TLBs only after we're certain all the PTE updates
459 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
460 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
463 static void gen6_ggtt_clear_range(struct drm_device
*dev
,
464 unsigned int first_entry
,
465 unsigned int num_entries
)
467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
468 gen6_gtt_pte_t scratch_pte
, __iomem
*gtt_base
=
469 (gen6_gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
470 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
473 if (WARN(num_entries
> max_entries
,
474 "First entry = %d; Num entries = %d (max=%d)\n",
475 first_entry
, num_entries
, max_entries
))
476 num_entries
= max_entries
;
478 scratch_pte
= gen6_pte_encode(dev
, dev_priv
->gtt
.scratch_page_dma
,
480 for (i
= 0; i
< num_entries
; i
++)
481 iowrite32(scratch_pte
, >t_base
[i
]);
486 static void i915_ggtt_insert_entries(struct drm_device
*dev
,
488 unsigned int pg_start
,
489 enum i915_cache_level cache_level
)
491 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
492 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
494 intel_gtt_insert_sg_entries(st
, pg_start
, flags
);
498 static void i915_ggtt_clear_range(struct drm_device
*dev
,
499 unsigned int first_entry
,
500 unsigned int num_entries
)
502 intel_gtt_clear_range(first_entry
, num_entries
);
506 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
507 enum i915_cache_level cache_level
)
509 struct drm_device
*dev
= obj
->base
.dev
;
510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
512 dev_priv
->gtt
.gtt_insert_entries(dev
, obj
->pages
,
513 obj
->gtt_space
->start
>> PAGE_SHIFT
,
516 obj
->has_global_gtt_mapping
= 1;
519 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
)
521 struct drm_device
*dev
= obj
->base
.dev
;
522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
524 dev_priv
->gtt
.gtt_clear_range(obj
->base
.dev
,
525 obj
->gtt_space
->start
>> PAGE_SHIFT
,
526 obj
->base
.size
>> PAGE_SHIFT
);
528 obj
->has_global_gtt_mapping
= 0;
531 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
533 struct drm_device
*dev
= obj
->base
.dev
;
534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
537 interruptible
= do_idling(dev_priv
);
539 if (!obj
->has_dma_mapping
)
540 dma_unmap_sg(&dev
->pdev
->dev
,
541 obj
->pages
->sgl
, obj
->pages
->nents
,
542 PCI_DMA_BIDIRECTIONAL
);
544 undo_idling(dev_priv
, interruptible
);
547 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
549 unsigned long *start
,
552 if (node
->color
!= color
)
555 if (!list_empty(&node
->node_list
)) {
556 node
= list_entry(node
->node_list
.next
,
559 if (node
->allocated
&& node
->color
!= color
)
563 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
565 unsigned long mappable_end
,
568 /* Let GEM Manage all of the aperture.
570 * However, leave one page at the end still bound to the scratch page.
571 * There are a number of places where the hardware apparently prefetches
572 * past the end of the object, and we've seen multiple hangs with the
573 * GPU head pointer stuck in a batchbuffer bound at the last page of the
574 * aperture. One page should be enough to keep any prefetching inside
577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
578 struct drm_mm_node
*entry
;
579 struct drm_i915_gem_object
*obj
;
580 unsigned long hole_start
, hole_end
;
582 BUG_ON(mappable_end
> end
);
584 /* Subtract the guard page ... */
585 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
- PAGE_SIZE
);
587 dev_priv
->mm
.gtt_space
.color_adjust
= i915_gtt_color_adjust
;
589 /* Mark any preallocated objects as occupied */
590 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
591 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
592 obj
->gtt_offset
, obj
->base
.size
);
594 BUG_ON(obj
->gtt_space
!= I915_GTT_RESERVED
);
595 obj
->gtt_space
= drm_mm_create_block(&dev_priv
->mm
.gtt_space
,
599 obj
->has_global_gtt_mapping
= 1;
602 dev_priv
->gtt
.start
= start
;
603 dev_priv
->gtt
.total
= end
- start
;
605 /* Clear any non-preallocated blocks */
606 drm_mm_for_each_hole(entry
, &dev_priv
->mm
.gtt_space
,
607 hole_start
, hole_end
) {
608 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
609 hole_start
, hole_end
);
610 dev_priv
->gtt
.gtt_clear_range(dev
, hole_start
/ PAGE_SIZE
,
611 (hole_end
-hole_start
) / PAGE_SIZE
);
614 /* And finally clear the reserved guard page */
615 dev_priv
->gtt
.gtt_clear_range(dev
, end
/ PAGE_SIZE
- 1, 1);
619 intel_enable_ppgtt(struct drm_device
*dev
)
621 if (i915_enable_ppgtt
>= 0)
622 return i915_enable_ppgtt
;
624 #ifdef CONFIG_INTEL_IOMMU
625 /* Disable ppgtt on SNB if VT-d is on. */
626 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
633 void i915_gem_init_global_gtt(struct drm_device
*dev
)
635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
636 unsigned long gtt_size
, mappable_size
;
638 gtt_size
= dev_priv
->gtt
.total
;
639 mappable_size
= dev_priv
->gtt
.mappable_end
;
641 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
644 if (INTEL_INFO(dev
)->gen
<= 7) {
645 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
646 * aperture accordingly when using aliasing ppgtt. */
647 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
650 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
652 ret
= i915_gem_init_aliasing_ppgtt(dev
);
656 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret
);
657 drm_mm_takedown(&dev_priv
->mm
.gtt_space
);
658 gtt_size
+= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
660 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
663 static int setup_scratch_page(struct drm_device
*dev
)
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
673 set_pages_uc(page
, 1);
675 #ifdef CONFIG_INTEL_IOMMU
676 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
677 PCI_DMA_BIDIRECTIONAL
);
678 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
681 dma_addr
= page_to_phys(page
);
683 dev_priv
->gtt
.scratch_page
= page
;
684 dev_priv
->gtt
.scratch_page_dma
= dma_addr
;
689 static void teardown_scratch_page(struct drm_device
*dev
)
691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
692 set_pages_wb(dev_priv
->gtt
.scratch_page
, 1);
693 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.scratch_page_dma
,
694 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
695 put_page(dev_priv
->gtt
.scratch_page
);
696 __free_page(dev_priv
->gtt
.scratch_page
);
699 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
701 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
702 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
703 return snb_gmch_ctl
<< 20;
706 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
708 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
709 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
710 return snb_gmch_ctl
<< 25; /* 32 MB units */
713 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl
)
715 static const int stolen_decoder
[] = {
716 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
717 snb_gmch_ctl
>>= IVB_GMCH_GMS_SHIFT
;
718 snb_gmch_ctl
&= IVB_GMCH_GMS_MASK
;
719 return stolen_decoder
[snb_gmch_ctl
] << 20;
722 static int gen6_gmch_probe(struct drm_device
*dev
,
725 phys_addr_t
*mappable_base
,
726 unsigned long *mappable_end
)
728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
729 phys_addr_t gtt_bus_addr
;
730 unsigned int gtt_size
;
734 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
735 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
737 /* 64/512MB is the current min/max we actually know of, but this is just
738 * a coarse sanity check.
740 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
741 DRM_ERROR("Unknown GMADR size (%lx)\n",
742 dev_priv
->gtt
.mappable_end
);
746 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
747 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
748 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
749 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
751 if (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
))
752 *stolen
= gen7_get_stolen_size(snb_gmch_ctl
);
754 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
756 *gtt_total
= (gtt_size
/ sizeof(gen6_gtt_pte_t
)) << PAGE_SHIFT
;
758 /* For Modern GENs the PTEs and register space are split in the BAR */
759 gtt_bus_addr
= pci_resource_start(dev
->pdev
, 0) +
760 (pci_resource_len(dev
->pdev
, 0) / 2);
762 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_bus_addr
, gtt_size
);
763 if (!dev_priv
->gtt
.gsm
) {
764 DRM_ERROR("Failed to map the gtt page table\n");
768 ret
= setup_scratch_page(dev
);
770 DRM_ERROR("Scratch setup failed\n");
772 dev_priv
->gtt
.gtt_clear_range
= gen6_ggtt_clear_range
;
773 dev_priv
->gtt
.gtt_insert_entries
= gen6_ggtt_insert_entries
;
778 static void gen6_gmch_remove(struct drm_device
*dev
)
780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
781 iounmap(dev_priv
->gtt
.gsm
);
782 teardown_scratch_page(dev_priv
->dev
);
785 static int i915_gmch_probe(struct drm_device
*dev
,
788 phys_addr_t
*mappable_base
,
789 unsigned long *mappable_end
)
791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
794 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
796 DRM_ERROR("failed to set up gmch\n");
800 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
802 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
803 dev_priv
->gtt
.gtt_clear_range
= i915_ggtt_clear_range
;
804 dev_priv
->gtt
.gtt_insert_entries
= i915_ggtt_insert_entries
;
809 static void i915_gmch_remove(struct drm_device
*dev
)
814 int i915_gem_gtt_init(struct drm_device
*dev
)
816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
817 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
818 unsigned long gtt_size
;
821 if (INTEL_INFO(dev
)->gen
<= 5) {
822 dev_priv
->gtt
.gtt_probe
= i915_gmch_probe
;
823 dev_priv
->gtt
.gtt_remove
= i915_gmch_remove
;
825 dev_priv
->gtt
.gtt_probe
= gen6_gmch_probe
;
826 dev_priv
->gtt
.gtt_remove
= gen6_gmch_remove
;
829 ret
= dev_priv
->gtt
.gtt_probe(dev
, &dev_priv
->gtt
.total
,
830 &dev_priv
->gtt
.stolen_size
,
836 gtt_size
= (dev_priv
->gtt
.total
>> PAGE_SHIFT
) * sizeof(gen6_gtt_pte_t
);
838 /* GMADR is the PCI mmio aperture into the global GTT. */
839 DRM_INFO("Memory usable by graphics device = %zdM\n",
840 dev_priv
->gtt
.total
>> 20);
841 DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
842 dev_priv
->gtt
.mappable_end
>> 20);
843 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
844 dev_priv
->gtt
.stolen_size
>> 20);