2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
95 const struct i915_ggtt_view i915_ggtt_view_normal
;
96 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
97 .type
= I915_GGTT_VIEW_ROTATED
100 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
);
101 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
);
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static void ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
152 static void ppgtt_unbind_vma(struct i915_vma
*vma
);
154 static inline gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
155 enum i915_cache_level level
,
158 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
162 case I915_CACHE_NONE
:
163 pte
|= PPAT_UNCACHED_INDEX
;
166 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
169 pte
|= PPAT_CACHED_INDEX
;
176 static inline gen8_pde_t
gen8_pde_encode(struct drm_device
*dev
,
178 enum i915_cache_level level
)
180 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
182 if (level
!= I915_CACHE_NONE
)
183 pde
|= PPAT_CACHED_PDE_INDEX
;
185 pde
|= PPAT_UNCACHED_INDEX
;
189 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
190 enum i915_cache_level level
,
191 bool valid
, u32 unused
)
193 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
194 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
197 case I915_CACHE_L3_LLC
:
199 pte
|= GEN6_PTE_CACHE_LLC
;
201 case I915_CACHE_NONE
:
202 pte
|= GEN6_PTE_UNCACHED
;
211 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
212 enum i915_cache_level level
,
213 bool valid
, u32 unused
)
215 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
216 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
219 case I915_CACHE_L3_LLC
:
220 pte
|= GEN7_PTE_CACHE_L3_LLC
;
223 pte
|= GEN6_PTE_CACHE_LLC
;
225 case I915_CACHE_NONE
:
226 pte
|= GEN6_PTE_UNCACHED
;
235 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
236 enum i915_cache_level level
,
237 bool valid
, u32 flags
)
239 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
240 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
242 if (!(flags
& PTE_READ_ONLY
))
243 pte
|= BYT_PTE_WRITEABLE
;
245 if (level
!= I915_CACHE_NONE
)
246 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
251 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
252 enum i915_cache_level level
,
253 bool valid
, u32 unused
)
255 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
256 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
258 if (level
!= I915_CACHE_NONE
)
259 pte
|= HSW_WB_LLC_AGE3
;
264 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
265 enum i915_cache_level level
,
266 bool valid
, u32 unused
)
268 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
269 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
272 case I915_CACHE_NONE
:
275 pte
|= HSW_WT_ELLC_LLC_AGE3
;
278 pte
|= HSW_WB_ELLC_LLC_AGE3
;
285 #define i915_dma_unmap_single(px, dev) \
286 __i915_dma_unmap_single((px)->daddr, dev)
288 static inline void __i915_dma_unmap_single(dma_addr_t daddr
,
289 struct drm_device
*dev
)
291 struct device
*device
= &dev
->pdev
->dev
;
293 dma_unmap_page(device
, daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
297 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
298 * @px: Page table/dir/etc to get a DMA map for
301 * Page table allocations are unified across all gens. They always require a
302 * single 4k allocation, as well as a DMA mapping. If we keep the structs
303 * symmetric here, the simple macro covers us for every page table type.
305 * Return: 0 if success.
307 #define i915_dma_map_single(px, dev) \
308 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
310 static inline int i915_dma_map_page_single(struct page
*page
,
311 struct drm_device
*dev
,
314 struct device
*device
= &dev
->pdev
->dev
;
316 *daddr
= dma_map_page(device
, page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
317 if (dma_mapping_error(device
, *daddr
))
323 static void unmap_and_free_pt(struct i915_page_table
*pt
,
324 struct drm_device
*dev
)
326 if (WARN_ON(!pt
->page
))
329 i915_dma_unmap_single(pt
, dev
);
330 __free_page(pt
->page
);
331 kfree(pt
->used_ptes
);
335 static void gen8_initialize_pt(struct i915_address_space
*vm
,
336 struct i915_page_table
*pt
)
338 gen8_pte_t
*pt_vaddr
, scratch_pte
;
341 pt_vaddr
= kmap_atomic(pt
->page
);
342 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
343 I915_CACHE_LLC
, true);
345 for (i
= 0; i
< GEN8_PTES
; i
++)
346 pt_vaddr
[i
] = scratch_pte
;
348 if (!HAS_LLC(vm
->dev
))
349 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
350 kunmap_atomic(pt_vaddr
);
353 static struct i915_page_table
*alloc_pt_single(struct drm_device
*dev
)
355 struct i915_page_table
*pt
;
356 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
357 GEN8_PTES
: GEN6_PTES
;
360 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
362 return ERR_PTR(-ENOMEM
);
364 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
370 pt
->page
= alloc_page(GFP_KERNEL
);
374 ret
= i915_dma_map_single(pt
, dev
);
381 __free_page(pt
->page
);
383 kfree(pt
->used_ptes
);
391 * alloc_pt_range() - Allocate a multiple page tables
392 * @pd: The page directory which will have at least @count entries
393 * available to point to the allocated page tables.
394 * @pde: First page directory entry for which we are allocating.
395 * @count: Number of pages to allocate.
398 * Allocates multiple page table pages and sets the appropriate entries in the
399 * page table structure within the page directory. Function cleans up after
400 * itself on any failures.
402 * Return: 0 if allocation succeeded.
404 static int alloc_pt_range(struct i915_page_directory
*pd
, uint16_t pde
, size_t count
,
405 struct drm_device
*dev
)
409 /* 512 is the max page tables per page_directory on any platform. */
410 if (WARN_ON(pde
+ count
> I915_PDES
))
413 for (i
= pde
; i
< pde
+ count
; i
++) {
414 struct i915_page_table
*pt
= alloc_pt_single(dev
);
420 WARN(pd
->page_table
[i
],
421 "Leaking page directory entry %d (%p)\n",
422 i
, pd
->page_table
[i
]);
423 pd
->page_table
[i
] = pt
;
430 unmap_and_free_pt(pd
->page_table
[i
], dev
);
434 static void unmap_and_free_pd(struct i915_page_directory
*pd
)
437 __free_page(pd
->page
);
442 static struct i915_page_directory
*alloc_pd_single(void)
444 struct i915_page_directory
*pd
;
446 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
448 return ERR_PTR(-ENOMEM
);
450 pd
->page
= alloc_page(GFP_KERNEL
);
453 return ERR_PTR(-ENOMEM
);
459 /* Broadwell Page Directory Pointer Descriptors */
460 static int gen8_write_pdp(struct intel_engine_cs
*ring
, unsigned entry
,
467 ret
= intel_ring_begin(ring
, 6);
471 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
472 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
473 intel_ring_emit(ring
, (u32
)(val
>> 32));
474 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
475 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
476 intel_ring_emit(ring
, (u32
)(val
));
477 intel_ring_advance(ring
);
482 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
483 struct intel_engine_cs
*ring
)
487 /* bit of a hack to find the actual last used pd */
488 int used_pd
= ppgtt
->num_pd_entries
/ I915_PDES
;
490 for (i
= used_pd
- 1; i
>= 0; i
--) {
491 dma_addr_t addr
= ppgtt
->pdp
.page_directory
[i
]->daddr
;
492 ret
= gen8_write_pdp(ring
, i
, addr
);
500 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
505 struct i915_hw_ppgtt
*ppgtt
=
506 container_of(vm
, struct i915_hw_ppgtt
, base
);
507 gen8_pte_t
*pt_vaddr
, scratch_pte
;
508 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
509 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
510 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
511 unsigned num_entries
= length
>> PAGE_SHIFT
;
512 unsigned last_pte
, i
;
514 scratch_pte
= gen8_pte_encode(ppgtt
->base
.scratch
.addr
,
515 I915_CACHE_LLC
, use_scratch
);
517 while (num_entries
) {
518 struct i915_page_directory
*pd
;
519 struct i915_page_table
*pt
;
520 struct page
*page_table
;
522 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
525 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
527 if (WARN_ON(!pd
->page_table
[pde
]))
530 pt
= pd
->page_table
[pde
];
532 if (WARN_ON(!pt
->page
))
535 page_table
= pt
->page
;
537 last_pte
= pte
+ num_entries
;
538 if (last_pte
> GEN8_PTES
)
539 last_pte
= GEN8_PTES
;
541 pt_vaddr
= kmap_atomic(page_table
);
543 for (i
= pte
; i
< last_pte
; i
++) {
544 pt_vaddr
[i
] = scratch_pte
;
548 if (!HAS_LLC(ppgtt
->base
.dev
))
549 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
550 kunmap_atomic(pt_vaddr
);
553 if (++pde
== I915_PDES
) {
560 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
561 struct sg_table
*pages
,
563 enum i915_cache_level cache_level
, u32 unused
)
565 struct i915_hw_ppgtt
*ppgtt
=
566 container_of(vm
, struct i915_hw_ppgtt
, base
);
567 gen8_pte_t
*pt_vaddr
;
568 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
569 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
570 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
571 struct sg_page_iter sg_iter
;
575 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
576 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
579 if (pt_vaddr
== NULL
) {
580 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
581 struct i915_page_table
*pt
= pd
->page_table
[pde
];
582 struct page
*page_table
= pt
->page
;
584 pt_vaddr
= kmap_atomic(page_table
);
588 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
590 if (++pte
== GEN8_PTES
) {
591 if (!HAS_LLC(ppgtt
->base
.dev
))
592 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
593 kunmap_atomic(pt_vaddr
);
595 if (++pde
== I915_PDES
) {
603 if (!HAS_LLC(ppgtt
->base
.dev
))
604 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
605 kunmap_atomic(pt_vaddr
);
609 static void gen8_free_page_tables(struct i915_page_directory
*pd
, struct drm_device
*dev
)
616 for (i
= 0; i
< I915_PDES
; i
++) {
617 if (WARN_ON(!pd
->page_table
[i
]))
620 unmap_and_free_pt(pd
->page_table
[i
], dev
);
621 pd
->page_table
[i
] = NULL
;
625 static void gen8_ppgtt_free(struct i915_hw_ppgtt
*ppgtt
)
629 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
630 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
633 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
634 unmap_and_free_pd(ppgtt
->pdp
.page_directory
[i
]);
638 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
640 struct i915_hw_ppgtt
*ppgtt
=
641 container_of(vm
, struct i915_hw_ppgtt
, base
);
643 gen8_ppgtt_free(ppgtt
);
646 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt
*ppgtt
)
650 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
651 ret
= alloc_pt_range(ppgtt
->pdp
.page_directory
[i
],
652 0, I915_PDES
, ppgtt
->base
.dev
);
661 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
666 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
,
671 for (i
= 0; i
< max_pdp
; i
++) {
672 ppgtt
->pdp
.page_directory
[i
] = alloc_pd_single();
673 if (IS_ERR(ppgtt
->pdp
.page_directory
[i
]))
677 ppgtt
->num_pd_pages
= max_pdp
;
678 BUG_ON(ppgtt
->num_pd_pages
> GEN8_LEGACY_PDPES
);
684 unmap_and_free_pd(ppgtt
->pdp
.page_directory
[i
]);
689 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
,
694 ret
= gen8_ppgtt_allocate_page_directories(ppgtt
, max_pdp
);
698 ret
= gen8_ppgtt_allocate_page_tables(ppgtt
);
702 ppgtt
->num_pd_entries
= max_pdp
* I915_PDES
;
707 gen8_ppgtt_free(ppgtt
);
711 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt
*ppgtt
,
717 pd_addr
= pci_map_page(ppgtt
->base
.dev
->pdev
,
718 ppgtt
->pdp
.page_directory
[pd
]->page
, 0,
719 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
721 ret
= pci_dma_mapping_error(ppgtt
->base
.dev
->pdev
, pd_addr
);
725 ppgtt
->pdp
.page_directory
[pd
]->daddr
= pd_addr
;
730 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt
*ppgtt
,
735 struct i915_page_directory
*pdir
= ppgtt
->pdp
.page_directory
[pd
];
736 struct i915_page_table
*ptab
= pdir
->page_table
[pt
];
737 struct page
*p
= ptab
->page
;
740 gen8_initialize_pt(&ppgtt
->base
, ptab
);
742 pt_addr
= pci_map_page(ppgtt
->base
.dev
->pdev
,
743 p
, 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
744 ret
= pci_dma_mapping_error(ppgtt
->base
.dev
->pdev
, pt_addr
);
748 ptab
->daddr
= pt_addr
;
754 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
755 * with a net effect resembling a 2-level page table in normal x86 terms. Each
756 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
759 * FIXME: split allocation into smaller pieces. For now we only ever do this
760 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
761 * TODO: Do something with the size parameter
763 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
, uint64_t size
)
765 const int max_pdp
= DIV_ROUND_UP(size
, 1 << 30);
766 const int min_pt_pages
= I915_PDES
* max_pdp
;
770 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size
);
772 /* 1. Do all our allocations for page directories and page tables.
773 * We allocate more than was asked so that we can point the unused parts
774 * to valid entries that point to scratch page. Dynamic page tables
775 * will fix this eventually.
777 ret
= gen8_ppgtt_alloc(ppgtt
, GEN8_LEGACY_PDPES
);
782 * 2. Create DMA mappings for the page directories and page tables.
784 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
785 ret
= gen8_ppgtt_setup_page_directories(ppgtt
, i
);
789 for (j
= 0; j
< I915_PDES
; j
++) {
790 ret
= gen8_ppgtt_setup_page_tables(ppgtt
, i
, j
);
797 * 3. Map all the page directory entires to point to the page tables
800 * For now, the PPGTT helper functions all require that the PDEs are
801 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
802 * will never need to touch the PDEs again.
804 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
805 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[i
];
806 gen8_pde_t
*pd_vaddr
;
807 pd_vaddr
= kmap_atomic(ppgtt
->pdp
.page_directory
[i
]->page
);
808 for (j
= 0; j
< I915_PDES
; j
++) {
809 struct i915_page_table
*pt
= pd
->page_table
[j
];
810 dma_addr_t addr
= pt
->daddr
;
811 pd_vaddr
[j
] = gen8_pde_encode(ppgtt
->base
.dev
, addr
,
814 if (!HAS_LLC(ppgtt
->base
.dev
))
815 drm_clflush_virt_range(pd_vaddr
, PAGE_SIZE
);
816 kunmap_atomic(pd_vaddr
);
819 ppgtt
->switch_mm
= gen8_mm_switch
;
820 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
821 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
822 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
823 ppgtt
->base
.start
= 0;
825 /* This is the area that we advertise as usable for the caller */
826 ppgtt
->base
.total
= max_pdp
* I915_PDES
* GEN8_PTES
* PAGE_SIZE
;
828 /* Set all ptes to a valid scratch page. Also above requested space */
829 ppgtt
->base
.clear_range(&ppgtt
->base
, 0,
830 ppgtt
->num_pd_pages
* GEN8_PTES
* PAGE_SIZE
,
833 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
834 ppgtt
->num_pd_pages
, ppgtt
->num_pd_pages
- max_pdp
);
835 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
836 ppgtt
->num_pd_entries
,
837 (ppgtt
->num_pd_entries
- min_pt_pages
) + size
% (1<<30));
841 gen8_ppgtt_free(ppgtt
);
845 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
847 struct drm_i915_private
*dev_priv
= ppgtt
->base
.dev
->dev_private
;
848 struct i915_address_space
*vm
= &ppgtt
->base
;
849 gen6_pte_t __iomem
*pd_addr
;
850 gen6_pte_t scratch_pte
;
854 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
856 pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
857 ppgtt
->pd
.pd_offset
/ sizeof(gen6_pte_t
);
859 seq_printf(m
, " VM %p (pd_offset %x-%x):\n", vm
,
861 ppgtt
->pd
.pd_offset
+ ppgtt
->num_pd_entries
);
862 for (pde
= 0; pde
< ppgtt
->num_pd_entries
; pde
++) {
864 gen6_pte_t
*pt_vaddr
;
865 dma_addr_t pt_addr
= ppgtt
->pd
.page_table
[pde
]->daddr
;
866 pd_entry
= readl(pd_addr
+ pde
);
867 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
869 if (pd_entry
!= expected
)
870 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
874 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
876 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[pde
]->page
);
877 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
879 (pde
* PAGE_SIZE
* GEN6_PTES
) +
883 for (i
= 0; i
< 4; i
++)
884 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
889 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
890 for (i
= 0; i
< 4; i
++) {
891 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
892 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
894 seq_puts(m
, " SCRATCH ");
898 kunmap_atomic(pt_vaddr
);
902 /* Write pde (index) from the page directory @pd to the page table @pt */
903 static void gen6_write_pde(struct i915_page_directory
*pd
,
904 const int pde
, struct i915_page_table
*pt
)
906 /* Caller needs to make sure the write completes if necessary */
907 struct i915_hw_ppgtt
*ppgtt
=
908 container_of(pd
, struct i915_hw_ppgtt
, pd
);
911 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt
->daddr
);
912 pd_entry
|= GEN6_PDE_VALID
;
914 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
917 /* Write all the page tables found in the ppgtt structure to incrementing page
919 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
920 struct i915_page_directory
*pd
,
921 uint32_t start
, uint32_t length
)
923 struct i915_page_table
*pt
;
926 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
927 gen6_write_pde(pd
, pde
, pt
);
929 /* Make sure write is complete before other code can use this page
930 * table. Also require for WC mapped PTEs */
931 readl(dev_priv
->gtt
.gsm
);
934 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
936 BUG_ON(ppgtt
->pd
.pd_offset
& 0x3f);
938 return (ppgtt
->pd
.pd_offset
/ 64) << 16;
941 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
942 struct intel_engine_cs
*ring
)
946 /* NB: TLBs must be flushed and invalidated before a switch */
947 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
951 ret
= intel_ring_begin(ring
, 6);
955 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
956 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
957 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
958 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
959 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
960 intel_ring_emit(ring
, MI_NOOP
);
961 intel_ring_advance(ring
);
966 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
967 struct intel_engine_cs
*ring
)
969 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
971 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
972 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
976 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
977 struct intel_engine_cs
*ring
)
981 /* NB: TLBs must be flushed and invalidated before a switch */
982 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
986 ret
= intel_ring_begin(ring
, 6);
990 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
991 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
992 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
993 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
994 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
995 intel_ring_emit(ring
, MI_NOOP
);
996 intel_ring_advance(ring
);
998 /* XXX: RCS is the only one to auto invalidate the TLBs? */
999 if (ring
->id
!= RCS
) {
1000 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1008 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1009 struct intel_engine_cs
*ring
)
1011 struct drm_device
*dev
= ppgtt
->base
.dev
;
1012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1015 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1016 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1018 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1023 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1026 struct intel_engine_cs
*ring
;
1029 for_each_ring(ring
, dev_priv
, j
) {
1030 I915_WRITE(RING_MODE_GEN7(ring
),
1031 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1035 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1038 struct intel_engine_cs
*ring
;
1039 uint32_t ecochk
, ecobits
;
1042 ecobits
= I915_READ(GAC_ECO_BITS
);
1043 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1045 ecochk
= I915_READ(GAM_ECOCHK
);
1046 if (IS_HASWELL(dev
)) {
1047 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1049 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1050 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1052 I915_WRITE(GAM_ECOCHK
, ecochk
);
1054 for_each_ring(ring
, dev_priv
, i
) {
1055 /* GFX_MODE is per-ring on gen7+ */
1056 I915_WRITE(RING_MODE_GEN7(ring
),
1057 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1061 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1064 uint32_t ecochk
, gab_ctl
, ecobits
;
1066 ecobits
= I915_READ(GAC_ECO_BITS
);
1067 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1068 ECOBITS_PPGTT_CACHE64B
);
1070 gab_ctl
= I915_READ(GAB_CTL
);
1071 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1073 ecochk
= I915_READ(GAM_ECOCHK
);
1074 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1076 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1079 /* PPGTT support for Sandybdrige/Gen6 and later */
1080 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1085 struct i915_hw_ppgtt
*ppgtt
=
1086 container_of(vm
, struct i915_hw_ppgtt
, base
);
1087 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1088 unsigned first_entry
= start
>> PAGE_SHIFT
;
1089 unsigned num_entries
= length
>> PAGE_SHIFT
;
1090 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1091 unsigned first_pte
= first_entry
% GEN6_PTES
;
1092 unsigned last_pte
, i
;
1094 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
1096 while (num_entries
) {
1097 last_pte
= first_pte
+ num_entries
;
1098 if (last_pte
> GEN6_PTES
)
1099 last_pte
= GEN6_PTES
;
1101 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[act_pt
]->page
);
1103 for (i
= first_pte
; i
< last_pte
; i
++)
1104 pt_vaddr
[i
] = scratch_pte
;
1106 kunmap_atomic(pt_vaddr
);
1108 num_entries
-= last_pte
- first_pte
;
1114 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1115 struct sg_table
*pages
,
1117 enum i915_cache_level cache_level
, u32 flags
)
1119 struct i915_hw_ppgtt
*ppgtt
=
1120 container_of(vm
, struct i915_hw_ppgtt
, base
);
1121 gen6_pte_t
*pt_vaddr
;
1122 unsigned first_entry
= start
>> PAGE_SHIFT
;
1123 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1124 unsigned act_pte
= first_entry
% GEN6_PTES
;
1125 struct sg_page_iter sg_iter
;
1128 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1129 if (pt_vaddr
== NULL
)
1130 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[act_pt
]->page
);
1133 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1134 cache_level
, true, flags
);
1136 if (++act_pte
== GEN6_PTES
) {
1137 kunmap_atomic(pt_vaddr
);
1144 kunmap_atomic(pt_vaddr
);
1147 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1148 * are switching between contexts with the same LRCA, we also must do a force
1151 static inline void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1153 /* If current vm != vm, */
1154 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1157 static void gen6_initialize_pt(struct i915_address_space
*vm
,
1158 struct i915_page_table
*pt
)
1160 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1163 WARN_ON(vm
->scratch
.addr
== 0);
1165 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
,
1166 I915_CACHE_LLC
, true, 0);
1168 pt_vaddr
= kmap_atomic(pt
->page
);
1170 for (i
= 0; i
< GEN6_PTES
; i
++)
1171 pt_vaddr
[i
] = scratch_pte
;
1173 kunmap_atomic(pt_vaddr
);
1176 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1177 uint64_t start
, uint64_t length
)
1179 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1180 struct drm_device
*dev
= vm
->dev
;
1181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1182 struct i915_hw_ppgtt
*ppgtt
=
1183 container_of(vm
, struct i915_hw_ppgtt
, base
);
1184 struct i915_page_table
*pt
;
1185 const uint32_t start_save
= start
, length_save
= length
;
1189 WARN_ON(upper_32_bits(start
));
1191 bitmap_zero(new_page_tables
, I915_PDES
);
1193 /* The allocation is done in two stages so that we can bail out with
1194 * minimal amount of pain. The first stage finds new page tables that
1195 * need allocation. The second stage marks use ptes within the page
1198 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1199 if (pt
!= ppgtt
->scratch_pt
) {
1200 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1204 /* We've already allocated a page table */
1205 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1207 pt
= alloc_pt_single(dev
);
1213 gen6_initialize_pt(vm
, pt
);
1215 ppgtt
->pd
.page_table
[pde
] = pt
;
1216 set_bit(pde
, new_page_tables
);
1217 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1221 length
= length_save
;
1223 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1224 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1226 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1227 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1228 gen6_pte_count(start
, length
));
1230 if (test_and_clear_bit(pde
, new_page_tables
))
1231 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1233 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1234 gen6_pte_index(start
),
1235 gen6_pte_count(start
, length
),
1237 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1241 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1243 /* Make sure write is complete before other code can use this page
1244 * table. Also require for WC mapped PTEs */
1245 readl(dev_priv
->gtt
.gsm
);
1247 mark_tlbs_dirty(ppgtt
);
1251 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1252 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1254 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1255 unmap_and_free_pt(pt
, vm
->dev
);
1258 mark_tlbs_dirty(ppgtt
);
1262 static void gen6_ppgtt_free(struct i915_hw_ppgtt
*ppgtt
)
1266 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
1267 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[i
];
1269 if (pt
!= ppgtt
->scratch_pt
)
1270 unmap_and_free_pt(ppgtt
->pd
.page_table
[i
], ppgtt
->base
.dev
);
1273 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1274 unmap_and_free_pd(&ppgtt
->pd
);
1277 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1279 struct i915_hw_ppgtt
*ppgtt
=
1280 container_of(vm
, struct i915_hw_ppgtt
, base
);
1282 drm_mm_remove_node(&ppgtt
->node
);
1284 gen6_ppgtt_free(ppgtt
);
1287 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1289 struct drm_device
*dev
= ppgtt
->base
.dev
;
1290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1291 bool retried
= false;
1294 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1295 * allocator works in address space sizes, so it's multiplied by page
1296 * size. We allocate at the top of the GTT to avoid fragmentation.
1298 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1299 ppgtt
->scratch_pt
= alloc_pt_single(ppgtt
->base
.dev
);
1300 if (IS_ERR(ppgtt
->scratch_pt
))
1301 return PTR_ERR(ppgtt
->scratch_pt
);
1303 gen6_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1306 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1307 &ppgtt
->node
, GEN6_PD_SIZE
,
1309 0, dev_priv
->gtt
.base
.total
,
1311 if (ret
== -ENOSPC
&& !retried
) {
1312 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1313 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1315 0, dev_priv
->gtt
.base
.total
,
1328 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1329 DRM_DEBUG("Forced to use aperture for PDEs\n");
1331 ppgtt
->num_pd_entries
= I915_PDES
;
1335 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1339 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1341 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1344 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1345 uint64_t start
, uint64_t length
)
1347 struct i915_page_table
*unused
;
1350 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1351 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1354 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
, bool aliasing
)
1356 struct drm_device
*dev
= ppgtt
->base
.dev
;
1357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1360 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1362 ppgtt
->switch_mm
= gen6_mm_switch
;
1363 } else if (IS_HASWELL(dev
)) {
1364 ppgtt
->switch_mm
= hsw_mm_switch
;
1365 } else if (IS_GEN7(dev
)) {
1366 ppgtt
->switch_mm
= gen7_mm_switch
;
1370 if (intel_vgpu_active(dev
))
1371 ppgtt
->switch_mm
= vgpu_mm_switch
;
1373 ret
= gen6_ppgtt_alloc(ppgtt
);
1378 /* preallocate all pts */
1379 ret
= alloc_pt_range(&ppgtt
->pd
, 0, ppgtt
->num_pd_entries
,
1383 gen6_ppgtt_cleanup(&ppgtt
->base
);
1388 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1389 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1390 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1391 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1392 ppgtt
->base
.start
= 0;
1393 ppgtt
->base
.total
= ppgtt
->num_pd_entries
* GEN6_PTES
* PAGE_SIZE
;
1394 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1396 ppgtt
->pd
.pd_offset
=
1397 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1399 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1400 ppgtt
->pd
.pd_offset
/ sizeof(gen6_pte_t
);
1403 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1405 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1407 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1409 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1410 ppgtt
->node
.size
>> 20,
1411 ppgtt
->node
.start
/ PAGE_SIZE
);
1413 DRM_DEBUG("Adding PPGTT at offset %x\n",
1414 ppgtt
->pd
.pd_offset
<< 10);
1419 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
,
1422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1424 ppgtt
->base
.dev
= dev
;
1425 ppgtt
->base
.scratch
= dev_priv
->gtt
.base
.scratch
;
1427 if (INTEL_INFO(dev
)->gen
< 8)
1428 return gen6_ppgtt_init(ppgtt
, aliasing
);
1430 return gen8_ppgtt_init(ppgtt
, dev_priv
->gtt
.base
.total
);
1432 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1437 ret
= __hw_ppgtt_init(dev
, ppgtt
, false);
1439 kref_init(&ppgtt
->ref
);
1440 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1442 i915_init_vm(dev_priv
, &ppgtt
->base
);
1448 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 struct intel_engine_cs
*ring
;
1452 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1455 /* In the case of execlists, PPGTT is enabled by the context descriptor
1456 * and the PDPs are contained within the context itself. We don't
1457 * need to do anything here. */
1458 if (i915
.enable_execlists
)
1461 if (!USES_PPGTT(dev
))
1465 gen6_ppgtt_enable(dev
);
1466 else if (IS_GEN7(dev
))
1467 gen7_ppgtt_enable(dev
);
1468 else if (INTEL_INFO(dev
)->gen
>= 8)
1469 gen8_ppgtt_enable(dev
);
1471 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1474 for_each_ring(ring
, dev_priv
, i
) {
1475 ret
= ppgtt
->switch_mm(ppgtt
, ring
);
1483 struct i915_hw_ppgtt
*
1484 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1486 struct i915_hw_ppgtt
*ppgtt
;
1489 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1491 return ERR_PTR(-ENOMEM
);
1493 ret
= i915_ppgtt_init(dev
, ppgtt
);
1496 return ERR_PTR(ret
);
1499 ppgtt
->file_priv
= fpriv
;
1501 trace_i915_ppgtt_create(&ppgtt
->base
);
1506 void i915_ppgtt_release(struct kref
*kref
)
1508 struct i915_hw_ppgtt
*ppgtt
=
1509 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1511 trace_i915_ppgtt_release(&ppgtt
->base
);
1513 /* vmas should already be unbound */
1514 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1515 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1517 list_del(&ppgtt
->base
.global_link
);
1518 drm_mm_takedown(&ppgtt
->base
.mm
);
1520 ppgtt
->base
.cleanup(&ppgtt
->base
);
1525 ppgtt_bind_vma(struct i915_vma
*vma
,
1526 enum i915_cache_level cache_level
,
1529 /* Currently applicable only to VLV */
1530 if (vma
->obj
->gt_ro
)
1531 flags
|= PTE_READ_ONLY
;
1533 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
1534 cache_level
, flags
);
1537 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
1539 vma
->vm
->clear_range(vma
->vm
,
1541 vma
->obj
->base
.size
,
1545 extern int intel_iommu_gfx_mapped
;
1546 /* Certain Gen5 chipsets require require idling the GPU before
1547 * unmapping anything from the GTT when VT-d is enabled.
1549 static inline bool needs_idle_maps(struct drm_device
*dev
)
1551 #ifdef CONFIG_INTEL_IOMMU
1552 /* Query intel_iommu to see if we need the workaround. Presumably that
1555 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1561 static bool do_idling(struct drm_i915_private
*dev_priv
)
1563 bool ret
= dev_priv
->mm
.interruptible
;
1565 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1566 dev_priv
->mm
.interruptible
= false;
1567 if (i915_gpu_idle(dev_priv
->dev
)) {
1568 DRM_ERROR("Couldn't idle GPU\n");
1569 /* Wait a bit, in hopes it avoids the hang */
1577 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1579 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1580 dev_priv
->mm
.interruptible
= interruptible
;
1583 void i915_check_and_clear_faults(struct drm_device
*dev
)
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 struct intel_engine_cs
*ring
;
1589 if (INTEL_INFO(dev
)->gen
< 6)
1592 for_each_ring(ring
, dev_priv
, i
) {
1594 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1595 if (fault_reg
& RING_FAULT_VALID
) {
1596 DRM_DEBUG_DRIVER("Unexpected fault\n"
1598 "\tAddress space: %s\n"
1601 fault_reg
& PAGE_MASK
,
1602 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1603 RING_FAULT_SRCID(fault_reg
),
1604 RING_FAULT_FAULT_TYPE(fault_reg
));
1605 I915_WRITE(RING_FAULT_REG(ring
),
1606 fault_reg
& ~RING_FAULT_VALID
);
1609 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1612 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1614 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1615 intel_gtt_chipset_flush();
1617 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1618 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1622 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1626 /* Don't bother messing with faults pre GEN6 as we have little
1627 * documentation supporting that it's a good idea.
1629 if (INTEL_INFO(dev
)->gen
< 6)
1632 i915_check_and_clear_faults(dev
);
1634 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1635 dev_priv
->gtt
.base
.start
,
1636 dev_priv
->gtt
.base
.total
,
1639 i915_ggtt_flush(dev_priv
);
1642 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
1644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1645 struct drm_i915_gem_object
*obj
;
1646 struct i915_address_space
*vm
;
1648 i915_check_and_clear_faults(dev
);
1650 /* First fill our portion of the GTT with scratch pages */
1651 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1652 dev_priv
->gtt
.base
.start
,
1653 dev_priv
->gtt
.base
.total
,
1656 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1657 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
1658 &dev_priv
->gtt
.base
);
1662 i915_gem_clflush_object(obj
, obj
->pin_display
);
1663 /* The bind_vma code tries to be smart about tracking mappings.
1664 * Unfortunately above, we've just wiped out the mappings
1665 * without telling our object about it. So we need to fake it.
1667 * Bind is not expected to fail since this is only called on
1668 * resume and assumption is all requirements exist already.
1670 vma
->bound
&= ~GLOBAL_BIND
;
1671 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
));
1675 if (INTEL_INFO(dev
)->gen
>= 8) {
1676 if (IS_CHERRYVIEW(dev
))
1677 chv_setup_private_ppat(dev_priv
);
1679 bdw_setup_private_ppat(dev_priv
);
1684 if (USES_PPGTT(dev
)) {
1685 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
1686 /* TODO: Perhaps it shouldn't be gen6 specific */
1688 struct i915_hw_ppgtt
*ppgtt
=
1689 container_of(vm
, struct i915_hw_ppgtt
,
1692 if (i915_is_ggtt(vm
))
1693 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1695 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
1696 0, ppgtt
->base
.total
);
1700 i915_ggtt_flush(dev_priv
);
1703 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1705 if (obj
->has_dma_mapping
)
1708 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1709 obj
->pages
->sgl
, obj
->pages
->nents
,
1710 PCI_DMA_BIDIRECTIONAL
))
1716 static inline void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1721 iowrite32((u32
)pte
, addr
);
1722 iowrite32(pte
>> 32, addr
+ 4);
1726 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1727 struct sg_table
*st
,
1729 enum i915_cache_level level
, u32 unused
)
1731 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1732 unsigned first_entry
= start
>> PAGE_SHIFT
;
1733 gen8_pte_t __iomem
*gtt_entries
=
1734 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1736 struct sg_page_iter sg_iter
;
1737 dma_addr_t addr
= 0; /* shut up gcc */
1739 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1740 addr
= sg_dma_address(sg_iter
.sg
) +
1741 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1742 gen8_set_pte(>t_entries
[i
],
1743 gen8_pte_encode(addr
, level
, true));
1748 * XXX: This serves as a posting read to make sure that the PTE has
1749 * actually been updated. There is some concern that even though
1750 * registers and PTEs are within the same BAR that they are potentially
1751 * of NUMA access patterns. Therefore, even with the way we assume
1752 * hardware should work, we must keep this posting read for paranoia.
1755 WARN_ON(readq(>t_entries
[i
-1])
1756 != gen8_pte_encode(addr
, level
, true));
1758 /* This next bit makes the above posting read even more important. We
1759 * want to flush the TLBs only after we're certain all the PTE updates
1762 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1763 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1767 * Binds an object into the global gtt with the specified cache level. The object
1768 * will be accessible to the GPU via commands whose operands reference offsets
1769 * within the global GTT as well as accessible by the GPU through the GMADR
1770 * mapped BAR (dev_priv->mm.gtt->gtt).
1772 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1773 struct sg_table
*st
,
1775 enum i915_cache_level level
, u32 flags
)
1777 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1778 unsigned first_entry
= start
>> PAGE_SHIFT
;
1779 gen6_pte_t __iomem
*gtt_entries
=
1780 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1782 struct sg_page_iter sg_iter
;
1783 dma_addr_t addr
= 0;
1785 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1786 addr
= sg_page_iter_dma_address(&sg_iter
);
1787 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1791 /* XXX: This serves as a posting read to make sure that the PTE has
1792 * actually been updated. There is some concern that even though
1793 * registers and PTEs are within the same BAR that they are potentially
1794 * of NUMA access patterns. Therefore, even with the way we assume
1795 * hardware should work, we must keep this posting read for paranoia.
1798 unsigned long gtt
= readl(>t_entries
[i
-1]);
1799 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1802 /* This next bit makes the above posting read even more important. We
1803 * want to flush the TLBs only after we're certain all the PTE updates
1806 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1807 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1810 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1815 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1816 unsigned first_entry
= start
>> PAGE_SHIFT
;
1817 unsigned num_entries
= length
>> PAGE_SHIFT
;
1818 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1819 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1820 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1823 if (WARN(num_entries
> max_entries
,
1824 "First entry = %d; Num entries = %d (max=%d)\n",
1825 first_entry
, num_entries
, max_entries
))
1826 num_entries
= max_entries
;
1828 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
1831 for (i
= 0; i
< num_entries
; i
++)
1832 gen8_set_pte(>t_base
[i
], scratch_pte
);
1836 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1841 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1842 unsigned first_entry
= start
>> PAGE_SHIFT
;
1843 unsigned num_entries
= length
>> PAGE_SHIFT
;
1844 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1845 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1846 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1849 if (WARN(num_entries
> max_entries
,
1850 "First entry = %d; Num entries = %d (max=%d)\n",
1851 first_entry
, num_entries
, max_entries
))
1852 num_entries
= max_entries
;
1854 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, use_scratch
, 0);
1856 for (i
= 0; i
< num_entries
; i
++)
1857 iowrite32(scratch_pte
, >t_base
[i
]);
1862 static void i915_ggtt_bind_vma(struct i915_vma
*vma
,
1863 enum i915_cache_level cache_level
,
1866 const unsigned long entry
= vma
->node
.start
>> PAGE_SHIFT
;
1867 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1868 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1870 BUG_ON(!i915_is_ggtt(vma
->vm
));
1871 intel_gtt_insert_sg_entries(vma
->ggtt_view
.pages
, entry
, flags
);
1872 vma
->bound
= GLOBAL_BIND
;
1875 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1880 unsigned first_entry
= start
>> PAGE_SHIFT
;
1881 unsigned num_entries
= length
>> PAGE_SHIFT
;
1882 intel_gtt_clear_range(first_entry
, num_entries
);
1885 static void i915_ggtt_unbind_vma(struct i915_vma
*vma
)
1887 const unsigned int first
= vma
->node
.start
>> PAGE_SHIFT
;
1888 const unsigned int size
= vma
->obj
->base
.size
>> PAGE_SHIFT
;
1890 BUG_ON(!i915_is_ggtt(vma
->vm
));
1892 intel_gtt_clear_range(first
, size
);
1895 static void ggtt_bind_vma(struct i915_vma
*vma
,
1896 enum i915_cache_level cache_level
,
1899 struct drm_device
*dev
= vma
->vm
->dev
;
1900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1901 struct drm_i915_gem_object
*obj
= vma
->obj
;
1902 struct sg_table
*pages
= obj
->pages
;
1904 /* Currently applicable only to VLV */
1906 flags
|= PTE_READ_ONLY
;
1908 if (i915_is_ggtt(vma
->vm
))
1909 pages
= vma
->ggtt_view
.pages
;
1911 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1912 * or we have a global mapping already but the cacheability flags have
1913 * changed, set the global PTEs.
1915 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1916 * instead if none of the above hold true.
1918 * NB: A global mapping should only be needed for special regions like
1919 * "gtt mappable", SNB errata, or if specified via special execbuf
1920 * flags. At all other times, the GPU will use the aliasing PPGTT.
1922 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1923 if (!(vma
->bound
& GLOBAL_BIND
) ||
1924 (cache_level
!= obj
->cache_level
)) {
1925 vma
->vm
->insert_entries(vma
->vm
, pages
,
1927 cache_level
, flags
);
1928 vma
->bound
|= GLOBAL_BIND
;
1932 if (dev_priv
->mm
.aliasing_ppgtt
&&
1933 (!(vma
->bound
& LOCAL_BIND
) ||
1934 (cache_level
!= obj
->cache_level
))) {
1935 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1936 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
1938 cache_level
, flags
);
1939 vma
->bound
|= LOCAL_BIND
;
1943 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1945 struct drm_device
*dev
= vma
->vm
->dev
;
1946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 struct drm_i915_gem_object
*obj
= vma
->obj
;
1949 if (vma
->bound
& GLOBAL_BIND
) {
1950 vma
->vm
->clear_range(vma
->vm
,
1954 vma
->bound
&= ~GLOBAL_BIND
;
1957 if (vma
->bound
& LOCAL_BIND
) {
1958 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1959 appgtt
->base
.clear_range(&appgtt
->base
,
1963 vma
->bound
&= ~LOCAL_BIND
;
1967 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1969 struct drm_device
*dev
= obj
->base
.dev
;
1970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1973 interruptible
= do_idling(dev_priv
);
1975 if (!obj
->has_dma_mapping
)
1976 dma_unmap_sg(&dev
->pdev
->dev
,
1977 obj
->pages
->sgl
, obj
->pages
->nents
,
1978 PCI_DMA_BIDIRECTIONAL
);
1980 undo_idling(dev_priv
, interruptible
);
1983 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1984 unsigned long color
,
1988 if (node
->color
!= color
)
1991 if (!list_empty(&node
->node_list
)) {
1992 node
= list_entry(node
->node_list
.next
,
1995 if (node
->allocated
&& node
->color
!= color
)
2000 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2001 unsigned long start
,
2002 unsigned long mappable_end
,
2005 /* Let GEM Manage all of the aperture.
2007 * However, leave one page at the end still bound to the scratch page.
2008 * There are a number of places where the hardware apparently prefetches
2009 * past the end of the object, and we've seen multiple hangs with the
2010 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2011 * aperture. One page should be enough to keep any prefetching inside
2014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2015 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2016 struct drm_mm_node
*entry
;
2017 struct drm_i915_gem_object
*obj
;
2018 unsigned long hole_start
, hole_end
;
2021 BUG_ON(mappable_end
> end
);
2023 /* Subtract the guard page ... */
2024 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2026 dev_priv
->gtt
.base
.start
= start
;
2027 dev_priv
->gtt
.base
.total
= end
- start
;
2029 if (intel_vgpu_active(dev
)) {
2030 ret
= intel_vgt_balloon(dev
);
2036 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2038 /* Mark any preallocated objects as occupied */
2039 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2040 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2042 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2043 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2045 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2046 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2048 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2051 vma
->bound
|= GLOBAL_BIND
;
2054 /* Clear any non-preallocated blocks */
2055 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2056 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2057 hole_start
, hole_end
);
2058 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2059 hole_end
- hole_start
, true);
2062 /* And finally clear the reserved guard page */
2063 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2065 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2066 struct i915_hw_ppgtt
*ppgtt
;
2068 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2072 ret
= __hw_ppgtt_init(dev
, ppgtt
, true);
2078 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2084 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2087 unsigned long gtt_size
, mappable_size
;
2089 gtt_size
= dev_priv
->gtt
.base
.total
;
2090 mappable_size
= dev_priv
->gtt
.mappable_end
;
2092 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2095 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2098 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2100 if (dev_priv
->mm
.aliasing_ppgtt
) {
2101 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2103 ppgtt
->base
.cleanup(&ppgtt
->base
);
2106 if (drm_mm_initialized(&vm
->mm
)) {
2107 if (intel_vgpu_active(dev
))
2108 intel_vgt_deballoon();
2110 drm_mm_takedown(&vm
->mm
);
2111 list_del(&vm
->global_link
);
2117 static int setup_scratch_page(struct drm_device
*dev
)
2119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2121 dma_addr_t dma_addr
;
2123 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
2126 set_pages_uc(page
, 1);
2128 #ifdef CONFIG_INTEL_IOMMU
2129 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
2130 PCI_DMA_BIDIRECTIONAL
);
2131 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
2134 dma_addr
= page_to_phys(page
);
2136 dev_priv
->gtt
.base
.scratch
.page
= page
;
2137 dev_priv
->gtt
.base
.scratch
.addr
= dma_addr
;
2142 static void teardown_scratch_page(struct drm_device
*dev
)
2144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2145 struct page
*page
= dev_priv
->gtt
.base
.scratch
.page
;
2147 set_pages_wb(page
, 1);
2148 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.base
.scratch
.addr
,
2149 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
2153 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2155 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2156 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2157 return snb_gmch_ctl
<< 20;
2160 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2162 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2163 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2165 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2167 #ifdef CONFIG_X86_32
2168 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2169 if (bdw_gmch_ctl
> 4)
2173 return bdw_gmch_ctl
<< 20;
2176 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2178 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2179 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2182 return 1 << (20 + gmch_ctrl
);
2187 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2189 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2190 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2191 return snb_gmch_ctl
<< 25; /* 32 MB units */
2194 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2196 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2197 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2198 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2201 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2203 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2204 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2207 * 0x0 to 0x10: 32MB increments starting at 0MB
2208 * 0x11 to 0x16: 4MB increments starting at 8MB
2209 * 0x17 to 0x1d: 4MB increments start at 36MB
2211 if (gmch_ctrl
< 0x11)
2212 return gmch_ctrl
<< 25;
2213 else if (gmch_ctrl
< 0x17)
2214 return (gmch_ctrl
- 0x11 + 2) << 22;
2216 return (gmch_ctrl
- 0x17 + 9) << 22;
2219 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2221 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2222 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2224 if (gen9_gmch_ctl
< 0xf0)
2225 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2227 /* 4MB increments starting at 0xf0 for 4MB */
2228 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2231 static int ggtt_probe_common(struct drm_device
*dev
,
2234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 phys_addr_t gtt_phys_addr
;
2238 /* For Modern GENs the PTEs and register space are split in the BAR */
2239 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2240 (pci_resource_len(dev
->pdev
, 0) / 2);
2242 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2243 if (!dev_priv
->gtt
.gsm
) {
2244 DRM_ERROR("Failed to map the gtt page table\n");
2248 ret
= setup_scratch_page(dev
);
2250 DRM_ERROR("Scratch setup failed\n");
2251 /* iounmap will also get called at remove, but meh */
2252 iounmap(dev_priv
->gtt
.gsm
);
2258 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2259 * bits. When using advanced contexts each context stores its own PAT, but
2260 * writing this data shouldn't be harmful even in those cases. */
2261 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2265 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2266 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2267 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2268 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2269 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2270 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2271 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2272 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2274 if (!USES_PPGTT(dev_priv
->dev
))
2275 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2276 * so RTL will always use the value corresponding to
2278 * So let's disable cache for GGTT to avoid screen corruptions.
2279 * MOCS still can be used though.
2280 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2281 * before this patch, i.e. the same uncached + snooping access
2282 * like on gen6/7 seems to be in effect.
2283 * - So this just fixes blitter/render access. Again it looks
2284 * like it's not just uncached access, but uncached + snooping.
2285 * So we can still hold onto all our assumptions wrt cpu
2286 * clflushing on LLC machines.
2288 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2290 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2291 * write would work. */
2292 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2293 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2296 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2301 * Map WB on BDW to snooped on CHV.
2303 * Only the snoop bit has meaning for CHV, the rest is
2306 * The hardware will never snoop for certain types of accesses:
2307 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2308 * - PPGTT page tables
2309 * - some other special cycles
2311 * As with BDW, we also need to consider the following for GT accesses:
2312 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2313 * so RTL will always use the value corresponding to
2315 * Which means we must set the snoop bit in PAT entry 0
2316 * in order to keep the global status page working.
2318 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2322 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2323 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2324 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2325 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2327 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2328 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2331 static int gen8_gmch_probe(struct drm_device
*dev
,
2334 phys_addr_t
*mappable_base
,
2335 unsigned long *mappable_end
)
2337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2338 unsigned int gtt_size
;
2342 /* TODO: We're not aware of mappable constraints on gen8 yet */
2343 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2344 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2346 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2347 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2349 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2351 if (INTEL_INFO(dev
)->gen
>= 9) {
2352 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2353 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2354 } else if (IS_CHERRYVIEW(dev
)) {
2355 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2356 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2358 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2359 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2362 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2364 if (IS_CHERRYVIEW(dev
))
2365 chv_setup_private_ppat(dev_priv
);
2367 bdw_setup_private_ppat(dev_priv
);
2369 ret
= ggtt_probe_common(dev
, gtt_size
);
2371 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2372 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2377 static int gen6_gmch_probe(struct drm_device
*dev
,
2380 phys_addr_t
*mappable_base
,
2381 unsigned long *mappable_end
)
2383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2384 unsigned int gtt_size
;
2388 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2389 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2391 /* 64/512MB is the current min/max we actually know of, but this is just
2392 * a coarse sanity check.
2394 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2395 DRM_ERROR("Unknown GMADR size (%lx)\n",
2396 dev_priv
->gtt
.mappable_end
);
2400 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2401 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2402 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2404 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2406 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2407 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2409 ret
= ggtt_probe_common(dev
, gtt_size
);
2411 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2412 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2417 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2420 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2423 teardown_scratch_page(vm
->dev
);
2426 static int i915_gmch_probe(struct drm_device
*dev
,
2429 phys_addr_t
*mappable_base
,
2430 unsigned long *mappable_end
)
2432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2437 DRM_ERROR("failed to set up gmch\n");
2441 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2443 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2444 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2446 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2447 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2452 static void i915_gmch_remove(struct i915_address_space
*vm
)
2454 intel_gmch_remove();
2457 int i915_gem_gtt_init(struct drm_device
*dev
)
2459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2460 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2463 if (INTEL_INFO(dev
)->gen
<= 5) {
2464 gtt
->gtt_probe
= i915_gmch_probe
;
2465 gtt
->base
.cleanup
= i915_gmch_remove
;
2466 } else if (INTEL_INFO(dev
)->gen
< 8) {
2467 gtt
->gtt_probe
= gen6_gmch_probe
;
2468 gtt
->base
.cleanup
= gen6_gmch_remove
;
2469 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2470 gtt
->base
.pte_encode
= iris_pte_encode
;
2471 else if (IS_HASWELL(dev
))
2472 gtt
->base
.pte_encode
= hsw_pte_encode
;
2473 else if (IS_VALLEYVIEW(dev
))
2474 gtt
->base
.pte_encode
= byt_pte_encode
;
2475 else if (INTEL_INFO(dev
)->gen
>= 7)
2476 gtt
->base
.pte_encode
= ivb_pte_encode
;
2478 gtt
->base
.pte_encode
= snb_pte_encode
;
2480 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2481 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2484 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2485 >t
->mappable_base
, >t
->mappable_end
);
2489 gtt
->base
.dev
= dev
;
2491 /* GMADR is the PCI mmio aperture into the global GTT. */
2492 DRM_INFO("Memory usable by graphics device = %zdM\n",
2493 gtt
->base
.total
>> 20);
2494 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt
->mappable_end
>> 20);
2495 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2496 #ifdef CONFIG_INTEL_IOMMU
2497 if (intel_iommu_gfx_mapped
)
2498 DRM_INFO("VT-d active for gfx access\n");
2501 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2502 * user's requested state against the hardware/driver capabilities. We
2503 * do this now so that we can print out any log messages once rather
2504 * than every time we check intel_enable_ppgtt().
2506 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2507 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2512 static struct i915_vma
*
2513 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2514 struct i915_address_space
*vm
,
2515 const struct i915_ggtt_view
*ggtt_view
)
2517 struct i915_vma
*vma
;
2519 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2520 return ERR_PTR(-EINVAL
);
2521 vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
2523 return ERR_PTR(-ENOMEM
);
2525 INIT_LIST_HEAD(&vma
->vma_link
);
2526 INIT_LIST_HEAD(&vma
->mm_list
);
2527 INIT_LIST_HEAD(&vma
->exec_list
);
2531 if (INTEL_INFO(vm
->dev
)->gen
>= 6) {
2532 if (i915_is_ggtt(vm
)) {
2533 vma
->ggtt_view
= *ggtt_view
;
2535 vma
->unbind_vma
= ggtt_unbind_vma
;
2536 vma
->bind_vma
= ggtt_bind_vma
;
2538 vma
->unbind_vma
= ppgtt_unbind_vma
;
2539 vma
->bind_vma
= ppgtt_bind_vma
;
2542 BUG_ON(!i915_is_ggtt(vm
));
2543 vma
->ggtt_view
= *ggtt_view
;
2544 vma
->unbind_vma
= i915_ggtt_unbind_vma
;
2545 vma
->bind_vma
= i915_ggtt_bind_vma
;
2548 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2549 if (!i915_is_ggtt(vm
))
2550 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2556 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2557 struct i915_address_space
*vm
)
2559 struct i915_vma
*vma
;
2561 vma
= i915_gem_obj_to_vma(obj
, vm
);
2563 vma
= __i915_gem_vma_create(obj
, vm
,
2564 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2570 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2571 const struct i915_ggtt_view
*view
)
2573 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2574 struct i915_vma
*vma
;
2577 return ERR_PTR(-EINVAL
);
2579 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2585 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2592 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2593 struct sg_table
*st
)
2595 unsigned int column
, row
;
2596 unsigned int src_idx
;
2597 struct scatterlist
*sg
= st
->sgl
;
2601 for (column
= 0; column
< width
; column
++) {
2602 src_idx
= width
* (height
- 1) + column
;
2603 for (row
= 0; row
< height
; row
++) {
2605 /* We don't need the pages, but need to initialize
2606 * the entries so the sg list can be happily traversed.
2607 * The only thing we need are DMA addresses.
2609 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2610 sg_dma_address(sg
) = in
[src_idx
];
2611 sg_dma_len(sg
) = PAGE_SIZE
;
2618 static struct sg_table
*
2619 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2620 struct drm_i915_gem_object
*obj
)
2622 struct drm_device
*dev
= obj
->base
.dev
;
2623 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2624 unsigned long size
, pages
, rot_pages
;
2625 struct sg_page_iter sg_iter
;
2627 dma_addr_t
*page_addr_list
;
2628 struct sg_table
*st
;
2629 unsigned int tile_pitch
, tile_height
;
2630 unsigned int width_pages
, height_pages
;
2633 pages
= obj
->base
.size
/ PAGE_SIZE
;
2635 /* Calculate tiling geometry. */
2636 tile_height
= intel_tile_height(dev
, rot_info
->pixel_format
,
2637 rot_info
->fb_modifier
);
2638 tile_pitch
= PAGE_SIZE
/ tile_height
;
2639 width_pages
= DIV_ROUND_UP(rot_info
->pitch
, tile_pitch
);
2640 height_pages
= DIV_ROUND_UP(rot_info
->height
, tile_height
);
2641 rot_pages
= width_pages
* height_pages
;
2642 size
= rot_pages
* PAGE_SIZE
;
2644 /* Allocate a temporary list of source pages for random access. */
2645 page_addr_list
= drm_malloc_ab(pages
, sizeof(dma_addr_t
));
2646 if (!page_addr_list
)
2647 return ERR_PTR(ret
);
2649 /* Allocate target SG list. */
2650 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2654 ret
= sg_alloc_table(st
, rot_pages
, GFP_KERNEL
);
2658 /* Populate source page list from the object. */
2660 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2661 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2665 /* Rotate the pages. */
2666 rotate_pages(page_addr_list
, width_pages
, height_pages
, st
);
2669 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2670 size
, rot_info
->pitch
, rot_info
->height
,
2671 rot_info
->pixel_format
, width_pages
, height_pages
,
2674 drm_free_large(page_addr_list
);
2681 drm_free_large(page_addr_list
);
2684 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2685 size
, ret
, rot_info
->pitch
, rot_info
->height
,
2686 rot_info
->pixel_format
, width_pages
, height_pages
,
2688 return ERR_PTR(ret
);
2692 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2696 if (vma
->ggtt_view
.pages
)
2699 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2700 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2701 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2702 vma
->ggtt_view
.pages
=
2703 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2705 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2706 vma
->ggtt_view
.type
);
2708 if (!vma
->ggtt_view
.pages
) {
2709 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2710 vma
->ggtt_view
.type
);
2712 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2713 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2714 vma
->ggtt_view
.pages
= NULL
;
2715 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2716 vma
->ggtt_view
.type
, ret
);
2723 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2725 * @cache_level: mapping cache level
2726 * @flags: flags like global or local mapping
2728 * DMA addresses are taken from the scatter-gather table of this object (or of
2729 * this VMA in case of non-default GGTT views) and PTE entries set up.
2730 * Note that DMA addresses are also the only part of the SG table we care about.
2732 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2735 if (i915_is_ggtt(vma
->vm
)) {
2736 int ret
= i915_get_ggtt_vma_pages(vma
);
2742 vma
->bind_vma(vma
, cache_level
, flags
);