drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 /* PPGTT stuff */
  32 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  33
  34 #define GEN6_PDE_VALID                  (1 << 0)
  35 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  36 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  37
  38 #define GEN6_PTE_VALID                  (1 << 0)
  39 #define GEN6_PTE_UNCACHED               (1 << 1)
  40 #define HSW_PTE_UNCACHED                (0)
  41 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  42 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  43 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  44
  45 static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  46                                       dma_addr_t addr,
  47                                       enum i915_cache_level level)
  48 {
  49         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  50         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  51
  52         switch (level) {
  53         case I915_CACHE_LLC_MLC:
  54                 pte |= GEN6_PTE_CACHE_LLC_MLC;
  55                 break;
  56         case I915_CACHE_LLC:
  57                 pte |= GEN6_PTE_CACHE_LLC;
  58                 break;
  59         case I915_CACHE_NONE:
  60                 pte |= GEN6_PTE_UNCACHED;
  61                 break;
  62         default:
  63                 BUG();
  64         }
  65
  66         return pte;
  67 }
  68
  69 #define BYT_PTE_WRITEABLE               (1 << 1)
  70 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
  71
  72 static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
  73                                      dma_addr_t addr,
  74                                      enum i915_cache_level level)
  75 {
  76         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  77         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  78
  79         /* Mark the page as writeable.  Other platforms don't have a
  80          * setting for read-only/writable, so this matches that behavior.
  81          */
  82         pte |= BYT_PTE_WRITEABLE;
  83
  84         if (level != I915_CACHE_NONE)
  85                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
  86
  87         return pte;
  88 }
  89
  90 static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,
  91                                      dma_addr_t addr,
  92                                      enum i915_cache_level level)
  93 {
  94         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  95         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  96
  97         if (level != I915_CACHE_NONE)
  98                 pte |= GEN6_PTE_CACHE_LLC;
  99
 100         return pte;
 101 }
 102
 103 static int gen6_ppgtt_enable(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         uint32_t pd_offset;
 107         struct intel_ring_buffer *ring;
 108         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 109         gen6_gtt_pte_t __iomem *pd_addr;
 110         uint32_t pd_entry;
 111         int i;
 112
 113         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 114                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 115         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 116                 dma_addr_t pt_addr;
 117
 118                 pt_addr = ppgtt->pt_dma_addr[i];
 119                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 120                 pd_entry |= GEN6_PDE_VALID;
 121
 122                 writel(pd_entry, pd_addr + i);
 123         }
 124         readl(pd_addr);
 125
 126         pd_offset = ppgtt->pd_offset;
 127         pd_offset /= 64; /* in cachelines, */
 128         pd_offset <<= 16;
 129
 130         if (INTEL_INFO(dev)->gen == 6) {
 131                 uint32_t ecochk, gab_ctl, ecobits;
 132
 133                 ecobits = I915_READ(GAC_ECO_BITS);
 134                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 135                                          ECOBITS_PPGTT_CACHE64B);
 136
 137                 gab_ctl = I915_READ(GAB_CTL);
 138                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 139
 140                 ecochk = I915_READ(GAM_ECOCHK);
 141                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 142                                        ECOCHK_PPGTT_CACHE64B);
 143                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 144         } else if (INTEL_INFO(dev)->gen >= 7) {
 145                 uint32_t ecochk, ecobits;
 146
 147                 ecobits = I915_READ(GAC_ECO_BITS);
 148                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 149
 150                 ecochk = I915_READ(GAM_ECOCHK);
 151                 if (IS_HASWELL(dev)) {
 152                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 153                 } else {
 154                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 155                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 156                 }
 157                 I915_WRITE(GAM_ECOCHK, ecochk);
 158                 /* GFX_MODE is per-ring on gen7+ */
 159         }
 160
 161         for_each_ring(ring, dev_priv, i) {
 162                 if (INTEL_INFO(dev)->gen >= 7)
 163                         I915_WRITE(RING_MODE_GEN7(ring),
 164                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 165
 166                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 167                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 168         }
 169         return 0;
 170 }
 171
 172 /* PPGTT support for Sandybdrige/Gen6 and later */
 173 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 174                                    unsigned first_entry,
 175                                    unsigned num_entries)
 176 {
 177         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 178         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 179         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 180         unsigned last_pte, i;
 181
 182         scratch_pte = ppgtt->pte_encode(ppgtt->dev,
 183                                         ppgtt->scratch_page_dma_addr,
 184                                         I915_CACHE_LLC);
 185
 186         while (num_entries) {
 187                 last_pte = first_pte + num_entries;
 188                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 189                         last_pte = I915_PPGTT_PT_ENTRIES;
 190
 191                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 192
 193                 for (i = first_pte; i < last_pte; i++)
 194                         pt_vaddr[i] = scratch_pte;
 195
 196                 kunmap_atomic(pt_vaddr);
 197
 198                 num_entries -= last_pte - first_pte;
 199                 first_pte = 0;
 200                 act_pt++;
 201         }
 202 }
 203
 204 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 205                                       struct sg_table *pages,
 206                                       unsigned first_entry,
 207                                       enum i915_cache_level cache_level)
 208 {
 209         gen6_gtt_pte_t *pt_vaddr;
 210         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 211         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 212         struct sg_page_iter sg_iter;
 213
 214         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 215         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 216                 dma_addr_t page_addr;
 217
 218                 page_addr = sg_page_iter_dma_address(&sg_iter);
 219                 pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,
 220                                                       cache_level);
 221                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 222                         kunmap_atomic(pt_vaddr);
 223                         act_pt++;
 224                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 225                         act_pte = 0;
 226
 227                 }
 228         }
 229         kunmap_atomic(pt_vaddr);
 230 }
 231
 232 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 233 {
 234         int i;
 235
 236         if (ppgtt->pt_dma_addr) {
 237                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 238                         pci_unmap_page(ppgtt->dev->pdev,
 239                                        ppgtt->pt_dma_addr[i],
 240                                        4096, PCI_DMA_BIDIRECTIONAL);
 241         }
 242
 243         kfree(ppgtt->pt_dma_addr);
 244         for (i = 0; i < ppgtt->num_pd_entries; i++)
 245                 __free_page(ppgtt->pt_pages[i]);
 246         kfree(ppgtt->pt_pages);
 247         kfree(ppgtt);
 248 }
 249
 250 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 251 {
 252         struct drm_device *dev = ppgtt->dev;
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         unsigned first_pd_entry_in_global_pt;
 255         int i;
 256         int ret = -ENOMEM;
 257
 258         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 259          * entries. For aliasing ppgtt support we just steal them at the end for
 260          * now. */
 261         first_pd_entry_in_global_pt =
 262                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 263
 264         if (IS_HASWELL(dev)) {
 265                 ppgtt->pte_encode = hsw_pte_encode;
 266         } else if (IS_VALLEYVIEW(dev)) {
 267                 ppgtt->pte_encode = byt_pte_encode;
 268         } else {
 269                 ppgtt->pte_encode = gen6_pte_encode;
 270         }
 271         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 272         ppgtt->enable = gen6_ppgtt_enable;
 273         ppgtt->clear_range = gen6_ppgtt_clear_range;
 274         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 275         ppgtt->cleanup = gen6_ppgtt_cleanup;
 276         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 277                                   GFP_KERNEL);
 278         if (!ppgtt->pt_pages)
 279                 return -ENOMEM;
 280
 281         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 282                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 283                 if (!ppgtt->pt_pages[i])
 284                         goto err_pt_alloc;
 285         }
 286
 287         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 288                                      GFP_KERNEL);
 289         if (!ppgtt->pt_dma_addr)
 290                 goto err_pt_alloc;
 291
 292         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 293                 dma_addr_t pt_addr;
 294
 295                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 296                                        PCI_DMA_BIDIRECTIONAL);
 297
 298                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 299                         ret = -EIO;
 300                         goto err_pd_pin;
 301
 302                 }
 303                 ppgtt->pt_dma_addr[i] = pt_addr;
 304         }
 305
 306         ppgtt->clear_range(ppgtt, 0,
 307                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 308
 309         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 310
 311         return 0;
 312
 313 err_pd_pin:
 314         if (ppgtt->pt_dma_addr) {
 315                 for (i--; i >= 0; i--)
 316                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 317                                        4096, PCI_DMA_BIDIRECTIONAL);
 318         }
 319 err_pt_alloc:
 320         kfree(ppgtt->pt_dma_addr);
 321         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 322                 if (ppgtt->pt_pages[i])
 323                         __free_page(ppgtt->pt_pages[i]);
 324         }
 325         kfree(ppgtt->pt_pages);
 326
 327         return ret;
 328 }
 329
 330 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 331 {
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333         struct i915_hw_ppgtt *ppgtt;
 334         int ret;
 335
 336         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 337         if (!ppgtt)
 338                 return -ENOMEM;
 339
 340         ppgtt->dev = dev;
 341         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 342
 343         if (INTEL_INFO(dev)->gen < 8)
 344                 ret = gen6_ppgtt_init(ppgtt);
 345         else
 346                 BUG();
 347
 348         if (ret)
 349                 kfree(ppgtt);
 350         else
 351                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 352
 353         return ret;
 354 }
 355
 356 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 360
 361         if (!ppgtt)
 362                 return;
 363
 364         ppgtt->cleanup(ppgtt);
 365         dev_priv->mm.aliasing_ppgtt = NULL;
 366 }
 367
 368 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 369                             struct drm_i915_gem_object *obj,
 370                             enum i915_cache_level cache_level)
 371 {
 372         ppgtt->insert_entries(ppgtt, obj->pages,
 373                               obj->gtt_space->start >> PAGE_SHIFT,
 374                               cache_level);
 375 }
 376
 377 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 378                               struct drm_i915_gem_object *obj)
 379 {
 380         ppgtt->clear_range(ppgtt,
 381                            obj->gtt_space->start >> PAGE_SHIFT,
 382                            obj->base.size >> PAGE_SHIFT);
 383 }
 384
 385 extern int intel_iommu_gfx_mapped;
 386 /* Certain Gen5 chipsets require require idling the GPU before
 387  * unmapping anything from the GTT when VT-d is enabled.
 388  */
 389 static inline bool needs_idle_maps(struct drm_device *dev)
 390 {
 391 #ifdef CONFIG_INTEL_IOMMU
 392         /* Query intel_iommu to see if we need the workaround. Presumably that
 393          * was loaded first.
 394          */
 395         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 396                 return true;
 397 #endif
 398         return false;
 399 }
 400
 401 static bool do_idling(struct drm_i915_private *dev_priv)
 402 {
 403         bool ret = dev_priv->mm.interruptible;
 404
 405         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 406                 dev_priv->mm.interruptible = false;
 407                 if (i915_gpu_idle(dev_priv->dev)) {
 408                         DRM_ERROR("Couldn't idle GPU\n");
 409                         /* Wait a bit, in hopes it avoids the hang */
 410                         udelay(10);
 411                 }
 412         }
 413
 414         return ret;
 415 }
 416
 417 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 418 {
 419         if (unlikely(dev_priv->gtt.do_idle_maps))
 420                 dev_priv->mm.interruptible = interruptible;
 421 }
 422
 423 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 424 {
 425         struct drm_i915_private *dev_priv = dev->dev_private;
 426         struct drm_i915_gem_object *obj;
 427
 428         /* First fill our portion of the GTT with scratch pages */
 429         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 430                                       dev_priv->gtt.total / PAGE_SIZE);
 431
 432         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 433                 i915_gem_clflush_object(obj);
 434                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 435         }
 436
 437         i915_gem_chipset_flush(dev);
 438 }
 439
 440 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 441 {
 442         if (obj->has_dma_mapping)
 443                 return 0;
 444
 445         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 446                         obj->pages->sgl, obj->pages->nents,
 447                         PCI_DMA_BIDIRECTIONAL))
 448                 return -ENOSPC;
 449
 450         return 0;
 451 }
 452
 453 /*
 454  * Binds an object into the global gtt with the specified cache level. The object
 455  * will be accessible to the GPU via commands whose operands reference offsets
 456  * within the global GTT as well as accessible by the GPU through the GMADR
 457  * mapped BAR (dev_priv->mm.gtt->gtt).
 458  */
 459 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 460                                      struct sg_table *st,
 461                                      unsigned int first_entry,
 462                                      enum i915_cache_level level)
 463 {
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         gen6_gtt_pte_t __iomem *gtt_entries =
 466                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 467         int i = 0;
 468         struct sg_page_iter sg_iter;
 469         dma_addr_t addr;
 470
 471         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 472                 addr = sg_page_iter_dma_address(&sg_iter);
 473                 iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),
 474                           &gtt_entries[i]);
 475                 i++;
 476         }
 477
 478         /* XXX: This serves as a posting read to make sure that the PTE has
 479          * actually been updated. There is some concern that even though
 480          * registers and PTEs are within the same BAR that they are potentially
 481          * of NUMA access patterns. Therefore, even with the way we assume
 482          * hardware should work, we must keep this posting read for paranoia.
 483          */
 484         if (i != 0)
 485                 WARN_ON(readl(&gtt_entries[i-1])
 486                         != dev_priv->gtt.pte_encode(dev, addr, level));
 487
 488         /* This next bit makes the above posting read even more important. We
 489          * want to flush the TLBs only after we're certain all the PTE updates
 490          * have finished.
 491          */
 492         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 493         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 494 }
 495
 496 static void gen6_ggtt_clear_range(struct drm_device *dev,
 497                                   unsigned int first_entry,
 498                                   unsigned int num_entries)
 499 {
 500         struct drm_i915_private *dev_priv = dev->dev_private;
 501         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 502                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 503         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 504         int i;
 505
 506         if (WARN(num_entries > max_entries,
 507                  "First entry = %d; Num entries = %d (max=%d)\n",
 508                  first_entry, num_entries, max_entries))
 509                 num_entries = max_entries;
 510
 511         scratch_pte = dev_priv->gtt.pte_encode(dev,
 512                                                dev_priv->gtt.scratch_page_dma,
 513                                                I915_CACHE_LLC);
 514         for (i = 0; i < num_entries; i++)
 515                 iowrite32(scratch_pte, &gtt_base[i]);
 516         readl(gtt_base);
 517 }
 518
 519
 520 static void i915_ggtt_insert_entries(struct drm_device *dev,
 521                                      struct sg_table *st,
 522                                      unsigned int pg_start,
 523                                      enum i915_cache_level cache_level)
 524 {
 525         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 526                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 527
 528         intel_gtt_insert_sg_entries(st, pg_start, flags);
 529
 530 }
 531
 532 static void i915_ggtt_clear_range(struct drm_device *dev,
 533                                   unsigned int first_entry,
 534                                   unsigned int num_entries)
 535 {
 536         intel_gtt_clear_range(first_entry, num_entries);
 537 }
 538
 539
 540 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 541                               enum i915_cache_level cache_level)
 542 {
 543         struct drm_device *dev = obj->base.dev;
 544         struct drm_i915_private *dev_priv = dev->dev_private;
 545
 546         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 547                                          obj->gtt_space->start >> PAGE_SHIFT,
 548                                          cache_level);
 549
 550         obj->has_global_gtt_mapping = 1;
 551 }
 552
 553 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 554 {
 555         struct drm_device *dev = obj->base.dev;
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557
 558         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 559                                       obj->gtt_space->start >> PAGE_SHIFT,
 560                                       obj->base.size >> PAGE_SHIFT);
 561
 562         obj->has_global_gtt_mapping = 0;
 563 }
 564
 565 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 566 {
 567         struct drm_device *dev = obj->base.dev;
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         bool interruptible;
 570
 571         interruptible = do_idling(dev_priv);
 572
 573         if (!obj->has_dma_mapping)
 574                 dma_unmap_sg(&dev->pdev->dev,
 575                              obj->pages->sgl, obj->pages->nents,
 576                              PCI_DMA_BIDIRECTIONAL);
 577
 578         undo_idling(dev_priv, interruptible);
 579 }
 580
 581 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 582                                   unsigned long color,
 583                                   unsigned long *start,
 584                                   unsigned long *end)
 585 {
 586         if (node->color != color)
 587                 *start += 4096;
 588
 589         if (!list_empty(&node->node_list)) {
 590                 node = list_entry(node->node_list.next,
 591                                   struct drm_mm_node,
 592                                   node_list);
 593                 if (node->allocated && node->color != color)
 594                         *end -= 4096;
 595         }
 596 }
 597 void i915_gem_setup_global_gtt(struct drm_device *dev,
 598                                unsigned long start,
 599                                unsigned long mappable_end,
 600                                unsigned long end)
 601 {
 602         /* Let GEM Manage all of the aperture.
 603          *
 604          * However, leave one page at the end still bound to the scratch page.
 605          * There are a number of places where the hardware apparently prefetches
 606          * past the end of the object, and we've seen multiple hangs with the
 607          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 608          * aperture.  One page should be enough to keep any prefetching inside
 609          * of the aperture.
 610          */
 611         drm_i915_private_t *dev_priv = dev->dev_private;
 612         struct drm_mm_node *entry;
 613         struct drm_i915_gem_object *obj;
 614         unsigned long hole_start, hole_end;
 615
 616         BUG_ON(mappable_end > end);
 617
 618         /* Subtract the guard page ... */
 619         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 620         if (!HAS_LLC(dev))
 621                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 622
 623         /* Mark any preallocated objects as occupied */
 624         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 625                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 626                               obj->gtt_offset, obj->base.size);
 627
 628                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 629                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 630                                                      obj->gtt_offset,
 631                                                      obj->base.size,
 632                                                      false);
 633                 obj->has_global_gtt_mapping = 1;
 634         }
 635
 636         dev_priv->gtt.start = start;
 637         dev_priv->gtt.total = end - start;
 638
 639         /* Clear any non-preallocated blocks */
 640         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 641                              hole_start, hole_end) {
 642                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 643                               hole_start, hole_end);
 644                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 645                                               (hole_end-hole_start) / PAGE_SIZE);
 646         }
 647
 648         /* And finally clear the reserved guard page */
 649         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 650 }
 651
 652 static bool
 653 intel_enable_ppgtt(struct drm_device *dev)
 654 {
 655         if (i915_enable_ppgtt >= 0)
 656                 return i915_enable_ppgtt;
 657
 658 #ifdef CONFIG_INTEL_IOMMU
 659         /* Disable ppgtt on SNB if VT-d is on. */
 660         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 661                 return false;
 662 #endif
 663
 664         return true;
 665 }
 666
 667 void i915_gem_init_global_gtt(struct drm_device *dev)
 668 {
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         unsigned long gtt_size, mappable_size;
 671
 672         gtt_size = dev_priv->gtt.total;
 673         mappable_size = dev_priv->gtt.mappable_end;
 674
 675         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 676                 int ret;
 677
 678                 if (INTEL_INFO(dev)->gen <= 7) {
 679                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 680                          * aperture accordingly when using aliasing ppgtt. */
 681                         gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 682                 }
 683
 684                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 685
 686                 ret = i915_gem_init_aliasing_ppgtt(dev);
 687                 if (!ret)
 688                         return;
 689
 690                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 691                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 692                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 693         }
 694         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 695 }
 696
 697 static int setup_scratch_page(struct drm_device *dev)
 698 {
 699         struct drm_i915_private *dev_priv = dev->dev_private;
 700         struct page *page;
 701         dma_addr_t dma_addr;
 702
 703         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 704         if (page == NULL)
 705                 return -ENOMEM;
 706         get_page(page);
 707         set_pages_uc(page, 1);
 708
 709 #ifdef CONFIG_INTEL_IOMMU
 710         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 711                                 PCI_DMA_BIDIRECTIONAL);
 712         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 713                 return -EINVAL;
 714 #else
 715         dma_addr = page_to_phys(page);
 716 #endif
 717         dev_priv->gtt.scratch_page = page;
 718         dev_priv->gtt.scratch_page_dma = dma_addr;
 719
 720         return 0;
 721 }
 722
 723 static void teardown_scratch_page(struct drm_device *dev)
 724 {
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 727         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 728                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 729         put_page(dev_priv->gtt.scratch_page);
 730         __free_page(dev_priv->gtt.scratch_page);
 731 }
 732
 733 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 734 {
 735         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 736         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 737         return snb_gmch_ctl << 20;
 738 }
 739
 740 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 741 {
 742         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 743         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 744         return snb_gmch_ctl << 25; /* 32 MB units */
 745 }
 746
 747 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 748 {
 749         static const int stolen_decoder[] = {
 750                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 751         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 752         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 753         return stolen_decoder[snb_gmch_ctl] << 20;
 754 }
 755
 756 static int gen6_gmch_probe(struct drm_device *dev,
 757                            size_t *gtt_total,
 758                            size_t *stolen,
 759                            phys_addr_t *mappable_base,
 760                            unsigned long *mappable_end)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         phys_addr_t gtt_bus_addr;
 764         unsigned int gtt_size;
 765         u16 snb_gmch_ctl;
 766         int ret;
 767
 768         *mappable_base = pci_resource_start(dev->pdev, 2);
 769         *mappable_end = pci_resource_len(dev->pdev, 2);
 770
 771         /* 64/512MB is the current min/max we actually know of, but this is just
 772          * a coarse sanity check.
 773          */
 774         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 775                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 776                           dev_priv->gtt.mappable_end);
 777                 return -ENXIO;
 778         }
 779
 780         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 781                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 782         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 783         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 784
 785         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 786                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 787         else
 788                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 789
 790         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 791
 792         /* For Modern GENs the PTEs and register space are split in the BAR */
 793         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 794                 (pci_resource_len(dev->pdev, 0) / 2);
 795
 796         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 797         if (!dev_priv->gtt.gsm) {
 798                 DRM_ERROR("Failed to map the gtt page table\n");
 799                 return -ENOMEM;
 800         }
 801
 802         ret = setup_scratch_page(dev);
 803         if (ret)
 804                 DRM_ERROR("Scratch setup failed\n");
 805
 806         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 807         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 808
 809         return ret;
 810 }
 811
 812 static void gen6_gmch_remove(struct drm_device *dev)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         iounmap(dev_priv->gtt.gsm);
 816         teardown_scratch_page(dev_priv->dev);
 817 }
 818
 819 static int i915_gmch_probe(struct drm_device *dev,
 820                            size_t *gtt_total,
 821                            size_t *stolen,
 822                            phys_addr_t *mappable_base,
 823                            unsigned long *mappable_end)
 824 {
 825         struct drm_i915_private *dev_priv = dev->dev_private;
 826         int ret;
 827
 828         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 829         if (!ret) {
 830                 DRM_ERROR("failed to set up gmch\n");
 831                 return -EIO;
 832         }
 833
 834         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 835
 836         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 837         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 838         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 839
 840         return 0;
 841 }
 842
 843 static void i915_gmch_remove(struct drm_device *dev)
 844 {
 845         intel_gmch_remove();
 846 }
 847
 848 int i915_gem_gtt_init(struct drm_device *dev)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         struct i915_gtt *gtt = &dev_priv->gtt;
 852         int ret;
 853
 854         if (INTEL_INFO(dev)->gen <= 5) {
 855                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 856                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 857         } else {
 858                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 859                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 860                 if (IS_HASWELL(dev)) {
 861                         dev_priv->gtt.pte_encode = hsw_pte_encode;
 862                 } else if (IS_VALLEYVIEW(dev)) {
 863                         dev_priv->gtt.pte_encode = byt_pte_encode;
 864                 } else {
 865                         dev_priv->gtt.pte_encode = gen6_pte_encode;
 866                 }
 867         }
 868
 869         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 870                                      &dev_priv->gtt.stolen_size,
 871                                      &gtt->mappable_base,
 872                                      &gtt->mappable_end);
 873         if (ret)
 874                 return ret;
 875
 876         /* GMADR is the PCI mmio aperture into the global GTT. */
 877         DRM_INFO("Memory usable by graphics device = %zdM\n",
 878                  dev_priv->gtt.total >> 20);
 879         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 880                          dev_priv->gtt.mappable_end >> 20);
 881         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 882                          dev_priv->gtt.stolen_size >> 20);
 883
 884         return 0;
 885 }