2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
107 bool has_full_48bit_ppgtt
;
109 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
110 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 has_full_48bit_ppgtt
= IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9;
113 if (intel_vgpu_active(dev
))
114 has_full_ppgtt
= false; /* emulation is too hard */
117 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
118 * execlists, the sole mechanism available to submit work.
120 if (INTEL_INFO(dev
)->gen
< 9 &&
121 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
124 if (enable_ppgtt
== 1)
127 if (enable_ppgtt
== 2 && has_full_ppgtt
)
130 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
133 #ifdef CONFIG_INTEL_IOMMU
134 /* Disable ppgtt on SNB if VT-d is on. */
135 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
136 DRM_INFO("Disabling PPGTT because VT-d is on\n");
141 /* Early VLV doesn't have this */
142 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
143 dev
->pdev
->revision
< 0xb) {
144 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
148 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
149 return has_full_48bit_ppgtt
? 3 : 2;
151 return has_aliasing_ppgtt
? 1 : 0;
154 static int ppgtt_bind_vma(struct i915_vma
*vma
,
155 enum i915_cache_level cache_level
,
160 /* Currently applicable only to VLV */
162 pte_flags
|= PTE_READ_ONLY
;
164 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
165 cache_level
, pte_flags
);
170 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
172 vma
->vm
->clear_range(vma
->vm
,
178 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
179 enum i915_cache_level level
,
182 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
186 case I915_CACHE_NONE
:
187 pte
|= PPAT_UNCACHED_INDEX
;
190 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
193 pte
|= PPAT_CACHED_INDEX
;
200 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
201 const enum i915_cache_level level
)
203 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
205 if (level
!= I915_CACHE_NONE
)
206 pde
|= PPAT_CACHED_PDE_INDEX
;
208 pde
|= PPAT_UNCACHED_INDEX
;
212 #define gen8_pdpe_encode gen8_pde_encode
213 #define gen8_pml4e_encode gen8_pde_encode
215 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
216 enum i915_cache_level level
,
217 bool valid
, u32 unused
)
219 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
220 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
223 case I915_CACHE_L3_LLC
:
225 pte
|= GEN6_PTE_CACHE_LLC
;
227 case I915_CACHE_NONE
:
228 pte
|= GEN6_PTE_UNCACHED
;
237 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
238 enum i915_cache_level level
,
239 bool valid
, u32 unused
)
241 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
242 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
245 case I915_CACHE_L3_LLC
:
246 pte
|= GEN7_PTE_CACHE_L3_LLC
;
249 pte
|= GEN6_PTE_CACHE_LLC
;
251 case I915_CACHE_NONE
:
252 pte
|= GEN6_PTE_UNCACHED
;
261 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
262 enum i915_cache_level level
,
263 bool valid
, u32 flags
)
265 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
266 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
268 if (!(flags
& PTE_READ_ONLY
))
269 pte
|= BYT_PTE_WRITEABLE
;
271 if (level
!= I915_CACHE_NONE
)
272 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
277 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
278 enum i915_cache_level level
,
279 bool valid
, u32 unused
)
281 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
282 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
284 if (level
!= I915_CACHE_NONE
)
285 pte
|= HSW_WB_LLC_AGE3
;
290 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
291 enum i915_cache_level level
,
292 bool valid
, u32 unused
)
294 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
295 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
298 case I915_CACHE_NONE
:
301 pte
|= HSW_WT_ELLC_LLC_AGE3
;
304 pte
|= HSW_WB_ELLC_LLC_AGE3
;
311 static int __setup_page_dma(struct drm_device
*dev
,
312 struct i915_page_dma
*p
, gfp_t flags
)
314 struct device
*device
= &dev
->pdev
->dev
;
316 p
->page
= alloc_page(flags
);
320 p
->daddr
= dma_map_page(device
,
321 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
323 if (dma_mapping_error(device
, p
->daddr
)) {
324 __free_page(p
->page
);
331 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
333 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
336 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
338 if (WARN_ON(!p
->page
))
341 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
342 __free_page(p
->page
);
343 memset(p
, 0, sizeof(*p
));
346 static void *kmap_page_dma(struct i915_page_dma
*p
)
348 return kmap_atomic(p
->page
);
351 /* We use the flushing unmap only with ppgtt structures:
352 * page directories, page tables and scratch pages.
354 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
356 /* There are only few exceptions for gen >=6. chv and bxt.
357 * And we are not sure about the latter so play safe for now.
359 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
360 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
362 kunmap_atomic(vaddr
);
365 #define kmap_px(px) kmap_page_dma(px_base(px))
366 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
368 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
369 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
370 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
371 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
373 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
377 uint64_t * const vaddr
= kmap_page_dma(p
);
379 for (i
= 0; i
< 512; i
++)
382 kunmap_page_dma(dev
, vaddr
);
385 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
386 const uint32_t val32
)
392 fill_page_dma(dev
, p
, v
);
395 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
397 struct i915_page_scratch
*sp
;
400 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
402 return ERR_PTR(-ENOMEM
);
404 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
410 set_pages_uc(px_page(sp
), 1);
415 static void free_scratch_page(struct drm_device
*dev
,
416 struct i915_page_scratch
*sp
)
418 set_pages_wb(px_page(sp
), 1);
424 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
426 struct i915_page_table
*pt
;
427 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
428 GEN8_PTES
: GEN6_PTES
;
431 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
433 return ERR_PTR(-ENOMEM
);
435 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
441 ret
= setup_px(dev
, pt
);
448 kfree(pt
->used_ptes
);
455 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
458 kfree(pt
->used_ptes
);
462 static void gen8_initialize_pt(struct i915_address_space
*vm
,
463 struct i915_page_table
*pt
)
465 gen8_pte_t scratch_pte
;
467 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
468 I915_CACHE_LLC
, true);
470 fill_px(vm
->dev
, pt
, scratch_pte
);
473 static void gen6_initialize_pt(struct i915_address_space
*vm
,
474 struct i915_page_table
*pt
)
476 gen6_pte_t scratch_pte
;
478 WARN_ON(px_dma(vm
->scratch_page
) == 0);
480 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
481 I915_CACHE_LLC
, true, 0);
483 fill32_px(vm
->dev
, pt
, scratch_pte
);
486 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
488 struct i915_page_directory
*pd
;
491 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
493 return ERR_PTR(-ENOMEM
);
495 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
496 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
500 ret
= setup_px(dev
, pd
);
507 kfree(pd
->used_pdes
);
514 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
518 kfree(pd
->used_pdes
);
523 static void gen8_initialize_pd(struct i915_address_space
*vm
,
524 struct i915_page_directory
*pd
)
526 gen8_pde_t scratch_pde
;
528 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
530 fill_px(vm
->dev
, pd
, scratch_pde
);
533 static int __pdp_init(struct drm_device
*dev
,
534 struct i915_page_directory_pointer
*pdp
)
536 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
538 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
539 sizeof(unsigned long),
541 if (!pdp
->used_pdpes
)
544 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
546 if (!pdp
->page_directory
) {
547 kfree(pdp
->used_pdpes
);
548 /* the PDP might be the statically allocated top level. Keep it
549 * as clean as possible */
550 pdp
->used_pdpes
= NULL
;
557 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
559 kfree(pdp
->used_pdpes
);
560 kfree(pdp
->page_directory
);
561 pdp
->page_directory
= NULL
;
565 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
567 struct i915_page_directory_pointer
*pdp
;
570 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
572 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
574 return ERR_PTR(-ENOMEM
);
576 ret
= __pdp_init(dev
, pdp
);
580 ret
= setup_px(dev
, pdp
);
594 static void free_pdp(struct drm_device
*dev
,
595 struct i915_page_directory_pointer
*pdp
)
598 if (USES_FULL_48BIT_PPGTT(dev
)) {
599 cleanup_px(dev
, pdp
);
604 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
605 struct i915_page_directory_pointer
*pdp
)
607 gen8_ppgtt_pdpe_t scratch_pdpe
;
609 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
611 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
614 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
615 struct i915_pml4
*pml4
)
617 gen8_ppgtt_pml4e_t scratch_pml4e
;
619 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
622 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
626 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
627 struct i915_page_directory_pointer
*pdp
,
628 struct i915_page_directory
*pd
,
631 gen8_ppgtt_pdpe_t
*page_directorypo
;
633 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
636 page_directorypo
= kmap_px(pdp
);
637 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
638 kunmap_px(ppgtt
, page_directorypo
);
642 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
643 struct i915_pml4
*pml4
,
644 struct i915_page_directory_pointer
*pdp
,
647 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
649 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
650 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
651 kunmap_px(ppgtt
, pagemap
);
654 /* Broadwell Page Directory Pointer Descriptors */
655 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
659 struct intel_engine_cs
*ring
= req
->ring
;
664 ret
= intel_ring_begin(req
, 6);
668 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
669 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
670 intel_ring_emit(ring
, upper_32_bits(addr
));
671 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
672 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
673 intel_ring_emit(ring
, lower_32_bits(addr
));
674 intel_ring_advance(ring
);
679 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
680 struct drm_i915_gem_request
*req
)
684 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
685 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
687 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
695 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
696 struct drm_i915_gem_request
*req
)
698 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
701 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
702 struct i915_page_directory_pointer
*pdp
,
705 gen8_pte_t scratch_pte
)
707 struct i915_hw_ppgtt
*ppgtt
=
708 container_of(vm
, struct i915_hw_ppgtt
, base
);
709 gen8_pte_t
*pt_vaddr
;
710 unsigned pdpe
= gen8_pdpe_index(start
);
711 unsigned pde
= gen8_pde_index(start
);
712 unsigned pte
= gen8_pte_index(start
);
713 unsigned num_entries
= length
>> PAGE_SHIFT
;
714 unsigned last_pte
, i
;
719 while (num_entries
) {
720 struct i915_page_directory
*pd
;
721 struct i915_page_table
*pt
;
723 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
726 pd
= pdp
->page_directory
[pdpe
];
728 if (WARN_ON(!pd
->page_table
[pde
]))
731 pt
= pd
->page_table
[pde
];
733 if (WARN_ON(!px_page(pt
)))
736 last_pte
= pte
+ num_entries
;
737 if (last_pte
> GEN8_PTES
)
738 last_pte
= GEN8_PTES
;
740 pt_vaddr
= kmap_px(pt
);
742 for (i
= pte
; i
< last_pte
; i
++) {
743 pt_vaddr
[i
] = scratch_pte
;
747 kunmap_px(ppgtt
, pt
);
750 if (++pde
== I915_PDES
) {
751 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
758 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
763 struct i915_hw_ppgtt
*ppgtt
=
764 container_of(vm
, struct i915_hw_ppgtt
, base
);
765 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
766 I915_CACHE_LLC
, use_scratch
);
768 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
769 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
772 uint64_t templ4
, pml4e
;
773 struct i915_page_directory_pointer
*pdp
;
775 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, templ4
, pml4e
) {
776 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
783 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
784 struct i915_page_directory_pointer
*pdp
,
785 struct sg_page_iter
*sg_iter
,
787 enum i915_cache_level cache_level
)
789 struct i915_hw_ppgtt
*ppgtt
=
790 container_of(vm
, struct i915_hw_ppgtt
, base
);
791 gen8_pte_t
*pt_vaddr
;
792 unsigned pdpe
= gen8_pdpe_index(start
);
793 unsigned pde
= gen8_pde_index(start
);
794 unsigned pte
= gen8_pte_index(start
);
798 while (__sg_page_iter_next(sg_iter
)) {
799 if (pt_vaddr
== NULL
) {
800 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
801 struct i915_page_table
*pt
= pd
->page_table
[pde
];
802 pt_vaddr
= kmap_px(pt
);
806 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
808 if (++pte
== GEN8_PTES
) {
809 kunmap_px(ppgtt
, pt_vaddr
);
811 if (++pde
== I915_PDES
) {
812 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
821 kunmap_px(ppgtt
, pt_vaddr
);
824 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
825 struct sg_table
*pages
,
827 enum i915_cache_level cache_level
,
830 struct i915_hw_ppgtt
*ppgtt
=
831 container_of(vm
, struct i915_hw_ppgtt
, base
);
832 struct sg_page_iter sg_iter
;
834 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
836 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
837 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
840 struct i915_page_directory_pointer
*pdp
;
841 uint64_t templ4
, pml4e
;
842 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
844 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, templ4
, pml4e
) {
845 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
851 static void gen8_free_page_tables(struct drm_device
*dev
,
852 struct i915_page_directory
*pd
)
859 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
860 if (WARN_ON(!pd
->page_table
[i
]))
863 free_pt(dev
, pd
->page_table
[i
]);
864 pd
->page_table
[i
] = NULL
;
868 static int gen8_init_scratch(struct i915_address_space
*vm
)
870 struct drm_device
*dev
= vm
->dev
;
872 vm
->scratch_page
= alloc_scratch_page(dev
);
873 if (IS_ERR(vm
->scratch_page
))
874 return PTR_ERR(vm
->scratch_page
);
876 vm
->scratch_pt
= alloc_pt(dev
);
877 if (IS_ERR(vm
->scratch_pt
)) {
878 free_scratch_page(dev
, vm
->scratch_page
);
879 return PTR_ERR(vm
->scratch_pt
);
882 vm
->scratch_pd
= alloc_pd(dev
);
883 if (IS_ERR(vm
->scratch_pd
)) {
884 free_pt(dev
, vm
->scratch_pt
);
885 free_scratch_page(dev
, vm
->scratch_page
);
886 return PTR_ERR(vm
->scratch_pd
);
889 if (USES_FULL_48BIT_PPGTT(dev
)) {
890 vm
->scratch_pdp
= alloc_pdp(dev
);
891 if (IS_ERR(vm
->scratch_pdp
)) {
892 free_pd(dev
, vm
->scratch_pd
);
893 free_pt(dev
, vm
->scratch_pt
);
894 free_scratch_page(dev
, vm
->scratch_page
);
895 return PTR_ERR(vm
->scratch_pdp
);
899 gen8_initialize_pt(vm
, vm
->scratch_pt
);
900 gen8_initialize_pd(vm
, vm
->scratch_pd
);
901 if (USES_FULL_48BIT_PPGTT(dev
))
902 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
907 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
909 enum vgt_g2v_type msg
;
910 struct drm_device
*dev
= ppgtt
->base
.dev
;
911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
912 unsigned int offset
= vgtif_reg(pdp0_lo
);
915 if (USES_FULL_48BIT_PPGTT(dev
)) {
916 u64 daddr
= px_dma(&ppgtt
->pml4
);
918 I915_WRITE(offset
, lower_32_bits(daddr
));
919 I915_WRITE(offset
+ 4, upper_32_bits(daddr
));
921 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
922 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
924 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
925 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
927 I915_WRITE(offset
, lower_32_bits(daddr
));
928 I915_WRITE(offset
+ 4, upper_32_bits(daddr
));
933 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
934 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
937 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
942 static void gen8_free_scratch(struct i915_address_space
*vm
)
944 struct drm_device
*dev
= vm
->dev
;
946 if (USES_FULL_48BIT_PPGTT(dev
))
947 free_pdp(dev
, vm
->scratch_pdp
);
948 free_pd(dev
, vm
->scratch_pd
);
949 free_pt(dev
, vm
->scratch_pt
);
950 free_scratch_page(dev
, vm
->scratch_page
);
953 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
954 struct i915_page_directory_pointer
*pdp
)
958 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
959 if (WARN_ON(!pdp
->page_directory
[i
]))
962 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
963 free_pd(dev
, pdp
->page_directory
[i
]);
969 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
973 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
974 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
977 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
980 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
983 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
985 struct i915_hw_ppgtt
*ppgtt
=
986 container_of(vm
, struct i915_hw_ppgtt
, base
);
988 if (intel_vgpu_active(vm
->dev
))
989 gen8_ppgtt_notify_vgt(ppgtt
, false);
991 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
992 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
994 gen8_ppgtt_cleanup_4lvl(ppgtt
);
996 gen8_free_scratch(vm
);
1000 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1001 * @vm: Master vm structure.
1002 * @pd: Page directory for this address range.
1003 * @start: Starting virtual address to begin allocations.
1004 * @length: Size of the allocations.
1005 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1006 * caller to free on error.
1008 * Allocate the required number of page tables. Extremely similar to
1009 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1010 * the page directory boundary (instead of the page directory pointer). That
1011 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1012 * possible, and likely that the caller will need to use multiple calls of this
1013 * function to achieve the appropriate allocation.
1015 * Return: 0 if success; negative error code otherwise.
1017 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1018 struct i915_page_directory
*pd
,
1021 unsigned long *new_pts
)
1023 struct drm_device
*dev
= vm
->dev
;
1024 struct i915_page_table
*pt
;
1028 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
1029 /* Don't reallocate page tables */
1030 if (test_bit(pde
, pd
->used_pdes
)) {
1031 /* Scratch is never allocated this way */
1032 WARN_ON(pt
== vm
->scratch_pt
);
1040 gen8_initialize_pt(vm
, pt
);
1041 pd
->page_table
[pde
] = pt
;
1042 __set_bit(pde
, new_pts
);
1043 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1049 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1050 free_pt(dev
, pd
->page_table
[pde
]);
1056 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1057 * @vm: Master vm structure.
1058 * @pdp: Page directory pointer for this address range.
1059 * @start: Starting virtual address to begin allocations.
1060 * @length: Size of the allocations.
1061 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1062 * caller to free on error.
1064 * Allocate the required number of page directories starting at the pde index of
1065 * @start, and ending at the pde index @start + @length. This function will skip
1066 * over already allocated page directories within the range, and only allocate
1067 * new ones, setting the appropriate pointer within the pdp as well as the
1068 * correct position in the bitmap @new_pds.
1070 * The function will only allocate the pages within the range for a give page
1071 * directory pointer. In other words, if @start + @length straddles a virtually
1072 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1073 * required by the caller, This is not currently possible, and the BUG in the
1074 * code will prevent it.
1076 * Return: 0 if success; negative error code otherwise.
1079 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1080 struct i915_page_directory_pointer
*pdp
,
1083 unsigned long *new_pds
)
1085 struct drm_device
*dev
= vm
->dev
;
1086 struct i915_page_directory
*pd
;
1089 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1091 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1093 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1094 if (test_bit(pdpe
, pdp
->used_pdpes
))
1101 gen8_initialize_pd(vm
, pd
);
1102 pdp
->page_directory
[pdpe
] = pd
;
1103 __set_bit(pdpe
, new_pds
);
1104 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1110 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1111 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1117 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1118 * @vm: Master vm structure.
1119 * @pml4: Page map level 4 for this address range.
1120 * @start: Starting virtual address to begin allocations.
1121 * @length: Size of the allocations.
1122 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1123 * caller to free on error.
1125 * Allocate the required number of page directory pointers. Extremely similar to
1126 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1127 * The main difference is here we are limited by the pml4 boundary (instead of
1128 * the page directory pointer).
1130 * Return: 0 if success; negative error code otherwise.
1133 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1134 struct i915_pml4
*pml4
,
1137 unsigned long *new_pdps
)
1139 struct drm_device
*dev
= vm
->dev
;
1140 struct i915_page_directory_pointer
*pdp
;
1144 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1146 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1147 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1148 pdp
= alloc_pdp(dev
);
1152 gen8_initialize_pdp(vm
, pdp
);
1153 pml4
->pdps
[pml4e
] = pdp
;
1154 __set_bit(pml4e
, new_pdps
);
1155 trace_i915_page_directory_pointer_entry_alloc(vm
,
1165 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1166 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1172 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1178 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1179 * of these are based on the number of PDPEs in the system.
1182 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1183 unsigned long **new_pts
,
1189 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1193 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1204 free_gen8_temp_bitmaps(pds
, pts
);
1208 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1209 * the page table structures, we mark them dirty so that
1210 * context switching/execlist queuing code takes extra steps
1211 * to ensure that tlbs are flushed.
1213 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1215 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1218 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1219 struct i915_page_directory_pointer
*pdp
,
1223 struct i915_hw_ppgtt
*ppgtt
=
1224 container_of(vm
, struct i915_hw_ppgtt
, base
);
1225 unsigned long *new_page_dirs
, *new_page_tables
;
1226 struct drm_device
*dev
= vm
->dev
;
1227 struct i915_page_directory
*pd
;
1228 const uint64_t orig_start
= start
;
1229 const uint64_t orig_length
= length
;
1232 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1235 /* Wrap is never okay since we can only represent 48b, and we don't
1236 * actually use the other side of the canonical address space.
1238 if (WARN_ON(start
+ length
< start
))
1241 if (WARN_ON(start
+ length
> vm
->total
))
1244 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1248 /* Do the allocations first so we can easily bail out */
1249 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1252 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1256 /* For every page directory referenced, allocate page tables */
1257 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1258 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1259 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1265 length
= orig_length
;
1267 /* Allocations have completed successfully, so set the bitmaps, and do
1269 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1270 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1271 struct i915_page_table
*pt
;
1272 uint64_t pd_len
= length
;
1273 uint64_t pd_start
= start
;
1276 /* Every pd should be allocated, we just did that above. */
1279 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1280 /* Same reasoning as pd */
1283 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1285 /* Set our used ptes within the page table */
1286 bitmap_set(pt
->used_ptes
,
1287 gen8_pte_index(pd_start
),
1288 gen8_pte_count(pd_start
, pd_len
));
1290 /* Our pde is now pointing to the pagetable, pt */
1291 __set_bit(pde
, pd
->used_pdes
);
1293 /* Map the PDE to the page table */
1294 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1296 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1297 gen8_pte_index(start
),
1298 gen8_pte_count(start
, length
),
1301 /* NB: We haven't yet mapped ptes to pages. At this
1302 * point we're still relying on insert_entries() */
1305 kunmap_px(ppgtt
, page_directory
);
1306 __set_bit(pdpe
, pdp
->used_pdpes
);
1307 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1310 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1311 mark_tlbs_dirty(ppgtt
);
1316 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1317 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1318 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1321 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1322 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1324 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1325 mark_tlbs_dirty(ppgtt
);
1329 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1330 struct i915_pml4
*pml4
,
1334 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1335 struct i915_hw_ppgtt
*ppgtt
=
1336 container_of(vm
, struct i915_hw_ppgtt
, base
);
1337 struct i915_page_directory_pointer
*pdp
;
1338 uint64_t temp
, pml4e
;
1341 /* Do the pml4 allocations first, so we don't need to track the newly
1342 * allocated tables below the pdp */
1343 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1345 /* The pagedirectory and pagetable allocations are done in the shared 3
1346 * and 4 level code. Just allocate the pdps.
1348 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1353 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1354 "The allocation has spanned more than 512GB. "
1355 "It is highly likely this is incorrect.");
1357 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1360 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1364 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1367 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1368 GEN8_PML4ES_PER_PML4
);
1373 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1374 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1379 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1380 uint64_t start
, uint64_t length
)
1382 struct i915_hw_ppgtt
*ppgtt
=
1383 container_of(vm
, struct i915_hw_ppgtt
, base
);
1385 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1386 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1388 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1391 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1392 uint64_t start
, uint64_t length
,
1393 gen8_pte_t scratch_pte
,
1396 struct i915_page_directory
*pd
;
1400 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1401 struct i915_page_table
*pt
;
1402 uint64_t pd_len
= length
;
1403 uint64_t pd_start
= start
;
1406 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1409 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1410 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1412 gen8_pte_t
*pt_vaddr
;
1414 if (!test_bit(pde
, pd
->used_pdes
))
1417 pt_vaddr
= kmap_px(pt
);
1418 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1420 (pdpe
<< GEN8_PDPE_SHIFT
) |
1421 (pde
<< GEN8_PDE_SHIFT
) |
1422 (pte
<< GEN8_PTE_SHIFT
);
1426 for (i
= 0; i
< 4; i
++)
1427 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1432 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1433 for (i
= 0; i
< 4; i
++) {
1434 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1435 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1437 seq_puts(m
, " SCRATCH ");
1441 /* don't use kunmap_px, it could trigger
1442 * an unnecessary flush.
1444 kunmap_atomic(pt_vaddr
);
1449 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1451 struct i915_address_space
*vm
= &ppgtt
->base
;
1452 uint64_t start
= ppgtt
->base
.start
;
1453 uint64_t length
= ppgtt
->base
.total
;
1454 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1455 I915_CACHE_LLC
, true);
1457 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1458 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1460 uint64_t templ4
, pml4e
;
1461 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1462 struct i915_page_directory_pointer
*pdp
;
1464 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, templ4
, pml4e
) {
1465 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1468 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1469 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1474 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1476 unsigned long *new_page_dirs
, *new_page_tables
;
1477 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1480 /* We allocate temp bitmap for page tables for no gain
1481 * but as this is for init only, lets keep the things simple
1483 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1487 /* Allocate for all pdps regardless of how the ppgtt
1490 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1494 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1496 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1502 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1503 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1504 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1508 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1512 ret
= gen8_init_scratch(&ppgtt
->base
);
1516 ppgtt
->base
.start
= 0;
1517 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1518 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1519 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1520 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1521 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1522 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1523 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1525 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1526 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1530 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1532 ppgtt
->base
.total
= 1ULL << 48;
1533 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1535 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1539 ppgtt
->base
.total
= 1ULL << 32;
1540 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1541 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1545 if (intel_vgpu_active(ppgtt
->base
.dev
)) {
1546 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1552 if (intel_vgpu_active(ppgtt
->base
.dev
))
1553 gen8_ppgtt_notify_vgt(ppgtt
, true);
1558 gen8_free_scratch(&ppgtt
->base
);
1562 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1564 struct i915_address_space
*vm
= &ppgtt
->base
;
1565 struct i915_page_table
*unused
;
1566 gen6_pte_t scratch_pte
;
1568 uint32_t pte
, pde
, temp
;
1569 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1571 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1572 I915_CACHE_LLC
, true, 0);
1574 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1576 gen6_pte_t
*pt_vaddr
;
1577 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1578 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1579 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1581 if (pd_entry
!= expected
)
1582 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1586 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1588 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1590 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1592 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1596 for (i
= 0; i
< 4; i
++)
1597 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1602 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1603 for (i
= 0; i
< 4; i
++) {
1604 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1605 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1607 seq_puts(m
, " SCRATCH ");
1611 kunmap_px(ppgtt
, pt_vaddr
);
1615 /* Write pde (index) from the page directory @pd to the page table @pt */
1616 static void gen6_write_pde(struct i915_page_directory
*pd
,
1617 const int pde
, struct i915_page_table
*pt
)
1619 /* Caller needs to make sure the write completes if necessary */
1620 struct i915_hw_ppgtt
*ppgtt
=
1621 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1624 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1625 pd_entry
|= GEN6_PDE_VALID
;
1627 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1630 /* Write all the page tables found in the ppgtt structure to incrementing page
1632 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1633 struct i915_page_directory
*pd
,
1634 uint32_t start
, uint32_t length
)
1636 struct i915_page_table
*pt
;
1639 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1640 gen6_write_pde(pd
, pde
, pt
);
1642 /* Make sure write is complete before other code can use this page
1643 * table. Also require for WC mapped PTEs */
1644 readl(dev_priv
->gtt
.gsm
);
1647 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1649 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1651 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1654 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1655 struct drm_i915_gem_request
*req
)
1657 struct intel_engine_cs
*ring
= req
->ring
;
1660 /* NB: TLBs must be flushed and invalidated before a switch */
1661 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1665 ret
= intel_ring_begin(req
, 6);
1669 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1670 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1671 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1672 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1673 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1674 intel_ring_emit(ring
, MI_NOOP
);
1675 intel_ring_advance(ring
);
1680 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1681 struct drm_i915_gem_request
*req
)
1683 struct intel_engine_cs
*ring
= req
->ring
;
1684 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1686 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1687 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1691 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1692 struct drm_i915_gem_request
*req
)
1694 struct intel_engine_cs
*ring
= req
->ring
;
1697 /* NB: TLBs must be flushed and invalidated before a switch */
1698 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1702 ret
= intel_ring_begin(req
, 6);
1706 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1707 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1708 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1709 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1710 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1711 intel_ring_emit(ring
, MI_NOOP
);
1712 intel_ring_advance(ring
);
1714 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1715 if (ring
->id
!= RCS
) {
1716 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1724 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1725 struct drm_i915_gem_request
*req
)
1727 struct intel_engine_cs
*ring
= req
->ring
;
1728 struct drm_device
*dev
= ppgtt
->base
.dev
;
1729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1732 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1733 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1735 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1740 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1743 struct intel_engine_cs
*ring
;
1746 for_each_ring(ring
, dev_priv
, j
) {
1747 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1748 I915_WRITE(RING_MODE_GEN7(ring
),
1749 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1753 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1756 struct intel_engine_cs
*ring
;
1757 uint32_t ecochk
, ecobits
;
1760 ecobits
= I915_READ(GAC_ECO_BITS
);
1761 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1763 ecochk
= I915_READ(GAM_ECOCHK
);
1764 if (IS_HASWELL(dev
)) {
1765 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1767 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1768 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1770 I915_WRITE(GAM_ECOCHK
, ecochk
);
1772 for_each_ring(ring
, dev_priv
, i
) {
1773 /* GFX_MODE is per-ring on gen7+ */
1774 I915_WRITE(RING_MODE_GEN7(ring
),
1775 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1779 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1782 uint32_t ecochk
, gab_ctl
, ecobits
;
1784 ecobits
= I915_READ(GAC_ECO_BITS
);
1785 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1786 ECOBITS_PPGTT_CACHE64B
);
1788 gab_ctl
= I915_READ(GAB_CTL
);
1789 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1791 ecochk
= I915_READ(GAM_ECOCHK
);
1792 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1794 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1797 /* PPGTT support for Sandybdrige/Gen6 and later */
1798 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1803 struct i915_hw_ppgtt
*ppgtt
=
1804 container_of(vm
, struct i915_hw_ppgtt
, base
);
1805 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1806 unsigned first_entry
= start
>> PAGE_SHIFT
;
1807 unsigned num_entries
= length
>> PAGE_SHIFT
;
1808 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1809 unsigned first_pte
= first_entry
% GEN6_PTES
;
1810 unsigned last_pte
, i
;
1812 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1813 I915_CACHE_LLC
, true, 0);
1815 while (num_entries
) {
1816 last_pte
= first_pte
+ num_entries
;
1817 if (last_pte
> GEN6_PTES
)
1818 last_pte
= GEN6_PTES
;
1820 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1822 for (i
= first_pte
; i
< last_pte
; i
++)
1823 pt_vaddr
[i
] = scratch_pte
;
1825 kunmap_px(ppgtt
, pt_vaddr
);
1827 num_entries
-= last_pte
- first_pte
;
1833 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1834 struct sg_table
*pages
,
1836 enum i915_cache_level cache_level
, u32 flags
)
1838 struct i915_hw_ppgtt
*ppgtt
=
1839 container_of(vm
, struct i915_hw_ppgtt
, base
);
1840 gen6_pte_t
*pt_vaddr
;
1841 unsigned first_entry
= start
>> PAGE_SHIFT
;
1842 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1843 unsigned act_pte
= first_entry
% GEN6_PTES
;
1844 struct sg_page_iter sg_iter
;
1847 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1848 if (pt_vaddr
== NULL
)
1849 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1852 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1853 cache_level
, true, flags
);
1855 if (++act_pte
== GEN6_PTES
) {
1856 kunmap_px(ppgtt
, pt_vaddr
);
1863 kunmap_px(ppgtt
, pt_vaddr
);
1866 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1867 uint64_t start_in
, uint64_t length_in
)
1869 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1870 struct drm_device
*dev
= vm
->dev
;
1871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1872 struct i915_hw_ppgtt
*ppgtt
=
1873 container_of(vm
, struct i915_hw_ppgtt
, base
);
1874 struct i915_page_table
*pt
;
1875 uint32_t start
, length
, start_save
, length_save
;
1879 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1882 start
= start_save
= start_in
;
1883 length
= length_save
= length_in
;
1885 bitmap_zero(new_page_tables
, I915_PDES
);
1887 /* The allocation is done in two stages so that we can bail out with
1888 * minimal amount of pain. The first stage finds new page tables that
1889 * need allocation. The second stage marks use ptes within the page
1892 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1893 if (pt
!= vm
->scratch_pt
) {
1894 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1898 /* We've already allocated a page table */
1899 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1907 gen6_initialize_pt(vm
, pt
);
1909 ppgtt
->pd
.page_table
[pde
] = pt
;
1910 __set_bit(pde
, new_page_tables
);
1911 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1915 length
= length_save
;
1917 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1918 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1920 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1921 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1922 gen6_pte_count(start
, length
));
1924 if (__test_and_clear_bit(pde
, new_page_tables
))
1925 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1927 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1928 gen6_pte_index(start
),
1929 gen6_pte_count(start
, length
),
1931 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1935 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1937 /* Make sure write is complete before other code can use this page
1938 * table. Also require for WC mapped PTEs */
1939 readl(dev_priv
->gtt
.gsm
);
1941 mark_tlbs_dirty(ppgtt
);
1945 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1946 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1948 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1949 free_pt(vm
->dev
, pt
);
1952 mark_tlbs_dirty(ppgtt
);
1956 static int gen6_init_scratch(struct i915_address_space
*vm
)
1958 struct drm_device
*dev
= vm
->dev
;
1960 vm
->scratch_page
= alloc_scratch_page(dev
);
1961 if (IS_ERR(vm
->scratch_page
))
1962 return PTR_ERR(vm
->scratch_page
);
1964 vm
->scratch_pt
= alloc_pt(dev
);
1965 if (IS_ERR(vm
->scratch_pt
)) {
1966 free_scratch_page(dev
, vm
->scratch_page
);
1967 return PTR_ERR(vm
->scratch_pt
);
1970 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1975 static void gen6_free_scratch(struct i915_address_space
*vm
)
1977 struct drm_device
*dev
= vm
->dev
;
1979 free_pt(dev
, vm
->scratch_pt
);
1980 free_scratch_page(dev
, vm
->scratch_page
);
1983 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1985 struct i915_hw_ppgtt
*ppgtt
=
1986 container_of(vm
, struct i915_hw_ppgtt
, base
);
1987 struct i915_page_table
*pt
;
1990 drm_mm_remove_node(&ppgtt
->node
);
1992 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1993 if (pt
!= vm
->scratch_pt
)
1994 free_pt(ppgtt
->base
.dev
, pt
);
1997 gen6_free_scratch(vm
);
2000 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
2002 struct i915_address_space
*vm
= &ppgtt
->base
;
2003 struct drm_device
*dev
= ppgtt
->base
.dev
;
2004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2005 bool retried
= false;
2008 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2009 * allocator works in address space sizes, so it's multiplied by page
2010 * size. We allocate at the top of the GTT to avoid fragmentation.
2012 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
2014 ret
= gen6_init_scratch(vm
);
2019 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
2020 &ppgtt
->node
, GEN6_PD_SIZE
,
2022 0, dev_priv
->gtt
.base
.total
,
2024 if (ret
== -ENOSPC
&& !retried
) {
2025 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
2026 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2028 0, dev_priv
->gtt
.base
.total
,
2041 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
2042 DRM_DEBUG("Forced to use aperture for PDEs\n");
2047 gen6_free_scratch(vm
);
2051 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2053 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2056 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2057 uint64_t start
, uint64_t length
)
2059 struct i915_page_table
*unused
;
2062 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
2063 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2066 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2068 struct drm_device
*dev
= ppgtt
->base
.dev
;
2069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2072 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
2074 ppgtt
->switch_mm
= gen6_mm_switch
;
2075 } else if (IS_HASWELL(dev
)) {
2076 ppgtt
->switch_mm
= hsw_mm_switch
;
2077 } else if (IS_GEN7(dev
)) {
2078 ppgtt
->switch_mm
= gen7_mm_switch
;
2082 if (intel_vgpu_active(dev
))
2083 ppgtt
->switch_mm
= vgpu_mm_switch
;
2085 ret
= gen6_ppgtt_alloc(ppgtt
);
2089 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2090 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2091 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2092 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2093 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2094 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2095 ppgtt
->base
.start
= 0;
2096 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2097 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2099 ppgtt
->pd
.base
.ggtt_offset
=
2100 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2102 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
2103 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2105 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2107 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2109 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2110 ppgtt
->node
.size
>> 20,
2111 ppgtt
->node
.start
/ PAGE_SIZE
);
2113 DRM_DEBUG("Adding PPGTT at offset %x\n",
2114 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2119 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2121 ppgtt
->base
.dev
= dev
;
2123 if (INTEL_INFO(dev
)->gen
< 8)
2124 return gen6_ppgtt_init(ppgtt
);
2126 return gen8_ppgtt_init(ppgtt
);
2129 static void i915_address_space_init(struct i915_address_space
*vm
,
2130 struct drm_i915_private
*dev_priv
)
2132 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2133 vm
->dev
= dev_priv
->dev
;
2134 INIT_LIST_HEAD(&vm
->active_list
);
2135 INIT_LIST_HEAD(&vm
->inactive_list
);
2136 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2139 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2146 kref_init(&ppgtt
->ref
);
2147 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2153 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2155 /* In the case of execlists, PPGTT is enabled by the context descriptor
2156 * and the PDPs are contained within the context itself. We don't
2157 * need to do anything here. */
2158 if (i915
.enable_execlists
)
2161 if (!USES_PPGTT(dev
))
2165 gen6_ppgtt_enable(dev
);
2166 else if (IS_GEN7(dev
))
2167 gen7_ppgtt_enable(dev
);
2168 else if (INTEL_INFO(dev
)->gen
>= 8)
2169 gen8_ppgtt_enable(dev
);
2171 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2176 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
2178 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
2179 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2181 if (i915
.enable_execlists
)
2187 return ppgtt
->switch_mm(ppgtt
, req
);
2190 struct i915_hw_ppgtt
*
2191 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
2193 struct i915_hw_ppgtt
*ppgtt
;
2196 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2198 return ERR_PTR(-ENOMEM
);
2200 ret
= i915_ppgtt_init(dev
, ppgtt
);
2203 return ERR_PTR(ret
);
2206 ppgtt
->file_priv
= fpriv
;
2208 trace_i915_ppgtt_create(&ppgtt
->base
);
2213 void i915_ppgtt_release(struct kref
*kref
)
2215 struct i915_hw_ppgtt
*ppgtt
=
2216 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2218 trace_i915_ppgtt_release(&ppgtt
->base
);
2220 /* vmas should already be unbound */
2221 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2222 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2224 list_del(&ppgtt
->base
.global_link
);
2225 drm_mm_takedown(&ppgtt
->base
.mm
);
2227 ppgtt
->base
.cleanup(&ppgtt
->base
);
2231 extern int intel_iommu_gfx_mapped
;
2232 /* Certain Gen5 chipsets require require idling the GPU before
2233 * unmapping anything from the GTT when VT-d is enabled.
2235 static bool needs_idle_maps(struct drm_device
*dev
)
2237 #ifdef CONFIG_INTEL_IOMMU
2238 /* Query intel_iommu to see if we need the workaround. Presumably that
2241 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
2247 static bool do_idling(struct drm_i915_private
*dev_priv
)
2249 bool ret
= dev_priv
->mm
.interruptible
;
2251 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
2252 dev_priv
->mm
.interruptible
= false;
2253 if (i915_gpu_idle(dev_priv
->dev
)) {
2254 DRM_ERROR("Couldn't idle GPU\n");
2255 /* Wait a bit, in hopes it avoids the hang */
2263 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
2265 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2266 dev_priv
->mm
.interruptible
= interruptible
;
2269 void i915_check_and_clear_faults(struct drm_device
*dev
)
2271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2272 struct intel_engine_cs
*ring
;
2275 if (INTEL_INFO(dev
)->gen
< 6)
2278 for_each_ring(ring
, dev_priv
, i
) {
2280 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
2281 if (fault_reg
& RING_FAULT_VALID
) {
2282 DRM_DEBUG_DRIVER("Unexpected fault\n"
2284 "\tAddress space: %s\n"
2287 fault_reg
& PAGE_MASK
,
2288 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2289 RING_FAULT_SRCID(fault_reg
),
2290 RING_FAULT_FAULT_TYPE(fault_reg
));
2291 I915_WRITE(RING_FAULT_REG(ring
),
2292 fault_reg
& ~RING_FAULT_VALID
);
2295 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
2298 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2300 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
2301 intel_gtt_chipset_flush();
2303 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2304 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2308 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2312 /* Don't bother messing with faults pre GEN6 as we have little
2313 * documentation supporting that it's a good idea.
2315 if (INTEL_INFO(dev
)->gen
< 6)
2318 i915_check_and_clear_faults(dev
);
2320 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2321 dev_priv
->gtt
.base
.start
,
2322 dev_priv
->gtt
.base
.total
,
2325 i915_ggtt_flush(dev_priv
);
2328 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2330 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2331 obj
->pages
->sgl
, obj
->pages
->nents
,
2332 PCI_DMA_BIDIRECTIONAL
))
2338 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2343 iowrite32((u32
)pte
, addr
);
2344 iowrite32(pte
>> 32, addr
+ 4);
2348 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2349 struct sg_table
*st
,
2351 enum i915_cache_level level
, u32 unused
)
2353 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2354 unsigned first_entry
= start
>> PAGE_SHIFT
;
2355 gen8_pte_t __iomem
*gtt_entries
=
2356 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2358 struct sg_page_iter sg_iter
;
2359 dma_addr_t addr
= 0; /* shut up gcc */
2361 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2362 addr
= sg_dma_address(sg_iter
.sg
) +
2363 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
2364 gen8_set_pte(>t_entries
[i
],
2365 gen8_pte_encode(addr
, level
, true));
2370 * XXX: This serves as a posting read to make sure that the PTE has
2371 * actually been updated. There is some concern that even though
2372 * registers and PTEs are within the same BAR that they are potentially
2373 * of NUMA access patterns. Therefore, even with the way we assume
2374 * hardware should work, we must keep this posting read for paranoia.
2377 WARN_ON(readq(>t_entries
[i
-1])
2378 != gen8_pte_encode(addr
, level
, true));
2380 /* This next bit makes the above posting read even more important. We
2381 * want to flush the TLBs only after we're certain all the PTE updates
2384 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2385 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2389 * Binds an object into the global gtt with the specified cache level. The object
2390 * will be accessible to the GPU via commands whose operands reference offsets
2391 * within the global GTT as well as accessible by the GPU through the GMADR
2392 * mapped BAR (dev_priv->mm.gtt->gtt).
2394 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2395 struct sg_table
*st
,
2397 enum i915_cache_level level
, u32 flags
)
2399 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2400 unsigned first_entry
= start
>> PAGE_SHIFT
;
2401 gen6_pte_t __iomem
*gtt_entries
=
2402 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2404 struct sg_page_iter sg_iter
;
2405 dma_addr_t addr
= 0;
2407 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2408 addr
= sg_page_iter_dma_address(&sg_iter
);
2409 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
2413 /* XXX: This serves as a posting read to make sure that the PTE has
2414 * actually been updated. There is some concern that even though
2415 * registers and PTEs are within the same BAR that they are potentially
2416 * of NUMA access patterns. Therefore, even with the way we assume
2417 * hardware should work, we must keep this posting read for paranoia.
2420 unsigned long gtt
= readl(>t_entries
[i
-1]);
2421 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
2424 /* This next bit makes the above posting read even more important. We
2425 * want to flush the TLBs only after we're certain all the PTE updates
2428 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2429 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2432 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2437 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2438 unsigned first_entry
= start
>> PAGE_SHIFT
;
2439 unsigned num_entries
= length
>> PAGE_SHIFT
;
2440 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2441 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2442 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2445 if (WARN(num_entries
> max_entries
,
2446 "First entry = %d; Num entries = %d (max=%d)\n",
2447 first_entry
, num_entries
, max_entries
))
2448 num_entries
= max_entries
;
2450 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2453 for (i
= 0; i
< num_entries
; i
++)
2454 gen8_set_pte(>t_base
[i
], scratch_pte
);
2458 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2463 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2464 unsigned first_entry
= start
>> PAGE_SHIFT
;
2465 unsigned num_entries
= length
>> PAGE_SHIFT
;
2466 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2467 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2468 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2471 if (WARN(num_entries
> max_entries
,
2472 "First entry = %d; Num entries = %d (max=%d)\n",
2473 first_entry
, num_entries
, max_entries
))
2474 num_entries
= max_entries
;
2476 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2477 I915_CACHE_LLC
, use_scratch
, 0);
2479 for (i
= 0; i
< num_entries
; i
++)
2480 iowrite32(scratch_pte
, >t_base
[i
]);
2484 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2485 struct sg_table
*pages
,
2487 enum i915_cache_level cache_level
, u32 unused
)
2489 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2490 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2492 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2496 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2501 unsigned first_entry
= start
>> PAGE_SHIFT
;
2502 unsigned num_entries
= length
>> PAGE_SHIFT
;
2503 intel_gtt_clear_range(first_entry
, num_entries
);
2506 static int ggtt_bind_vma(struct i915_vma
*vma
,
2507 enum i915_cache_level cache_level
,
2510 struct drm_i915_gem_object
*obj
= vma
->obj
;
2514 ret
= i915_get_ggtt_vma_pages(vma
);
2518 /* Currently applicable only to VLV */
2520 pte_flags
|= PTE_READ_ONLY
;
2522 vma
->vm
->insert_entries(vma
->vm
, vma
->ggtt_view
.pages
,
2524 cache_level
, pte_flags
);
2527 * Without aliasing PPGTT there's no difference between
2528 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2529 * upgrade to both bound if we bind either to avoid double-binding.
2531 vma
->bound
|= GLOBAL_BIND
| LOCAL_BIND
;
2536 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2537 enum i915_cache_level cache_level
,
2540 struct drm_device
*dev
= vma
->vm
->dev
;
2541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2542 struct drm_i915_gem_object
*obj
= vma
->obj
;
2543 struct sg_table
*pages
= obj
->pages
;
2547 ret
= i915_get_ggtt_vma_pages(vma
);
2550 pages
= vma
->ggtt_view
.pages
;
2552 /* Currently applicable only to VLV */
2554 pte_flags
|= PTE_READ_ONLY
;
2557 if (flags
& GLOBAL_BIND
) {
2558 vma
->vm
->insert_entries(vma
->vm
, pages
,
2560 cache_level
, pte_flags
);
2563 if (flags
& LOCAL_BIND
) {
2564 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2565 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2567 cache_level
, pte_flags
);
2573 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2575 struct drm_device
*dev
= vma
->vm
->dev
;
2576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 struct drm_i915_gem_object
*obj
= vma
->obj
;
2578 const uint64_t size
= min_t(uint64_t,
2582 if (vma
->bound
& GLOBAL_BIND
) {
2583 vma
->vm
->clear_range(vma
->vm
,
2589 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2590 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2592 appgtt
->base
.clear_range(&appgtt
->base
,
2599 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2601 struct drm_device
*dev
= obj
->base
.dev
;
2602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2605 interruptible
= do_idling(dev_priv
);
2607 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2608 PCI_DMA_BIDIRECTIONAL
);
2610 undo_idling(dev_priv
, interruptible
);
2613 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2614 unsigned long color
,
2618 if (node
->color
!= color
)
2621 if (!list_empty(&node
->node_list
)) {
2622 node
= list_entry(node
->node_list
.next
,
2625 if (node
->allocated
&& node
->color
!= color
)
2630 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2635 /* Let GEM Manage all of the aperture.
2637 * However, leave one page at the end still bound to the scratch page.
2638 * There are a number of places where the hardware apparently prefetches
2639 * past the end of the object, and we've seen multiple hangs with the
2640 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2641 * aperture. One page should be enough to keep any prefetching inside
2644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2645 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2646 struct drm_mm_node
*entry
;
2647 struct drm_i915_gem_object
*obj
;
2648 unsigned long hole_start
, hole_end
;
2651 BUG_ON(mappable_end
> end
);
2653 ggtt_vm
->start
= start
;
2655 /* Subtract the guard page before address space initialization to
2656 * shrink the range used by drm_mm */
2657 ggtt_vm
->total
= end
- start
- PAGE_SIZE
;
2658 i915_address_space_init(ggtt_vm
, dev_priv
);
2659 ggtt_vm
->total
+= PAGE_SIZE
;
2661 if (intel_vgpu_active(dev
)) {
2662 ret
= intel_vgt_balloon(dev
);
2668 ggtt_vm
->mm
.color_adjust
= i915_gtt_color_adjust
;
2670 /* Mark any preallocated objects as occupied */
2671 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2672 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2674 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2675 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2677 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2678 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2680 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2683 vma
->bound
|= GLOBAL_BIND
;
2684 list_add_tail(&vma
->mm_list
, &ggtt_vm
->inactive_list
);
2687 /* Clear any non-preallocated blocks */
2688 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2689 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2690 hole_start
, hole_end
);
2691 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2692 hole_end
- hole_start
, true);
2695 /* And finally clear the reserved guard page */
2696 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2698 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2699 struct i915_hw_ppgtt
*ppgtt
;
2701 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2705 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2707 ppgtt
->base
.cleanup(&ppgtt
->base
);
2712 if (ppgtt
->base
.allocate_va_range
)
2713 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2716 ppgtt
->base
.cleanup(&ppgtt
->base
);
2721 ppgtt
->base
.clear_range(&ppgtt
->base
,
2726 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2727 WARN_ON(dev_priv
->gtt
.base
.bind_vma
!= ggtt_bind_vma
);
2728 dev_priv
->gtt
.base
.bind_vma
= aliasing_gtt_bind_vma
;
2734 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2737 u64 gtt_size
, mappable_size
;
2739 gtt_size
= dev_priv
->gtt
.base
.total
;
2740 mappable_size
= dev_priv
->gtt
.mappable_end
;
2742 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2745 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2750 if (dev_priv
->mm
.aliasing_ppgtt
) {
2751 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2753 ppgtt
->base
.cleanup(&ppgtt
->base
);
2756 if (drm_mm_initialized(&vm
->mm
)) {
2757 if (intel_vgpu_active(dev
))
2758 intel_vgt_deballoon();
2760 drm_mm_takedown(&vm
->mm
);
2761 list_del(&vm
->global_link
);
2767 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2769 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2770 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2771 return snb_gmch_ctl
<< 20;
2774 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2776 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2777 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2779 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2781 #ifdef CONFIG_X86_32
2782 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2783 if (bdw_gmch_ctl
> 4)
2787 return bdw_gmch_ctl
<< 20;
2790 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2792 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2793 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2796 return 1 << (20 + gmch_ctrl
);
2801 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2803 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2804 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2805 return snb_gmch_ctl
<< 25; /* 32 MB units */
2808 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2810 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2811 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2812 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2815 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2817 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2818 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2821 * 0x0 to 0x10: 32MB increments starting at 0MB
2822 * 0x11 to 0x16: 4MB increments starting at 8MB
2823 * 0x17 to 0x1d: 4MB increments start at 36MB
2825 if (gmch_ctrl
< 0x11)
2826 return gmch_ctrl
<< 25;
2827 else if (gmch_ctrl
< 0x17)
2828 return (gmch_ctrl
- 0x11 + 2) << 22;
2830 return (gmch_ctrl
- 0x17 + 9) << 22;
2833 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2835 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2836 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2838 if (gen9_gmch_ctl
< 0xf0)
2839 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2841 /* 4MB increments starting at 0xf0 for 4MB */
2842 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2845 static int ggtt_probe_common(struct drm_device
*dev
,
2848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2849 struct i915_page_scratch
*scratch_page
;
2850 phys_addr_t gtt_phys_addr
;
2852 /* For Modern GENs the PTEs and register space are split in the BAR */
2853 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2854 (pci_resource_len(dev
->pdev
, 0) / 2);
2857 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2858 * dropped. For WC mappings in general we have 64 byte burst writes
2859 * when the WC buffer is flushed, so we can't use it, but have to
2860 * resort to an uncached mapping. The WC issue is easily caught by the
2861 * readback check when writing GTT PTE entries.
2863 if (IS_BROXTON(dev
))
2864 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2866 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2867 if (!dev_priv
->gtt
.gsm
) {
2868 DRM_ERROR("Failed to map the gtt page table\n");
2872 scratch_page
= alloc_scratch_page(dev
);
2873 if (IS_ERR(scratch_page
)) {
2874 DRM_ERROR("Scratch setup failed\n");
2875 /* iounmap will also get called at remove, but meh */
2876 iounmap(dev_priv
->gtt
.gsm
);
2877 return PTR_ERR(scratch_page
);
2880 dev_priv
->gtt
.base
.scratch_page
= scratch_page
;
2885 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2886 * bits. When using advanced contexts each context stores its own PAT, but
2887 * writing this data shouldn't be harmful even in those cases. */
2888 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2892 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2893 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2894 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2895 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2896 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2897 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2898 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2899 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2901 if (!USES_PPGTT(dev_priv
->dev
))
2902 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2903 * so RTL will always use the value corresponding to
2905 * So let's disable cache for GGTT to avoid screen corruptions.
2906 * MOCS still can be used though.
2907 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2908 * before this patch, i.e. the same uncached + snooping access
2909 * like on gen6/7 seems to be in effect.
2910 * - So this just fixes blitter/render access. Again it looks
2911 * like it's not just uncached access, but uncached + snooping.
2912 * So we can still hold onto all our assumptions wrt cpu
2913 * clflushing on LLC machines.
2915 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2917 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2918 * write would work. */
2919 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2920 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2923 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2928 * Map WB on BDW to snooped on CHV.
2930 * Only the snoop bit has meaning for CHV, the rest is
2933 * The hardware will never snoop for certain types of accesses:
2934 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2935 * - PPGTT page tables
2936 * - some other special cycles
2938 * As with BDW, we also need to consider the following for GT accesses:
2939 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2940 * so RTL will always use the value corresponding to
2942 * Which means we must set the snoop bit in PAT entry 0
2943 * in order to keep the global status page working.
2945 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2949 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2950 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2951 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2952 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2954 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2955 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2958 static int gen8_gmch_probe(struct drm_device
*dev
,
2961 phys_addr_t
*mappable_base
,
2964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2969 /* TODO: We're not aware of mappable constraints on gen8 yet */
2970 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2971 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2973 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2974 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2976 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2978 if (INTEL_INFO(dev
)->gen
>= 9) {
2979 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2980 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2981 } else if (IS_CHERRYVIEW(dev
)) {
2982 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2983 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2985 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2986 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2989 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2991 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2992 chv_setup_private_ppat(dev_priv
);
2994 bdw_setup_private_ppat(dev_priv
);
2996 ret
= ggtt_probe_common(dev
, gtt_size
);
2998 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2999 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
3000 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
3001 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
3006 static int gen6_gmch_probe(struct drm_device
*dev
,
3009 phys_addr_t
*mappable_base
,
3012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3013 unsigned int gtt_size
;
3017 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
3018 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
3020 /* 64/512MB is the current min/max we actually know of, but this is just
3021 * a coarse sanity check.
3023 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
3024 DRM_ERROR("Unknown GMADR size (%llx)\n",
3025 dev_priv
->gtt
.mappable_end
);
3029 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
3030 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
3031 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3033 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
3035 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3036 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3038 ret
= ggtt_probe_common(dev
, gtt_size
);
3040 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
3041 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
3042 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
3043 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
3048 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3051 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
3054 free_scratch_page(vm
->dev
, vm
->scratch_page
);
3057 static int i915_gmch_probe(struct drm_device
*dev
,
3060 phys_addr_t
*mappable_base
,
3063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3066 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
3068 DRM_ERROR("failed to set up gmch\n");
3072 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
3074 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
3075 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
3076 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
3077 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
3078 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
3080 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
3081 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3086 static void i915_gmch_remove(struct i915_address_space
*vm
)
3088 intel_gmch_remove();
3091 int i915_gem_gtt_init(struct drm_device
*dev
)
3093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3094 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3097 if (INTEL_INFO(dev
)->gen
<= 5) {
3098 gtt
->gtt_probe
= i915_gmch_probe
;
3099 gtt
->base
.cleanup
= i915_gmch_remove
;
3100 } else if (INTEL_INFO(dev
)->gen
< 8) {
3101 gtt
->gtt_probe
= gen6_gmch_probe
;
3102 gtt
->base
.cleanup
= gen6_gmch_remove
;
3103 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
3104 gtt
->base
.pte_encode
= iris_pte_encode
;
3105 else if (IS_HASWELL(dev
))
3106 gtt
->base
.pte_encode
= hsw_pte_encode
;
3107 else if (IS_VALLEYVIEW(dev
))
3108 gtt
->base
.pte_encode
= byt_pte_encode
;
3109 else if (INTEL_INFO(dev
)->gen
>= 7)
3110 gtt
->base
.pte_encode
= ivb_pte_encode
;
3112 gtt
->base
.pte_encode
= snb_pte_encode
;
3114 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
3115 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
3118 gtt
->base
.dev
= dev
;
3120 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
3121 >t
->mappable_base
, >t
->mappable_end
);
3125 /* GMADR is the PCI mmio aperture into the global GTT. */
3126 DRM_INFO("Memory usable by graphics device = %lluM\n",
3127 gtt
->base
.total
>> 20);
3128 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
3129 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
3130 #ifdef CONFIG_INTEL_IOMMU
3131 if (intel_iommu_gfx_mapped
)
3132 DRM_INFO("VT-d active for gfx access\n");
3135 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3136 * user's requested state against the hardware/driver capabilities. We
3137 * do this now so that we can print out any log messages once rather
3138 * than every time we check intel_enable_ppgtt().
3140 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
3141 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
3146 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3149 struct drm_i915_gem_object
*obj
;
3150 struct i915_address_space
*vm
;
3151 struct i915_vma
*vma
;
3154 i915_check_and_clear_faults(dev
);
3156 /* First fill our portion of the GTT with scratch pages */
3157 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
3158 dev_priv
->gtt
.base
.start
,
3159 dev_priv
->gtt
.base
.total
,
3162 /* Cache flush objects bound into GGTT and rebind them. */
3163 vm
= &dev_priv
->gtt
.base
;
3164 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3166 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3170 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3177 i915_gem_clflush_object(obj
, obj
->pin_display
);
3180 if (INTEL_INFO(dev
)->gen
>= 8) {
3181 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3182 chv_setup_private_ppat(dev_priv
);
3184 bdw_setup_private_ppat(dev_priv
);
3189 if (USES_PPGTT(dev
)) {
3190 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3191 /* TODO: Perhaps it shouldn't be gen6 specific */
3193 struct i915_hw_ppgtt
*ppgtt
=
3194 container_of(vm
, struct i915_hw_ppgtt
,
3197 if (i915_is_ggtt(vm
))
3198 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3200 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3201 0, ppgtt
->base
.total
);
3205 i915_ggtt_flush(dev_priv
);
3208 static struct i915_vma
*
3209 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
3210 struct i915_address_space
*vm
,
3211 const struct i915_ggtt_view
*ggtt_view
)
3213 struct i915_vma
*vma
;
3215 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3216 return ERR_PTR(-EINVAL
);
3218 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3220 return ERR_PTR(-ENOMEM
);
3222 INIT_LIST_HEAD(&vma
->vma_link
);
3223 INIT_LIST_HEAD(&vma
->mm_list
);
3224 INIT_LIST_HEAD(&vma
->exec_list
);
3228 if (i915_is_ggtt(vm
))
3229 vma
->ggtt_view
= *ggtt_view
;
3231 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
3232 if (!i915_is_ggtt(vm
))
3233 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3239 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3240 struct i915_address_space
*vm
)
3242 struct i915_vma
*vma
;
3244 vma
= i915_gem_obj_to_vma(obj
, vm
);
3246 vma
= __i915_gem_vma_create(obj
, vm
,
3247 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3253 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3254 const struct i915_ggtt_view
*view
)
3256 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
3257 struct i915_vma
*vma
;
3260 return ERR_PTR(-EINVAL
);
3262 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3268 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
3274 static struct scatterlist
*
3275 rotate_pages(dma_addr_t
*in
, unsigned int offset
,
3276 unsigned int width
, unsigned int height
,
3277 struct sg_table
*st
, struct scatterlist
*sg
)
3279 unsigned int column
, row
;
3280 unsigned int src_idx
;
3287 for (column
= 0; column
< width
; column
++) {
3288 src_idx
= width
* (height
- 1) + column
;
3289 for (row
= 0; row
< height
; row
++) {
3291 /* We don't need the pages, but need to initialize
3292 * the entries so the sg list can be happily traversed.
3293 * The only thing we need are DMA addresses.
3295 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3296 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3297 sg_dma_len(sg
) = PAGE_SIZE
;
3306 static struct sg_table
*
3307 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
3308 struct drm_i915_gem_object
*obj
)
3310 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
3311 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
3312 unsigned int size_pages_uv
;
3313 struct sg_page_iter sg_iter
;
3315 dma_addr_t
*page_addr_list
;
3316 struct sg_table
*st
;
3317 unsigned int uv_start_page
;
3318 struct scatterlist
*sg
;
3321 /* Allocate a temporary list of source pages for random access. */
3322 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
3323 sizeof(dma_addr_t
));
3324 if (!page_addr_list
)
3325 return ERR_PTR(ret
);
3327 /* Account for UV plane with NV12. */
3328 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
)
3329 size_pages_uv
= rot_info
->size_uv
>> PAGE_SHIFT
;
3333 /* Allocate target SG list. */
3334 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3338 ret
= sg_alloc_table(st
, size_pages
+ size_pages_uv
, GFP_KERNEL
);
3342 /* Populate source page list from the object. */
3344 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
3345 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
3349 /* Rotate the pages. */
3350 sg
= rotate_pages(page_addr_list
, 0,
3351 rot_info
->width_pages
, rot_info
->height_pages
,
3354 /* Append the UV plane if NV12. */
3355 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
) {
3356 uv_start_page
= size_pages
;
3358 /* Check for tile-row un-alignment. */
3359 if (offset_in_page(rot_info
->uv_offset
))
3362 rot_info
->uv_start_page
= uv_start_page
;
3364 rotate_pages(page_addr_list
, uv_start_page
,
3365 rot_info
->width_pages_uv
,
3366 rot_info
->height_pages_uv
,
3371 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3372 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
3373 rot_info
->pixel_format
, rot_info
->width_pages
,
3374 rot_info
->height_pages
, size_pages
+ size_pages_uv
,
3377 drm_free_large(page_addr_list
);
3384 drm_free_large(page_addr_list
);
3387 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3388 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
3389 rot_info
->pixel_format
, rot_info
->width_pages
,
3390 rot_info
->height_pages
, size_pages
+ size_pages_uv
,
3392 return ERR_PTR(ret
);
3395 static struct sg_table
*
3396 intel_partial_pages(const struct i915_ggtt_view
*view
,
3397 struct drm_i915_gem_object
*obj
)
3399 struct sg_table
*st
;
3400 struct scatterlist
*sg
;
3401 struct sg_page_iter obj_sg_iter
;
3404 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3408 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3414 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3415 view
->params
.partial
.offset
)
3417 if (st
->nents
>= view
->params
.partial
.size
)
3420 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3421 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3422 sg_dma_len(sg
) = PAGE_SIZE
;
3433 return ERR_PTR(ret
);
3437 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3441 if (vma
->ggtt_view
.pages
)
3444 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3445 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3446 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3447 vma
->ggtt_view
.pages
=
3448 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
3449 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3450 vma
->ggtt_view
.pages
=
3451 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3453 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3454 vma
->ggtt_view
.type
);
3456 if (!vma
->ggtt_view
.pages
) {
3457 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3458 vma
->ggtt_view
.type
);
3460 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3461 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3462 vma
->ggtt_view
.pages
= NULL
;
3463 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3464 vma
->ggtt_view
.type
, ret
);
3471 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3473 * @cache_level: mapping cache level
3474 * @flags: flags like global or local mapping
3476 * DMA addresses are taken from the scatter-gather table of this object (or of
3477 * this VMA in case of non-default GGTT views) and PTE entries set up.
3478 * Note that DMA addresses are also the only part of the SG table we care about.
3480 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3486 if (WARN_ON(flags
== 0))
3490 if (flags
& PIN_GLOBAL
)
3491 bind_flags
|= GLOBAL_BIND
;
3492 if (flags
& PIN_USER
)
3493 bind_flags
|= LOCAL_BIND
;
3495 if (flags
& PIN_UPDATE
)
3496 bind_flags
|= vma
->bound
;
3498 bind_flags
&= ~vma
->bound
;
3500 if (bind_flags
== 0)
3503 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3504 trace_i915_va_alloc(vma
->vm
,
3507 VM_TO_TRACE_NAME(vma
->vm
));
3509 /* XXX: i915_vma_pin() will fix this +- hack */
3511 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3519 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3523 vma
->bound
|= bind_flags
;
3529 * i915_ggtt_view_size - Get the size of a GGTT view.
3530 * @obj: Object the view is of.
3531 * @view: The view in question.
3533 * @return The size of the GGTT view in bytes.
3536 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3537 const struct i915_ggtt_view
*view
)
3539 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3540 return obj
->base
.size
;
3541 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3542 return view
->rotation_info
.size
;
3543 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3544 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3546 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3547 return obj
->base
.size
;