2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_trace.h"
31 #include "intel_drv.h"
33 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
);
34 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
);
36 bool intel_enable_ppgtt(struct drm_device
*dev
, bool full
)
38 if (i915
.enable_ppgtt
== 0)
41 if (i915
.enable_ppgtt
== 1 && full
)
47 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
49 if (enable_ppgtt
== 0 || !HAS_ALIASING_PPGTT(dev
))
52 if (enable_ppgtt
== 1)
55 if (enable_ppgtt
== 2 && HAS_PPGTT(dev
))
58 #ifdef CONFIG_INTEL_IOMMU
59 /* Disable ppgtt on SNB if VT-d is on. */
60 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
61 DRM_INFO("Disabling PPGTT because VT-d is on\n");
66 /* Early VLV doesn't have this */
67 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
68 dev
->pdev
->revision
< 0xb) {
69 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
73 return HAS_ALIASING_PPGTT(dev
) ? 1 : 0;
77 static void ppgtt_bind_vma(struct i915_vma
*vma
,
78 enum i915_cache_level cache_level
,
80 static void ppgtt_unbind_vma(struct i915_vma
*vma
);
81 static int gen8_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
);
83 static inline gen8_gtt_pte_t
gen8_pte_encode(dma_addr_t addr
,
84 enum i915_cache_level level
,
87 gen8_gtt_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
92 pte
|= PPAT_UNCACHED_INDEX
;
95 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
98 pte
|= PPAT_CACHED_INDEX
;
105 static inline gen8_ppgtt_pde_t
gen8_pde_encode(struct drm_device
*dev
,
107 enum i915_cache_level level
)
109 gen8_ppgtt_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
111 if (level
!= I915_CACHE_NONE
)
112 pde
|= PPAT_CACHED_PDE_INDEX
;
114 pde
|= PPAT_UNCACHED_INDEX
;
118 static gen6_gtt_pte_t
snb_pte_encode(dma_addr_t addr
,
119 enum i915_cache_level level
,
120 bool valid
, u32 unused
)
122 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
123 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
126 case I915_CACHE_L3_LLC
:
128 pte
|= GEN6_PTE_CACHE_LLC
;
130 case I915_CACHE_NONE
:
131 pte
|= GEN6_PTE_UNCACHED
;
140 static gen6_gtt_pte_t
ivb_pte_encode(dma_addr_t addr
,
141 enum i915_cache_level level
,
142 bool valid
, u32 unused
)
144 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
145 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
148 case I915_CACHE_L3_LLC
:
149 pte
|= GEN7_PTE_CACHE_L3_LLC
;
152 pte
|= GEN6_PTE_CACHE_LLC
;
154 case I915_CACHE_NONE
:
155 pte
|= GEN6_PTE_UNCACHED
;
164 static gen6_gtt_pte_t
byt_pte_encode(dma_addr_t addr
,
165 enum i915_cache_level level
,
166 bool valid
, u32 flags
)
168 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
169 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
171 /* Mark the page as writeable. Other platforms don't have a
172 * setting for read-only/writable, so this matches that behavior.
174 if (!(flags
& PTE_READ_ONLY
))
175 pte
|= BYT_PTE_WRITEABLE
;
177 if (level
!= I915_CACHE_NONE
)
178 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
183 static gen6_gtt_pte_t
hsw_pte_encode(dma_addr_t addr
,
184 enum i915_cache_level level
,
185 bool valid
, u32 unused
)
187 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
188 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
190 if (level
!= I915_CACHE_NONE
)
191 pte
|= HSW_WB_LLC_AGE3
;
196 static gen6_gtt_pte_t
iris_pte_encode(dma_addr_t addr
,
197 enum i915_cache_level level
,
198 bool valid
, u32 unused
)
200 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
201 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
204 case I915_CACHE_NONE
:
207 pte
|= HSW_WT_ELLC_LLC_AGE3
;
210 pte
|= HSW_WB_ELLC_LLC_AGE3
;
217 /* Broadwell Page Directory Pointer Descriptors */
218 static int gen8_write_pdp(struct intel_engine_cs
*ring
, unsigned entry
,
219 uint64_t val
, bool synchronous
)
221 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
227 I915_WRITE(GEN8_RING_PDP_UDW(ring
, entry
), val
>> 32);
228 I915_WRITE(GEN8_RING_PDP_LDW(ring
, entry
), (u32
)val
);
232 ret
= intel_ring_begin(ring
, 6);
236 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
237 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
238 intel_ring_emit(ring
, (u32
)(val
>> 32));
239 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
240 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
241 intel_ring_emit(ring
, (u32
)(val
));
242 intel_ring_advance(ring
);
247 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
248 struct intel_engine_cs
*ring
,
253 /* bit of a hack to find the actual last used pd */
254 int used_pd
= ppgtt
->num_pd_entries
/ GEN8_PDES_PER_PAGE
;
256 for (i
= used_pd
- 1; i
>= 0; i
--) {
257 dma_addr_t addr
= ppgtt
->pd_dma_addr
[i
];
258 ret
= gen8_write_pdp(ring
, i
, addr
, synchronous
);
266 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
271 struct i915_hw_ppgtt
*ppgtt
=
272 container_of(vm
, struct i915_hw_ppgtt
, base
);
273 gen8_gtt_pte_t
*pt_vaddr
, scratch_pte
;
274 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
275 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
276 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
277 unsigned num_entries
= length
>> PAGE_SHIFT
;
278 unsigned last_pte
, i
;
280 scratch_pte
= gen8_pte_encode(ppgtt
->base
.scratch
.addr
,
281 I915_CACHE_LLC
, use_scratch
);
283 while (num_entries
) {
284 struct page
*page_table
= ppgtt
->gen8_pt_pages
[pdpe
][pde
];
286 last_pte
= pte
+ num_entries
;
287 if (last_pte
> GEN8_PTES_PER_PAGE
)
288 last_pte
= GEN8_PTES_PER_PAGE
;
290 pt_vaddr
= kmap_atomic(page_table
);
292 for (i
= pte
; i
< last_pte
; i
++) {
293 pt_vaddr
[i
] = scratch_pte
;
297 if (!HAS_LLC(ppgtt
->base
.dev
))
298 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
299 kunmap_atomic(pt_vaddr
);
302 if (++pde
== GEN8_PDES_PER_PAGE
) {
309 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
310 struct sg_table
*pages
,
312 enum i915_cache_level cache_level
, u32 unused
)
314 struct i915_hw_ppgtt
*ppgtt
=
315 container_of(vm
, struct i915_hw_ppgtt
, base
);
316 gen8_gtt_pte_t
*pt_vaddr
;
317 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
318 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
319 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
320 struct sg_page_iter sg_iter
;
324 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
325 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPS
))
328 if (pt_vaddr
== NULL
)
329 pt_vaddr
= kmap_atomic(ppgtt
->gen8_pt_pages
[pdpe
][pde
]);
332 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
334 if (++pte
== GEN8_PTES_PER_PAGE
) {
335 if (!HAS_LLC(ppgtt
->base
.dev
))
336 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
337 kunmap_atomic(pt_vaddr
);
339 if (++pde
== GEN8_PDES_PER_PAGE
) {
347 if (!HAS_LLC(ppgtt
->base
.dev
))
348 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
349 kunmap_atomic(pt_vaddr
);
353 static void gen8_free_page_tables(struct page
**pt_pages
)
357 if (pt_pages
== NULL
)
360 for (i
= 0; i
< GEN8_PDES_PER_PAGE
; i
++)
362 __free_pages(pt_pages
[i
], 0);
365 static void gen8_ppgtt_free(const struct i915_hw_ppgtt
*ppgtt
)
369 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
370 gen8_free_page_tables(ppgtt
->gen8_pt_pages
[i
]);
371 kfree(ppgtt
->gen8_pt_pages
[i
]);
372 kfree(ppgtt
->gen8_pt_dma_addr
[i
]);
375 __free_pages(ppgtt
->pd_pages
, get_order(ppgtt
->num_pd_pages
<< PAGE_SHIFT
));
378 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt
*ppgtt
)
380 struct pci_dev
*hwdev
= ppgtt
->base
.dev
->pdev
;
383 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
384 /* TODO: In the future we'll support sparse mappings, so this
385 * will have to change. */
386 if (!ppgtt
->pd_dma_addr
[i
])
389 pci_unmap_page(hwdev
, ppgtt
->pd_dma_addr
[i
], PAGE_SIZE
,
390 PCI_DMA_BIDIRECTIONAL
);
392 for (j
= 0; j
< GEN8_PDES_PER_PAGE
; j
++) {
393 dma_addr_t addr
= ppgtt
->gen8_pt_dma_addr
[i
][j
];
395 pci_unmap_page(hwdev
, addr
, PAGE_SIZE
,
396 PCI_DMA_BIDIRECTIONAL
);
401 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
403 struct i915_hw_ppgtt
*ppgtt
=
404 container_of(vm
, struct i915_hw_ppgtt
, base
);
406 list_del(&vm
->global_link
);
407 drm_mm_takedown(&vm
->mm
);
409 gen8_ppgtt_unmap_pages(ppgtt
);
410 gen8_ppgtt_free(ppgtt
);
413 static struct page
**__gen8_alloc_page_tables(void)
415 struct page
**pt_pages
;
418 pt_pages
= kcalloc(GEN8_PDES_PER_PAGE
, sizeof(struct page
*), GFP_KERNEL
);
420 return ERR_PTR(-ENOMEM
);
422 for (i
= 0; i
< GEN8_PDES_PER_PAGE
; i
++) {
423 pt_pages
[i
] = alloc_page(GFP_KERNEL
);
431 gen8_free_page_tables(pt_pages
);
433 return ERR_PTR(-ENOMEM
);
436 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt
*ppgtt
,
439 struct page
**pt_pages
[GEN8_LEGACY_PDPS
];
442 for (i
= 0; i
< max_pdp
; i
++) {
443 pt_pages
[i
] = __gen8_alloc_page_tables();
444 if (IS_ERR(pt_pages
[i
])) {
445 ret
= PTR_ERR(pt_pages
[i
]);
450 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
451 * "atomic" - for cleanup purposes.
453 for (i
= 0; i
< max_pdp
; i
++)
454 ppgtt
->gen8_pt_pages
[i
] = pt_pages
[i
];
460 gen8_free_page_tables(pt_pages
[i
]);
467 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt
*ppgtt
)
471 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
472 ppgtt
->gen8_pt_dma_addr
[i
] = kcalloc(GEN8_PDES_PER_PAGE
,
475 if (!ppgtt
->gen8_pt_dma_addr
[i
])
482 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
,
485 ppgtt
->pd_pages
= alloc_pages(GFP_KERNEL
, get_order(max_pdp
<< PAGE_SHIFT
));
486 if (!ppgtt
->pd_pages
)
489 ppgtt
->num_pd_pages
= 1 << get_order(max_pdp
<< PAGE_SHIFT
);
490 BUG_ON(ppgtt
->num_pd_pages
> GEN8_LEGACY_PDPS
);
495 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
,
500 ret
= gen8_ppgtt_allocate_page_directories(ppgtt
, max_pdp
);
504 ret
= gen8_ppgtt_allocate_page_tables(ppgtt
, max_pdp
);
506 __free_pages(ppgtt
->pd_pages
, get_order(max_pdp
<< PAGE_SHIFT
));
510 ppgtt
->num_pd_entries
= max_pdp
* GEN8_PDES_PER_PAGE
;
512 ret
= gen8_ppgtt_allocate_dma(ppgtt
);
514 gen8_ppgtt_free(ppgtt
);
519 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt
*ppgtt
,
525 pd_addr
= pci_map_page(ppgtt
->base
.dev
->pdev
,
526 &ppgtt
->pd_pages
[pd
], 0,
527 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
529 ret
= pci_dma_mapping_error(ppgtt
->base
.dev
->pdev
, pd_addr
);
533 ppgtt
->pd_dma_addr
[pd
] = pd_addr
;
538 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt
*ppgtt
,
546 p
= ppgtt
->gen8_pt_pages
[pd
][pt
];
547 pt_addr
= pci_map_page(ppgtt
->base
.dev
->pdev
,
548 p
, 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
549 ret
= pci_dma_mapping_error(ppgtt
->base
.dev
->pdev
, pt_addr
);
553 ppgtt
->gen8_pt_dma_addr
[pd
][pt
] = pt_addr
;
559 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
560 * with a net effect resembling a 2-level page table in normal x86 terms. Each
561 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
564 * FIXME: split allocation into smaller pieces. For now we only ever do this
565 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
566 * TODO: Do something with the size parameter
568 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
, uint64_t size
)
570 const int max_pdp
= DIV_ROUND_UP(size
, 1 << 30);
571 const int min_pt_pages
= GEN8_PDES_PER_PAGE
* max_pdp
;
575 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size
);
577 /* 1. Do all our allocations for page directories and page tables. */
578 ret
= gen8_ppgtt_alloc(ppgtt
, max_pdp
);
583 * 2. Create DMA mappings for the page directories and page tables.
585 for (i
= 0; i
< max_pdp
; i
++) {
586 ret
= gen8_ppgtt_setup_page_directories(ppgtt
, i
);
590 for (j
= 0; j
< GEN8_PDES_PER_PAGE
; j
++) {
591 ret
= gen8_ppgtt_setup_page_tables(ppgtt
, i
, j
);
598 * 3. Map all the page directory entires to point to the page tables
601 * For now, the PPGTT helper functions all require that the PDEs are
602 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
603 * will never need to touch the PDEs again.
605 for (i
= 0; i
< max_pdp
; i
++) {
606 gen8_ppgtt_pde_t
*pd_vaddr
;
607 pd_vaddr
= kmap_atomic(&ppgtt
->pd_pages
[i
]);
608 for (j
= 0; j
< GEN8_PDES_PER_PAGE
; j
++) {
609 dma_addr_t addr
= ppgtt
->gen8_pt_dma_addr
[i
][j
];
610 pd_vaddr
[j
] = gen8_pde_encode(ppgtt
->base
.dev
, addr
,
613 if (!HAS_LLC(ppgtt
->base
.dev
))
614 drm_clflush_virt_range(pd_vaddr
, PAGE_SIZE
);
615 kunmap_atomic(pd_vaddr
);
618 ppgtt
->enable
= gen8_ppgtt_enable
;
619 ppgtt
->switch_mm
= gen8_mm_switch
;
620 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
621 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
622 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
623 ppgtt
->base
.start
= 0;
624 ppgtt
->base
.total
= ppgtt
->num_pd_entries
* GEN8_PTES_PER_PAGE
* PAGE_SIZE
;
626 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
628 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
629 ppgtt
->num_pd_pages
, ppgtt
->num_pd_pages
- max_pdp
);
630 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
631 ppgtt
->num_pd_entries
,
632 (ppgtt
->num_pd_entries
- min_pt_pages
) + size
% (1<<30));
636 gen8_ppgtt_unmap_pages(ppgtt
);
637 gen8_ppgtt_free(ppgtt
);
641 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
643 struct drm_i915_private
*dev_priv
= ppgtt
->base
.dev
->dev_private
;
644 struct i915_address_space
*vm
= &ppgtt
->base
;
645 gen6_gtt_pte_t __iomem
*pd_addr
;
646 gen6_gtt_pte_t scratch_pte
;
650 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
652 pd_addr
= (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
653 ppgtt
->pd_offset
/ sizeof(gen6_gtt_pte_t
);
655 seq_printf(m
, " VM %p (pd_offset %x-%x):\n", vm
,
656 ppgtt
->pd_offset
, ppgtt
->pd_offset
+ ppgtt
->num_pd_entries
);
657 for (pde
= 0; pde
< ppgtt
->num_pd_entries
; pde
++) {
659 gen6_gtt_pte_t
*pt_vaddr
;
660 dma_addr_t pt_addr
= ppgtt
->pt_dma_addr
[pde
];
661 pd_entry
= readl(pd_addr
+ pde
);
662 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
664 if (pd_entry
!= expected
)
665 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
669 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
671 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[pde
]);
672 for (pte
= 0; pte
< I915_PPGTT_PT_ENTRIES
; pte
+=4) {
674 (pde
* PAGE_SIZE
* I915_PPGTT_PT_ENTRIES
) +
678 for (i
= 0; i
< 4; i
++)
679 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
684 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
685 for (i
= 0; i
< 4; i
++) {
686 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
687 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
689 seq_puts(m
, " SCRATCH ");
693 kunmap_atomic(pt_vaddr
);
697 static void gen6_write_pdes(struct i915_hw_ppgtt
*ppgtt
)
699 struct drm_i915_private
*dev_priv
= ppgtt
->base
.dev
->dev_private
;
700 gen6_gtt_pte_t __iomem
*pd_addr
;
704 WARN_ON(ppgtt
->pd_offset
& 0x3f);
705 pd_addr
= (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
706 ppgtt
->pd_offset
/ sizeof(gen6_gtt_pte_t
);
707 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
710 pt_addr
= ppgtt
->pt_dma_addr
[i
];
711 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
712 pd_entry
|= GEN6_PDE_VALID
;
714 writel(pd_entry
, pd_addr
+ i
);
719 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
721 BUG_ON(ppgtt
->pd_offset
& 0x3f);
723 return (ppgtt
->pd_offset
/ 64) << 16;
726 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
727 struct intel_engine_cs
*ring
,
730 struct drm_device
*dev
= ppgtt
->base
.dev
;
731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
734 /* If we're in reset, we can assume the GPU is sufficiently idle to
735 * manually frob these bits. Ideally we could use the ring functions,
736 * except our error handling makes it quite difficult (can't use
737 * intel_ring_begin, ring->flush, or intel_ring_advance)
739 * FIXME: We should try not to special case reset
742 i915_reset_in_progress(&dev_priv
->gpu_error
)) {
743 WARN_ON(ppgtt
!= dev_priv
->mm
.aliasing_ppgtt
);
744 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
745 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
746 POSTING_READ(RING_PP_DIR_BASE(ring
));
750 /* NB: TLBs must be flushed and invalidated before a switch */
751 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
755 ret
= intel_ring_begin(ring
, 6);
759 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
760 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
761 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
762 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
763 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
764 intel_ring_emit(ring
, MI_NOOP
);
765 intel_ring_advance(ring
);
770 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
771 struct intel_engine_cs
*ring
,
774 struct drm_device
*dev
= ppgtt
->base
.dev
;
775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
778 /* If we're in reset, we can assume the GPU is sufficiently idle to
779 * manually frob these bits. Ideally we could use the ring functions,
780 * except our error handling makes it quite difficult (can't use
781 * intel_ring_begin, ring->flush, or intel_ring_advance)
783 * FIXME: We should try not to special case reset
786 i915_reset_in_progress(&dev_priv
->gpu_error
)) {
787 WARN_ON(ppgtt
!= dev_priv
->mm
.aliasing_ppgtt
);
788 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
789 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
790 POSTING_READ(RING_PP_DIR_BASE(ring
));
794 /* NB: TLBs must be flushed and invalidated before a switch */
795 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
799 ret
= intel_ring_begin(ring
, 6);
803 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
804 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
805 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
806 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
807 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
808 intel_ring_emit(ring
, MI_NOOP
);
809 intel_ring_advance(ring
);
811 /* XXX: RCS is the only one to auto invalidate the TLBs? */
812 if (ring
->id
!= RCS
) {
813 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
821 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
822 struct intel_engine_cs
*ring
,
825 struct drm_device
*dev
= ppgtt
->base
.dev
;
826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
831 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
832 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
834 POSTING_READ(RING_PP_DIR_DCLV(ring
));
839 static int gen8_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
)
841 struct drm_device
*dev
= ppgtt
->base
.dev
;
842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
843 struct intel_engine_cs
*ring
;
846 for_each_ring(ring
, dev_priv
, j
) {
847 I915_WRITE(RING_MODE_GEN7(ring
),
848 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
850 /* We promise to do a switch later with FULL PPGTT. If this is
851 * aliasing, this is the one and only switch we'll do */
852 if (USES_FULL_PPGTT(dev
))
855 ret
= ppgtt
->switch_mm(ppgtt
, ring
, true);
863 for_each_ring(ring
, dev_priv
, j
)
864 I915_WRITE(RING_MODE_GEN7(ring
),
865 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE
));
869 static int gen7_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
)
871 struct drm_device
*dev
= ppgtt
->base
.dev
;
872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
873 struct intel_engine_cs
*ring
;
874 uint32_t ecochk
, ecobits
;
877 ecobits
= I915_READ(GAC_ECO_BITS
);
878 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
880 ecochk
= I915_READ(GAM_ECOCHK
);
881 if (IS_HASWELL(dev
)) {
882 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
884 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
885 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
887 I915_WRITE(GAM_ECOCHK
, ecochk
);
889 for_each_ring(ring
, dev_priv
, i
) {
891 /* GFX_MODE is per-ring on gen7+ */
892 I915_WRITE(RING_MODE_GEN7(ring
),
893 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
895 /* We promise to do a switch later with FULL PPGTT. If this is
896 * aliasing, this is the one and only switch we'll do */
897 if (USES_FULL_PPGTT(dev
))
900 ret
= ppgtt
->switch_mm(ppgtt
, ring
, true);
908 static int gen6_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
)
910 struct drm_device
*dev
= ppgtt
->base
.dev
;
911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
912 struct intel_engine_cs
*ring
;
913 uint32_t ecochk
, gab_ctl
, ecobits
;
916 ecobits
= I915_READ(GAC_ECO_BITS
);
917 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
918 ECOBITS_PPGTT_CACHE64B
);
920 gab_ctl
= I915_READ(GAB_CTL
);
921 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
923 ecochk
= I915_READ(GAM_ECOCHK
);
924 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
926 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
928 for_each_ring(ring
, dev_priv
, i
) {
929 int ret
= ppgtt
->switch_mm(ppgtt
, ring
, true);
937 /* PPGTT support for Sandybdrige/Gen6 and later */
938 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
943 struct i915_hw_ppgtt
*ppgtt
=
944 container_of(vm
, struct i915_hw_ppgtt
, base
);
945 gen6_gtt_pte_t
*pt_vaddr
, scratch_pte
;
946 unsigned first_entry
= start
>> PAGE_SHIFT
;
947 unsigned num_entries
= length
>> PAGE_SHIFT
;
948 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
949 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
950 unsigned last_pte
, i
;
952 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
954 while (num_entries
) {
955 last_pte
= first_pte
+ num_entries
;
956 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
957 last_pte
= I915_PPGTT_PT_ENTRIES
;
959 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
961 for (i
= first_pte
; i
< last_pte
; i
++)
962 pt_vaddr
[i
] = scratch_pte
;
964 kunmap_atomic(pt_vaddr
);
966 num_entries
-= last_pte
- first_pte
;
972 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
973 struct sg_table
*pages
,
975 enum i915_cache_level cache_level
, u32 flags
)
977 struct i915_hw_ppgtt
*ppgtt
=
978 container_of(vm
, struct i915_hw_ppgtt
, base
);
979 gen6_gtt_pte_t
*pt_vaddr
;
980 unsigned first_entry
= start
>> PAGE_SHIFT
;
981 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
982 unsigned act_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
983 struct sg_page_iter sg_iter
;
986 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
987 if (pt_vaddr
== NULL
)
988 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
991 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
992 cache_level
, true, flags
);
994 if (++act_pte
== I915_PPGTT_PT_ENTRIES
) {
995 kunmap_atomic(pt_vaddr
);
1002 kunmap_atomic(pt_vaddr
);
1005 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt
*ppgtt
)
1009 if (ppgtt
->pt_dma_addr
) {
1010 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
1011 pci_unmap_page(ppgtt
->base
.dev
->pdev
,
1012 ppgtt
->pt_dma_addr
[i
],
1013 4096, PCI_DMA_BIDIRECTIONAL
);
1017 static void gen6_ppgtt_free(struct i915_hw_ppgtt
*ppgtt
)
1021 kfree(ppgtt
->pt_dma_addr
);
1022 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
1023 __free_page(ppgtt
->pt_pages
[i
]);
1024 kfree(ppgtt
->pt_pages
);
1027 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1029 struct i915_hw_ppgtt
*ppgtt
=
1030 container_of(vm
, struct i915_hw_ppgtt
, base
);
1032 list_del(&vm
->global_link
);
1033 drm_mm_takedown(&ppgtt
->base
.mm
);
1034 drm_mm_remove_node(&ppgtt
->node
);
1036 gen6_ppgtt_unmap_pages(ppgtt
);
1037 gen6_ppgtt_free(ppgtt
);
1040 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1042 struct drm_device
*dev
= ppgtt
->base
.dev
;
1043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1044 bool retried
= false;
1047 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1048 * allocator works in address space sizes, so it's multiplied by page
1049 * size. We allocate at the top of the GTT to avoid fragmentation.
1051 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1053 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1054 &ppgtt
->node
, GEN6_PD_SIZE
,
1056 0, dev_priv
->gtt
.base
.total
,
1058 if (ret
== -ENOSPC
&& !retried
) {
1059 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1060 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1062 0, dev_priv
->gtt
.base
.total
,
1071 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1072 DRM_DEBUG("Forced to use aperture for PDEs\n");
1074 ppgtt
->num_pd_entries
= GEN6_PPGTT_PD_ENTRIES
;
1078 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt
*ppgtt
)
1082 ppgtt
->pt_pages
= kcalloc(ppgtt
->num_pd_entries
, sizeof(struct page
*),
1085 if (!ppgtt
->pt_pages
)
1088 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
1089 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
1090 if (!ppgtt
->pt_pages
[i
]) {
1091 gen6_ppgtt_free(ppgtt
);
1099 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1103 ret
= gen6_ppgtt_allocate_page_directories(ppgtt
);
1107 ret
= gen6_ppgtt_allocate_page_tables(ppgtt
);
1109 drm_mm_remove_node(&ppgtt
->node
);
1113 ppgtt
->pt_dma_addr
= kcalloc(ppgtt
->num_pd_entries
, sizeof(dma_addr_t
),
1115 if (!ppgtt
->pt_dma_addr
) {
1116 drm_mm_remove_node(&ppgtt
->node
);
1117 gen6_ppgtt_free(ppgtt
);
1124 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt
*ppgtt
)
1126 struct drm_device
*dev
= ppgtt
->base
.dev
;
1129 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
1132 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
1133 PCI_DMA_BIDIRECTIONAL
);
1135 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
1136 gen6_ppgtt_unmap_pages(ppgtt
);
1140 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
1146 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1148 struct drm_device
*dev
= ppgtt
->base
.dev
;
1149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1152 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1154 ppgtt
->enable
= gen6_ppgtt_enable
;
1155 ppgtt
->switch_mm
= gen6_mm_switch
;
1156 } else if (IS_HASWELL(dev
)) {
1157 ppgtt
->enable
= gen7_ppgtt_enable
;
1158 ppgtt
->switch_mm
= hsw_mm_switch
;
1159 } else if (IS_GEN7(dev
)) {
1160 ppgtt
->enable
= gen7_ppgtt_enable
;
1161 ppgtt
->switch_mm
= gen7_mm_switch
;
1165 ret
= gen6_ppgtt_alloc(ppgtt
);
1169 ret
= gen6_ppgtt_setup_page_tables(ppgtt
);
1171 gen6_ppgtt_free(ppgtt
);
1175 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1176 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1177 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1178 ppgtt
->base
.start
= 0;
1179 ppgtt
->base
.total
= ppgtt
->num_pd_entries
* I915_PPGTT_PT_ENTRIES
* PAGE_SIZE
;
1180 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1183 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_gtt_pte_t
);
1185 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1187 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1188 ppgtt
->node
.size
>> 20,
1189 ppgtt
->node
.start
/ PAGE_SIZE
);
1194 int i915_gem_init_ppgtt(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1199 ppgtt
->base
.dev
= dev
;
1200 ppgtt
->base
.scratch
= dev_priv
->gtt
.base
.scratch
;
1202 if (INTEL_INFO(dev
)->gen
< 8)
1203 ret
= gen6_ppgtt_init(ppgtt
);
1204 else if (IS_GEN8(dev
))
1205 ret
= gen8_ppgtt_init(ppgtt
, dev_priv
->gtt
.base
.total
);
1210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1211 kref_init(&ppgtt
->ref
);
1212 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1214 i915_init_vm(dev_priv
, &ppgtt
->base
);
1215 if (INTEL_INFO(dev
)->gen
< 8) {
1216 gen6_write_pdes(ppgtt
);
1217 DRM_DEBUG("Adding PPGTT at offset %x\n",
1218 ppgtt
->pd_offset
<< 10);
1226 ppgtt_bind_vma(struct i915_vma
*vma
,
1227 enum i915_cache_level cache_level
,
1230 /* Currently applicable only to VLV */
1231 if (vma
->obj
->gt_ro
)
1232 flags
|= PTE_READ_ONLY
;
1234 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
1235 cache_level
, flags
);
1238 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
1240 vma
->vm
->clear_range(vma
->vm
,
1242 vma
->obj
->base
.size
,
1246 extern int intel_iommu_gfx_mapped
;
1247 /* Certain Gen5 chipsets require require idling the GPU before
1248 * unmapping anything from the GTT when VT-d is enabled.
1250 static inline bool needs_idle_maps(struct drm_device
*dev
)
1252 #ifdef CONFIG_INTEL_IOMMU
1253 /* Query intel_iommu to see if we need the workaround. Presumably that
1256 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1262 static bool do_idling(struct drm_i915_private
*dev_priv
)
1264 bool ret
= dev_priv
->mm
.interruptible
;
1266 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1267 dev_priv
->mm
.interruptible
= false;
1268 if (i915_gpu_idle(dev_priv
->dev
)) {
1269 DRM_ERROR("Couldn't idle GPU\n");
1270 /* Wait a bit, in hopes it avoids the hang */
1278 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1280 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1281 dev_priv
->mm
.interruptible
= interruptible
;
1284 void i915_check_and_clear_faults(struct drm_device
*dev
)
1286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1287 struct intel_engine_cs
*ring
;
1290 if (INTEL_INFO(dev
)->gen
< 6)
1293 for_each_ring(ring
, dev_priv
, i
) {
1295 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1296 if (fault_reg
& RING_FAULT_VALID
) {
1297 DRM_DEBUG_DRIVER("Unexpected fault\n"
1298 "\tAddr: 0x%08lx\\n"
1299 "\tAddress space: %s\n"
1302 fault_reg
& PAGE_MASK
,
1303 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1304 RING_FAULT_SRCID(fault_reg
),
1305 RING_FAULT_FAULT_TYPE(fault_reg
));
1306 I915_WRITE(RING_FAULT_REG(ring
),
1307 fault_reg
& ~RING_FAULT_VALID
);
1310 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1313 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1317 /* Don't bother messing with faults pre GEN6 as we have little
1318 * documentation supporting that it's a good idea.
1320 if (INTEL_INFO(dev
)->gen
< 6)
1323 i915_check_and_clear_faults(dev
);
1325 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1326 dev_priv
->gtt
.base
.start
,
1327 dev_priv
->gtt
.base
.total
,
1331 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
1333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1334 struct drm_i915_gem_object
*obj
;
1335 struct i915_address_space
*vm
;
1337 i915_check_and_clear_faults(dev
);
1339 /* First fill our portion of the GTT with scratch pages */
1340 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1341 dev_priv
->gtt
.base
.start
,
1342 dev_priv
->gtt
.base
.total
,
1345 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1346 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
1347 &dev_priv
->gtt
.base
);
1351 i915_gem_clflush_object(obj
, obj
->pin_display
);
1352 /* The bind_vma code tries to be smart about tracking mappings.
1353 * Unfortunately above, we've just wiped out the mappings
1354 * without telling our object about it. So we need to fake it.
1356 obj
->has_global_gtt_mapping
= 0;
1357 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
1361 if (INTEL_INFO(dev
)->gen
>= 8) {
1362 if (IS_CHERRYVIEW(dev
))
1363 chv_setup_private_ppat(dev_priv
);
1365 bdw_setup_private_ppat(dev_priv
);
1370 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
1371 /* TODO: Perhaps it shouldn't be gen6 specific */
1372 if (i915_is_ggtt(vm
)) {
1373 if (dev_priv
->mm
.aliasing_ppgtt
)
1374 gen6_write_pdes(dev_priv
->mm
.aliasing_ppgtt
);
1378 gen6_write_pdes(container_of(vm
, struct i915_hw_ppgtt
, base
));
1381 i915_gem_chipset_flush(dev
);
1384 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1386 if (obj
->has_dma_mapping
)
1389 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1390 obj
->pages
->sgl
, obj
->pages
->nents
,
1391 PCI_DMA_BIDIRECTIONAL
))
1397 static inline void gen8_set_pte(void __iomem
*addr
, gen8_gtt_pte_t pte
)
1402 iowrite32((u32
)pte
, addr
);
1403 iowrite32(pte
>> 32, addr
+ 4);
1407 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1408 struct sg_table
*st
,
1410 enum i915_cache_level level
, u32 unused
)
1412 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1413 unsigned first_entry
= start
>> PAGE_SHIFT
;
1414 gen8_gtt_pte_t __iomem
*gtt_entries
=
1415 (gen8_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1417 struct sg_page_iter sg_iter
;
1418 dma_addr_t addr
= 0; /* shut up gcc */
1420 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1421 addr
= sg_dma_address(sg_iter
.sg
) +
1422 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1423 gen8_set_pte(>t_entries
[i
],
1424 gen8_pte_encode(addr
, level
, true));
1429 * XXX: This serves as a posting read to make sure that the PTE has
1430 * actually been updated. There is some concern that even though
1431 * registers and PTEs are within the same BAR that they are potentially
1432 * of NUMA access patterns. Therefore, even with the way we assume
1433 * hardware should work, we must keep this posting read for paranoia.
1436 WARN_ON(readq(>t_entries
[i
-1])
1437 != gen8_pte_encode(addr
, level
, true));
1439 /* This next bit makes the above posting read even more important. We
1440 * want to flush the TLBs only after we're certain all the PTE updates
1443 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1444 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1448 * Binds an object into the global gtt with the specified cache level. The object
1449 * will be accessible to the GPU via commands whose operands reference offsets
1450 * within the global GTT as well as accessible by the GPU through the GMADR
1451 * mapped BAR (dev_priv->mm.gtt->gtt).
1453 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1454 struct sg_table
*st
,
1456 enum i915_cache_level level
, u32 flags
)
1458 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1459 unsigned first_entry
= start
>> PAGE_SHIFT
;
1460 gen6_gtt_pte_t __iomem
*gtt_entries
=
1461 (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1463 struct sg_page_iter sg_iter
;
1464 dma_addr_t addr
= 0;
1466 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1467 addr
= sg_page_iter_dma_address(&sg_iter
);
1468 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1472 /* XXX: This serves as a posting read to make sure that the PTE has
1473 * actually been updated. There is some concern that even though
1474 * registers and PTEs are within the same BAR that they are potentially
1475 * of NUMA access patterns. Therefore, even with the way we assume
1476 * hardware should work, we must keep this posting read for paranoia.
1479 unsigned long gtt
= readl(>t_entries
[i
-1]);
1480 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1483 /* This next bit makes the above posting read even more important. We
1484 * want to flush the TLBs only after we're certain all the PTE updates
1487 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1488 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1491 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1496 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1497 unsigned first_entry
= start
>> PAGE_SHIFT
;
1498 unsigned num_entries
= length
>> PAGE_SHIFT
;
1499 gen8_gtt_pte_t scratch_pte
, __iomem
*gtt_base
=
1500 (gen8_gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1501 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1504 if (WARN(num_entries
> max_entries
,
1505 "First entry = %d; Num entries = %d (max=%d)\n",
1506 first_entry
, num_entries
, max_entries
))
1507 num_entries
= max_entries
;
1509 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
1512 for (i
= 0; i
< num_entries
; i
++)
1513 gen8_set_pte(>t_base
[i
], scratch_pte
);
1517 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1522 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1523 unsigned first_entry
= start
>> PAGE_SHIFT
;
1524 unsigned num_entries
= length
>> PAGE_SHIFT
;
1525 gen6_gtt_pte_t scratch_pte
, __iomem
*gtt_base
=
1526 (gen6_gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1527 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1530 if (WARN(num_entries
> max_entries
,
1531 "First entry = %d; Num entries = %d (max=%d)\n",
1532 first_entry
, num_entries
, max_entries
))
1533 num_entries
= max_entries
;
1535 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, use_scratch
, 0);
1537 for (i
= 0; i
< num_entries
; i
++)
1538 iowrite32(scratch_pte
, >t_base
[i
]);
1543 static void i915_ggtt_bind_vma(struct i915_vma
*vma
,
1544 enum i915_cache_level cache_level
,
1547 const unsigned long entry
= vma
->node
.start
>> PAGE_SHIFT
;
1548 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1549 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1551 BUG_ON(!i915_is_ggtt(vma
->vm
));
1552 intel_gtt_insert_sg_entries(vma
->obj
->pages
, entry
, flags
);
1553 vma
->obj
->has_global_gtt_mapping
= 1;
1556 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1561 unsigned first_entry
= start
>> PAGE_SHIFT
;
1562 unsigned num_entries
= length
>> PAGE_SHIFT
;
1563 intel_gtt_clear_range(first_entry
, num_entries
);
1566 static void i915_ggtt_unbind_vma(struct i915_vma
*vma
)
1568 const unsigned int first
= vma
->node
.start
>> PAGE_SHIFT
;
1569 const unsigned int size
= vma
->obj
->base
.size
>> PAGE_SHIFT
;
1571 BUG_ON(!i915_is_ggtt(vma
->vm
));
1572 vma
->obj
->has_global_gtt_mapping
= 0;
1573 intel_gtt_clear_range(first
, size
);
1576 static void ggtt_bind_vma(struct i915_vma
*vma
,
1577 enum i915_cache_level cache_level
,
1580 struct drm_device
*dev
= vma
->vm
->dev
;
1581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 struct drm_i915_gem_object
*obj
= vma
->obj
;
1584 /* Currently applicable only to VLV */
1586 flags
|= PTE_READ_ONLY
;
1588 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1589 * or we have a global mapping already but the cacheability flags have
1590 * changed, set the global PTEs.
1592 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1593 * instead if none of the above hold true.
1595 * NB: A global mapping should only be needed for special regions like
1596 * "gtt mappable", SNB errata, or if specified via special execbuf
1597 * flags. At all other times, the GPU will use the aliasing PPGTT.
1599 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1600 if (!obj
->has_global_gtt_mapping
||
1601 (cache_level
!= obj
->cache_level
)) {
1602 vma
->vm
->insert_entries(vma
->vm
, obj
->pages
,
1604 cache_level
, flags
);
1605 obj
->has_global_gtt_mapping
= 1;
1609 if (dev_priv
->mm
.aliasing_ppgtt
&&
1610 (!obj
->has_aliasing_ppgtt_mapping
||
1611 (cache_level
!= obj
->cache_level
))) {
1612 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1613 appgtt
->base
.insert_entries(&appgtt
->base
,
1616 cache_level
, flags
);
1617 vma
->obj
->has_aliasing_ppgtt_mapping
= 1;
1621 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1623 struct drm_device
*dev
= vma
->vm
->dev
;
1624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1625 struct drm_i915_gem_object
*obj
= vma
->obj
;
1627 if (obj
->has_global_gtt_mapping
) {
1628 vma
->vm
->clear_range(vma
->vm
,
1632 obj
->has_global_gtt_mapping
= 0;
1635 if (obj
->has_aliasing_ppgtt_mapping
) {
1636 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1637 appgtt
->base
.clear_range(&appgtt
->base
,
1641 obj
->has_aliasing_ppgtt_mapping
= 0;
1645 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1647 struct drm_device
*dev
= obj
->base
.dev
;
1648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1651 interruptible
= do_idling(dev_priv
);
1653 if (!obj
->has_dma_mapping
)
1654 dma_unmap_sg(&dev
->pdev
->dev
,
1655 obj
->pages
->sgl
, obj
->pages
->nents
,
1656 PCI_DMA_BIDIRECTIONAL
);
1658 undo_idling(dev_priv
, interruptible
);
1661 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1662 unsigned long color
,
1663 unsigned long *start
,
1666 if (node
->color
!= color
)
1669 if (!list_empty(&node
->node_list
)) {
1670 node
= list_entry(node
->node_list
.next
,
1673 if (node
->allocated
&& node
->color
!= color
)
1678 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
1679 unsigned long start
,
1680 unsigned long mappable_end
,
1683 /* Let GEM Manage all of the aperture.
1685 * However, leave one page at the end still bound to the scratch page.
1686 * There are a number of places where the hardware apparently prefetches
1687 * past the end of the object, and we've seen multiple hangs with the
1688 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1689 * aperture. One page should be enough to keep any prefetching inside
1692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1693 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
1694 struct drm_mm_node
*entry
;
1695 struct drm_i915_gem_object
*obj
;
1696 unsigned long hole_start
, hole_end
;
1698 BUG_ON(mappable_end
> end
);
1700 /* Subtract the guard page ... */
1701 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
1703 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
1705 /* Mark any preallocated objects as occupied */
1706 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1707 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
1709 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1710 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
1712 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
1713 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
1715 DRM_DEBUG_KMS("Reservation failed\n");
1716 obj
->has_global_gtt_mapping
= 1;
1719 dev_priv
->gtt
.base
.start
= start
;
1720 dev_priv
->gtt
.base
.total
= end
- start
;
1722 /* Clear any non-preallocated blocks */
1723 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
1724 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1725 hole_start
, hole_end
);
1726 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
1727 hole_end
- hole_start
, true);
1730 /* And finally clear the reserved guard page */
1731 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
1734 void i915_gem_init_global_gtt(struct drm_device
*dev
)
1736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1737 unsigned long gtt_size
, mappable_size
;
1739 gtt_size
= dev_priv
->gtt
.base
.total
;
1740 mappable_size
= dev_priv
->gtt
.mappable_end
;
1742 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
1745 static int setup_scratch_page(struct drm_device
*dev
)
1747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1749 dma_addr_t dma_addr
;
1751 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
1755 set_pages_uc(page
, 1);
1757 #ifdef CONFIG_INTEL_IOMMU
1758 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
1759 PCI_DMA_BIDIRECTIONAL
);
1760 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
1763 dma_addr
= page_to_phys(page
);
1765 dev_priv
->gtt
.base
.scratch
.page
= page
;
1766 dev_priv
->gtt
.base
.scratch
.addr
= dma_addr
;
1771 static void teardown_scratch_page(struct drm_device
*dev
)
1773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1774 struct page
*page
= dev_priv
->gtt
.base
.scratch
.page
;
1776 set_pages_wb(page
, 1);
1777 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.base
.scratch
.addr
,
1778 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
1783 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
1785 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
1786 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
1787 return snb_gmch_ctl
<< 20;
1790 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
1792 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
1793 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
1795 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
1797 #ifdef CONFIG_X86_32
1798 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1799 if (bdw_gmch_ctl
> 4)
1803 return bdw_gmch_ctl
<< 20;
1806 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
1808 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
1809 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
1812 return 1 << (20 + gmch_ctrl
);
1817 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
1819 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
1820 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
1821 return snb_gmch_ctl
<< 25; /* 32 MB units */
1824 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
1826 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
1827 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
1828 return bdw_gmch_ctl
<< 25; /* 32 MB units */
1831 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
1833 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
1834 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
1837 * 0x0 to 0x10: 32MB increments starting at 0MB
1838 * 0x11 to 0x16: 4MB increments starting at 8MB
1839 * 0x17 to 0x1d: 4MB increments start at 36MB
1841 if (gmch_ctrl
< 0x11)
1842 return gmch_ctrl
<< 25;
1843 else if (gmch_ctrl
< 0x17)
1844 return (gmch_ctrl
- 0x11 + 2) << 22;
1846 return (gmch_ctrl
- 0x17 + 9) << 22;
1849 static int ggtt_probe_common(struct drm_device
*dev
,
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 phys_addr_t gtt_phys_addr
;
1856 /* For Modern GENs the PTEs and register space are split in the BAR */
1857 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
1858 (pci_resource_len(dev
->pdev
, 0) / 2);
1860 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
1861 if (!dev_priv
->gtt
.gsm
) {
1862 DRM_ERROR("Failed to map the gtt page table\n");
1866 ret
= setup_scratch_page(dev
);
1868 DRM_ERROR("Scratch setup failed\n");
1869 /* iounmap will also get called at remove, but meh */
1870 iounmap(dev_priv
->gtt
.gsm
);
1876 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1877 * bits. When using advanced contexts each context stores its own PAT, but
1878 * writing this data shouldn't be harmful even in those cases. */
1879 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
1883 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
1884 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
1885 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
1886 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
1887 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
1888 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
1889 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
1890 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
1892 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1893 * write would work. */
1894 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
1895 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
1898 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
1903 * Map WB on BDW to snooped on CHV.
1905 * Only the snoop bit has meaning for CHV, the rest is
1908 * Note that the harware enforces snooping for all page
1909 * table accesses. The snoop bit is actually ignored for
1912 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
1916 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
1917 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
1918 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
1919 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
1921 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
1922 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
1925 static int gen8_gmch_probe(struct drm_device
*dev
,
1928 phys_addr_t
*mappable_base
,
1929 unsigned long *mappable_end
)
1931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1932 unsigned int gtt_size
;
1936 /* TODO: We're not aware of mappable constraints on gen8 yet */
1937 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
1938 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
1940 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
1941 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
1943 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
1945 if (IS_CHERRYVIEW(dev
)) {
1946 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
1947 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
1949 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
1950 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
1953 *gtt_total
= (gtt_size
/ sizeof(gen8_gtt_pte_t
)) << PAGE_SHIFT
;
1955 if (IS_CHERRYVIEW(dev
))
1956 chv_setup_private_ppat(dev_priv
);
1958 bdw_setup_private_ppat(dev_priv
);
1960 ret
= ggtt_probe_common(dev
, gtt_size
);
1962 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
1963 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
1968 static int gen6_gmch_probe(struct drm_device
*dev
,
1971 phys_addr_t
*mappable_base
,
1972 unsigned long *mappable_end
)
1974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1975 unsigned int gtt_size
;
1979 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
1980 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
1982 /* 64/512MB is the current min/max we actually know of, but this is just
1983 * a coarse sanity check.
1985 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
1986 DRM_ERROR("Unknown GMADR size (%lx)\n",
1987 dev_priv
->gtt
.mappable_end
);
1991 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
1992 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
1993 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
1995 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
1997 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
1998 *gtt_total
= (gtt_size
/ sizeof(gen6_gtt_pte_t
)) << PAGE_SHIFT
;
2000 ret
= ggtt_probe_common(dev
, gtt_size
);
2002 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2003 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2008 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2011 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2013 if (drm_mm_initialized(&vm
->mm
)) {
2014 drm_mm_takedown(&vm
->mm
);
2015 list_del(&vm
->global_link
);
2018 teardown_scratch_page(vm
->dev
);
2021 static int i915_gmch_probe(struct drm_device
*dev
,
2024 phys_addr_t
*mappable_base
,
2025 unsigned long *mappable_end
)
2027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2030 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2032 DRM_ERROR("failed to set up gmch\n");
2036 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2038 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2039 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2041 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2042 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2047 static void i915_gmch_remove(struct i915_address_space
*vm
)
2049 if (drm_mm_initialized(&vm
->mm
)) {
2050 drm_mm_takedown(&vm
->mm
);
2051 list_del(&vm
->global_link
);
2053 intel_gmch_remove();
2056 int i915_gem_gtt_init(struct drm_device
*dev
)
2058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2059 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2062 if (INTEL_INFO(dev
)->gen
<= 5) {
2063 gtt
->gtt_probe
= i915_gmch_probe
;
2064 gtt
->base
.cleanup
= i915_gmch_remove
;
2065 } else if (INTEL_INFO(dev
)->gen
< 8) {
2066 gtt
->gtt_probe
= gen6_gmch_probe
;
2067 gtt
->base
.cleanup
= gen6_gmch_remove
;
2068 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2069 gtt
->base
.pte_encode
= iris_pte_encode
;
2070 else if (IS_HASWELL(dev
))
2071 gtt
->base
.pte_encode
= hsw_pte_encode
;
2072 else if (IS_VALLEYVIEW(dev
))
2073 gtt
->base
.pte_encode
= byt_pte_encode
;
2074 else if (INTEL_INFO(dev
)->gen
>= 7)
2075 gtt
->base
.pte_encode
= ivb_pte_encode
;
2077 gtt
->base
.pte_encode
= snb_pte_encode
;
2079 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2080 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2083 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2084 >t
->mappable_base
, >t
->mappable_end
);
2088 gtt
->base
.dev
= dev
;
2090 /* GMADR is the PCI mmio aperture into the global GTT. */
2091 DRM_INFO("Memory usable by graphics device = %zdM\n",
2092 gtt
->base
.total
>> 20);
2093 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt
->mappable_end
>> 20);
2094 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2095 #ifdef CONFIG_INTEL_IOMMU
2096 if (intel_iommu_gfx_mapped
)
2097 DRM_INFO("VT-d active for gfx access\n");
2100 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2101 * user's requested state against the hardware/driver capabilities. We
2102 * do this now so that we can print out any log messages once rather
2103 * than every time we check intel_enable_ppgtt().
2105 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2106 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2111 static struct i915_vma
*__i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2112 struct i915_address_space
*vm
)
2114 struct i915_vma
*vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
2116 return ERR_PTR(-ENOMEM
);
2118 INIT_LIST_HEAD(&vma
->vma_link
);
2119 INIT_LIST_HEAD(&vma
->mm_list
);
2120 INIT_LIST_HEAD(&vma
->exec_list
);
2124 switch (INTEL_INFO(vm
->dev
)->gen
) {
2128 if (i915_is_ggtt(vm
)) {
2129 vma
->unbind_vma
= ggtt_unbind_vma
;
2130 vma
->bind_vma
= ggtt_bind_vma
;
2132 vma
->unbind_vma
= ppgtt_unbind_vma
;
2133 vma
->bind_vma
= ppgtt_bind_vma
;
2140 BUG_ON(!i915_is_ggtt(vm
));
2141 vma
->unbind_vma
= i915_ggtt_unbind_vma
;
2142 vma
->bind_vma
= i915_ggtt_bind_vma
;
2148 /* Keep GGTT vmas first to make debug easier */
2149 if (i915_is_ggtt(vm
))
2150 list_add(&vma
->vma_link
, &obj
->vma_list
);
2152 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2158 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2159 struct i915_address_space
*vm
)
2161 struct i915_vma
*vma
;
2163 vma
= i915_gem_obj_to_vma(obj
, vm
);
2165 vma
= __i915_gem_vma_create(obj
, vm
);