2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_trace.h"
31 #include "intel_drv.h"
33 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
);
34 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
);
36 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
38 if (enable_ppgtt
== 0 || !HAS_ALIASING_PPGTT(dev
))
41 if (enable_ppgtt
== 1)
44 if (enable_ppgtt
== 2 && HAS_PPGTT(dev
))
47 #ifdef CONFIG_INTEL_IOMMU
48 /* Disable ppgtt on SNB if VT-d is on. */
49 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
50 DRM_INFO("Disabling PPGTT because VT-d is on\n");
55 /* Early VLV doesn't have this */
56 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
57 dev
->pdev
->revision
< 0xb) {
58 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
62 return HAS_ALIASING_PPGTT(dev
) ? 1 : 0;
66 static void ppgtt_bind_vma(struct i915_vma
*vma
,
67 enum i915_cache_level cache_level
,
69 static void ppgtt_unbind_vma(struct i915_vma
*vma
);
70 static int gen8_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
);
72 static inline gen8_gtt_pte_t
gen8_pte_encode(dma_addr_t addr
,
73 enum i915_cache_level level
,
76 gen8_gtt_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
81 pte
|= PPAT_UNCACHED_INDEX
;
84 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
87 pte
|= PPAT_CACHED_INDEX
;
94 static inline gen8_ppgtt_pde_t
gen8_pde_encode(struct drm_device
*dev
,
96 enum i915_cache_level level
)
98 gen8_ppgtt_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
100 if (level
!= I915_CACHE_NONE
)
101 pde
|= PPAT_CACHED_PDE_INDEX
;
103 pde
|= PPAT_UNCACHED_INDEX
;
107 static gen6_gtt_pte_t
snb_pte_encode(dma_addr_t addr
,
108 enum i915_cache_level level
,
109 bool valid
, u32 unused
)
111 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
112 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
115 case I915_CACHE_L3_LLC
:
117 pte
|= GEN6_PTE_CACHE_LLC
;
119 case I915_CACHE_NONE
:
120 pte
|= GEN6_PTE_UNCACHED
;
129 static gen6_gtt_pte_t
ivb_pte_encode(dma_addr_t addr
,
130 enum i915_cache_level level
,
131 bool valid
, u32 unused
)
133 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
134 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
137 case I915_CACHE_L3_LLC
:
138 pte
|= GEN7_PTE_CACHE_L3_LLC
;
141 pte
|= GEN6_PTE_CACHE_LLC
;
143 case I915_CACHE_NONE
:
144 pte
|= GEN6_PTE_UNCACHED
;
153 static gen6_gtt_pte_t
byt_pte_encode(dma_addr_t addr
,
154 enum i915_cache_level level
,
155 bool valid
, u32 flags
)
157 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
158 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
160 /* Mark the page as writeable. Other platforms don't have a
161 * setting for read-only/writable, so this matches that behavior.
163 if (!(flags
& PTE_READ_ONLY
))
164 pte
|= BYT_PTE_WRITEABLE
;
166 if (level
!= I915_CACHE_NONE
)
167 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
172 static gen6_gtt_pte_t
hsw_pte_encode(dma_addr_t addr
,
173 enum i915_cache_level level
,
174 bool valid
, u32 unused
)
176 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
177 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
179 if (level
!= I915_CACHE_NONE
)
180 pte
|= HSW_WB_LLC_AGE3
;
185 static gen6_gtt_pte_t
iris_pte_encode(dma_addr_t addr
,
186 enum i915_cache_level level
,
187 bool valid
, u32 unused
)
189 gen6_gtt_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
190 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
193 case I915_CACHE_NONE
:
196 pte
|= HSW_WT_ELLC_LLC_AGE3
;
199 pte
|= HSW_WB_ELLC_LLC_AGE3
;
206 /* Broadwell Page Directory Pointer Descriptors */
207 static int gen8_write_pdp(struct intel_engine_cs
*ring
, unsigned entry
,
208 uint64_t val
, bool synchronous
)
210 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
216 I915_WRITE(GEN8_RING_PDP_UDW(ring
, entry
), val
>> 32);
217 I915_WRITE(GEN8_RING_PDP_LDW(ring
, entry
), (u32
)val
);
221 ret
= intel_ring_begin(ring
, 6);
225 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
226 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
227 intel_ring_emit(ring
, (u32
)(val
>> 32));
228 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
229 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
230 intel_ring_emit(ring
, (u32
)(val
));
231 intel_ring_advance(ring
);
236 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
237 struct intel_engine_cs
*ring
,
242 /* bit of a hack to find the actual last used pd */
243 int used_pd
= ppgtt
->num_pd_entries
/ GEN8_PDES_PER_PAGE
;
245 for (i
= used_pd
- 1; i
>= 0; i
--) {
246 dma_addr_t addr
= ppgtt
->pd_dma_addr
[i
];
247 ret
= gen8_write_pdp(ring
, i
, addr
, synchronous
);
255 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
260 struct i915_hw_ppgtt
*ppgtt
=
261 container_of(vm
, struct i915_hw_ppgtt
, base
);
262 gen8_gtt_pte_t
*pt_vaddr
, scratch_pte
;
263 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
264 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
265 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
266 unsigned num_entries
= length
>> PAGE_SHIFT
;
267 unsigned last_pte
, i
;
269 scratch_pte
= gen8_pte_encode(ppgtt
->base
.scratch
.addr
,
270 I915_CACHE_LLC
, use_scratch
);
272 while (num_entries
) {
273 struct page
*page_table
= ppgtt
->gen8_pt_pages
[pdpe
][pde
];
275 last_pte
= pte
+ num_entries
;
276 if (last_pte
> GEN8_PTES_PER_PAGE
)
277 last_pte
= GEN8_PTES_PER_PAGE
;
279 pt_vaddr
= kmap_atomic(page_table
);
281 for (i
= pte
; i
< last_pte
; i
++) {
282 pt_vaddr
[i
] = scratch_pte
;
286 if (!HAS_LLC(ppgtt
->base
.dev
))
287 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
288 kunmap_atomic(pt_vaddr
);
291 if (++pde
== GEN8_PDES_PER_PAGE
) {
298 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
299 struct sg_table
*pages
,
301 enum i915_cache_level cache_level
, u32 unused
)
303 struct i915_hw_ppgtt
*ppgtt
=
304 container_of(vm
, struct i915_hw_ppgtt
, base
);
305 gen8_gtt_pte_t
*pt_vaddr
;
306 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
307 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
308 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
309 struct sg_page_iter sg_iter
;
313 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
314 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPS
))
317 if (pt_vaddr
== NULL
)
318 pt_vaddr
= kmap_atomic(ppgtt
->gen8_pt_pages
[pdpe
][pde
]);
321 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
323 if (++pte
== GEN8_PTES_PER_PAGE
) {
324 if (!HAS_LLC(ppgtt
->base
.dev
))
325 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
326 kunmap_atomic(pt_vaddr
);
328 if (++pde
== GEN8_PDES_PER_PAGE
) {
336 if (!HAS_LLC(ppgtt
->base
.dev
))
337 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
338 kunmap_atomic(pt_vaddr
);
342 static void gen8_free_page_tables(struct page
**pt_pages
)
346 if (pt_pages
== NULL
)
349 for (i
= 0; i
< GEN8_PDES_PER_PAGE
; i
++)
351 __free_pages(pt_pages
[i
], 0);
354 static void gen8_ppgtt_free(const struct i915_hw_ppgtt
*ppgtt
)
358 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
359 gen8_free_page_tables(ppgtt
->gen8_pt_pages
[i
]);
360 kfree(ppgtt
->gen8_pt_pages
[i
]);
361 kfree(ppgtt
->gen8_pt_dma_addr
[i
]);
364 __free_pages(ppgtt
->pd_pages
, get_order(ppgtt
->num_pd_pages
<< PAGE_SHIFT
));
367 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt
*ppgtt
)
369 struct pci_dev
*hwdev
= ppgtt
->base
.dev
->pdev
;
372 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
373 /* TODO: In the future we'll support sparse mappings, so this
374 * will have to change. */
375 if (!ppgtt
->pd_dma_addr
[i
])
378 pci_unmap_page(hwdev
, ppgtt
->pd_dma_addr
[i
], PAGE_SIZE
,
379 PCI_DMA_BIDIRECTIONAL
);
381 for (j
= 0; j
< GEN8_PDES_PER_PAGE
; j
++) {
382 dma_addr_t addr
= ppgtt
->gen8_pt_dma_addr
[i
][j
];
384 pci_unmap_page(hwdev
, addr
, PAGE_SIZE
,
385 PCI_DMA_BIDIRECTIONAL
);
390 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
392 struct i915_hw_ppgtt
*ppgtt
=
393 container_of(vm
, struct i915_hw_ppgtt
, base
);
395 list_del(&vm
->global_link
);
396 drm_mm_takedown(&vm
->mm
);
398 gen8_ppgtt_unmap_pages(ppgtt
);
399 gen8_ppgtt_free(ppgtt
);
402 static struct page
**__gen8_alloc_page_tables(void)
404 struct page
**pt_pages
;
407 pt_pages
= kcalloc(GEN8_PDES_PER_PAGE
, sizeof(struct page
*), GFP_KERNEL
);
409 return ERR_PTR(-ENOMEM
);
411 for (i
= 0; i
< GEN8_PDES_PER_PAGE
; i
++) {
412 pt_pages
[i
] = alloc_page(GFP_KERNEL
);
420 gen8_free_page_tables(pt_pages
);
422 return ERR_PTR(-ENOMEM
);
425 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt
*ppgtt
,
428 struct page
**pt_pages
[GEN8_LEGACY_PDPS
];
431 for (i
= 0; i
< max_pdp
; i
++) {
432 pt_pages
[i
] = __gen8_alloc_page_tables();
433 if (IS_ERR(pt_pages
[i
])) {
434 ret
= PTR_ERR(pt_pages
[i
]);
439 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
440 * "atomic" - for cleanup purposes.
442 for (i
= 0; i
< max_pdp
; i
++)
443 ppgtt
->gen8_pt_pages
[i
] = pt_pages
[i
];
449 gen8_free_page_tables(pt_pages
[i
]);
456 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt
*ppgtt
)
460 for (i
= 0; i
< ppgtt
->num_pd_pages
; i
++) {
461 ppgtt
->gen8_pt_dma_addr
[i
] = kcalloc(GEN8_PDES_PER_PAGE
,
464 if (!ppgtt
->gen8_pt_dma_addr
[i
])
471 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
,
474 ppgtt
->pd_pages
= alloc_pages(GFP_KERNEL
, get_order(max_pdp
<< PAGE_SHIFT
));
475 if (!ppgtt
->pd_pages
)
478 ppgtt
->num_pd_pages
= 1 << get_order(max_pdp
<< PAGE_SHIFT
);
479 BUG_ON(ppgtt
->num_pd_pages
> GEN8_LEGACY_PDPS
);
484 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
,
489 ret
= gen8_ppgtt_allocate_page_directories(ppgtt
, max_pdp
);
493 ret
= gen8_ppgtt_allocate_page_tables(ppgtt
, max_pdp
);
495 __free_pages(ppgtt
->pd_pages
, get_order(max_pdp
<< PAGE_SHIFT
));
499 ppgtt
->num_pd_entries
= max_pdp
* GEN8_PDES_PER_PAGE
;
501 ret
= gen8_ppgtt_allocate_dma(ppgtt
);
503 gen8_ppgtt_free(ppgtt
);
508 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt
*ppgtt
,
514 pd_addr
= pci_map_page(ppgtt
->base
.dev
->pdev
,
515 &ppgtt
->pd_pages
[pd
], 0,
516 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
518 ret
= pci_dma_mapping_error(ppgtt
->base
.dev
->pdev
, pd_addr
);
522 ppgtt
->pd_dma_addr
[pd
] = pd_addr
;
527 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt
*ppgtt
,
535 p
= ppgtt
->gen8_pt_pages
[pd
][pt
];
536 pt_addr
= pci_map_page(ppgtt
->base
.dev
->pdev
,
537 p
, 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
538 ret
= pci_dma_mapping_error(ppgtt
->base
.dev
->pdev
, pt_addr
);
542 ppgtt
->gen8_pt_dma_addr
[pd
][pt
] = pt_addr
;
548 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
549 * with a net effect resembling a 2-level page table in normal x86 terms. Each
550 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
553 * FIXME: split allocation into smaller pieces. For now we only ever do this
554 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
555 * TODO: Do something with the size parameter
557 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
, uint64_t size
)
559 const int max_pdp
= DIV_ROUND_UP(size
, 1 << 30);
560 const int min_pt_pages
= GEN8_PDES_PER_PAGE
* max_pdp
;
564 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size
);
566 /* 1. Do all our allocations for page directories and page tables. */
567 ret
= gen8_ppgtt_alloc(ppgtt
, max_pdp
);
572 * 2. Create DMA mappings for the page directories and page tables.
574 for (i
= 0; i
< max_pdp
; i
++) {
575 ret
= gen8_ppgtt_setup_page_directories(ppgtt
, i
);
579 for (j
= 0; j
< GEN8_PDES_PER_PAGE
; j
++) {
580 ret
= gen8_ppgtt_setup_page_tables(ppgtt
, i
, j
);
587 * 3. Map all the page directory entires to point to the page tables
590 * For now, the PPGTT helper functions all require that the PDEs are
591 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
592 * will never need to touch the PDEs again.
594 for (i
= 0; i
< max_pdp
; i
++) {
595 gen8_ppgtt_pde_t
*pd_vaddr
;
596 pd_vaddr
= kmap_atomic(&ppgtt
->pd_pages
[i
]);
597 for (j
= 0; j
< GEN8_PDES_PER_PAGE
; j
++) {
598 dma_addr_t addr
= ppgtt
->gen8_pt_dma_addr
[i
][j
];
599 pd_vaddr
[j
] = gen8_pde_encode(ppgtt
->base
.dev
, addr
,
602 if (!HAS_LLC(ppgtt
->base
.dev
))
603 drm_clflush_virt_range(pd_vaddr
, PAGE_SIZE
);
604 kunmap_atomic(pd_vaddr
);
607 ppgtt
->enable
= gen8_ppgtt_enable
;
608 ppgtt
->switch_mm
= gen8_mm_switch
;
609 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
610 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
611 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
612 ppgtt
->base
.start
= 0;
613 ppgtt
->base
.total
= ppgtt
->num_pd_entries
* GEN8_PTES_PER_PAGE
* PAGE_SIZE
;
615 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
617 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
618 ppgtt
->num_pd_pages
, ppgtt
->num_pd_pages
- max_pdp
);
619 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
620 ppgtt
->num_pd_entries
,
621 (ppgtt
->num_pd_entries
- min_pt_pages
) + size
% (1<<30));
625 gen8_ppgtt_unmap_pages(ppgtt
);
626 gen8_ppgtt_free(ppgtt
);
630 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
632 struct drm_i915_private
*dev_priv
= ppgtt
->base
.dev
->dev_private
;
633 struct i915_address_space
*vm
= &ppgtt
->base
;
634 gen6_gtt_pte_t __iomem
*pd_addr
;
635 gen6_gtt_pte_t scratch_pte
;
639 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
641 pd_addr
= (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
642 ppgtt
->pd_offset
/ sizeof(gen6_gtt_pte_t
);
644 seq_printf(m
, " VM %p (pd_offset %x-%x):\n", vm
,
645 ppgtt
->pd_offset
, ppgtt
->pd_offset
+ ppgtt
->num_pd_entries
);
646 for (pde
= 0; pde
< ppgtt
->num_pd_entries
; pde
++) {
648 gen6_gtt_pte_t
*pt_vaddr
;
649 dma_addr_t pt_addr
= ppgtt
->pt_dma_addr
[pde
];
650 pd_entry
= readl(pd_addr
+ pde
);
651 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
653 if (pd_entry
!= expected
)
654 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
658 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
660 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[pde
]);
661 for (pte
= 0; pte
< I915_PPGTT_PT_ENTRIES
; pte
+=4) {
663 (pde
* PAGE_SIZE
* I915_PPGTT_PT_ENTRIES
) +
667 for (i
= 0; i
< 4; i
++)
668 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
673 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
674 for (i
= 0; i
< 4; i
++) {
675 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
676 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
678 seq_puts(m
, " SCRATCH ");
682 kunmap_atomic(pt_vaddr
);
686 static void gen6_write_pdes(struct i915_hw_ppgtt
*ppgtt
)
688 struct drm_i915_private
*dev_priv
= ppgtt
->base
.dev
->dev_private
;
689 gen6_gtt_pte_t __iomem
*pd_addr
;
693 WARN_ON(ppgtt
->pd_offset
& 0x3f);
694 pd_addr
= (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
695 ppgtt
->pd_offset
/ sizeof(gen6_gtt_pte_t
);
696 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
699 pt_addr
= ppgtt
->pt_dma_addr
[i
];
700 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
701 pd_entry
|= GEN6_PDE_VALID
;
703 writel(pd_entry
, pd_addr
+ i
);
708 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
710 BUG_ON(ppgtt
->pd_offset
& 0x3f);
712 return (ppgtt
->pd_offset
/ 64) << 16;
715 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
716 struct intel_engine_cs
*ring
,
719 struct drm_device
*dev
= ppgtt
->base
.dev
;
720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
723 /* If we're in reset, we can assume the GPU is sufficiently idle to
724 * manually frob these bits. Ideally we could use the ring functions,
725 * except our error handling makes it quite difficult (can't use
726 * intel_ring_begin, ring->flush, or intel_ring_advance)
728 * FIXME: We should try not to special case reset
731 i915_reset_in_progress(&dev_priv
->gpu_error
)) {
732 WARN_ON(ppgtt
!= dev_priv
->mm
.aliasing_ppgtt
);
733 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
734 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
735 POSTING_READ(RING_PP_DIR_BASE(ring
));
739 /* NB: TLBs must be flushed and invalidated before a switch */
740 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
744 ret
= intel_ring_begin(ring
, 6);
748 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
749 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
750 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
751 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
752 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
753 intel_ring_emit(ring
, MI_NOOP
);
754 intel_ring_advance(ring
);
759 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
760 struct intel_engine_cs
*ring
,
763 struct drm_device
*dev
= ppgtt
->base
.dev
;
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 /* If we're in reset, we can assume the GPU is sufficiently idle to
768 * manually frob these bits. Ideally we could use the ring functions,
769 * except our error handling makes it quite difficult (can't use
770 * intel_ring_begin, ring->flush, or intel_ring_advance)
772 * FIXME: We should try not to special case reset
775 i915_reset_in_progress(&dev_priv
->gpu_error
)) {
776 WARN_ON(ppgtt
!= dev_priv
->mm
.aliasing_ppgtt
);
777 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
778 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
779 POSTING_READ(RING_PP_DIR_BASE(ring
));
783 /* NB: TLBs must be flushed and invalidated before a switch */
784 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
788 ret
= intel_ring_begin(ring
, 6);
792 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
793 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
794 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
795 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
796 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
797 intel_ring_emit(ring
, MI_NOOP
);
798 intel_ring_advance(ring
);
800 /* XXX: RCS is the only one to auto invalidate the TLBs? */
801 if (ring
->id
!= RCS
) {
802 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
810 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
811 struct intel_engine_cs
*ring
,
814 struct drm_device
*dev
= ppgtt
->base
.dev
;
815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
821 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
823 POSTING_READ(RING_PP_DIR_DCLV(ring
));
828 static int gen8_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
)
830 struct drm_device
*dev
= ppgtt
->base
.dev
;
831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
832 struct intel_engine_cs
*ring
;
835 for_each_ring(ring
, dev_priv
, j
) {
836 I915_WRITE(RING_MODE_GEN7(ring
),
837 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
839 /* We promise to do a switch later with FULL PPGTT. If this is
840 * aliasing, this is the one and only switch we'll do */
841 if (USES_FULL_PPGTT(dev
))
844 ret
= ppgtt
->switch_mm(ppgtt
, ring
, true);
852 for_each_ring(ring
, dev_priv
, j
)
853 I915_WRITE(RING_MODE_GEN7(ring
),
854 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE
));
858 static int gen7_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
)
860 struct drm_device
*dev
= ppgtt
->base
.dev
;
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
862 struct intel_engine_cs
*ring
;
863 uint32_t ecochk
, ecobits
;
866 ecobits
= I915_READ(GAC_ECO_BITS
);
867 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
869 ecochk
= I915_READ(GAM_ECOCHK
);
870 if (IS_HASWELL(dev
)) {
871 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
873 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
874 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
876 I915_WRITE(GAM_ECOCHK
, ecochk
);
878 for_each_ring(ring
, dev_priv
, i
) {
880 /* GFX_MODE is per-ring on gen7+ */
881 I915_WRITE(RING_MODE_GEN7(ring
),
882 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
884 /* We promise to do a switch later with FULL PPGTT. If this is
885 * aliasing, this is the one and only switch we'll do */
886 if (USES_FULL_PPGTT(dev
))
889 ret
= ppgtt
->switch_mm(ppgtt
, ring
, true);
897 static int gen6_ppgtt_enable(struct i915_hw_ppgtt
*ppgtt
)
899 struct drm_device
*dev
= ppgtt
->base
.dev
;
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 struct intel_engine_cs
*ring
;
902 uint32_t ecochk
, gab_ctl
, ecobits
;
905 ecobits
= I915_READ(GAC_ECO_BITS
);
906 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
907 ECOBITS_PPGTT_CACHE64B
);
909 gab_ctl
= I915_READ(GAB_CTL
);
910 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
912 ecochk
= I915_READ(GAM_ECOCHK
);
913 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
915 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
917 for_each_ring(ring
, dev_priv
, i
) {
918 int ret
= ppgtt
->switch_mm(ppgtt
, ring
, true);
926 /* PPGTT support for Sandybdrige/Gen6 and later */
927 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
932 struct i915_hw_ppgtt
*ppgtt
=
933 container_of(vm
, struct i915_hw_ppgtt
, base
);
934 gen6_gtt_pte_t
*pt_vaddr
, scratch_pte
;
935 unsigned first_entry
= start
>> PAGE_SHIFT
;
936 unsigned num_entries
= length
>> PAGE_SHIFT
;
937 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
938 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
939 unsigned last_pte
, i
;
941 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
943 while (num_entries
) {
944 last_pte
= first_pte
+ num_entries
;
945 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
946 last_pte
= I915_PPGTT_PT_ENTRIES
;
948 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
950 for (i
= first_pte
; i
< last_pte
; i
++)
951 pt_vaddr
[i
] = scratch_pte
;
953 kunmap_atomic(pt_vaddr
);
955 num_entries
-= last_pte
- first_pte
;
961 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
962 struct sg_table
*pages
,
964 enum i915_cache_level cache_level
, u32 flags
)
966 struct i915_hw_ppgtt
*ppgtt
=
967 container_of(vm
, struct i915_hw_ppgtt
, base
);
968 gen6_gtt_pte_t
*pt_vaddr
;
969 unsigned first_entry
= start
>> PAGE_SHIFT
;
970 unsigned act_pt
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
971 unsigned act_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
972 struct sg_page_iter sg_iter
;
975 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
976 if (pt_vaddr
== NULL
)
977 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pt
]);
980 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
981 cache_level
, true, flags
);
983 if (++act_pte
== I915_PPGTT_PT_ENTRIES
) {
984 kunmap_atomic(pt_vaddr
);
991 kunmap_atomic(pt_vaddr
);
994 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt
*ppgtt
)
998 if (ppgtt
->pt_dma_addr
) {
999 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
1000 pci_unmap_page(ppgtt
->base
.dev
->pdev
,
1001 ppgtt
->pt_dma_addr
[i
],
1002 4096, PCI_DMA_BIDIRECTIONAL
);
1006 static void gen6_ppgtt_free(struct i915_hw_ppgtt
*ppgtt
)
1010 kfree(ppgtt
->pt_dma_addr
);
1011 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
1012 __free_page(ppgtt
->pt_pages
[i
]);
1013 kfree(ppgtt
->pt_pages
);
1016 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1018 struct i915_hw_ppgtt
*ppgtt
=
1019 container_of(vm
, struct i915_hw_ppgtt
, base
);
1021 list_del(&vm
->global_link
);
1022 drm_mm_takedown(&ppgtt
->base
.mm
);
1023 drm_mm_remove_node(&ppgtt
->node
);
1025 gen6_ppgtt_unmap_pages(ppgtt
);
1026 gen6_ppgtt_free(ppgtt
);
1029 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1031 struct drm_device
*dev
= ppgtt
->base
.dev
;
1032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1033 bool retried
= false;
1036 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1037 * allocator works in address space sizes, so it's multiplied by page
1038 * size. We allocate at the top of the GTT to avoid fragmentation.
1040 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1042 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1043 &ppgtt
->node
, GEN6_PD_SIZE
,
1045 0, dev_priv
->gtt
.base
.total
,
1047 if (ret
== -ENOSPC
&& !retried
) {
1048 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1049 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1051 0, dev_priv
->gtt
.base
.total
,
1060 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1061 DRM_DEBUG("Forced to use aperture for PDEs\n");
1063 ppgtt
->num_pd_entries
= GEN6_PPGTT_PD_ENTRIES
;
1067 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt
*ppgtt
)
1071 ppgtt
->pt_pages
= kcalloc(ppgtt
->num_pd_entries
, sizeof(struct page
*),
1074 if (!ppgtt
->pt_pages
)
1077 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
1078 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
1079 if (!ppgtt
->pt_pages
[i
]) {
1080 gen6_ppgtt_free(ppgtt
);
1088 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1092 ret
= gen6_ppgtt_allocate_page_directories(ppgtt
);
1096 ret
= gen6_ppgtt_allocate_page_tables(ppgtt
);
1098 drm_mm_remove_node(&ppgtt
->node
);
1102 ppgtt
->pt_dma_addr
= kcalloc(ppgtt
->num_pd_entries
, sizeof(dma_addr_t
),
1104 if (!ppgtt
->pt_dma_addr
) {
1105 drm_mm_remove_node(&ppgtt
->node
);
1106 gen6_ppgtt_free(ppgtt
);
1113 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt
*ppgtt
)
1115 struct drm_device
*dev
= ppgtt
->base
.dev
;
1118 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
1121 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
1122 PCI_DMA_BIDIRECTIONAL
);
1124 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
1125 gen6_ppgtt_unmap_pages(ppgtt
);
1129 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
1135 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1137 struct drm_device
*dev
= ppgtt
->base
.dev
;
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1141 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1143 ppgtt
->enable
= gen6_ppgtt_enable
;
1144 ppgtt
->switch_mm
= gen6_mm_switch
;
1145 } else if (IS_HASWELL(dev
)) {
1146 ppgtt
->enable
= gen7_ppgtt_enable
;
1147 ppgtt
->switch_mm
= hsw_mm_switch
;
1148 } else if (IS_GEN7(dev
)) {
1149 ppgtt
->enable
= gen7_ppgtt_enable
;
1150 ppgtt
->switch_mm
= gen7_mm_switch
;
1154 ret
= gen6_ppgtt_alloc(ppgtt
);
1158 ret
= gen6_ppgtt_setup_page_tables(ppgtt
);
1160 gen6_ppgtt_free(ppgtt
);
1164 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1165 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1166 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1167 ppgtt
->base
.start
= 0;
1168 ppgtt
->base
.total
= ppgtt
->num_pd_entries
* I915_PPGTT_PT_ENTRIES
* PAGE_SIZE
;
1169 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1172 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_gtt_pte_t
);
1174 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1176 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1177 ppgtt
->node
.size
>> 20,
1178 ppgtt
->node
.start
/ PAGE_SIZE
);
1183 int i915_gem_init_ppgtt(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1188 ppgtt
->base
.dev
= dev
;
1189 ppgtt
->base
.scratch
= dev_priv
->gtt
.base
.scratch
;
1191 if (INTEL_INFO(dev
)->gen
< 8)
1192 ret
= gen6_ppgtt_init(ppgtt
);
1193 else if (IS_GEN8(dev
))
1194 ret
= gen8_ppgtt_init(ppgtt
, dev_priv
->gtt
.base
.total
);
1199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1200 kref_init(&ppgtt
->ref
);
1201 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1203 i915_init_vm(dev_priv
, &ppgtt
->base
);
1204 if (INTEL_INFO(dev
)->gen
< 8) {
1205 gen6_write_pdes(ppgtt
);
1206 DRM_DEBUG("Adding PPGTT at offset %x\n",
1207 ppgtt
->pd_offset
<< 10);
1215 ppgtt_bind_vma(struct i915_vma
*vma
,
1216 enum i915_cache_level cache_level
,
1219 /* Currently applicable only to VLV */
1220 if (vma
->obj
->gt_ro
)
1221 flags
|= PTE_READ_ONLY
;
1223 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
1224 cache_level
, flags
);
1227 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
1229 vma
->vm
->clear_range(vma
->vm
,
1231 vma
->obj
->base
.size
,
1235 extern int intel_iommu_gfx_mapped
;
1236 /* Certain Gen5 chipsets require require idling the GPU before
1237 * unmapping anything from the GTT when VT-d is enabled.
1239 static inline bool needs_idle_maps(struct drm_device
*dev
)
1241 #ifdef CONFIG_INTEL_IOMMU
1242 /* Query intel_iommu to see if we need the workaround. Presumably that
1245 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1251 static bool do_idling(struct drm_i915_private
*dev_priv
)
1253 bool ret
= dev_priv
->mm
.interruptible
;
1255 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1256 dev_priv
->mm
.interruptible
= false;
1257 if (i915_gpu_idle(dev_priv
->dev
)) {
1258 DRM_ERROR("Couldn't idle GPU\n");
1259 /* Wait a bit, in hopes it avoids the hang */
1267 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1269 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1270 dev_priv
->mm
.interruptible
= interruptible
;
1273 void i915_check_and_clear_faults(struct drm_device
*dev
)
1275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1276 struct intel_engine_cs
*ring
;
1279 if (INTEL_INFO(dev
)->gen
< 6)
1282 for_each_ring(ring
, dev_priv
, i
) {
1284 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1285 if (fault_reg
& RING_FAULT_VALID
) {
1286 DRM_DEBUG_DRIVER("Unexpected fault\n"
1287 "\tAddr: 0x%08lx\\n"
1288 "\tAddress space: %s\n"
1291 fault_reg
& PAGE_MASK
,
1292 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1293 RING_FAULT_SRCID(fault_reg
),
1294 RING_FAULT_FAULT_TYPE(fault_reg
));
1295 I915_WRITE(RING_FAULT_REG(ring
),
1296 fault_reg
& ~RING_FAULT_VALID
);
1299 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1302 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1306 /* Don't bother messing with faults pre GEN6 as we have little
1307 * documentation supporting that it's a good idea.
1309 if (INTEL_INFO(dev
)->gen
< 6)
1312 i915_check_and_clear_faults(dev
);
1314 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1315 dev_priv
->gtt
.base
.start
,
1316 dev_priv
->gtt
.base
.total
,
1320 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
1322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1323 struct drm_i915_gem_object
*obj
;
1324 struct i915_address_space
*vm
;
1326 i915_check_and_clear_faults(dev
);
1328 /* First fill our portion of the GTT with scratch pages */
1329 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1330 dev_priv
->gtt
.base
.start
,
1331 dev_priv
->gtt
.base
.total
,
1334 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1335 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
1336 &dev_priv
->gtt
.base
);
1340 i915_gem_clflush_object(obj
, obj
->pin_display
);
1341 /* The bind_vma code tries to be smart about tracking mappings.
1342 * Unfortunately above, we've just wiped out the mappings
1343 * without telling our object about it. So we need to fake it.
1345 obj
->has_global_gtt_mapping
= 0;
1346 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
1350 if (INTEL_INFO(dev
)->gen
>= 8) {
1351 if (IS_CHERRYVIEW(dev
))
1352 chv_setup_private_ppat(dev_priv
);
1354 bdw_setup_private_ppat(dev_priv
);
1359 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
1360 /* TODO: Perhaps it shouldn't be gen6 specific */
1361 if (i915_is_ggtt(vm
)) {
1362 if (dev_priv
->mm
.aliasing_ppgtt
)
1363 gen6_write_pdes(dev_priv
->mm
.aliasing_ppgtt
);
1367 gen6_write_pdes(container_of(vm
, struct i915_hw_ppgtt
, base
));
1370 i915_gem_chipset_flush(dev
);
1373 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1375 if (obj
->has_dma_mapping
)
1378 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1379 obj
->pages
->sgl
, obj
->pages
->nents
,
1380 PCI_DMA_BIDIRECTIONAL
))
1386 static inline void gen8_set_pte(void __iomem
*addr
, gen8_gtt_pte_t pte
)
1391 iowrite32((u32
)pte
, addr
);
1392 iowrite32(pte
>> 32, addr
+ 4);
1396 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1397 struct sg_table
*st
,
1399 enum i915_cache_level level
, u32 unused
)
1401 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1402 unsigned first_entry
= start
>> PAGE_SHIFT
;
1403 gen8_gtt_pte_t __iomem
*gtt_entries
=
1404 (gen8_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1406 struct sg_page_iter sg_iter
;
1407 dma_addr_t addr
= 0; /* shut up gcc */
1409 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1410 addr
= sg_dma_address(sg_iter
.sg
) +
1411 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1412 gen8_set_pte(>t_entries
[i
],
1413 gen8_pte_encode(addr
, level
, true));
1418 * XXX: This serves as a posting read to make sure that the PTE has
1419 * actually been updated. There is some concern that even though
1420 * registers and PTEs are within the same BAR that they are potentially
1421 * of NUMA access patterns. Therefore, even with the way we assume
1422 * hardware should work, we must keep this posting read for paranoia.
1425 WARN_ON(readq(>t_entries
[i
-1])
1426 != gen8_pte_encode(addr
, level
, true));
1428 /* This next bit makes the above posting read even more important. We
1429 * want to flush the TLBs only after we're certain all the PTE updates
1432 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1433 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1437 * Binds an object into the global gtt with the specified cache level. The object
1438 * will be accessible to the GPU via commands whose operands reference offsets
1439 * within the global GTT as well as accessible by the GPU through the GMADR
1440 * mapped BAR (dev_priv->mm.gtt->gtt).
1442 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1443 struct sg_table
*st
,
1445 enum i915_cache_level level
, u32 flags
)
1447 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1448 unsigned first_entry
= start
>> PAGE_SHIFT
;
1449 gen6_gtt_pte_t __iomem
*gtt_entries
=
1450 (gen6_gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1452 struct sg_page_iter sg_iter
;
1453 dma_addr_t addr
= 0;
1455 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1456 addr
= sg_page_iter_dma_address(&sg_iter
);
1457 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1461 /* XXX: This serves as a posting read to make sure that the PTE has
1462 * actually been updated. There is some concern that even though
1463 * registers and PTEs are within the same BAR that they are potentially
1464 * of NUMA access patterns. Therefore, even with the way we assume
1465 * hardware should work, we must keep this posting read for paranoia.
1468 unsigned long gtt
= readl(>t_entries
[i
-1]);
1469 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1472 /* This next bit makes the above posting read even more important. We
1473 * want to flush the TLBs only after we're certain all the PTE updates
1476 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1477 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1480 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1485 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1486 unsigned first_entry
= start
>> PAGE_SHIFT
;
1487 unsigned num_entries
= length
>> PAGE_SHIFT
;
1488 gen8_gtt_pte_t scratch_pte
, __iomem
*gtt_base
=
1489 (gen8_gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1490 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1493 if (WARN(num_entries
> max_entries
,
1494 "First entry = %d; Num entries = %d (max=%d)\n",
1495 first_entry
, num_entries
, max_entries
))
1496 num_entries
= max_entries
;
1498 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
1501 for (i
= 0; i
< num_entries
; i
++)
1502 gen8_set_pte(>t_base
[i
], scratch_pte
);
1506 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1511 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1512 unsigned first_entry
= start
>> PAGE_SHIFT
;
1513 unsigned num_entries
= length
>> PAGE_SHIFT
;
1514 gen6_gtt_pte_t scratch_pte
, __iomem
*gtt_base
=
1515 (gen6_gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1516 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1519 if (WARN(num_entries
> max_entries
,
1520 "First entry = %d; Num entries = %d (max=%d)\n",
1521 first_entry
, num_entries
, max_entries
))
1522 num_entries
= max_entries
;
1524 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, use_scratch
, 0);
1526 for (i
= 0; i
< num_entries
; i
++)
1527 iowrite32(scratch_pte
, >t_base
[i
]);
1532 static void i915_ggtt_bind_vma(struct i915_vma
*vma
,
1533 enum i915_cache_level cache_level
,
1536 const unsigned long entry
= vma
->node
.start
>> PAGE_SHIFT
;
1537 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1538 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1540 BUG_ON(!i915_is_ggtt(vma
->vm
));
1541 intel_gtt_insert_sg_entries(vma
->obj
->pages
, entry
, flags
);
1542 vma
->obj
->has_global_gtt_mapping
= 1;
1545 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1550 unsigned first_entry
= start
>> PAGE_SHIFT
;
1551 unsigned num_entries
= length
>> PAGE_SHIFT
;
1552 intel_gtt_clear_range(first_entry
, num_entries
);
1555 static void i915_ggtt_unbind_vma(struct i915_vma
*vma
)
1557 const unsigned int first
= vma
->node
.start
>> PAGE_SHIFT
;
1558 const unsigned int size
= vma
->obj
->base
.size
>> PAGE_SHIFT
;
1560 BUG_ON(!i915_is_ggtt(vma
->vm
));
1561 vma
->obj
->has_global_gtt_mapping
= 0;
1562 intel_gtt_clear_range(first
, size
);
1565 static void ggtt_bind_vma(struct i915_vma
*vma
,
1566 enum i915_cache_level cache_level
,
1569 struct drm_device
*dev
= vma
->vm
->dev
;
1570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1571 struct drm_i915_gem_object
*obj
= vma
->obj
;
1573 /* Currently applicable only to VLV */
1575 flags
|= PTE_READ_ONLY
;
1577 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1578 * or we have a global mapping already but the cacheability flags have
1579 * changed, set the global PTEs.
1581 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1582 * instead if none of the above hold true.
1584 * NB: A global mapping should only be needed for special regions like
1585 * "gtt mappable", SNB errata, or if specified via special execbuf
1586 * flags. At all other times, the GPU will use the aliasing PPGTT.
1588 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1589 if (!obj
->has_global_gtt_mapping
||
1590 (cache_level
!= obj
->cache_level
)) {
1591 vma
->vm
->insert_entries(vma
->vm
, obj
->pages
,
1593 cache_level
, flags
);
1594 obj
->has_global_gtt_mapping
= 1;
1598 if (dev_priv
->mm
.aliasing_ppgtt
&&
1599 (!obj
->has_aliasing_ppgtt_mapping
||
1600 (cache_level
!= obj
->cache_level
))) {
1601 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1602 appgtt
->base
.insert_entries(&appgtt
->base
,
1605 cache_level
, flags
);
1606 vma
->obj
->has_aliasing_ppgtt_mapping
= 1;
1610 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1612 struct drm_device
*dev
= vma
->vm
->dev
;
1613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1614 struct drm_i915_gem_object
*obj
= vma
->obj
;
1616 if (obj
->has_global_gtt_mapping
) {
1617 vma
->vm
->clear_range(vma
->vm
,
1621 obj
->has_global_gtt_mapping
= 0;
1624 if (obj
->has_aliasing_ppgtt_mapping
) {
1625 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1626 appgtt
->base
.clear_range(&appgtt
->base
,
1630 obj
->has_aliasing_ppgtt_mapping
= 0;
1634 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1636 struct drm_device
*dev
= obj
->base
.dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1640 interruptible
= do_idling(dev_priv
);
1642 if (!obj
->has_dma_mapping
)
1643 dma_unmap_sg(&dev
->pdev
->dev
,
1644 obj
->pages
->sgl
, obj
->pages
->nents
,
1645 PCI_DMA_BIDIRECTIONAL
);
1647 undo_idling(dev_priv
, interruptible
);
1650 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1651 unsigned long color
,
1652 unsigned long *start
,
1655 if (node
->color
!= color
)
1658 if (!list_empty(&node
->node_list
)) {
1659 node
= list_entry(node
->node_list
.next
,
1662 if (node
->allocated
&& node
->color
!= color
)
1667 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
1668 unsigned long start
,
1669 unsigned long mappable_end
,
1672 /* Let GEM Manage all of the aperture.
1674 * However, leave one page at the end still bound to the scratch page.
1675 * There are a number of places where the hardware apparently prefetches
1676 * past the end of the object, and we've seen multiple hangs with the
1677 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1678 * aperture. One page should be enough to keep any prefetching inside
1681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1682 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
1683 struct drm_mm_node
*entry
;
1684 struct drm_i915_gem_object
*obj
;
1685 unsigned long hole_start
, hole_end
;
1687 BUG_ON(mappable_end
> end
);
1689 /* Subtract the guard page ... */
1690 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
1692 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
1694 /* Mark any preallocated objects as occupied */
1695 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1696 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
1698 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1699 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
1701 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
1702 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
1704 DRM_DEBUG_KMS("Reservation failed\n");
1705 obj
->has_global_gtt_mapping
= 1;
1708 dev_priv
->gtt
.base
.start
= start
;
1709 dev_priv
->gtt
.base
.total
= end
- start
;
1711 /* Clear any non-preallocated blocks */
1712 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
1713 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1714 hole_start
, hole_end
);
1715 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
1716 hole_end
- hole_start
, true);
1719 /* And finally clear the reserved guard page */
1720 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
1723 void i915_gem_init_global_gtt(struct drm_device
*dev
)
1725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1726 unsigned long gtt_size
, mappable_size
;
1728 gtt_size
= dev_priv
->gtt
.base
.total
;
1729 mappable_size
= dev_priv
->gtt
.mappable_end
;
1731 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
1734 static int setup_scratch_page(struct drm_device
*dev
)
1736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1738 dma_addr_t dma_addr
;
1740 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
1744 set_pages_uc(page
, 1);
1746 #ifdef CONFIG_INTEL_IOMMU
1747 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
1748 PCI_DMA_BIDIRECTIONAL
);
1749 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
1752 dma_addr
= page_to_phys(page
);
1754 dev_priv
->gtt
.base
.scratch
.page
= page
;
1755 dev_priv
->gtt
.base
.scratch
.addr
= dma_addr
;
1760 static void teardown_scratch_page(struct drm_device
*dev
)
1762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1763 struct page
*page
= dev_priv
->gtt
.base
.scratch
.page
;
1765 set_pages_wb(page
, 1);
1766 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.base
.scratch
.addr
,
1767 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
1772 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
1774 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
1775 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
1776 return snb_gmch_ctl
<< 20;
1779 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
1781 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
1782 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
1784 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
1786 #ifdef CONFIG_X86_32
1787 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1788 if (bdw_gmch_ctl
> 4)
1792 return bdw_gmch_ctl
<< 20;
1795 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
1797 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
1798 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
1801 return 1 << (20 + gmch_ctrl
);
1806 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
1808 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
1809 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
1810 return snb_gmch_ctl
<< 25; /* 32 MB units */
1813 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
1815 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
1816 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
1817 return bdw_gmch_ctl
<< 25; /* 32 MB units */
1820 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
1822 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
1823 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
1826 * 0x0 to 0x10: 32MB increments starting at 0MB
1827 * 0x11 to 0x16: 4MB increments starting at 8MB
1828 * 0x17 to 0x1d: 4MB increments start at 36MB
1830 if (gmch_ctrl
< 0x11)
1831 return gmch_ctrl
<< 25;
1832 else if (gmch_ctrl
< 0x17)
1833 return (gmch_ctrl
- 0x11 + 2) << 22;
1835 return (gmch_ctrl
- 0x17 + 9) << 22;
1838 static int ggtt_probe_common(struct drm_device
*dev
,
1841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1842 phys_addr_t gtt_phys_addr
;
1845 /* For Modern GENs the PTEs and register space are split in the BAR */
1846 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
1847 (pci_resource_len(dev
->pdev
, 0) / 2);
1849 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
1850 if (!dev_priv
->gtt
.gsm
) {
1851 DRM_ERROR("Failed to map the gtt page table\n");
1855 ret
= setup_scratch_page(dev
);
1857 DRM_ERROR("Scratch setup failed\n");
1858 /* iounmap will also get called at remove, but meh */
1859 iounmap(dev_priv
->gtt
.gsm
);
1865 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1866 * bits. When using advanced contexts each context stores its own PAT, but
1867 * writing this data shouldn't be harmful even in those cases. */
1868 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
1872 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
1873 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
1874 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
1875 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
1876 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
1877 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
1878 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
1879 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
1881 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1882 * write would work. */
1883 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
1884 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
1887 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
1892 * Map WB on BDW to snooped on CHV.
1894 * Only the snoop bit has meaning for CHV, the rest is
1897 * Note that the harware enforces snooping for all page
1898 * table accesses. The snoop bit is actually ignored for
1901 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
1905 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
1906 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
1907 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
1908 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
1910 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
1911 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
1914 static int gen8_gmch_probe(struct drm_device
*dev
,
1917 phys_addr_t
*mappable_base
,
1918 unsigned long *mappable_end
)
1920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1921 unsigned int gtt_size
;
1925 /* TODO: We're not aware of mappable constraints on gen8 yet */
1926 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
1927 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
1929 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
1930 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
1932 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
1934 if (IS_CHERRYVIEW(dev
)) {
1935 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
1936 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
1938 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
1939 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
1942 *gtt_total
= (gtt_size
/ sizeof(gen8_gtt_pte_t
)) << PAGE_SHIFT
;
1944 if (IS_CHERRYVIEW(dev
))
1945 chv_setup_private_ppat(dev_priv
);
1947 bdw_setup_private_ppat(dev_priv
);
1949 ret
= ggtt_probe_common(dev
, gtt_size
);
1951 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
1952 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
1957 static int gen6_gmch_probe(struct drm_device
*dev
,
1960 phys_addr_t
*mappable_base
,
1961 unsigned long *mappable_end
)
1963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1964 unsigned int gtt_size
;
1968 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
1969 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
1971 /* 64/512MB is the current min/max we actually know of, but this is just
1972 * a coarse sanity check.
1974 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
1975 DRM_ERROR("Unknown GMADR size (%lx)\n",
1976 dev_priv
->gtt
.mappable_end
);
1980 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
1981 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
1982 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
1984 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
1986 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
1987 *gtt_total
= (gtt_size
/ sizeof(gen6_gtt_pte_t
)) << PAGE_SHIFT
;
1989 ret
= ggtt_probe_common(dev
, gtt_size
);
1991 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
1992 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
1997 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2000 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2002 if (drm_mm_initialized(&vm
->mm
)) {
2003 drm_mm_takedown(&vm
->mm
);
2004 list_del(&vm
->global_link
);
2007 teardown_scratch_page(vm
->dev
);
2010 static int i915_gmch_probe(struct drm_device
*dev
,
2013 phys_addr_t
*mappable_base
,
2014 unsigned long *mappable_end
)
2016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2019 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2021 DRM_ERROR("failed to set up gmch\n");
2025 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2027 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2028 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2030 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2031 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2036 static void i915_gmch_remove(struct i915_address_space
*vm
)
2038 if (drm_mm_initialized(&vm
->mm
)) {
2039 drm_mm_takedown(&vm
->mm
);
2040 list_del(&vm
->global_link
);
2042 intel_gmch_remove();
2045 int i915_gem_gtt_init(struct drm_device
*dev
)
2047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2048 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2051 if (INTEL_INFO(dev
)->gen
<= 5) {
2052 gtt
->gtt_probe
= i915_gmch_probe
;
2053 gtt
->base
.cleanup
= i915_gmch_remove
;
2054 } else if (INTEL_INFO(dev
)->gen
< 8) {
2055 gtt
->gtt_probe
= gen6_gmch_probe
;
2056 gtt
->base
.cleanup
= gen6_gmch_remove
;
2057 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2058 gtt
->base
.pte_encode
= iris_pte_encode
;
2059 else if (IS_HASWELL(dev
))
2060 gtt
->base
.pte_encode
= hsw_pte_encode
;
2061 else if (IS_VALLEYVIEW(dev
))
2062 gtt
->base
.pte_encode
= byt_pte_encode
;
2063 else if (INTEL_INFO(dev
)->gen
>= 7)
2064 gtt
->base
.pte_encode
= ivb_pte_encode
;
2066 gtt
->base
.pte_encode
= snb_pte_encode
;
2068 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2069 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2072 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2073 >t
->mappable_base
, >t
->mappable_end
);
2077 gtt
->base
.dev
= dev
;
2079 /* GMADR is the PCI mmio aperture into the global GTT. */
2080 DRM_INFO("Memory usable by graphics device = %zdM\n",
2081 gtt
->base
.total
>> 20);
2082 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt
->mappable_end
>> 20);
2083 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2084 #ifdef CONFIG_INTEL_IOMMU
2085 if (intel_iommu_gfx_mapped
)
2086 DRM_INFO("VT-d active for gfx access\n");
2089 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2090 * user's requested state against the hardware/driver capabilities. We
2091 * do this now so that we can print out any log messages once rather
2092 * than every time we check intel_enable_ppgtt().
2094 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2095 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2100 static struct i915_vma
*__i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2101 struct i915_address_space
*vm
)
2103 struct i915_vma
*vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
2105 return ERR_PTR(-ENOMEM
);
2107 INIT_LIST_HEAD(&vma
->vma_link
);
2108 INIT_LIST_HEAD(&vma
->mm_list
);
2109 INIT_LIST_HEAD(&vma
->exec_list
);
2113 switch (INTEL_INFO(vm
->dev
)->gen
) {
2117 if (i915_is_ggtt(vm
)) {
2118 vma
->unbind_vma
= ggtt_unbind_vma
;
2119 vma
->bind_vma
= ggtt_bind_vma
;
2121 vma
->unbind_vma
= ppgtt_unbind_vma
;
2122 vma
->bind_vma
= ppgtt_bind_vma
;
2129 BUG_ON(!i915_is_ggtt(vm
));
2130 vma
->unbind_vma
= i915_ggtt_unbind_vma
;
2131 vma
->bind_vma
= i915_ggtt_bind_vma
;
2137 /* Keep GGTT vmas first to make debug easier */
2138 if (i915_is_ggtt(vm
))
2139 list_add(&vma
->vma_link
, &obj
->vma_list
);
2141 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2147 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2148 struct i915_address_space
*vm
)
2150 struct i915_vma
*vma
;
2152 vma
= i915_gem_obj_to_vma(obj
, vm
);
2154 vma
= __i915_gem_vma_create(obj
, vm
);