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drm/i915: Track file_priv, not ctx in the ppgtt structure
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
35
36 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
37 {
38 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
39 return 0;
40
41 if (enable_ppgtt == 1)
42 return 1;
43
44 if (enable_ppgtt == 2 && HAS_PPGTT(dev))
45 return 2;
46
47 #ifdef CONFIG_INTEL_IOMMU
48 /* Disable ppgtt on SNB if VT-d is on. */
49 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
50 DRM_INFO("Disabling PPGTT because VT-d is on\n");
51 return 0;
52 }
53 #endif
54
55 /* Early VLV doesn't have this */
56 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
57 dev->pdev->revision < 0xb) {
58 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
59 return 0;
60 }
61
62 return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
63 }
64
65
66 static void ppgtt_bind_vma(struct i915_vma *vma,
67 enum i915_cache_level cache_level,
68 u32 flags);
69 static void ppgtt_unbind_vma(struct i915_vma *vma);
70 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
71
72 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
73 enum i915_cache_level level,
74 bool valid)
75 {
76 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
77 pte |= addr;
78
79 switch (level) {
80 case I915_CACHE_NONE:
81 pte |= PPAT_UNCACHED_INDEX;
82 break;
83 case I915_CACHE_WT:
84 pte |= PPAT_DISPLAY_ELLC_INDEX;
85 break;
86 default:
87 pte |= PPAT_CACHED_INDEX;
88 break;
89 }
90
91 return pte;
92 }
93
94 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
95 dma_addr_t addr,
96 enum i915_cache_level level)
97 {
98 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
99 pde |= addr;
100 if (level != I915_CACHE_NONE)
101 pde |= PPAT_CACHED_PDE_INDEX;
102 else
103 pde |= PPAT_UNCACHED_INDEX;
104 return pde;
105 }
106
107 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
108 enum i915_cache_level level,
109 bool valid, u32 unused)
110 {
111 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
112 pte |= GEN6_PTE_ADDR_ENCODE(addr);
113
114 switch (level) {
115 case I915_CACHE_L3_LLC:
116 case I915_CACHE_LLC:
117 pte |= GEN6_PTE_CACHE_LLC;
118 break;
119 case I915_CACHE_NONE:
120 pte |= GEN6_PTE_UNCACHED;
121 break;
122 default:
123 WARN_ON(1);
124 }
125
126 return pte;
127 }
128
129 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
130 enum i915_cache_level level,
131 bool valid, u32 unused)
132 {
133 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
134 pte |= GEN6_PTE_ADDR_ENCODE(addr);
135
136 switch (level) {
137 case I915_CACHE_L3_LLC:
138 pte |= GEN7_PTE_CACHE_L3_LLC;
139 break;
140 case I915_CACHE_LLC:
141 pte |= GEN6_PTE_CACHE_LLC;
142 break;
143 case I915_CACHE_NONE:
144 pte |= GEN6_PTE_UNCACHED;
145 break;
146 default:
147 WARN_ON(1);
148 }
149
150 return pte;
151 }
152
153 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
154 enum i915_cache_level level,
155 bool valid, u32 flags)
156 {
157 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
158 pte |= GEN6_PTE_ADDR_ENCODE(addr);
159
160 /* Mark the page as writeable. Other platforms don't have a
161 * setting for read-only/writable, so this matches that behavior.
162 */
163 if (!(flags & PTE_READ_ONLY))
164 pte |= BYT_PTE_WRITEABLE;
165
166 if (level != I915_CACHE_NONE)
167 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
168
169 return pte;
170 }
171
172 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
173 enum i915_cache_level level,
174 bool valid, u32 unused)
175 {
176 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
177 pte |= HSW_PTE_ADDR_ENCODE(addr);
178
179 if (level != I915_CACHE_NONE)
180 pte |= HSW_WB_LLC_AGE3;
181
182 return pte;
183 }
184
185 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
186 enum i915_cache_level level,
187 bool valid, u32 unused)
188 {
189 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
190 pte |= HSW_PTE_ADDR_ENCODE(addr);
191
192 switch (level) {
193 case I915_CACHE_NONE:
194 break;
195 case I915_CACHE_WT:
196 pte |= HSW_WT_ELLC_LLC_AGE3;
197 break;
198 default:
199 pte |= HSW_WB_ELLC_LLC_AGE3;
200 break;
201 }
202
203 return pte;
204 }
205
206 /* Broadwell Page Directory Pointer Descriptors */
207 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
208 uint64_t val, bool synchronous)
209 {
210 struct drm_i915_private *dev_priv = ring->dev->dev_private;
211 int ret;
212
213 BUG_ON(entry >= 4);
214
215 if (synchronous) {
216 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
217 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
218 return 0;
219 }
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
226 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
227 intel_ring_emit(ring, (u32)(val >> 32));
228 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
229 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
230 intel_ring_emit(ring, (u32)(val));
231 intel_ring_advance(ring);
232
233 return 0;
234 }
235
236 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
237 struct intel_engine_cs *ring,
238 bool synchronous)
239 {
240 int i, ret;
241
242 /* bit of a hack to find the actual last used pd */
243 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
244
245 for (i = used_pd - 1; i >= 0; i--) {
246 dma_addr_t addr = ppgtt->pd_dma_addr[i];
247 ret = gen8_write_pdp(ring, i, addr, synchronous);
248 if (ret)
249 return ret;
250 }
251
252 return 0;
253 }
254
255 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
256 uint64_t start,
257 uint64_t length,
258 bool use_scratch)
259 {
260 struct i915_hw_ppgtt *ppgtt =
261 container_of(vm, struct i915_hw_ppgtt, base);
262 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
263 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
264 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
265 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
266 unsigned num_entries = length >> PAGE_SHIFT;
267 unsigned last_pte, i;
268
269 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
270 I915_CACHE_LLC, use_scratch);
271
272 while (num_entries) {
273 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
274
275 last_pte = pte + num_entries;
276 if (last_pte > GEN8_PTES_PER_PAGE)
277 last_pte = GEN8_PTES_PER_PAGE;
278
279 pt_vaddr = kmap_atomic(page_table);
280
281 for (i = pte; i < last_pte; i++) {
282 pt_vaddr[i] = scratch_pte;
283 num_entries--;
284 }
285
286 if (!HAS_LLC(ppgtt->base.dev))
287 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
288 kunmap_atomic(pt_vaddr);
289
290 pte = 0;
291 if (++pde == GEN8_PDES_PER_PAGE) {
292 pdpe++;
293 pde = 0;
294 }
295 }
296 }
297
298 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
299 struct sg_table *pages,
300 uint64_t start,
301 enum i915_cache_level cache_level, u32 unused)
302 {
303 struct i915_hw_ppgtt *ppgtt =
304 container_of(vm, struct i915_hw_ppgtt, base);
305 gen8_gtt_pte_t *pt_vaddr;
306 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
307 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
308 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
309 struct sg_page_iter sg_iter;
310
311 pt_vaddr = NULL;
312
313 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
314 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
315 break;
316
317 if (pt_vaddr == NULL)
318 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
319
320 pt_vaddr[pte] =
321 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
322 cache_level, true);
323 if (++pte == GEN8_PTES_PER_PAGE) {
324 if (!HAS_LLC(ppgtt->base.dev))
325 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
326 kunmap_atomic(pt_vaddr);
327 pt_vaddr = NULL;
328 if (++pde == GEN8_PDES_PER_PAGE) {
329 pdpe++;
330 pde = 0;
331 }
332 pte = 0;
333 }
334 }
335 if (pt_vaddr) {
336 if (!HAS_LLC(ppgtt->base.dev))
337 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
338 kunmap_atomic(pt_vaddr);
339 }
340 }
341
342 static void gen8_free_page_tables(struct page **pt_pages)
343 {
344 int i;
345
346 if (pt_pages == NULL)
347 return;
348
349 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
350 if (pt_pages[i])
351 __free_pages(pt_pages[i], 0);
352 }
353
354 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
355 {
356 int i;
357
358 for (i = 0; i < ppgtt->num_pd_pages; i++) {
359 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
360 kfree(ppgtt->gen8_pt_pages[i]);
361 kfree(ppgtt->gen8_pt_dma_addr[i]);
362 }
363
364 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
365 }
366
367 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
368 {
369 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
370 int i, j;
371
372 for (i = 0; i < ppgtt->num_pd_pages; i++) {
373 /* TODO: In the future we'll support sparse mappings, so this
374 * will have to change. */
375 if (!ppgtt->pd_dma_addr[i])
376 continue;
377
378 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
379 PCI_DMA_BIDIRECTIONAL);
380
381 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
382 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
383 if (addr)
384 pci_unmap_page(hwdev, addr, PAGE_SIZE,
385 PCI_DMA_BIDIRECTIONAL);
386 }
387 }
388 }
389
390 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
391 {
392 struct i915_hw_ppgtt *ppgtt =
393 container_of(vm, struct i915_hw_ppgtt, base);
394
395 list_del(&vm->global_link);
396 drm_mm_takedown(&vm->mm);
397
398 gen8_ppgtt_unmap_pages(ppgtt);
399 gen8_ppgtt_free(ppgtt);
400 }
401
402 static struct page **__gen8_alloc_page_tables(void)
403 {
404 struct page **pt_pages;
405 int i;
406
407 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
408 if (!pt_pages)
409 return ERR_PTR(-ENOMEM);
410
411 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
412 pt_pages[i] = alloc_page(GFP_KERNEL);
413 if (!pt_pages[i])
414 goto bail;
415 }
416
417 return pt_pages;
418
419 bail:
420 gen8_free_page_tables(pt_pages);
421 kfree(pt_pages);
422 return ERR_PTR(-ENOMEM);
423 }
424
425 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
426 const int max_pdp)
427 {
428 struct page **pt_pages[GEN8_LEGACY_PDPS];
429 int i, ret;
430
431 for (i = 0; i < max_pdp; i++) {
432 pt_pages[i] = __gen8_alloc_page_tables();
433 if (IS_ERR(pt_pages[i])) {
434 ret = PTR_ERR(pt_pages[i]);
435 goto unwind_out;
436 }
437 }
438
439 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
440 * "atomic" - for cleanup purposes.
441 */
442 for (i = 0; i < max_pdp; i++)
443 ppgtt->gen8_pt_pages[i] = pt_pages[i];
444
445 return 0;
446
447 unwind_out:
448 while (i--) {
449 gen8_free_page_tables(pt_pages[i]);
450 kfree(pt_pages[i]);
451 }
452
453 return ret;
454 }
455
456 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
457 {
458 int i;
459
460 for (i = 0; i < ppgtt->num_pd_pages; i++) {
461 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
462 sizeof(dma_addr_t),
463 GFP_KERNEL);
464 if (!ppgtt->gen8_pt_dma_addr[i])
465 return -ENOMEM;
466 }
467
468 return 0;
469 }
470
471 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
472 const int max_pdp)
473 {
474 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
475 if (!ppgtt->pd_pages)
476 return -ENOMEM;
477
478 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
479 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
480
481 return 0;
482 }
483
484 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
485 const int max_pdp)
486 {
487 int ret;
488
489 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
490 if (ret)
491 return ret;
492
493 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
494 if (ret) {
495 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
496 return ret;
497 }
498
499 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
500
501 ret = gen8_ppgtt_allocate_dma(ppgtt);
502 if (ret)
503 gen8_ppgtt_free(ppgtt);
504
505 return ret;
506 }
507
508 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
509 const int pd)
510 {
511 dma_addr_t pd_addr;
512 int ret;
513
514 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
515 &ppgtt->pd_pages[pd], 0,
516 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
517
518 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
519 if (ret)
520 return ret;
521
522 ppgtt->pd_dma_addr[pd] = pd_addr;
523
524 return 0;
525 }
526
527 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
528 const int pd,
529 const int pt)
530 {
531 dma_addr_t pt_addr;
532 struct page *p;
533 int ret;
534
535 p = ppgtt->gen8_pt_pages[pd][pt];
536 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
537 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
538 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
539 if (ret)
540 return ret;
541
542 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
543
544 return 0;
545 }
546
547 /**
548 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
549 * with a net effect resembling a 2-level page table in normal x86 terms. Each
550 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
551 * space.
552 *
553 * FIXME: split allocation into smaller pieces. For now we only ever do this
554 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
555 * TODO: Do something with the size parameter
556 */
557 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
558 {
559 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
560 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
561 int i, j, ret;
562
563 if (size % (1<<30))
564 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
565
566 /* 1. Do all our allocations for page directories and page tables. */
567 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
568 if (ret)
569 return ret;
570
571 /*
572 * 2. Create DMA mappings for the page directories and page tables.
573 */
574 for (i = 0; i < max_pdp; i++) {
575 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
576 if (ret)
577 goto bail;
578
579 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
580 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
581 if (ret)
582 goto bail;
583 }
584 }
585
586 /*
587 * 3. Map all the page directory entires to point to the page tables
588 * we've allocated.
589 *
590 * For now, the PPGTT helper functions all require that the PDEs are
591 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
592 * will never need to touch the PDEs again.
593 */
594 for (i = 0; i < max_pdp; i++) {
595 gen8_ppgtt_pde_t *pd_vaddr;
596 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
597 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
598 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
599 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
600 I915_CACHE_LLC);
601 }
602 if (!HAS_LLC(ppgtt->base.dev))
603 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
604 kunmap_atomic(pd_vaddr);
605 }
606
607 ppgtt->enable = gen8_ppgtt_enable;
608 ppgtt->switch_mm = gen8_mm_switch;
609 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
610 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
611 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
612 ppgtt->base.start = 0;
613 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
614
615 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
616
617 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
618 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
619 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
620 ppgtt->num_pd_entries,
621 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
622 return 0;
623
624 bail:
625 gen8_ppgtt_unmap_pages(ppgtt);
626 gen8_ppgtt_free(ppgtt);
627 return ret;
628 }
629
630 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
631 {
632 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
633 struct i915_address_space *vm = &ppgtt->base;
634 gen6_gtt_pte_t __iomem *pd_addr;
635 gen6_gtt_pte_t scratch_pte;
636 uint32_t pd_entry;
637 int pte, pde;
638
639 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
640
641 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
642 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
643
644 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
645 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
646 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
647 u32 expected;
648 gen6_gtt_pte_t *pt_vaddr;
649 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
650 pd_entry = readl(pd_addr + pde);
651 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
652
653 if (pd_entry != expected)
654 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
655 pde,
656 pd_entry,
657 expected);
658 seq_printf(m, "\tPDE: %x\n", pd_entry);
659
660 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
661 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
662 unsigned long va =
663 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
664 (pte * PAGE_SIZE);
665 int i;
666 bool found = false;
667 for (i = 0; i < 4; i++)
668 if (pt_vaddr[pte + i] != scratch_pte)
669 found = true;
670 if (!found)
671 continue;
672
673 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
674 for (i = 0; i < 4; i++) {
675 if (pt_vaddr[pte + i] != scratch_pte)
676 seq_printf(m, " %08x", pt_vaddr[pte + i]);
677 else
678 seq_puts(m, " SCRATCH ");
679 }
680 seq_puts(m, "\n");
681 }
682 kunmap_atomic(pt_vaddr);
683 }
684 }
685
686 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
687 {
688 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
689 gen6_gtt_pte_t __iomem *pd_addr;
690 uint32_t pd_entry;
691 int i;
692
693 WARN_ON(ppgtt->pd_offset & 0x3f);
694 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
695 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
696 for (i = 0; i < ppgtt->num_pd_entries; i++) {
697 dma_addr_t pt_addr;
698
699 pt_addr = ppgtt->pt_dma_addr[i];
700 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
701 pd_entry |= GEN6_PDE_VALID;
702
703 writel(pd_entry, pd_addr + i);
704 }
705 readl(pd_addr);
706 }
707
708 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
709 {
710 BUG_ON(ppgtt->pd_offset & 0x3f);
711
712 return (ppgtt->pd_offset / 64) << 16;
713 }
714
715 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
716 struct intel_engine_cs *ring,
717 bool synchronous)
718 {
719 struct drm_device *dev = ppgtt->base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 int ret;
722
723 /* If we're in reset, we can assume the GPU is sufficiently idle to
724 * manually frob these bits. Ideally we could use the ring functions,
725 * except our error handling makes it quite difficult (can't use
726 * intel_ring_begin, ring->flush, or intel_ring_advance)
727 *
728 * FIXME: We should try not to special case reset
729 */
730 if (synchronous ||
731 i915_reset_in_progress(&dev_priv->gpu_error)) {
732 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
733 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
734 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
735 POSTING_READ(RING_PP_DIR_BASE(ring));
736 return 0;
737 }
738
739 /* NB: TLBs must be flushed and invalidated before a switch */
740 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
741 if (ret)
742 return ret;
743
744 ret = intel_ring_begin(ring, 6);
745 if (ret)
746 return ret;
747
748 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
749 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
750 intel_ring_emit(ring, PP_DIR_DCLV_2G);
751 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
752 intel_ring_emit(ring, get_pd_offset(ppgtt));
753 intel_ring_emit(ring, MI_NOOP);
754 intel_ring_advance(ring);
755
756 return 0;
757 }
758
759 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
760 struct intel_engine_cs *ring,
761 bool synchronous)
762 {
763 struct drm_device *dev = ppgtt->base.dev;
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 int ret;
766
767 /* If we're in reset, we can assume the GPU is sufficiently idle to
768 * manually frob these bits. Ideally we could use the ring functions,
769 * except our error handling makes it quite difficult (can't use
770 * intel_ring_begin, ring->flush, or intel_ring_advance)
771 *
772 * FIXME: We should try not to special case reset
773 */
774 if (synchronous ||
775 i915_reset_in_progress(&dev_priv->gpu_error)) {
776 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
777 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
778 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
779 POSTING_READ(RING_PP_DIR_BASE(ring));
780 return 0;
781 }
782
783 /* NB: TLBs must be flushed and invalidated before a switch */
784 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
785 if (ret)
786 return ret;
787
788 ret = intel_ring_begin(ring, 6);
789 if (ret)
790 return ret;
791
792 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
793 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
794 intel_ring_emit(ring, PP_DIR_DCLV_2G);
795 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
796 intel_ring_emit(ring, get_pd_offset(ppgtt));
797 intel_ring_emit(ring, MI_NOOP);
798 intel_ring_advance(ring);
799
800 /* XXX: RCS is the only one to auto invalidate the TLBs? */
801 if (ring->id != RCS) {
802 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
803 if (ret)
804 return ret;
805 }
806
807 return 0;
808 }
809
810 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
811 struct intel_engine_cs *ring,
812 bool synchronous)
813 {
814 struct drm_device *dev = ppgtt->base.dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816
817 if (!synchronous)
818 return 0;
819
820 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
821 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
822
823 POSTING_READ(RING_PP_DIR_DCLV(ring));
824
825 return 0;
826 }
827
828 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
829 {
830 struct drm_device *dev = ppgtt->base.dev;
831 struct drm_i915_private *dev_priv = dev->dev_private;
832 struct intel_engine_cs *ring;
833 int j, ret;
834
835 for_each_ring(ring, dev_priv, j) {
836 I915_WRITE(RING_MODE_GEN7(ring),
837 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
838
839 /* We promise to do a switch later with FULL PPGTT. If this is
840 * aliasing, this is the one and only switch we'll do */
841 if (USES_FULL_PPGTT(dev))
842 continue;
843
844 ret = ppgtt->switch_mm(ppgtt, ring, true);
845 if (ret)
846 goto err_out;
847 }
848
849 return 0;
850
851 err_out:
852 for_each_ring(ring, dev_priv, j)
853 I915_WRITE(RING_MODE_GEN7(ring),
854 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
855 return ret;
856 }
857
858 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
859 {
860 struct drm_device *dev = ppgtt->base.dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 struct intel_engine_cs *ring;
863 uint32_t ecochk, ecobits;
864 int i;
865
866 ecobits = I915_READ(GAC_ECO_BITS);
867 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
868
869 ecochk = I915_READ(GAM_ECOCHK);
870 if (IS_HASWELL(dev)) {
871 ecochk |= ECOCHK_PPGTT_WB_HSW;
872 } else {
873 ecochk |= ECOCHK_PPGTT_LLC_IVB;
874 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
875 }
876 I915_WRITE(GAM_ECOCHK, ecochk);
877
878 for_each_ring(ring, dev_priv, i) {
879 int ret;
880 /* GFX_MODE is per-ring on gen7+ */
881 I915_WRITE(RING_MODE_GEN7(ring),
882 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
883
884 /* We promise to do a switch later with FULL PPGTT. If this is
885 * aliasing, this is the one and only switch we'll do */
886 if (USES_FULL_PPGTT(dev))
887 continue;
888
889 ret = ppgtt->switch_mm(ppgtt, ring, true);
890 if (ret)
891 return ret;
892 }
893
894 return 0;
895 }
896
897 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
898 {
899 struct drm_device *dev = ppgtt->base.dev;
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 struct intel_engine_cs *ring;
902 uint32_t ecochk, gab_ctl, ecobits;
903 int i;
904
905 ecobits = I915_READ(GAC_ECO_BITS);
906 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
907 ECOBITS_PPGTT_CACHE64B);
908
909 gab_ctl = I915_READ(GAB_CTL);
910 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
911
912 ecochk = I915_READ(GAM_ECOCHK);
913 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
914
915 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
916
917 for_each_ring(ring, dev_priv, i) {
918 int ret = ppgtt->switch_mm(ppgtt, ring, true);
919 if (ret)
920 return ret;
921 }
922
923 return 0;
924 }
925
926 /* PPGTT support for Sandybdrige/Gen6 and later */
927 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
928 uint64_t start,
929 uint64_t length,
930 bool use_scratch)
931 {
932 struct i915_hw_ppgtt *ppgtt =
933 container_of(vm, struct i915_hw_ppgtt, base);
934 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
935 unsigned first_entry = start >> PAGE_SHIFT;
936 unsigned num_entries = length >> PAGE_SHIFT;
937 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
938 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
939 unsigned last_pte, i;
940
941 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
942
943 while (num_entries) {
944 last_pte = first_pte + num_entries;
945 if (last_pte > I915_PPGTT_PT_ENTRIES)
946 last_pte = I915_PPGTT_PT_ENTRIES;
947
948 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
949
950 for (i = first_pte; i < last_pte; i++)
951 pt_vaddr[i] = scratch_pte;
952
953 kunmap_atomic(pt_vaddr);
954
955 num_entries -= last_pte - first_pte;
956 first_pte = 0;
957 act_pt++;
958 }
959 }
960
961 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
962 struct sg_table *pages,
963 uint64_t start,
964 enum i915_cache_level cache_level, u32 flags)
965 {
966 struct i915_hw_ppgtt *ppgtt =
967 container_of(vm, struct i915_hw_ppgtt, base);
968 gen6_gtt_pte_t *pt_vaddr;
969 unsigned first_entry = start >> PAGE_SHIFT;
970 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
971 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
972 struct sg_page_iter sg_iter;
973
974 pt_vaddr = NULL;
975 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
976 if (pt_vaddr == NULL)
977 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
978
979 pt_vaddr[act_pte] =
980 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
981 cache_level, true, flags);
982
983 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
984 kunmap_atomic(pt_vaddr);
985 pt_vaddr = NULL;
986 act_pt++;
987 act_pte = 0;
988 }
989 }
990 if (pt_vaddr)
991 kunmap_atomic(pt_vaddr);
992 }
993
994 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
995 {
996 int i;
997
998 if (ppgtt->pt_dma_addr) {
999 for (i = 0; i < ppgtt->num_pd_entries; i++)
1000 pci_unmap_page(ppgtt->base.dev->pdev,
1001 ppgtt->pt_dma_addr[i],
1002 4096, PCI_DMA_BIDIRECTIONAL);
1003 }
1004 }
1005
1006 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1007 {
1008 int i;
1009
1010 kfree(ppgtt->pt_dma_addr);
1011 for (i = 0; i < ppgtt->num_pd_entries; i++)
1012 __free_page(ppgtt->pt_pages[i]);
1013 kfree(ppgtt->pt_pages);
1014 }
1015
1016 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1017 {
1018 struct i915_hw_ppgtt *ppgtt =
1019 container_of(vm, struct i915_hw_ppgtt, base);
1020
1021 list_del(&vm->global_link);
1022 drm_mm_takedown(&ppgtt->base.mm);
1023 drm_mm_remove_node(&ppgtt->node);
1024
1025 gen6_ppgtt_unmap_pages(ppgtt);
1026 gen6_ppgtt_free(ppgtt);
1027 }
1028
1029 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1030 {
1031 struct drm_device *dev = ppgtt->base.dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 bool retried = false;
1034 int ret;
1035
1036 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1037 * allocator works in address space sizes, so it's multiplied by page
1038 * size. We allocate at the top of the GTT to avoid fragmentation.
1039 */
1040 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1041 alloc:
1042 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1043 &ppgtt->node, GEN6_PD_SIZE,
1044 GEN6_PD_ALIGN, 0,
1045 0, dev_priv->gtt.base.total,
1046 DRM_MM_TOPDOWN);
1047 if (ret == -ENOSPC && !retried) {
1048 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1049 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1050 I915_CACHE_NONE,
1051 0, dev_priv->gtt.base.total,
1052 0);
1053 if (ret)
1054 return ret;
1055
1056 retried = true;
1057 goto alloc;
1058 }
1059
1060 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1061 DRM_DEBUG("Forced to use aperture for PDEs\n");
1062
1063 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1064 return ret;
1065 }
1066
1067 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1068 {
1069 int i;
1070
1071 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1072 GFP_KERNEL);
1073
1074 if (!ppgtt->pt_pages)
1075 return -ENOMEM;
1076
1077 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1078 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1079 if (!ppgtt->pt_pages[i]) {
1080 gen6_ppgtt_free(ppgtt);
1081 return -ENOMEM;
1082 }
1083 }
1084
1085 return 0;
1086 }
1087
1088 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1089 {
1090 int ret;
1091
1092 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1093 if (ret)
1094 return ret;
1095
1096 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1097 if (ret) {
1098 drm_mm_remove_node(&ppgtt->node);
1099 return ret;
1100 }
1101
1102 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1103 GFP_KERNEL);
1104 if (!ppgtt->pt_dma_addr) {
1105 drm_mm_remove_node(&ppgtt->node);
1106 gen6_ppgtt_free(ppgtt);
1107 return -ENOMEM;
1108 }
1109
1110 return 0;
1111 }
1112
1113 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1114 {
1115 struct drm_device *dev = ppgtt->base.dev;
1116 int i;
1117
1118 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1119 dma_addr_t pt_addr;
1120
1121 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1122 PCI_DMA_BIDIRECTIONAL);
1123
1124 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1125 gen6_ppgtt_unmap_pages(ppgtt);
1126 return -EIO;
1127 }
1128
1129 ppgtt->pt_dma_addr[i] = pt_addr;
1130 }
1131
1132 return 0;
1133 }
1134
1135 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1136 {
1137 struct drm_device *dev = ppgtt->base.dev;
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139 int ret;
1140
1141 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1142 if (IS_GEN6(dev)) {
1143 ppgtt->enable = gen6_ppgtt_enable;
1144 ppgtt->switch_mm = gen6_mm_switch;
1145 } else if (IS_HASWELL(dev)) {
1146 ppgtt->enable = gen7_ppgtt_enable;
1147 ppgtt->switch_mm = hsw_mm_switch;
1148 } else if (IS_GEN7(dev)) {
1149 ppgtt->enable = gen7_ppgtt_enable;
1150 ppgtt->switch_mm = gen7_mm_switch;
1151 } else
1152 BUG();
1153
1154 ret = gen6_ppgtt_alloc(ppgtt);
1155 if (ret)
1156 return ret;
1157
1158 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1159 if (ret) {
1160 gen6_ppgtt_free(ppgtt);
1161 return ret;
1162 }
1163
1164 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1165 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1166 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1167 ppgtt->base.start = 0;
1168 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1169 ppgtt->debug_dump = gen6_dump_ppgtt;
1170
1171 ppgtt->pd_offset =
1172 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1173
1174 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1175
1176 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1177 ppgtt->node.size >> 20,
1178 ppgtt->node.start / PAGE_SIZE);
1179
1180 return 0;
1181 }
1182
1183 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1184 {
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 int ret = 0;
1187
1188 ppgtt->base.dev = dev;
1189 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1190
1191 if (INTEL_INFO(dev)->gen < 8)
1192 ret = gen6_ppgtt_init(ppgtt);
1193 else if (IS_GEN8(dev))
1194 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1195 else
1196 BUG();
1197
1198 if (!ret) {
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 kref_init(&ppgtt->ref);
1201 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1202 ppgtt->base.total);
1203 i915_init_vm(dev_priv, &ppgtt->base);
1204 if (INTEL_INFO(dev)->gen < 8) {
1205 gen6_write_pdes(ppgtt);
1206 DRM_DEBUG("Adding PPGTT at offset %x\n",
1207 ppgtt->pd_offset << 10);
1208 }
1209 }
1210
1211 return ret;
1212 }
1213
1214 struct i915_hw_ppgtt *
1215 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1216 {
1217 struct i915_hw_ppgtt *ppgtt;
1218 int ret;
1219
1220 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1221 if (!ppgtt)
1222 return ERR_PTR(-ENOMEM);
1223
1224 ret = i915_ppgtt_init(dev, ppgtt);
1225 if (ret) {
1226 kfree(ppgtt);
1227 return ERR_PTR(ret);
1228 }
1229
1230 ppgtt->file_priv = fpriv;
1231
1232 return ppgtt;
1233 }
1234
1235 void i915_ppgtt_release(struct kref *kref)
1236 {
1237 struct i915_hw_ppgtt *ppgtt =
1238 container_of(kref, struct i915_hw_ppgtt, ref);
1239
1240 /* vmas should already be unbound */
1241 WARN_ON(!list_empty(&ppgtt->base.active_list));
1242 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1243
1244 ppgtt->base.cleanup(&ppgtt->base);
1245 kfree(ppgtt);
1246 }
1247
1248 static void
1249 ppgtt_bind_vma(struct i915_vma *vma,
1250 enum i915_cache_level cache_level,
1251 u32 flags)
1252 {
1253 /* Currently applicable only to VLV */
1254 if (vma->obj->gt_ro)
1255 flags |= PTE_READ_ONLY;
1256
1257 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1258 cache_level, flags);
1259 }
1260
1261 static void ppgtt_unbind_vma(struct i915_vma *vma)
1262 {
1263 vma->vm->clear_range(vma->vm,
1264 vma->node.start,
1265 vma->obj->base.size,
1266 true);
1267 }
1268
1269 extern int intel_iommu_gfx_mapped;
1270 /* Certain Gen5 chipsets require require idling the GPU before
1271 * unmapping anything from the GTT when VT-d is enabled.
1272 */
1273 static inline bool needs_idle_maps(struct drm_device *dev)
1274 {
1275 #ifdef CONFIG_INTEL_IOMMU
1276 /* Query intel_iommu to see if we need the workaround. Presumably that
1277 * was loaded first.
1278 */
1279 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1280 return true;
1281 #endif
1282 return false;
1283 }
1284
1285 static bool do_idling(struct drm_i915_private *dev_priv)
1286 {
1287 bool ret = dev_priv->mm.interruptible;
1288
1289 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1290 dev_priv->mm.interruptible = false;
1291 if (i915_gpu_idle(dev_priv->dev)) {
1292 DRM_ERROR("Couldn't idle GPU\n");
1293 /* Wait a bit, in hopes it avoids the hang */
1294 udelay(10);
1295 }
1296 }
1297
1298 return ret;
1299 }
1300
1301 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1302 {
1303 if (unlikely(dev_priv->gtt.do_idle_maps))
1304 dev_priv->mm.interruptible = interruptible;
1305 }
1306
1307 void i915_check_and_clear_faults(struct drm_device *dev)
1308 {
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 struct intel_engine_cs *ring;
1311 int i;
1312
1313 if (INTEL_INFO(dev)->gen < 6)
1314 return;
1315
1316 for_each_ring(ring, dev_priv, i) {
1317 u32 fault_reg;
1318 fault_reg = I915_READ(RING_FAULT_REG(ring));
1319 if (fault_reg & RING_FAULT_VALID) {
1320 DRM_DEBUG_DRIVER("Unexpected fault\n"
1321 "\tAddr: 0x%08lx\\n"
1322 "\tAddress space: %s\n"
1323 "\tSource ID: %d\n"
1324 "\tType: %d\n",
1325 fault_reg & PAGE_MASK,
1326 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1327 RING_FAULT_SRCID(fault_reg),
1328 RING_FAULT_FAULT_TYPE(fault_reg));
1329 I915_WRITE(RING_FAULT_REG(ring),
1330 fault_reg & ~RING_FAULT_VALID);
1331 }
1332 }
1333 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1334 }
1335
1336 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1337 {
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339
1340 /* Don't bother messing with faults pre GEN6 as we have little
1341 * documentation supporting that it's a good idea.
1342 */
1343 if (INTEL_INFO(dev)->gen < 6)
1344 return;
1345
1346 i915_check_and_clear_faults(dev);
1347
1348 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1349 dev_priv->gtt.base.start,
1350 dev_priv->gtt.base.total,
1351 true);
1352 }
1353
1354 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1355 {
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 struct drm_i915_gem_object *obj;
1358 struct i915_address_space *vm;
1359
1360 i915_check_and_clear_faults(dev);
1361
1362 /* First fill our portion of the GTT with scratch pages */
1363 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1364 dev_priv->gtt.base.start,
1365 dev_priv->gtt.base.total,
1366 true);
1367
1368 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1369 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1370 &dev_priv->gtt.base);
1371 if (!vma)
1372 continue;
1373
1374 i915_gem_clflush_object(obj, obj->pin_display);
1375 /* The bind_vma code tries to be smart about tracking mappings.
1376 * Unfortunately above, we've just wiped out the mappings
1377 * without telling our object about it. So we need to fake it.
1378 */
1379 obj->has_global_gtt_mapping = 0;
1380 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1381 }
1382
1383
1384 if (INTEL_INFO(dev)->gen >= 8) {
1385 if (IS_CHERRYVIEW(dev))
1386 chv_setup_private_ppat(dev_priv);
1387 else
1388 bdw_setup_private_ppat(dev_priv);
1389
1390 return;
1391 }
1392
1393 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1394 /* TODO: Perhaps it shouldn't be gen6 specific */
1395 if (i915_is_ggtt(vm)) {
1396 if (dev_priv->mm.aliasing_ppgtt)
1397 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1398 continue;
1399 }
1400
1401 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1402 }
1403
1404 i915_gem_chipset_flush(dev);
1405 }
1406
1407 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1408 {
1409 if (obj->has_dma_mapping)
1410 return 0;
1411
1412 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1413 obj->pages->sgl, obj->pages->nents,
1414 PCI_DMA_BIDIRECTIONAL))
1415 return -ENOSPC;
1416
1417 return 0;
1418 }
1419
1420 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1421 {
1422 #ifdef writeq
1423 writeq(pte, addr);
1424 #else
1425 iowrite32((u32)pte, addr);
1426 iowrite32(pte >> 32, addr + 4);
1427 #endif
1428 }
1429
1430 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1431 struct sg_table *st,
1432 uint64_t start,
1433 enum i915_cache_level level, u32 unused)
1434 {
1435 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1436 unsigned first_entry = start >> PAGE_SHIFT;
1437 gen8_gtt_pte_t __iomem *gtt_entries =
1438 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1439 int i = 0;
1440 struct sg_page_iter sg_iter;
1441 dma_addr_t addr = 0; /* shut up gcc */
1442
1443 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1444 addr = sg_dma_address(sg_iter.sg) +
1445 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1446 gen8_set_pte(&gtt_entries[i],
1447 gen8_pte_encode(addr, level, true));
1448 i++;
1449 }
1450
1451 /*
1452 * XXX: This serves as a posting read to make sure that the PTE has
1453 * actually been updated. There is some concern that even though
1454 * registers and PTEs are within the same BAR that they are potentially
1455 * of NUMA access patterns. Therefore, even with the way we assume
1456 * hardware should work, we must keep this posting read for paranoia.
1457 */
1458 if (i != 0)
1459 WARN_ON(readq(&gtt_entries[i-1])
1460 != gen8_pte_encode(addr, level, true));
1461
1462 /* This next bit makes the above posting read even more important. We
1463 * want to flush the TLBs only after we're certain all the PTE updates
1464 * have finished.
1465 */
1466 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1467 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1468 }
1469
1470 /*
1471 * Binds an object into the global gtt with the specified cache level. The object
1472 * will be accessible to the GPU via commands whose operands reference offsets
1473 * within the global GTT as well as accessible by the GPU through the GMADR
1474 * mapped BAR (dev_priv->mm.gtt->gtt).
1475 */
1476 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1477 struct sg_table *st,
1478 uint64_t start,
1479 enum i915_cache_level level, u32 flags)
1480 {
1481 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1482 unsigned first_entry = start >> PAGE_SHIFT;
1483 gen6_gtt_pte_t __iomem *gtt_entries =
1484 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1485 int i = 0;
1486 struct sg_page_iter sg_iter;
1487 dma_addr_t addr = 0;
1488
1489 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1490 addr = sg_page_iter_dma_address(&sg_iter);
1491 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1492 i++;
1493 }
1494
1495 /* XXX: This serves as a posting read to make sure that the PTE has
1496 * actually been updated. There is some concern that even though
1497 * registers and PTEs are within the same BAR that they are potentially
1498 * of NUMA access patterns. Therefore, even with the way we assume
1499 * hardware should work, we must keep this posting read for paranoia.
1500 */
1501 if (i != 0) {
1502 unsigned long gtt = readl(&gtt_entries[i-1]);
1503 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1504 }
1505
1506 /* This next bit makes the above posting read even more important. We
1507 * want to flush the TLBs only after we're certain all the PTE updates
1508 * have finished.
1509 */
1510 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1511 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1512 }
1513
1514 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1515 uint64_t start,
1516 uint64_t length,
1517 bool use_scratch)
1518 {
1519 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1520 unsigned first_entry = start >> PAGE_SHIFT;
1521 unsigned num_entries = length >> PAGE_SHIFT;
1522 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1523 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1524 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1525 int i;
1526
1527 if (WARN(num_entries > max_entries,
1528 "First entry = %d; Num entries = %d (max=%d)\n",
1529 first_entry, num_entries, max_entries))
1530 num_entries = max_entries;
1531
1532 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1533 I915_CACHE_LLC,
1534 use_scratch);
1535 for (i = 0; i < num_entries; i++)
1536 gen8_set_pte(&gtt_base[i], scratch_pte);
1537 readl(gtt_base);
1538 }
1539
1540 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1541 uint64_t start,
1542 uint64_t length,
1543 bool use_scratch)
1544 {
1545 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1546 unsigned first_entry = start >> PAGE_SHIFT;
1547 unsigned num_entries = length >> PAGE_SHIFT;
1548 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1549 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1550 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1551 int i;
1552
1553 if (WARN(num_entries > max_entries,
1554 "First entry = %d; Num entries = %d (max=%d)\n",
1555 first_entry, num_entries, max_entries))
1556 num_entries = max_entries;
1557
1558 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1559
1560 for (i = 0; i < num_entries; i++)
1561 iowrite32(scratch_pte, &gtt_base[i]);
1562 readl(gtt_base);
1563 }
1564
1565
1566 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1567 enum i915_cache_level cache_level,
1568 u32 unused)
1569 {
1570 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1571 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1572 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1573
1574 BUG_ON(!i915_is_ggtt(vma->vm));
1575 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1576 vma->obj->has_global_gtt_mapping = 1;
1577 }
1578
1579 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1580 uint64_t start,
1581 uint64_t length,
1582 bool unused)
1583 {
1584 unsigned first_entry = start >> PAGE_SHIFT;
1585 unsigned num_entries = length >> PAGE_SHIFT;
1586 intel_gtt_clear_range(first_entry, num_entries);
1587 }
1588
1589 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1590 {
1591 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1592 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1593
1594 BUG_ON(!i915_is_ggtt(vma->vm));
1595 vma->obj->has_global_gtt_mapping = 0;
1596 intel_gtt_clear_range(first, size);
1597 }
1598
1599 static void ggtt_bind_vma(struct i915_vma *vma,
1600 enum i915_cache_level cache_level,
1601 u32 flags)
1602 {
1603 struct drm_device *dev = vma->vm->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_i915_gem_object *obj = vma->obj;
1606
1607 /* Currently applicable only to VLV */
1608 if (obj->gt_ro)
1609 flags |= PTE_READ_ONLY;
1610
1611 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1612 * or we have a global mapping already but the cacheability flags have
1613 * changed, set the global PTEs.
1614 *
1615 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1616 * instead if none of the above hold true.
1617 *
1618 * NB: A global mapping should only be needed for special regions like
1619 * "gtt mappable", SNB errata, or if specified via special execbuf
1620 * flags. At all other times, the GPU will use the aliasing PPGTT.
1621 */
1622 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1623 if (!obj->has_global_gtt_mapping ||
1624 (cache_level != obj->cache_level)) {
1625 vma->vm->insert_entries(vma->vm, obj->pages,
1626 vma->node.start,
1627 cache_level, flags);
1628 obj->has_global_gtt_mapping = 1;
1629 }
1630 }
1631
1632 if (dev_priv->mm.aliasing_ppgtt &&
1633 (!obj->has_aliasing_ppgtt_mapping ||
1634 (cache_level != obj->cache_level))) {
1635 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1636 appgtt->base.insert_entries(&appgtt->base,
1637 vma->obj->pages,
1638 vma->node.start,
1639 cache_level, flags);
1640 vma->obj->has_aliasing_ppgtt_mapping = 1;
1641 }
1642 }
1643
1644 static void ggtt_unbind_vma(struct i915_vma *vma)
1645 {
1646 struct drm_device *dev = vma->vm->dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 struct drm_i915_gem_object *obj = vma->obj;
1649
1650 if (obj->has_global_gtt_mapping) {
1651 vma->vm->clear_range(vma->vm,
1652 vma->node.start,
1653 obj->base.size,
1654 true);
1655 obj->has_global_gtt_mapping = 0;
1656 }
1657
1658 if (obj->has_aliasing_ppgtt_mapping) {
1659 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1660 appgtt->base.clear_range(&appgtt->base,
1661 vma->node.start,
1662 obj->base.size,
1663 true);
1664 obj->has_aliasing_ppgtt_mapping = 0;
1665 }
1666 }
1667
1668 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1669 {
1670 struct drm_device *dev = obj->base.dev;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 bool interruptible;
1673
1674 interruptible = do_idling(dev_priv);
1675
1676 if (!obj->has_dma_mapping)
1677 dma_unmap_sg(&dev->pdev->dev,
1678 obj->pages->sgl, obj->pages->nents,
1679 PCI_DMA_BIDIRECTIONAL);
1680
1681 undo_idling(dev_priv, interruptible);
1682 }
1683
1684 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1685 unsigned long color,
1686 unsigned long *start,
1687 unsigned long *end)
1688 {
1689 if (node->color != color)
1690 *start += 4096;
1691
1692 if (!list_empty(&node->node_list)) {
1693 node = list_entry(node->node_list.next,
1694 struct drm_mm_node,
1695 node_list);
1696 if (node->allocated && node->color != color)
1697 *end -= 4096;
1698 }
1699 }
1700
1701 void i915_gem_setup_global_gtt(struct drm_device *dev,
1702 unsigned long start,
1703 unsigned long mappable_end,
1704 unsigned long end)
1705 {
1706 /* Let GEM Manage all of the aperture.
1707 *
1708 * However, leave one page at the end still bound to the scratch page.
1709 * There are a number of places where the hardware apparently prefetches
1710 * past the end of the object, and we've seen multiple hangs with the
1711 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1712 * aperture. One page should be enough to keep any prefetching inside
1713 * of the aperture.
1714 */
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1717 struct drm_mm_node *entry;
1718 struct drm_i915_gem_object *obj;
1719 unsigned long hole_start, hole_end;
1720
1721 BUG_ON(mappable_end > end);
1722
1723 /* Subtract the guard page ... */
1724 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1725 if (!HAS_LLC(dev))
1726 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1727
1728 /* Mark any preallocated objects as occupied */
1729 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1730 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1731 int ret;
1732 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1733 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1734
1735 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1736 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1737 if (ret)
1738 DRM_DEBUG_KMS("Reservation failed\n");
1739 obj->has_global_gtt_mapping = 1;
1740 }
1741
1742 dev_priv->gtt.base.start = start;
1743 dev_priv->gtt.base.total = end - start;
1744
1745 /* Clear any non-preallocated blocks */
1746 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1747 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1748 hole_start, hole_end);
1749 ggtt_vm->clear_range(ggtt_vm, hole_start,
1750 hole_end - hole_start, true);
1751 }
1752
1753 /* And finally clear the reserved guard page */
1754 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1755 }
1756
1757 void i915_gem_init_global_gtt(struct drm_device *dev)
1758 {
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 unsigned long gtt_size, mappable_size;
1761
1762 gtt_size = dev_priv->gtt.base.total;
1763 mappable_size = dev_priv->gtt.mappable_end;
1764
1765 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1766 }
1767
1768 static int setup_scratch_page(struct drm_device *dev)
1769 {
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 struct page *page;
1772 dma_addr_t dma_addr;
1773
1774 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1775 if (page == NULL)
1776 return -ENOMEM;
1777 get_page(page);
1778 set_pages_uc(page, 1);
1779
1780 #ifdef CONFIG_INTEL_IOMMU
1781 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1782 PCI_DMA_BIDIRECTIONAL);
1783 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1784 return -EINVAL;
1785 #else
1786 dma_addr = page_to_phys(page);
1787 #endif
1788 dev_priv->gtt.base.scratch.page = page;
1789 dev_priv->gtt.base.scratch.addr = dma_addr;
1790
1791 return 0;
1792 }
1793
1794 static void teardown_scratch_page(struct drm_device *dev)
1795 {
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 struct page *page = dev_priv->gtt.base.scratch.page;
1798
1799 set_pages_wb(page, 1);
1800 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1801 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1802 put_page(page);
1803 __free_page(page);
1804 }
1805
1806 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1807 {
1808 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1809 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1810 return snb_gmch_ctl << 20;
1811 }
1812
1813 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1814 {
1815 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1816 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1817 if (bdw_gmch_ctl)
1818 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1819
1820 #ifdef CONFIG_X86_32
1821 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1822 if (bdw_gmch_ctl > 4)
1823 bdw_gmch_ctl = 4;
1824 #endif
1825
1826 return bdw_gmch_ctl << 20;
1827 }
1828
1829 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1830 {
1831 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1832 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1833
1834 if (gmch_ctrl)
1835 return 1 << (20 + gmch_ctrl);
1836
1837 return 0;
1838 }
1839
1840 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1841 {
1842 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1843 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1844 return snb_gmch_ctl << 25; /* 32 MB units */
1845 }
1846
1847 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1848 {
1849 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1850 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1851 return bdw_gmch_ctl << 25; /* 32 MB units */
1852 }
1853
1854 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1855 {
1856 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1857 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1858
1859 /*
1860 * 0x0 to 0x10: 32MB increments starting at 0MB
1861 * 0x11 to 0x16: 4MB increments starting at 8MB
1862 * 0x17 to 0x1d: 4MB increments start at 36MB
1863 */
1864 if (gmch_ctrl < 0x11)
1865 return gmch_ctrl << 25;
1866 else if (gmch_ctrl < 0x17)
1867 return (gmch_ctrl - 0x11 + 2) << 22;
1868 else
1869 return (gmch_ctrl - 0x17 + 9) << 22;
1870 }
1871
1872 static int ggtt_probe_common(struct drm_device *dev,
1873 size_t gtt_size)
1874 {
1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876 phys_addr_t gtt_phys_addr;
1877 int ret;
1878
1879 /* For Modern GENs the PTEs and register space are split in the BAR */
1880 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1881 (pci_resource_len(dev->pdev, 0) / 2);
1882
1883 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1884 if (!dev_priv->gtt.gsm) {
1885 DRM_ERROR("Failed to map the gtt page table\n");
1886 return -ENOMEM;
1887 }
1888
1889 ret = setup_scratch_page(dev);
1890 if (ret) {
1891 DRM_ERROR("Scratch setup failed\n");
1892 /* iounmap will also get called at remove, but meh */
1893 iounmap(dev_priv->gtt.gsm);
1894 }
1895
1896 return ret;
1897 }
1898
1899 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1900 * bits. When using advanced contexts each context stores its own PAT, but
1901 * writing this data shouldn't be harmful even in those cases. */
1902 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1903 {
1904 uint64_t pat;
1905
1906 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1907 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1908 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1909 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1910 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1911 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1912 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1913 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1914
1915 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1916 * write would work. */
1917 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1918 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1919 }
1920
1921 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1922 {
1923 uint64_t pat;
1924
1925 /*
1926 * Map WB on BDW to snooped on CHV.
1927 *
1928 * Only the snoop bit has meaning for CHV, the rest is
1929 * ignored.
1930 *
1931 * Note that the harware enforces snooping for all page
1932 * table accesses. The snoop bit is actually ignored for
1933 * PDEs.
1934 */
1935 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1936 GEN8_PPAT(1, 0) |
1937 GEN8_PPAT(2, 0) |
1938 GEN8_PPAT(3, 0) |
1939 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1940 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1941 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1942 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1943
1944 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1945 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1946 }
1947
1948 static int gen8_gmch_probe(struct drm_device *dev,
1949 size_t *gtt_total,
1950 size_t *stolen,
1951 phys_addr_t *mappable_base,
1952 unsigned long *mappable_end)
1953 {
1954 struct drm_i915_private *dev_priv = dev->dev_private;
1955 unsigned int gtt_size;
1956 u16 snb_gmch_ctl;
1957 int ret;
1958
1959 /* TODO: We're not aware of mappable constraints on gen8 yet */
1960 *mappable_base = pci_resource_start(dev->pdev, 2);
1961 *mappable_end = pci_resource_len(dev->pdev, 2);
1962
1963 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1964 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1965
1966 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1967
1968 if (IS_CHERRYVIEW(dev)) {
1969 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1970 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1971 } else {
1972 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1973 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1974 }
1975
1976 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1977
1978 if (IS_CHERRYVIEW(dev))
1979 chv_setup_private_ppat(dev_priv);
1980 else
1981 bdw_setup_private_ppat(dev_priv);
1982
1983 ret = ggtt_probe_common(dev, gtt_size);
1984
1985 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1986 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1987
1988 return ret;
1989 }
1990
1991 static int gen6_gmch_probe(struct drm_device *dev,
1992 size_t *gtt_total,
1993 size_t *stolen,
1994 phys_addr_t *mappable_base,
1995 unsigned long *mappable_end)
1996 {
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 unsigned int gtt_size;
1999 u16 snb_gmch_ctl;
2000 int ret;
2001
2002 *mappable_base = pci_resource_start(dev->pdev, 2);
2003 *mappable_end = pci_resource_len(dev->pdev, 2);
2004
2005 /* 64/512MB is the current min/max we actually know of, but this is just
2006 * a coarse sanity check.
2007 */
2008 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2009 DRM_ERROR("Unknown GMADR size (%lx)\n",
2010 dev_priv->gtt.mappable_end);
2011 return -ENXIO;
2012 }
2013
2014 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2015 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2016 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2017
2018 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2019
2020 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2021 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2022
2023 ret = ggtt_probe_common(dev, gtt_size);
2024
2025 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2026 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2027
2028 return ret;
2029 }
2030
2031 static void gen6_gmch_remove(struct i915_address_space *vm)
2032 {
2033
2034 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2035
2036 if (drm_mm_initialized(&vm->mm)) {
2037 drm_mm_takedown(&vm->mm);
2038 list_del(&vm->global_link);
2039 }
2040 iounmap(gtt->gsm);
2041 teardown_scratch_page(vm->dev);
2042 }
2043
2044 static int i915_gmch_probe(struct drm_device *dev,
2045 size_t *gtt_total,
2046 size_t *stolen,
2047 phys_addr_t *mappable_base,
2048 unsigned long *mappable_end)
2049 {
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 int ret;
2052
2053 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2054 if (!ret) {
2055 DRM_ERROR("failed to set up gmch\n");
2056 return -EIO;
2057 }
2058
2059 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2060
2061 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2062 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2063
2064 if (unlikely(dev_priv->gtt.do_idle_maps))
2065 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2066
2067 return 0;
2068 }
2069
2070 static void i915_gmch_remove(struct i915_address_space *vm)
2071 {
2072 if (drm_mm_initialized(&vm->mm)) {
2073 drm_mm_takedown(&vm->mm);
2074 list_del(&vm->global_link);
2075 }
2076 intel_gmch_remove();
2077 }
2078
2079 int i915_gem_gtt_init(struct drm_device *dev)
2080 {
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct i915_gtt *gtt = &dev_priv->gtt;
2083 int ret;
2084
2085 if (INTEL_INFO(dev)->gen <= 5) {
2086 gtt->gtt_probe = i915_gmch_probe;
2087 gtt->base.cleanup = i915_gmch_remove;
2088 } else if (INTEL_INFO(dev)->gen < 8) {
2089 gtt->gtt_probe = gen6_gmch_probe;
2090 gtt->base.cleanup = gen6_gmch_remove;
2091 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2092 gtt->base.pte_encode = iris_pte_encode;
2093 else if (IS_HASWELL(dev))
2094 gtt->base.pte_encode = hsw_pte_encode;
2095 else if (IS_VALLEYVIEW(dev))
2096 gtt->base.pte_encode = byt_pte_encode;
2097 else if (INTEL_INFO(dev)->gen >= 7)
2098 gtt->base.pte_encode = ivb_pte_encode;
2099 else
2100 gtt->base.pte_encode = snb_pte_encode;
2101 } else {
2102 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2103 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2104 }
2105
2106 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2107 &gtt->mappable_base, &gtt->mappable_end);
2108 if (ret)
2109 return ret;
2110
2111 gtt->base.dev = dev;
2112
2113 /* GMADR is the PCI mmio aperture into the global GTT. */
2114 DRM_INFO("Memory usable by graphics device = %zdM\n",
2115 gtt->base.total >> 20);
2116 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2117 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2118 #ifdef CONFIG_INTEL_IOMMU
2119 if (intel_iommu_gfx_mapped)
2120 DRM_INFO("VT-d active for gfx access\n");
2121 #endif
2122 /*
2123 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2124 * user's requested state against the hardware/driver capabilities. We
2125 * do this now so that we can print out any log messages once rather
2126 * than every time we check intel_enable_ppgtt().
2127 */
2128 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2129 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2130
2131 return 0;
2132 }
2133
2134 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2135 struct i915_address_space *vm)
2136 {
2137 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2138 if (vma == NULL)
2139 return ERR_PTR(-ENOMEM);
2140
2141 INIT_LIST_HEAD(&vma->vma_link);
2142 INIT_LIST_HEAD(&vma->mm_list);
2143 INIT_LIST_HEAD(&vma->exec_list);
2144 vma->vm = vm;
2145 vma->obj = obj;
2146
2147 switch (INTEL_INFO(vm->dev)->gen) {
2148 case 8:
2149 case 7:
2150 case 6:
2151 if (i915_is_ggtt(vm)) {
2152 vma->unbind_vma = ggtt_unbind_vma;
2153 vma->bind_vma = ggtt_bind_vma;
2154 } else {
2155 vma->unbind_vma = ppgtt_unbind_vma;
2156 vma->bind_vma = ppgtt_bind_vma;
2157 }
2158 break;
2159 case 5:
2160 case 4:
2161 case 3:
2162 case 2:
2163 BUG_ON(!i915_is_ggtt(vm));
2164 vma->unbind_vma = i915_ggtt_unbind_vma;
2165 vma->bind_vma = i915_ggtt_bind_vma;
2166 break;
2167 default:
2168 BUG();
2169 }
2170
2171 /* Keep GGTT vmas first to make debug easier */
2172 if (i915_is_ggtt(vm))
2173 list_add(&vma->vma_link, &obj->vma_list);
2174 else
2175 list_add_tail(&vma->vma_link, &obj->vma_list);
2176
2177 return vma;
2178 }
2179
2180 struct i915_vma *
2181 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2182 struct i915_address_space *vm)
2183 {
2184 struct i915_vma *vma;
2185
2186 vma = i915_gem_obj_to_vma(obj, vm);
2187 if (!vma)
2188 vma = __i915_gem_vma_create(obj, vm);
2189
2190 i915_ppgtt_get(vm_to_ppgtt(vm));
2191
2192 return vma;
2193 }
Linux kernel - Deliverables
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