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drm/i915: Rework GPU reset sequence to match driver load & thaw
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
35
36 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
37 {
38 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
39 return 0;
40
41 if (enable_ppgtt == 1)
42 return 1;
43
44 if (enable_ppgtt == 2 && HAS_PPGTT(dev))
45 return 2;
46
47 #ifdef CONFIG_INTEL_IOMMU
48 /* Disable ppgtt on SNB if VT-d is on. */
49 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
50 DRM_INFO("Disabling PPGTT because VT-d is on\n");
51 return 0;
52 }
53 #endif
54
55 /* Early VLV doesn't have this */
56 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
57 dev->pdev->revision < 0xb) {
58 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
59 return 0;
60 }
61
62 return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
63 }
64
65
66 static void ppgtt_bind_vma(struct i915_vma *vma,
67 enum i915_cache_level cache_level,
68 u32 flags);
69 static void ppgtt_unbind_vma(struct i915_vma *vma);
70
71 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
72 enum i915_cache_level level,
73 bool valid)
74 {
75 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
76 pte |= addr;
77
78 switch (level) {
79 case I915_CACHE_NONE:
80 pte |= PPAT_UNCACHED_INDEX;
81 break;
82 case I915_CACHE_WT:
83 pte |= PPAT_DISPLAY_ELLC_INDEX;
84 break;
85 default:
86 pte |= PPAT_CACHED_INDEX;
87 break;
88 }
89
90 return pte;
91 }
92
93 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
94 dma_addr_t addr,
95 enum i915_cache_level level)
96 {
97 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
98 pde |= addr;
99 if (level != I915_CACHE_NONE)
100 pde |= PPAT_CACHED_PDE_INDEX;
101 else
102 pde |= PPAT_UNCACHED_INDEX;
103 return pde;
104 }
105
106 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
107 enum i915_cache_level level,
108 bool valid, u32 unused)
109 {
110 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
111 pte |= GEN6_PTE_ADDR_ENCODE(addr);
112
113 switch (level) {
114 case I915_CACHE_L3_LLC:
115 case I915_CACHE_LLC:
116 pte |= GEN6_PTE_CACHE_LLC;
117 break;
118 case I915_CACHE_NONE:
119 pte |= GEN6_PTE_UNCACHED;
120 break;
121 default:
122 WARN_ON(1);
123 }
124
125 return pte;
126 }
127
128 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
129 enum i915_cache_level level,
130 bool valid, u32 unused)
131 {
132 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
133 pte |= GEN6_PTE_ADDR_ENCODE(addr);
134
135 switch (level) {
136 case I915_CACHE_L3_LLC:
137 pte |= GEN7_PTE_CACHE_L3_LLC;
138 break;
139 case I915_CACHE_LLC:
140 pte |= GEN6_PTE_CACHE_LLC;
141 break;
142 case I915_CACHE_NONE:
143 pte |= GEN6_PTE_UNCACHED;
144 break;
145 default:
146 WARN_ON(1);
147 }
148
149 return pte;
150 }
151
152 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
153 enum i915_cache_level level,
154 bool valid, u32 flags)
155 {
156 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
157 pte |= GEN6_PTE_ADDR_ENCODE(addr);
158
159 /* Mark the page as writeable. Other platforms don't have a
160 * setting for read-only/writable, so this matches that behavior.
161 */
162 if (!(flags & PTE_READ_ONLY))
163 pte |= BYT_PTE_WRITEABLE;
164
165 if (level != I915_CACHE_NONE)
166 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
167
168 return pte;
169 }
170
171 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
172 enum i915_cache_level level,
173 bool valid, u32 unused)
174 {
175 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
176 pte |= HSW_PTE_ADDR_ENCODE(addr);
177
178 if (level != I915_CACHE_NONE)
179 pte |= HSW_WB_LLC_AGE3;
180
181 return pte;
182 }
183
184 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
185 enum i915_cache_level level,
186 bool valid, u32 unused)
187 {
188 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
189 pte |= HSW_PTE_ADDR_ENCODE(addr);
190
191 switch (level) {
192 case I915_CACHE_NONE:
193 break;
194 case I915_CACHE_WT:
195 pte |= HSW_WT_ELLC_LLC_AGE3;
196 break;
197 default:
198 pte |= HSW_WB_ELLC_LLC_AGE3;
199 break;
200 }
201
202 return pte;
203 }
204
205 /* Broadwell Page Directory Pointer Descriptors */
206 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
207 uint64_t val)
208 {
209 int ret;
210
211 BUG_ON(entry >= 4);
212
213 ret = intel_ring_begin(ring, 6);
214 if (ret)
215 return ret;
216
217 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
218 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
219 intel_ring_emit(ring, (u32)(val >> 32));
220 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
221 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
222 intel_ring_emit(ring, (u32)(val));
223 intel_ring_advance(ring);
224
225 return 0;
226 }
227
228 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
229 struct intel_engine_cs *ring)
230 {
231 int i, ret;
232
233 /* bit of a hack to find the actual last used pd */
234 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
235
236 for (i = used_pd - 1; i >= 0; i--) {
237 dma_addr_t addr = ppgtt->pd_dma_addr[i];
238 ret = gen8_write_pdp(ring, i, addr);
239 if (ret)
240 return ret;
241 }
242
243 return 0;
244 }
245
246 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
247 uint64_t start,
248 uint64_t length,
249 bool use_scratch)
250 {
251 struct i915_hw_ppgtt *ppgtt =
252 container_of(vm, struct i915_hw_ppgtt, base);
253 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
254 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
255 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
256 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
257 unsigned num_entries = length >> PAGE_SHIFT;
258 unsigned last_pte, i;
259
260 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
261 I915_CACHE_LLC, use_scratch);
262
263 while (num_entries) {
264 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
265
266 last_pte = pte + num_entries;
267 if (last_pte > GEN8_PTES_PER_PAGE)
268 last_pte = GEN8_PTES_PER_PAGE;
269
270 pt_vaddr = kmap_atomic(page_table);
271
272 for (i = pte; i < last_pte; i++) {
273 pt_vaddr[i] = scratch_pte;
274 num_entries--;
275 }
276
277 if (!HAS_LLC(ppgtt->base.dev))
278 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
279 kunmap_atomic(pt_vaddr);
280
281 pte = 0;
282 if (++pde == GEN8_PDES_PER_PAGE) {
283 pdpe++;
284 pde = 0;
285 }
286 }
287 }
288
289 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
290 struct sg_table *pages,
291 uint64_t start,
292 enum i915_cache_level cache_level, u32 unused)
293 {
294 struct i915_hw_ppgtt *ppgtt =
295 container_of(vm, struct i915_hw_ppgtt, base);
296 gen8_gtt_pte_t *pt_vaddr;
297 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
298 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
299 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
300 struct sg_page_iter sg_iter;
301
302 pt_vaddr = NULL;
303
304 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
305 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
306 break;
307
308 if (pt_vaddr == NULL)
309 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
310
311 pt_vaddr[pte] =
312 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
313 cache_level, true);
314 if (++pte == GEN8_PTES_PER_PAGE) {
315 if (!HAS_LLC(ppgtt->base.dev))
316 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
317 kunmap_atomic(pt_vaddr);
318 pt_vaddr = NULL;
319 if (++pde == GEN8_PDES_PER_PAGE) {
320 pdpe++;
321 pde = 0;
322 }
323 pte = 0;
324 }
325 }
326 if (pt_vaddr) {
327 if (!HAS_LLC(ppgtt->base.dev))
328 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
329 kunmap_atomic(pt_vaddr);
330 }
331 }
332
333 static void gen8_free_page_tables(struct page **pt_pages)
334 {
335 int i;
336
337 if (pt_pages == NULL)
338 return;
339
340 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
341 if (pt_pages[i])
342 __free_pages(pt_pages[i], 0);
343 }
344
345 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
346 {
347 int i;
348
349 for (i = 0; i < ppgtt->num_pd_pages; i++) {
350 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
351 kfree(ppgtt->gen8_pt_pages[i]);
352 kfree(ppgtt->gen8_pt_dma_addr[i]);
353 }
354
355 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
356 }
357
358 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
359 {
360 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
361 int i, j;
362
363 for (i = 0; i < ppgtt->num_pd_pages; i++) {
364 /* TODO: In the future we'll support sparse mappings, so this
365 * will have to change. */
366 if (!ppgtt->pd_dma_addr[i])
367 continue;
368
369 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
370 PCI_DMA_BIDIRECTIONAL);
371
372 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
373 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
374 if (addr)
375 pci_unmap_page(hwdev, addr, PAGE_SIZE,
376 PCI_DMA_BIDIRECTIONAL);
377 }
378 }
379 }
380
381 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
382 {
383 struct i915_hw_ppgtt *ppgtt =
384 container_of(vm, struct i915_hw_ppgtt, base);
385
386 gen8_ppgtt_unmap_pages(ppgtt);
387 gen8_ppgtt_free(ppgtt);
388 }
389
390 static struct page **__gen8_alloc_page_tables(void)
391 {
392 struct page **pt_pages;
393 int i;
394
395 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
396 if (!pt_pages)
397 return ERR_PTR(-ENOMEM);
398
399 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
400 pt_pages[i] = alloc_page(GFP_KERNEL);
401 if (!pt_pages[i])
402 goto bail;
403 }
404
405 return pt_pages;
406
407 bail:
408 gen8_free_page_tables(pt_pages);
409 kfree(pt_pages);
410 return ERR_PTR(-ENOMEM);
411 }
412
413 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
414 const int max_pdp)
415 {
416 struct page **pt_pages[GEN8_LEGACY_PDPS];
417 int i, ret;
418
419 for (i = 0; i < max_pdp; i++) {
420 pt_pages[i] = __gen8_alloc_page_tables();
421 if (IS_ERR(pt_pages[i])) {
422 ret = PTR_ERR(pt_pages[i]);
423 goto unwind_out;
424 }
425 }
426
427 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
428 * "atomic" - for cleanup purposes.
429 */
430 for (i = 0; i < max_pdp; i++)
431 ppgtt->gen8_pt_pages[i] = pt_pages[i];
432
433 return 0;
434
435 unwind_out:
436 while (i--) {
437 gen8_free_page_tables(pt_pages[i]);
438 kfree(pt_pages[i]);
439 }
440
441 return ret;
442 }
443
444 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
445 {
446 int i;
447
448 for (i = 0; i < ppgtt->num_pd_pages; i++) {
449 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
450 sizeof(dma_addr_t),
451 GFP_KERNEL);
452 if (!ppgtt->gen8_pt_dma_addr[i])
453 return -ENOMEM;
454 }
455
456 return 0;
457 }
458
459 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
460 const int max_pdp)
461 {
462 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
463 if (!ppgtt->pd_pages)
464 return -ENOMEM;
465
466 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
467 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
468
469 return 0;
470 }
471
472 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
473 const int max_pdp)
474 {
475 int ret;
476
477 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
478 if (ret)
479 return ret;
480
481 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
482 if (ret) {
483 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
484 return ret;
485 }
486
487 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
488
489 ret = gen8_ppgtt_allocate_dma(ppgtt);
490 if (ret)
491 gen8_ppgtt_free(ppgtt);
492
493 return ret;
494 }
495
496 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
497 const int pd)
498 {
499 dma_addr_t pd_addr;
500 int ret;
501
502 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
503 &ppgtt->pd_pages[pd], 0,
504 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
505
506 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
507 if (ret)
508 return ret;
509
510 ppgtt->pd_dma_addr[pd] = pd_addr;
511
512 return 0;
513 }
514
515 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
516 const int pd,
517 const int pt)
518 {
519 dma_addr_t pt_addr;
520 struct page *p;
521 int ret;
522
523 p = ppgtt->gen8_pt_pages[pd][pt];
524 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
525 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
526 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
527 if (ret)
528 return ret;
529
530 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
531
532 return 0;
533 }
534
535 /**
536 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
537 * with a net effect resembling a 2-level page table in normal x86 terms. Each
538 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
539 * space.
540 *
541 * FIXME: split allocation into smaller pieces. For now we only ever do this
542 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
543 * TODO: Do something with the size parameter
544 */
545 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
546 {
547 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
548 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
549 int i, j, ret;
550
551 if (size % (1<<30))
552 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
553
554 /* 1. Do all our allocations for page directories and page tables. */
555 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
556 if (ret)
557 return ret;
558
559 /*
560 * 2. Create DMA mappings for the page directories and page tables.
561 */
562 for (i = 0; i < max_pdp; i++) {
563 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
564 if (ret)
565 goto bail;
566
567 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
568 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
569 if (ret)
570 goto bail;
571 }
572 }
573
574 /*
575 * 3. Map all the page directory entires to point to the page tables
576 * we've allocated.
577 *
578 * For now, the PPGTT helper functions all require that the PDEs are
579 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
580 * will never need to touch the PDEs again.
581 */
582 for (i = 0; i < max_pdp; i++) {
583 gen8_ppgtt_pde_t *pd_vaddr;
584 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
585 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
586 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
587 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
588 I915_CACHE_LLC);
589 }
590 if (!HAS_LLC(ppgtt->base.dev))
591 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
592 kunmap_atomic(pd_vaddr);
593 }
594
595 ppgtt->switch_mm = gen8_mm_switch;
596 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
597 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
598 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
599 ppgtt->base.start = 0;
600 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
601
602 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
603
604 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
605 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
606 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
607 ppgtt->num_pd_entries,
608 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
609 return 0;
610
611 bail:
612 gen8_ppgtt_unmap_pages(ppgtt);
613 gen8_ppgtt_free(ppgtt);
614 return ret;
615 }
616
617 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
618 {
619 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
620 struct i915_address_space *vm = &ppgtt->base;
621 gen6_gtt_pte_t __iomem *pd_addr;
622 gen6_gtt_pte_t scratch_pte;
623 uint32_t pd_entry;
624 int pte, pde;
625
626 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
627
628 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
629 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
630
631 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
632 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
633 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
634 u32 expected;
635 gen6_gtt_pte_t *pt_vaddr;
636 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
637 pd_entry = readl(pd_addr + pde);
638 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
639
640 if (pd_entry != expected)
641 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
642 pde,
643 pd_entry,
644 expected);
645 seq_printf(m, "\tPDE: %x\n", pd_entry);
646
647 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
648 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
649 unsigned long va =
650 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
651 (pte * PAGE_SIZE);
652 int i;
653 bool found = false;
654 for (i = 0; i < 4; i++)
655 if (pt_vaddr[pte + i] != scratch_pte)
656 found = true;
657 if (!found)
658 continue;
659
660 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
661 for (i = 0; i < 4; i++) {
662 if (pt_vaddr[pte + i] != scratch_pte)
663 seq_printf(m, " %08x", pt_vaddr[pte + i]);
664 else
665 seq_puts(m, " SCRATCH ");
666 }
667 seq_puts(m, "\n");
668 }
669 kunmap_atomic(pt_vaddr);
670 }
671 }
672
673 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
674 {
675 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
676 gen6_gtt_pte_t __iomem *pd_addr;
677 uint32_t pd_entry;
678 int i;
679
680 WARN_ON(ppgtt->pd_offset & 0x3f);
681 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
682 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
683 for (i = 0; i < ppgtt->num_pd_entries; i++) {
684 dma_addr_t pt_addr;
685
686 pt_addr = ppgtt->pt_dma_addr[i];
687 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
688 pd_entry |= GEN6_PDE_VALID;
689
690 writel(pd_entry, pd_addr + i);
691 }
692 readl(pd_addr);
693 }
694
695 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
696 {
697 BUG_ON(ppgtt->pd_offset & 0x3f);
698
699 return (ppgtt->pd_offset / 64) << 16;
700 }
701
702 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
703 struct intel_engine_cs *ring)
704 {
705 int ret;
706
707 /* NB: TLBs must be flushed and invalidated before a switch */
708 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
709 if (ret)
710 return ret;
711
712 ret = intel_ring_begin(ring, 6);
713 if (ret)
714 return ret;
715
716 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
717 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
718 intel_ring_emit(ring, PP_DIR_DCLV_2G);
719 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
720 intel_ring_emit(ring, get_pd_offset(ppgtt));
721 intel_ring_emit(ring, MI_NOOP);
722 intel_ring_advance(ring);
723
724 return 0;
725 }
726
727 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
728 struct intel_engine_cs *ring)
729 {
730 int ret;
731
732 /* NB: TLBs must be flushed and invalidated before a switch */
733 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
734 if (ret)
735 return ret;
736
737 ret = intel_ring_begin(ring, 6);
738 if (ret)
739 return ret;
740
741 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
742 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
743 intel_ring_emit(ring, PP_DIR_DCLV_2G);
744 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
745 intel_ring_emit(ring, get_pd_offset(ppgtt));
746 intel_ring_emit(ring, MI_NOOP);
747 intel_ring_advance(ring);
748
749 /* XXX: RCS is the only one to auto invalidate the TLBs? */
750 if (ring->id != RCS) {
751 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
752 if (ret)
753 return ret;
754 }
755
756 return 0;
757 }
758
759 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
760 struct intel_engine_cs *ring)
761 {
762 struct drm_device *dev = ppgtt->base.dev;
763 struct drm_i915_private *dev_priv = dev->dev_private;
764
765
766 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
767 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
768
769 POSTING_READ(RING_PP_DIR_DCLV(ring));
770
771 return 0;
772 }
773
774 static void gen8_ppgtt_enable(struct drm_device *dev)
775 {
776 struct drm_i915_private *dev_priv = dev->dev_private;
777 struct intel_engine_cs *ring;
778 int j;
779
780 /* In the case of execlists, PPGTT is enabled by the context descriptor
781 * and the PDPs are contained within the context itself. We don't
782 * need to do anything here. */
783 if (i915.enable_execlists)
784 return;
785
786 for_each_ring(ring, dev_priv, j) {
787 I915_WRITE(RING_MODE_GEN7(ring),
788 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
789 }
790 }
791
792 static void gen7_ppgtt_enable(struct drm_device *dev)
793 {
794 struct drm_i915_private *dev_priv = dev->dev_private;
795 struct intel_engine_cs *ring;
796 uint32_t ecochk, ecobits;
797 int i;
798
799 ecobits = I915_READ(GAC_ECO_BITS);
800 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
801
802 ecochk = I915_READ(GAM_ECOCHK);
803 if (IS_HASWELL(dev)) {
804 ecochk |= ECOCHK_PPGTT_WB_HSW;
805 } else {
806 ecochk |= ECOCHK_PPGTT_LLC_IVB;
807 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
808 }
809 I915_WRITE(GAM_ECOCHK, ecochk);
810
811 for_each_ring(ring, dev_priv, i) {
812 /* GFX_MODE is per-ring on gen7+ */
813 I915_WRITE(RING_MODE_GEN7(ring),
814 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
815 }
816 }
817
818 static void gen6_ppgtt_enable(struct drm_device *dev)
819 {
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 uint32_t ecochk, gab_ctl, ecobits;
822
823 ecobits = I915_READ(GAC_ECO_BITS);
824 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
825 ECOBITS_PPGTT_CACHE64B);
826
827 gab_ctl = I915_READ(GAB_CTL);
828 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
829
830 ecochk = I915_READ(GAM_ECOCHK);
831 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
832
833 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
834 }
835
836 /* PPGTT support for Sandybdrige/Gen6 and later */
837 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
838 uint64_t start,
839 uint64_t length,
840 bool use_scratch)
841 {
842 struct i915_hw_ppgtt *ppgtt =
843 container_of(vm, struct i915_hw_ppgtt, base);
844 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
845 unsigned first_entry = start >> PAGE_SHIFT;
846 unsigned num_entries = length >> PAGE_SHIFT;
847 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
848 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
849 unsigned last_pte, i;
850
851 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
852
853 while (num_entries) {
854 last_pte = first_pte + num_entries;
855 if (last_pte > I915_PPGTT_PT_ENTRIES)
856 last_pte = I915_PPGTT_PT_ENTRIES;
857
858 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
859
860 for (i = first_pte; i < last_pte; i++)
861 pt_vaddr[i] = scratch_pte;
862
863 kunmap_atomic(pt_vaddr);
864
865 num_entries -= last_pte - first_pte;
866 first_pte = 0;
867 act_pt++;
868 }
869 }
870
871 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
872 struct sg_table *pages,
873 uint64_t start,
874 enum i915_cache_level cache_level, u32 flags)
875 {
876 struct i915_hw_ppgtt *ppgtt =
877 container_of(vm, struct i915_hw_ppgtt, base);
878 gen6_gtt_pte_t *pt_vaddr;
879 unsigned first_entry = start >> PAGE_SHIFT;
880 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
881 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
882 struct sg_page_iter sg_iter;
883
884 pt_vaddr = NULL;
885 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
886 if (pt_vaddr == NULL)
887 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
888
889 pt_vaddr[act_pte] =
890 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
891 cache_level, true, flags);
892
893 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
894 kunmap_atomic(pt_vaddr);
895 pt_vaddr = NULL;
896 act_pt++;
897 act_pte = 0;
898 }
899 }
900 if (pt_vaddr)
901 kunmap_atomic(pt_vaddr);
902 }
903
904 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
905 {
906 int i;
907
908 if (ppgtt->pt_dma_addr) {
909 for (i = 0; i < ppgtt->num_pd_entries; i++)
910 pci_unmap_page(ppgtt->base.dev->pdev,
911 ppgtt->pt_dma_addr[i],
912 4096, PCI_DMA_BIDIRECTIONAL);
913 }
914 }
915
916 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
917 {
918 int i;
919
920 kfree(ppgtt->pt_dma_addr);
921 for (i = 0; i < ppgtt->num_pd_entries; i++)
922 __free_page(ppgtt->pt_pages[i]);
923 kfree(ppgtt->pt_pages);
924 }
925
926 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
927 {
928 struct i915_hw_ppgtt *ppgtt =
929 container_of(vm, struct i915_hw_ppgtt, base);
930
931 drm_mm_remove_node(&ppgtt->node);
932
933 gen6_ppgtt_unmap_pages(ppgtt);
934 gen6_ppgtt_free(ppgtt);
935 }
936
937 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
938 {
939 struct drm_device *dev = ppgtt->base.dev;
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 bool retried = false;
942 int ret;
943
944 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
945 * allocator works in address space sizes, so it's multiplied by page
946 * size. We allocate at the top of the GTT to avoid fragmentation.
947 */
948 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
949 alloc:
950 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
951 &ppgtt->node, GEN6_PD_SIZE,
952 GEN6_PD_ALIGN, 0,
953 0, dev_priv->gtt.base.total,
954 DRM_MM_TOPDOWN);
955 if (ret == -ENOSPC && !retried) {
956 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
957 GEN6_PD_SIZE, GEN6_PD_ALIGN,
958 I915_CACHE_NONE,
959 0, dev_priv->gtt.base.total,
960 0);
961 if (ret)
962 return ret;
963
964 retried = true;
965 goto alloc;
966 }
967
968 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
969 DRM_DEBUG("Forced to use aperture for PDEs\n");
970
971 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
972 return ret;
973 }
974
975 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
976 {
977 int i;
978
979 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
980 GFP_KERNEL);
981
982 if (!ppgtt->pt_pages)
983 return -ENOMEM;
984
985 for (i = 0; i < ppgtt->num_pd_entries; i++) {
986 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
987 if (!ppgtt->pt_pages[i]) {
988 gen6_ppgtt_free(ppgtt);
989 return -ENOMEM;
990 }
991 }
992
993 return 0;
994 }
995
996 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
997 {
998 int ret;
999
1000 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1001 if (ret)
1002 return ret;
1003
1004 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1005 if (ret) {
1006 drm_mm_remove_node(&ppgtt->node);
1007 return ret;
1008 }
1009
1010 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1011 GFP_KERNEL);
1012 if (!ppgtt->pt_dma_addr) {
1013 drm_mm_remove_node(&ppgtt->node);
1014 gen6_ppgtt_free(ppgtt);
1015 return -ENOMEM;
1016 }
1017
1018 return 0;
1019 }
1020
1021 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1022 {
1023 struct drm_device *dev = ppgtt->base.dev;
1024 int i;
1025
1026 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1027 dma_addr_t pt_addr;
1028
1029 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1030 PCI_DMA_BIDIRECTIONAL);
1031
1032 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1033 gen6_ppgtt_unmap_pages(ppgtt);
1034 return -EIO;
1035 }
1036
1037 ppgtt->pt_dma_addr[i] = pt_addr;
1038 }
1039
1040 return 0;
1041 }
1042
1043 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1044 {
1045 struct drm_device *dev = ppgtt->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 int ret;
1048
1049 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1050 if (IS_GEN6(dev)) {
1051 ppgtt->switch_mm = gen6_mm_switch;
1052 } else if (IS_HASWELL(dev)) {
1053 ppgtt->switch_mm = hsw_mm_switch;
1054 } else if (IS_GEN7(dev)) {
1055 ppgtt->switch_mm = gen7_mm_switch;
1056 } else
1057 BUG();
1058
1059 ret = gen6_ppgtt_alloc(ppgtt);
1060 if (ret)
1061 return ret;
1062
1063 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1064 if (ret) {
1065 gen6_ppgtt_free(ppgtt);
1066 return ret;
1067 }
1068
1069 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1070 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1071 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1072 ppgtt->base.start = 0;
1073 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1074 ppgtt->debug_dump = gen6_dump_ppgtt;
1075
1076 ppgtt->pd_offset =
1077 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1078
1079 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1080
1081 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1082 ppgtt->node.size >> 20,
1083 ppgtt->node.start / PAGE_SIZE);
1084
1085 gen6_write_pdes(ppgtt);
1086 DRM_DEBUG("Adding PPGTT at offset %x\n",
1087 ppgtt->pd_offset << 10);
1088
1089 return 0;
1090 }
1091
1092 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1093 {
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095
1096 ppgtt->base.dev = dev;
1097 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1098
1099 if (INTEL_INFO(dev)->gen < 8)
1100 return gen6_ppgtt_init(ppgtt);
1101 else if (IS_GEN8(dev))
1102 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1103 else
1104 BUG();
1105 }
1106 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1107 {
1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109 int ret = 0;
1110
1111 ret = __hw_ppgtt_init(dev, ppgtt);
1112 if (ret == 0) {
1113 kref_init(&ppgtt->ref);
1114 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1115 ppgtt->base.total);
1116 i915_init_vm(dev_priv, &ppgtt->base);
1117 }
1118
1119 return ret;
1120 }
1121
1122 int i915_ppgtt_init_hw(struct drm_device *dev)
1123 {
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125 struct intel_engine_cs *ring;
1126 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1127 int i, ret = 0;
1128
1129 if (!USES_PPGTT(dev))
1130 return 0;
1131
1132 if (IS_GEN6(dev))
1133 gen6_ppgtt_enable(dev);
1134 else if (IS_GEN7(dev))
1135 gen7_ppgtt_enable(dev);
1136 else if (INTEL_INFO(dev)->gen >= 8)
1137 gen8_ppgtt_enable(dev);
1138 else
1139 WARN_ON(1);
1140
1141 if (ppgtt) {
1142 for_each_ring(ring, dev_priv, i) {
1143 ret = ppgtt->switch_mm(ppgtt, ring);
1144 if (ret != 0)
1145 return ret;
1146 }
1147 }
1148
1149 return ret;
1150 }
1151 struct i915_hw_ppgtt *
1152 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1153 {
1154 struct i915_hw_ppgtt *ppgtt;
1155 int ret;
1156
1157 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1158 if (!ppgtt)
1159 return ERR_PTR(-ENOMEM);
1160
1161 ret = i915_ppgtt_init(dev, ppgtt);
1162 if (ret) {
1163 kfree(ppgtt);
1164 return ERR_PTR(ret);
1165 }
1166
1167 ppgtt->file_priv = fpriv;
1168
1169 return ppgtt;
1170 }
1171
1172 void i915_ppgtt_release(struct kref *kref)
1173 {
1174 struct i915_hw_ppgtt *ppgtt =
1175 container_of(kref, struct i915_hw_ppgtt, ref);
1176
1177 /* vmas should already be unbound */
1178 WARN_ON(!list_empty(&ppgtt->base.active_list));
1179 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1180
1181 list_del(&ppgtt->base.global_link);
1182 drm_mm_takedown(&ppgtt->base.mm);
1183
1184 ppgtt->base.cleanup(&ppgtt->base);
1185 kfree(ppgtt);
1186 }
1187
1188 static void
1189 ppgtt_bind_vma(struct i915_vma *vma,
1190 enum i915_cache_level cache_level,
1191 u32 flags)
1192 {
1193 /* Currently applicable only to VLV */
1194 if (vma->obj->gt_ro)
1195 flags |= PTE_READ_ONLY;
1196
1197 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1198 cache_level, flags);
1199 }
1200
1201 static void ppgtt_unbind_vma(struct i915_vma *vma)
1202 {
1203 vma->vm->clear_range(vma->vm,
1204 vma->node.start,
1205 vma->obj->base.size,
1206 true);
1207 }
1208
1209 extern int intel_iommu_gfx_mapped;
1210 /* Certain Gen5 chipsets require require idling the GPU before
1211 * unmapping anything from the GTT when VT-d is enabled.
1212 */
1213 static inline bool needs_idle_maps(struct drm_device *dev)
1214 {
1215 #ifdef CONFIG_INTEL_IOMMU
1216 /* Query intel_iommu to see if we need the workaround. Presumably that
1217 * was loaded first.
1218 */
1219 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1220 return true;
1221 #endif
1222 return false;
1223 }
1224
1225 static bool do_idling(struct drm_i915_private *dev_priv)
1226 {
1227 bool ret = dev_priv->mm.interruptible;
1228
1229 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1230 dev_priv->mm.interruptible = false;
1231 if (i915_gpu_idle(dev_priv->dev)) {
1232 DRM_ERROR("Couldn't idle GPU\n");
1233 /* Wait a bit, in hopes it avoids the hang */
1234 udelay(10);
1235 }
1236 }
1237
1238 return ret;
1239 }
1240
1241 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1242 {
1243 if (unlikely(dev_priv->gtt.do_idle_maps))
1244 dev_priv->mm.interruptible = interruptible;
1245 }
1246
1247 void i915_check_and_clear_faults(struct drm_device *dev)
1248 {
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 struct intel_engine_cs *ring;
1251 int i;
1252
1253 if (INTEL_INFO(dev)->gen < 6)
1254 return;
1255
1256 for_each_ring(ring, dev_priv, i) {
1257 u32 fault_reg;
1258 fault_reg = I915_READ(RING_FAULT_REG(ring));
1259 if (fault_reg & RING_FAULT_VALID) {
1260 DRM_DEBUG_DRIVER("Unexpected fault\n"
1261 "\tAddr: 0x%08lx\\n"
1262 "\tAddress space: %s\n"
1263 "\tSource ID: %d\n"
1264 "\tType: %d\n",
1265 fault_reg & PAGE_MASK,
1266 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1267 RING_FAULT_SRCID(fault_reg),
1268 RING_FAULT_FAULT_TYPE(fault_reg));
1269 I915_WRITE(RING_FAULT_REG(ring),
1270 fault_reg & ~RING_FAULT_VALID);
1271 }
1272 }
1273 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1274 }
1275
1276 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1277 {
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279
1280 /* Don't bother messing with faults pre GEN6 as we have little
1281 * documentation supporting that it's a good idea.
1282 */
1283 if (INTEL_INFO(dev)->gen < 6)
1284 return;
1285
1286 i915_check_and_clear_faults(dev);
1287
1288 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1289 dev_priv->gtt.base.start,
1290 dev_priv->gtt.base.total,
1291 true);
1292 }
1293
1294 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1295 {
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 struct drm_i915_gem_object *obj;
1298 struct i915_address_space *vm;
1299
1300 i915_check_and_clear_faults(dev);
1301
1302 /* First fill our portion of the GTT with scratch pages */
1303 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1304 dev_priv->gtt.base.start,
1305 dev_priv->gtt.base.total,
1306 true);
1307
1308 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1309 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1310 &dev_priv->gtt.base);
1311 if (!vma)
1312 continue;
1313
1314 i915_gem_clflush_object(obj, obj->pin_display);
1315 /* The bind_vma code tries to be smart about tracking mappings.
1316 * Unfortunately above, we've just wiped out the mappings
1317 * without telling our object about it. So we need to fake it.
1318 */
1319 obj->has_global_gtt_mapping = 0;
1320 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1321 }
1322
1323
1324 if (INTEL_INFO(dev)->gen >= 8) {
1325 if (IS_CHERRYVIEW(dev))
1326 chv_setup_private_ppat(dev_priv);
1327 else
1328 bdw_setup_private_ppat(dev_priv);
1329
1330 return;
1331 }
1332
1333 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1334 /* TODO: Perhaps it shouldn't be gen6 specific */
1335 if (i915_is_ggtt(vm)) {
1336 if (dev_priv->mm.aliasing_ppgtt)
1337 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1338 continue;
1339 }
1340
1341 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1342 }
1343
1344 i915_gem_chipset_flush(dev);
1345 }
1346
1347 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1348 {
1349 if (obj->has_dma_mapping)
1350 return 0;
1351
1352 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1353 obj->pages->sgl, obj->pages->nents,
1354 PCI_DMA_BIDIRECTIONAL))
1355 return -ENOSPC;
1356
1357 return 0;
1358 }
1359
1360 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1361 {
1362 #ifdef writeq
1363 writeq(pte, addr);
1364 #else
1365 iowrite32((u32)pte, addr);
1366 iowrite32(pte >> 32, addr + 4);
1367 #endif
1368 }
1369
1370 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1371 struct sg_table *st,
1372 uint64_t start,
1373 enum i915_cache_level level, u32 unused)
1374 {
1375 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1376 unsigned first_entry = start >> PAGE_SHIFT;
1377 gen8_gtt_pte_t __iomem *gtt_entries =
1378 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1379 int i = 0;
1380 struct sg_page_iter sg_iter;
1381 dma_addr_t addr = 0; /* shut up gcc */
1382
1383 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1384 addr = sg_dma_address(sg_iter.sg) +
1385 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1386 gen8_set_pte(&gtt_entries[i],
1387 gen8_pte_encode(addr, level, true));
1388 i++;
1389 }
1390
1391 /*
1392 * XXX: This serves as a posting read to make sure that the PTE has
1393 * actually been updated. There is some concern that even though
1394 * registers and PTEs are within the same BAR that they are potentially
1395 * of NUMA access patterns. Therefore, even with the way we assume
1396 * hardware should work, we must keep this posting read for paranoia.
1397 */
1398 if (i != 0)
1399 WARN_ON(readq(&gtt_entries[i-1])
1400 != gen8_pte_encode(addr, level, true));
1401
1402 /* This next bit makes the above posting read even more important. We
1403 * want to flush the TLBs only after we're certain all the PTE updates
1404 * have finished.
1405 */
1406 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1407 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1408 }
1409
1410 /*
1411 * Binds an object into the global gtt with the specified cache level. The object
1412 * will be accessible to the GPU via commands whose operands reference offsets
1413 * within the global GTT as well as accessible by the GPU through the GMADR
1414 * mapped BAR (dev_priv->mm.gtt->gtt).
1415 */
1416 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1417 struct sg_table *st,
1418 uint64_t start,
1419 enum i915_cache_level level, u32 flags)
1420 {
1421 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1422 unsigned first_entry = start >> PAGE_SHIFT;
1423 gen6_gtt_pte_t __iomem *gtt_entries =
1424 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1425 int i = 0;
1426 struct sg_page_iter sg_iter;
1427 dma_addr_t addr = 0;
1428
1429 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1430 addr = sg_page_iter_dma_address(&sg_iter);
1431 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1432 i++;
1433 }
1434
1435 /* XXX: This serves as a posting read to make sure that the PTE has
1436 * actually been updated. There is some concern that even though
1437 * registers and PTEs are within the same BAR that they are potentially
1438 * of NUMA access patterns. Therefore, even with the way we assume
1439 * hardware should work, we must keep this posting read for paranoia.
1440 */
1441 if (i != 0) {
1442 unsigned long gtt = readl(&gtt_entries[i-1]);
1443 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1444 }
1445
1446 /* This next bit makes the above posting read even more important. We
1447 * want to flush the TLBs only after we're certain all the PTE updates
1448 * have finished.
1449 */
1450 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1451 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1452 }
1453
1454 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1455 uint64_t start,
1456 uint64_t length,
1457 bool use_scratch)
1458 {
1459 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1460 unsigned first_entry = start >> PAGE_SHIFT;
1461 unsigned num_entries = length >> PAGE_SHIFT;
1462 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1463 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1464 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1465 int i;
1466
1467 if (WARN(num_entries > max_entries,
1468 "First entry = %d; Num entries = %d (max=%d)\n",
1469 first_entry, num_entries, max_entries))
1470 num_entries = max_entries;
1471
1472 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1473 I915_CACHE_LLC,
1474 use_scratch);
1475 for (i = 0; i < num_entries; i++)
1476 gen8_set_pte(&gtt_base[i], scratch_pte);
1477 readl(gtt_base);
1478 }
1479
1480 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1481 uint64_t start,
1482 uint64_t length,
1483 bool use_scratch)
1484 {
1485 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1486 unsigned first_entry = start >> PAGE_SHIFT;
1487 unsigned num_entries = length >> PAGE_SHIFT;
1488 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1489 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1490 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1491 int i;
1492
1493 if (WARN(num_entries > max_entries,
1494 "First entry = %d; Num entries = %d (max=%d)\n",
1495 first_entry, num_entries, max_entries))
1496 num_entries = max_entries;
1497
1498 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1499
1500 for (i = 0; i < num_entries; i++)
1501 iowrite32(scratch_pte, &gtt_base[i]);
1502 readl(gtt_base);
1503 }
1504
1505
1506 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1507 enum i915_cache_level cache_level,
1508 u32 unused)
1509 {
1510 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1511 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1512 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1513
1514 BUG_ON(!i915_is_ggtt(vma->vm));
1515 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1516 vma->obj->has_global_gtt_mapping = 1;
1517 }
1518
1519 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1520 uint64_t start,
1521 uint64_t length,
1522 bool unused)
1523 {
1524 unsigned first_entry = start >> PAGE_SHIFT;
1525 unsigned num_entries = length >> PAGE_SHIFT;
1526 intel_gtt_clear_range(first_entry, num_entries);
1527 }
1528
1529 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1530 {
1531 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1532 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1533
1534 BUG_ON(!i915_is_ggtt(vma->vm));
1535 vma->obj->has_global_gtt_mapping = 0;
1536 intel_gtt_clear_range(first, size);
1537 }
1538
1539 static void ggtt_bind_vma(struct i915_vma *vma,
1540 enum i915_cache_level cache_level,
1541 u32 flags)
1542 {
1543 struct drm_device *dev = vma->vm->dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 struct drm_i915_gem_object *obj = vma->obj;
1546
1547 /* Currently applicable only to VLV */
1548 if (obj->gt_ro)
1549 flags |= PTE_READ_ONLY;
1550
1551 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1552 * or we have a global mapping already but the cacheability flags have
1553 * changed, set the global PTEs.
1554 *
1555 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1556 * instead if none of the above hold true.
1557 *
1558 * NB: A global mapping should only be needed for special regions like
1559 * "gtt mappable", SNB errata, or if specified via special execbuf
1560 * flags. At all other times, the GPU will use the aliasing PPGTT.
1561 */
1562 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1563 if (!obj->has_global_gtt_mapping ||
1564 (cache_level != obj->cache_level)) {
1565 vma->vm->insert_entries(vma->vm, obj->pages,
1566 vma->node.start,
1567 cache_level, flags);
1568 obj->has_global_gtt_mapping = 1;
1569 }
1570 }
1571
1572 if (dev_priv->mm.aliasing_ppgtt &&
1573 (!obj->has_aliasing_ppgtt_mapping ||
1574 (cache_level != obj->cache_level))) {
1575 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1576 appgtt->base.insert_entries(&appgtt->base,
1577 vma->obj->pages,
1578 vma->node.start,
1579 cache_level, flags);
1580 vma->obj->has_aliasing_ppgtt_mapping = 1;
1581 }
1582 }
1583
1584 static void ggtt_unbind_vma(struct i915_vma *vma)
1585 {
1586 struct drm_device *dev = vma->vm->dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 struct drm_i915_gem_object *obj = vma->obj;
1589
1590 if (obj->has_global_gtt_mapping) {
1591 vma->vm->clear_range(vma->vm,
1592 vma->node.start,
1593 obj->base.size,
1594 true);
1595 obj->has_global_gtt_mapping = 0;
1596 }
1597
1598 if (obj->has_aliasing_ppgtt_mapping) {
1599 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1600 appgtt->base.clear_range(&appgtt->base,
1601 vma->node.start,
1602 obj->base.size,
1603 true);
1604 obj->has_aliasing_ppgtt_mapping = 0;
1605 }
1606 }
1607
1608 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1609 {
1610 struct drm_device *dev = obj->base.dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 bool interruptible;
1613
1614 interruptible = do_idling(dev_priv);
1615
1616 if (!obj->has_dma_mapping)
1617 dma_unmap_sg(&dev->pdev->dev,
1618 obj->pages->sgl, obj->pages->nents,
1619 PCI_DMA_BIDIRECTIONAL);
1620
1621 undo_idling(dev_priv, interruptible);
1622 }
1623
1624 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1625 unsigned long color,
1626 unsigned long *start,
1627 unsigned long *end)
1628 {
1629 if (node->color != color)
1630 *start += 4096;
1631
1632 if (!list_empty(&node->node_list)) {
1633 node = list_entry(node->node_list.next,
1634 struct drm_mm_node,
1635 node_list);
1636 if (node->allocated && node->color != color)
1637 *end -= 4096;
1638 }
1639 }
1640
1641 int i915_gem_setup_global_gtt(struct drm_device *dev,
1642 unsigned long start,
1643 unsigned long mappable_end,
1644 unsigned long end)
1645 {
1646 /* Let GEM Manage all of the aperture.
1647 *
1648 * However, leave one page at the end still bound to the scratch page.
1649 * There are a number of places where the hardware apparently prefetches
1650 * past the end of the object, and we've seen multiple hangs with the
1651 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1652 * aperture. One page should be enough to keep any prefetching inside
1653 * of the aperture.
1654 */
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1657 struct drm_mm_node *entry;
1658 struct drm_i915_gem_object *obj;
1659 unsigned long hole_start, hole_end;
1660 int ret;
1661
1662 BUG_ON(mappable_end > end);
1663
1664 /* Subtract the guard page ... */
1665 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1666 if (!HAS_LLC(dev))
1667 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1668
1669 /* Mark any preallocated objects as occupied */
1670 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1671 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1672
1673 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1674 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1675
1676 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1677 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1678 if (ret) {
1679 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1680 return ret;
1681 }
1682 obj->has_global_gtt_mapping = 1;
1683 }
1684
1685 dev_priv->gtt.base.start = start;
1686 dev_priv->gtt.base.total = end - start;
1687
1688 /* Clear any non-preallocated blocks */
1689 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1690 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1691 hole_start, hole_end);
1692 ggtt_vm->clear_range(ggtt_vm, hole_start,
1693 hole_end - hole_start, true);
1694 }
1695
1696 /* And finally clear the reserved guard page */
1697 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1698
1699 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1700 struct i915_hw_ppgtt *ppgtt;
1701
1702 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1703 if (!ppgtt)
1704 return -ENOMEM;
1705
1706 ret = __hw_ppgtt_init(dev, ppgtt);
1707 if (ret != 0)
1708 return ret;
1709
1710 dev_priv->mm.aliasing_ppgtt = ppgtt;
1711 }
1712
1713 return 0;
1714 }
1715
1716 void i915_gem_init_global_gtt(struct drm_device *dev)
1717 {
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719 unsigned long gtt_size, mappable_size;
1720
1721 gtt_size = dev_priv->gtt.base.total;
1722 mappable_size = dev_priv->gtt.mappable_end;
1723
1724 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1725 }
1726
1727 void i915_global_gtt_cleanup(struct drm_device *dev)
1728 {
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 struct i915_address_space *vm = &dev_priv->gtt.base;
1731
1732 if (dev_priv->mm.aliasing_ppgtt) {
1733 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1734
1735 ppgtt->base.cleanup(&ppgtt->base);
1736 }
1737
1738 if (drm_mm_initialized(&vm->mm)) {
1739 drm_mm_takedown(&vm->mm);
1740 list_del(&vm->global_link);
1741 }
1742
1743 vm->cleanup(vm);
1744 }
1745
1746 static int setup_scratch_page(struct drm_device *dev)
1747 {
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 struct page *page;
1750 dma_addr_t dma_addr;
1751
1752 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1753 if (page == NULL)
1754 return -ENOMEM;
1755 get_page(page);
1756 set_pages_uc(page, 1);
1757
1758 #ifdef CONFIG_INTEL_IOMMU
1759 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1760 PCI_DMA_BIDIRECTIONAL);
1761 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1762 return -EINVAL;
1763 #else
1764 dma_addr = page_to_phys(page);
1765 #endif
1766 dev_priv->gtt.base.scratch.page = page;
1767 dev_priv->gtt.base.scratch.addr = dma_addr;
1768
1769 return 0;
1770 }
1771
1772 static void teardown_scratch_page(struct drm_device *dev)
1773 {
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 struct page *page = dev_priv->gtt.base.scratch.page;
1776
1777 set_pages_wb(page, 1);
1778 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1779 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1780 put_page(page);
1781 __free_page(page);
1782 }
1783
1784 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1785 {
1786 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1787 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1788 return snb_gmch_ctl << 20;
1789 }
1790
1791 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1792 {
1793 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1794 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1795 if (bdw_gmch_ctl)
1796 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1797
1798 #ifdef CONFIG_X86_32
1799 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1800 if (bdw_gmch_ctl > 4)
1801 bdw_gmch_ctl = 4;
1802 #endif
1803
1804 return bdw_gmch_ctl << 20;
1805 }
1806
1807 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1808 {
1809 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1810 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1811
1812 if (gmch_ctrl)
1813 return 1 << (20 + gmch_ctrl);
1814
1815 return 0;
1816 }
1817
1818 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1819 {
1820 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1821 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1822 return snb_gmch_ctl << 25; /* 32 MB units */
1823 }
1824
1825 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1826 {
1827 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1828 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1829 return bdw_gmch_ctl << 25; /* 32 MB units */
1830 }
1831
1832 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1833 {
1834 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1835 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1836
1837 /*
1838 * 0x0 to 0x10: 32MB increments starting at 0MB
1839 * 0x11 to 0x16: 4MB increments starting at 8MB
1840 * 0x17 to 0x1d: 4MB increments start at 36MB
1841 */
1842 if (gmch_ctrl < 0x11)
1843 return gmch_ctrl << 25;
1844 else if (gmch_ctrl < 0x17)
1845 return (gmch_ctrl - 0x11 + 2) << 22;
1846 else
1847 return (gmch_ctrl - 0x17 + 9) << 22;
1848 }
1849
1850 static int ggtt_probe_common(struct drm_device *dev,
1851 size_t gtt_size)
1852 {
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 phys_addr_t gtt_phys_addr;
1855 int ret;
1856
1857 /* For Modern GENs the PTEs and register space are split in the BAR */
1858 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1859 (pci_resource_len(dev->pdev, 0) / 2);
1860
1861 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1862 if (!dev_priv->gtt.gsm) {
1863 DRM_ERROR("Failed to map the gtt page table\n");
1864 return -ENOMEM;
1865 }
1866
1867 ret = setup_scratch_page(dev);
1868 if (ret) {
1869 DRM_ERROR("Scratch setup failed\n");
1870 /* iounmap will also get called at remove, but meh */
1871 iounmap(dev_priv->gtt.gsm);
1872 }
1873
1874 return ret;
1875 }
1876
1877 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1878 * bits. When using advanced contexts each context stores its own PAT, but
1879 * writing this data shouldn't be harmful even in those cases. */
1880 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1881 {
1882 uint64_t pat;
1883
1884 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1885 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1886 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1887 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1888 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1889 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1890 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1891 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1892
1893 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1894 * write would work. */
1895 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1896 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1897 }
1898
1899 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1900 {
1901 uint64_t pat;
1902
1903 /*
1904 * Map WB on BDW to snooped on CHV.
1905 *
1906 * Only the snoop bit has meaning for CHV, the rest is
1907 * ignored.
1908 *
1909 * Note that the harware enforces snooping for all page
1910 * table accesses. The snoop bit is actually ignored for
1911 * PDEs.
1912 */
1913 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1914 GEN8_PPAT(1, 0) |
1915 GEN8_PPAT(2, 0) |
1916 GEN8_PPAT(3, 0) |
1917 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1918 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1919 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1920 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1921
1922 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1923 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1924 }
1925
1926 static int gen8_gmch_probe(struct drm_device *dev,
1927 size_t *gtt_total,
1928 size_t *stolen,
1929 phys_addr_t *mappable_base,
1930 unsigned long *mappable_end)
1931 {
1932 struct drm_i915_private *dev_priv = dev->dev_private;
1933 unsigned int gtt_size;
1934 u16 snb_gmch_ctl;
1935 int ret;
1936
1937 /* TODO: We're not aware of mappable constraints on gen8 yet */
1938 *mappable_base = pci_resource_start(dev->pdev, 2);
1939 *mappable_end = pci_resource_len(dev->pdev, 2);
1940
1941 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1942 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1943
1944 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1945
1946 if (IS_CHERRYVIEW(dev)) {
1947 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1948 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1949 } else {
1950 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1951 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1952 }
1953
1954 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1955
1956 if (IS_CHERRYVIEW(dev))
1957 chv_setup_private_ppat(dev_priv);
1958 else
1959 bdw_setup_private_ppat(dev_priv);
1960
1961 ret = ggtt_probe_common(dev, gtt_size);
1962
1963 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1964 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1965
1966 return ret;
1967 }
1968
1969 static int gen6_gmch_probe(struct drm_device *dev,
1970 size_t *gtt_total,
1971 size_t *stolen,
1972 phys_addr_t *mappable_base,
1973 unsigned long *mappable_end)
1974 {
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 unsigned int gtt_size;
1977 u16 snb_gmch_ctl;
1978 int ret;
1979
1980 *mappable_base = pci_resource_start(dev->pdev, 2);
1981 *mappable_end = pci_resource_len(dev->pdev, 2);
1982
1983 /* 64/512MB is the current min/max we actually know of, but this is just
1984 * a coarse sanity check.
1985 */
1986 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1987 DRM_ERROR("Unknown GMADR size (%lx)\n",
1988 dev_priv->gtt.mappable_end);
1989 return -ENXIO;
1990 }
1991
1992 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1993 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1994 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1995
1996 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1997
1998 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1999 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2000
2001 ret = ggtt_probe_common(dev, gtt_size);
2002
2003 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2004 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2005
2006 return ret;
2007 }
2008
2009 static void gen6_gmch_remove(struct i915_address_space *vm)
2010 {
2011
2012 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2013
2014 iounmap(gtt->gsm);
2015 teardown_scratch_page(vm->dev);
2016 }
2017
2018 static int i915_gmch_probe(struct drm_device *dev,
2019 size_t *gtt_total,
2020 size_t *stolen,
2021 phys_addr_t *mappable_base,
2022 unsigned long *mappable_end)
2023 {
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025 int ret;
2026
2027 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2028 if (!ret) {
2029 DRM_ERROR("failed to set up gmch\n");
2030 return -EIO;
2031 }
2032
2033 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2034
2035 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2036 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2037
2038 if (unlikely(dev_priv->gtt.do_idle_maps))
2039 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2040
2041 return 0;
2042 }
2043
2044 static void i915_gmch_remove(struct i915_address_space *vm)
2045 {
2046 intel_gmch_remove();
2047 }
2048
2049 int i915_gem_gtt_init(struct drm_device *dev)
2050 {
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct i915_gtt *gtt = &dev_priv->gtt;
2053 int ret;
2054
2055 if (INTEL_INFO(dev)->gen <= 5) {
2056 gtt->gtt_probe = i915_gmch_probe;
2057 gtt->base.cleanup = i915_gmch_remove;
2058 } else if (INTEL_INFO(dev)->gen < 8) {
2059 gtt->gtt_probe = gen6_gmch_probe;
2060 gtt->base.cleanup = gen6_gmch_remove;
2061 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2062 gtt->base.pte_encode = iris_pte_encode;
2063 else if (IS_HASWELL(dev))
2064 gtt->base.pte_encode = hsw_pte_encode;
2065 else if (IS_VALLEYVIEW(dev))
2066 gtt->base.pte_encode = byt_pte_encode;
2067 else if (INTEL_INFO(dev)->gen >= 7)
2068 gtt->base.pte_encode = ivb_pte_encode;
2069 else
2070 gtt->base.pte_encode = snb_pte_encode;
2071 } else {
2072 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2073 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2074 }
2075
2076 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2077 &gtt->mappable_base, &gtt->mappable_end);
2078 if (ret)
2079 return ret;
2080
2081 gtt->base.dev = dev;
2082
2083 /* GMADR is the PCI mmio aperture into the global GTT. */
2084 DRM_INFO("Memory usable by graphics device = %zdM\n",
2085 gtt->base.total >> 20);
2086 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2087 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2088 #ifdef CONFIG_INTEL_IOMMU
2089 if (intel_iommu_gfx_mapped)
2090 DRM_INFO("VT-d active for gfx access\n");
2091 #endif
2092 /*
2093 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2094 * user's requested state against the hardware/driver capabilities. We
2095 * do this now so that we can print out any log messages once rather
2096 * than every time we check intel_enable_ppgtt().
2097 */
2098 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2099 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2100
2101 return 0;
2102 }
2103
2104 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2105 struct i915_address_space *vm)
2106 {
2107 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2108 if (vma == NULL)
2109 return ERR_PTR(-ENOMEM);
2110
2111 INIT_LIST_HEAD(&vma->vma_link);
2112 INIT_LIST_HEAD(&vma->mm_list);
2113 INIT_LIST_HEAD(&vma->exec_list);
2114 vma->vm = vm;
2115 vma->obj = obj;
2116
2117 switch (INTEL_INFO(vm->dev)->gen) {
2118 case 8:
2119 case 7:
2120 case 6:
2121 if (i915_is_ggtt(vm)) {
2122 vma->unbind_vma = ggtt_unbind_vma;
2123 vma->bind_vma = ggtt_bind_vma;
2124 } else {
2125 vma->unbind_vma = ppgtt_unbind_vma;
2126 vma->bind_vma = ppgtt_bind_vma;
2127 }
2128 break;
2129 case 5:
2130 case 4:
2131 case 3:
2132 case 2:
2133 BUG_ON(!i915_is_ggtt(vm));
2134 vma->unbind_vma = i915_ggtt_unbind_vma;
2135 vma->bind_vma = i915_ggtt_bind_vma;
2136 break;
2137 default:
2138 BUG();
2139 }
2140
2141 /* Keep GGTT vmas first to make debug easier */
2142 if (i915_is_ggtt(vm))
2143 list_add(&vma->vma_link, &obj->vma_list);
2144 else
2145 list_add_tail(&vma->vma_link, &obj->vma_list);
2146
2147 return vma;
2148 }
2149
2150 struct i915_vma *
2151 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2152 struct i915_address_space *vm)
2153 {
2154 struct i915_vma *vma;
2155
2156 vma = i915_gem_obj_to_vma(obj, vm);
2157 if (!vma)
2158 vma = __i915_gem_vma_create(obj, vm);
2159
2160 if (!i915_is_ggtt(vm))
2161 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2162
2163 return vma;
2164 }
Linux kernel - Deliverables
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