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drm/i915: move modeset_update_power_wells earlier
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 #define GEN6_PPGTT_PD_ENTRIES 512
34 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
35 typedef uint64_t gen8_gtt_pte_t;
36 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
37
38 /* PPGTT stuff */
39 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
40 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
41
42 #define GEN6_PDE_VALID (1 << 0)
43 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
44 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
45
46 #define GEN6_PTE_VALID (1 << 0)
47 #define GEN6_PTE_UNCACHED (1 << 1)
48 #define HSW_PTE_UNCACHED (0)
49 #define GEN6_PTE_CACHE_LLC (2 << 1)
50 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
51 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
52 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
53
54 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
55 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
56 */
57 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
58 (((bits) & 0x8) << (11 - 3)))
59 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
60 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
61 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
62 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
63 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
64 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
65
66 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
67 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
68
69 /* GEN8 legacy style addressis defined as a 3 level page table:
70 * 31:30 | 29:21 | 20:12 | 11:0
71 * PDPE | PDE | PTE | offset
72 * The difference as compared to normal x86 3 level page table is the PDPEs are
73 * programmed via register.
74 */
75 #define GEN8_PDPE_SHIFT 30
76 #define GEN8_PDPE_MASK 0x3
77 #define GEN8_PDE_SHIFT 21
78 #define GEN8_PDE_MASK 0x1ff
79 #define GEN8_PTE_SHIFT 12
80 #define GEN8_PTE_MASK 0x1ff
81
82 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
83 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
84 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
85 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
86
87 static void ppgtt_bind_vma(struct i915_vma *vma,
88 enum i915_cache_level cache_level,
89 u32 flags);
90 static void ppgtt_unbind_vma(struct i915_vma *vma);
91 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
92
93 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
94 enum i915_cache_level level,
95 bool valid)
96 {
97 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
98 pte |= addr;
99 if (level != I915_CACHE_NONE)
100 pte |= PPAT_CACHED_INDEX;
101 else
102 pte |= PPAT_UNCACHED_INDEX;
103 return pte;
104 }
105
106 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
107 dma_addr_t addr,
108 enum i915_cache_level level)
109 {
110 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
111 pde |= addr;
112 if (level != I915_CACHE_NONE)
113 pde |= PPAT_CACHED_PDE_INDEX;
114 else
115 pde |= PPAT_UNCACHED_INDEX;
116 return pde;
117 }
118
119 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
120 enum i915_cache_level level,
121 bool valid)
122 {
123 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
124 pte |= GEN6_PTE_ADDR_ENCODE(addr);
125
126 switch (level) {
127 case I915_CACHE_L3_LLC:
128 case I915_CACHE_LLC:
129 pte |= GEN6_PTE_CACHE_LLC;
130 break;
131 case I915_CACHE_NONE:
132 pte |= GEN6_PTE_UNCACHED;
133 break;
134 default:
135 WARN_ON(1);
136 }
137
138 return pte;
139 }
140
141 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
142 enum i915_cache_level level,
143 bool valid)
144 {
145 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
146 pte |= GEN6_PTE_ADDR_ENCODE(addr);
147
148 switch (level) {
149 case I915_CACHE_L3_LLC:
150 pte |= GEN7_PTE_CACHE_L3_LLC;
151 break;
152 case I915_CACHE_LLC:
153 pte |= GEN6_PTE_CACHE_LLC;
154 break;
155 case I915_CACHE_NONE:
156 pte |= GEN6_PTE_UNCACHED;
157 break;
158 default:
159 WARN_ON(1);
160 }
161
162 return pte;
163 }
164
165 #define BYT_PTE_WRITEABLE (1 << 1)
166 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
167
168 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
169 enum i915_cache_level level,
170 bool valid)
171 {
172 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
173 pte |= GEN6_PTE_ADDR_ENCODE(addr);
174
175 /* Mark the page as writeable. Other platforms don't have a
176 * setting for read-only/writable, so this matches that behavior.
177 */
178 pte |= BYT_PTE_WRITEABLE;
179
180 if (level != I915_CACHE_NONE)
181 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
182
183 return pte;
184 }
185
186 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
187 enum i915_cache_level level,
188 bool valid)
189 {
190 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
191 pte |= HSW_PTE_ADDR_ENCODE(addr);
192
193 if (level != I915_CACHE_NONE)
194 pte |= HSW_WB_LLC_AGE3;
195
196 return pte;
197 }
198
199 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
200 enum i915_cache_level level,
201 bool valid)
202 {
203 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
204 pte |= HSW_PTE_ADDR_ENCODE(addr);
205
206 switch (level) {
207 case I915_CACHE_NONE:
208 break;
209 case I915_CACHE_WT:
210 pte |= HSW_WT_ELLC_LLC_AGE3;
211 break;
212 default:
213 pte |= HSW_WB_ELLC_LLC_AGE3;
214 break;
215 }
216
217 return pte;
218 }
219
220 /* Broadwell Page Directory Pointer Descriptors */
221 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
222 uint64_t val, bool synchronous)
223 {
224 struct drm_i915_private *dev_priv = ring->dev->dev_private;
225 int ret;
226
227 BUG_ON(entry >= 4);
228
229 if (synchronous) {
230 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
231 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
232 return 0;
233 }
234
235 ret = intel_ring_begin(ring, 6);
236 if (ret)
237 return ret;
238
239 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
240 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
241 intel_ring_emit(ring, (u32)(val >> 32));
242 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
243 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
244 intel_ring_emit(ring, (u32)(val));
245 intel_ring_advance(ring);
246
247 return 0;
248 }
249
250 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
251 struct intel_ring_buffer *ring,
252 bool synchronous)
253 {
254 int i, ret;
255
256 /* bit of a hack to find the actual last used pd */
257 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
258
259 for (i = used_pd - 1; i >= 0; i--) {
260 dma_addr_t addr = ppgtt->pd_dma_addr[i];
261 ret = gen8_write_pdp(ring, i, addr, synchronous);
262 if (ret)
263 return ret;
264 }
265
266 return 0;
267 }
268
269 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
270 uint64_t start,
271 uint64_t length,
272 bool use_scratch)
273 {
274 struct i915_hw_ppgtt *ppgtt =
275 container_of(vm, struct i915_hw_ppgtt, base);
276 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
277 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
278 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
279 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
280 unsigned num_entries = length >> PAGE_SHIFT;
281 unsigned last_pte, i;
282
283 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
284 I915_CACHE_LLC, use_scratch);
285
286 while (num_entries) {
287 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
288
289 last_pte = pte + num_entries;
290 if (last_pte > GEN8_PTES_PER_PAGE)
291 last_pte = GEN8_PTES_PER_PAGE;
292
293 pt_vaddr = kmap_atomic(page_table);
294
295 for (i = pte; i < last_pte; i++) {
296 pt_vaddr[i] = scratch_pte;
297 num_entries--;
298 }
299
300 kunmap_atomic(pt_vaddr);
301
302 pte = 0;
303 if (++pde == GEN8_PDES_PER_PAGE) {
304 pdpe++;
305 pde = 0;
306 }
307 }
308 }
309
310 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
311 struct sg_table *pages,
312 uint64_t start,
313 enum i915_cache_level cache_level)
314 {
315 struct i915_hw_ppgtt *ppgtt =
316 container_of(vm, struct i915_hw_ppgtt, base);
317 gen8_gtt_pte_t *pt_vaddr;
318 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
319 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
320 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
321 struct sg_page_iter sg_iter;
322
323 pt_vaddr = NULL;
324
325 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
326 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
327 break;
328
329 if (pt_vaddr == NULL)
330 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
331
332 pt_vaddr[pte] =
333 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
334 cache_level, true);
335 if (++pte == GEN8_PTES_PER_PAGE) {
336 kunmap_atomic(pt_vaddr);
337 pt_vaddr = NULL;
338 if (++pde == GEN8_PDES_PER_PAGE) {
339 pdpe++;
340 pde = 0;
341 }
342 pte = 0;
343 }
344 }
345 if (pt_vaddr)
346 kunmap_atomic(pt_vaddr);
347 }
348
349 static void gen8_free_page_tables(struct page **pt_pages)
350 {
351 int i;
352
353 if (pt_pages == NULL)
354 return;
355
356 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
357 if (pt_pages[i])
358 __free_pages(pt_pages[i], 0);
359 }
360
361 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
362 {
363 int i;
364
365 for (i = 0; i < ppgtt->num_pd_pages; i++) {
366 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
367 kfree(ppgtt->gen8_pt_pages[i]);
368 kfree(ppgtt->gen8_pt_dma_addr[i]);
369 }
370
371 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
372 }
373
374 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
375 {
376 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
377 int i, j;
378
379 for (i = 0; i < ppgtt->num_pd_pages; i++) {
380 /* TODO: In the future we'll support sparse mappings, so this
381 * will have to change. */
382 if (!ppgtt->pd_dma_addr[i])
383 continue;
384
385 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
386 PCI_DMA_BIDIRECTIONAL);
387
388 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
389 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
390 if (addr)
391 pci_unmap_page(hwdev, addr, PAGE_SIZE,
392 PCI_DMA_BIDIRECTIONAL);
393 }
394 }
395 }
396
397 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
398 {
399 struct i915_hw_ppgtt *ppgtt =
400 container_of(vm, struct i915_hw_ppgtt, base);
401
402 list_del(&vm->global_link);
403 drm_mm_takedown(&vm->mm);
404
405 gen8_ppgtt_unmap_pages(ppgtt);
406 gen8_ppgtt_free(ppgtt);
407 }
408
409 static struct page **__gen8_alloc_page_tables(void)
410 {
411 struct page **pt_pages;
412 int i;
413
414 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
415 if (!pt_pages)
416 return ERR_PTR(-ENOMEM);
417
418 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
419 pt_pages[i] = alloc_page(GFP_KERNEL);
420 if (!pt_pages[i])
421 goto bail;
422 }
423
424 return pt_pages;
425
426 bail:
427 gen8_free_page_tables(pt_pages);
428 kfree(pt_pages);
429 return ERR_PTR(-ENOMEM);
430 }
431
432 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
433 const int max_pdp)
434 {
435 struct page **pt_pages[GEN8_LEGACY_PDPS];
436 int i, ret;
437
438 for (i = 0; i < max_pdp; i++) {
439 pt_pages[i] = __gen8_alloc_page_tables();
440 if (IS_ERR(pt_pages[i])) {
441 ret = PTR_ERR(pt_pages[i]);
442 goto unwind_out;
443 }
444 }
445
446 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
447 * "atomic" - for cleanup purposes.
448 */
449 for (i = 0; i < max_pdp; i++)
450 ppgtt->gen8_pt_pages[i] = pt_pages[i];
451
452 return 0;
453
454 unwind_out:
455 while (i--) {
456 gen8_free_page_tables(pt_pages[i]);
457 kfree(pt_pages[i]);
458 }
459
460 return ret;
461 }
462
463 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
464 {
465 int i;
466
467 for (i = 0; i < ppgtt->num_pd_pages; i++) {
468 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
469 sizeof(dma_addr_t),
470 GFP_KERNEL);
471 if (!ppgtt->gen8_pt_dma_addr[i])
472 return -ENOMEM;
473 }
474
475 return 0;
476 }
477
478 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
479 const int max_pdp)
480 {
481 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
482 if (!ppgtt->pd_pages)
483 return -ENOMEM;
484
485 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
486 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
487
488 return 0;
489 }
490
491 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
492 const int max_pdp)
493 {
494 int ret;
495
496 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
497 if (ret)
498 return ret;
499
500 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
501 if (ret) {
502 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
503 return ret;
504 }
505
506 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
507
508 ret = gen8_ppgtt_allocate_dma(ppgtt);
509 if (ret)
510 gen8_ppgtt_free(ppgtt);
511
512 return ret;
513 }
514
515 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
516 const int pd)
517 {
518 dma_addr_t pd_addr;
519 int ret;
520
521 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
522 &ppgtt->pd_pages[pd], 0,
523 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
524
525 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
526 if (ret)
527 return ret;
528
529 ppgtt->pd_dma_addr[pd] = pd_addr;
530
531 return 0;
532 }
533
534 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
535 const int pd,
536 const int pt)
537 {
538 dma_addr_t pt_addr;
539 struct page *p;
540 int ret;
541
542 p = ppgtt->gen8_pt_pages[pd][pt];
543 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
544 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
545 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
546 if (ret)
547 return ret;
548
549 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
550
551 return 0;
552 }
553
554 /**
555 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
556 * with a net effect resembling a 2-level page table in normal x86 terms. Each
557 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
558 * space.
559 *
560 * FIXME: split allocation into smaller pieces. For now we only ever do this
561 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
562 * TODO: Do something with the size parameter
563 */
564 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
565 {
566 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
567 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
568 int i, j, ret;
569
570 if (size % (1<<30))
571 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
572
573 /* 1. Do all our allocations for page directories and page tables. */
574 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
575 if (ret)
576 return ret;
577
578 /*
579 * 2. Create DMA mappings for the page directories and page tables.
580 */
581 for (i = 0; i < max_pdp; i++) {
582 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
583 if (ret)
584 goto bail;
585
586 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
587 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
588 if (ret)
589 goto bail;
590 }
591 }
592
593 /*
594 * 3. Map all the page directory entires to point to the page tables
595 * we've allocated.
596 *
597 * For now, the PPGTT helper functions all require that the PDEs are
598 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
599 * will never need to touch the PDEs again.
600 */
601 for (i = 0; i < max_pdp; i++) {
602 gen8_ppgtt_pde_t *pd_vaddr;
603 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
604 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
605 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
606 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
607 I915_CACHE_LLC);
608 }
609 kunmap_atomic(pd_vaddr);
610 }
611
612 ppgtt->enable = gen8_ppgtt_enable;
613 ppgtt->switch_mm = gen8_mm_switch;
614 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
615 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
616 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
617 ppgtt->base.start = 0;
618 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
619
620 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
621
622 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
623 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
624 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
625 ppgtt->num_pd_entries,
626 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
627 return 0;
628
629 bail:
630 gen8_ppgtt_unmap_pages(ppgtt);
631 gen8_ppgtt_free(ppgtt);
632 return ret;
633 }
634
635 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
636 {
637 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
638 struct i915_address_space *vm = &ppgtt->base;
639 gen6_gtt_pte_t __iomem *pd_addr;
640 gen6_gtt_pte_t scratch_pte;
641 uint32_t pd_entry;
642 int pte, pde;
643
644 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
645
646 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
647 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
648
649 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
650 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
651 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
652 u32 expected;
653 gen6_gtt_pte_t *pt_vaddr;
654 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
655 pd_entry = readl(pd_addr + pde);
656 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
657
658 if (pd_entry != expected)
659 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
660 pde,
661 pd_entry,
662 expected);
663 seq_printf(m, "\tPDE: %x\n", pd_entry);
664
665 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
666 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
667 unsigned long va =
668 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
669 (pte * PAGE_SIZE);
670 int i;
671 bool found = false;
672 for (i = 0; i < 4; i++)
673 if (pt_vaddr[pte + i] != scratch_pte)
674 found = true;
675 if (!found)
676 continue;
677
678 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
679 for (i = 0; i < 4; i++) {
680 if (pt_vaddr[pte + i] != scratch_pte)
681 seq_printf(m, " %08x", pt_vaddr[pte + i]);
682 else
683 seq_puts(m, " SCRATCH ");
684 }
685 seq_puts(m, "\n");
686 }
687 kunmap_atomic(pt_vaddr);
688 }
689 }
690
691 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
692 {
693 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
694 gen6_gtt_pte_t __iomem *pd_addr;
695 uint32_t pd_entry;
696 int i;
697
698 WARN_ON(ppgtt->pd_offset & 0x3f);
699 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
700 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
701 for (i = 0; i < ppgtt->num_pd_entries; i++) {
702 dma_addr_t pt_addr;
703
704 pt_addr = ppgtt->pt_dma_addr[i];
705 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
706 pd_entry |= GEN6_PDE_VALID;
707
708 writel(pd_entry, pd_addr + i);
709 }
710 readl(pd_addr);
711 }
712
713 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
714 {
715 BUG_ON(ppgtt->pd_offset & 0x3f);
716
717 return (ppgtt->pd_offset / 64) << 16;
718 }
719
720 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
721 struct intel_ring_buffer *ring,
722 bool synchronous)
723 {
724 struct drm_device *dev = ppgtt->base.dev;
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 int ret;
727
728 /* If we're in reset, we can assume the GPU is sufficiently idle to
729 * manually frob these bits. Ideally we could use the ring functions,
730 * except our error handling makes it quite difficult (can't use
731 * intel_ring_begin, ring->flush, or intel_ring_advance)
732 *
733 * FIXME: We should try not to special case reset
734 */
735 if (synchronous ||
736 i915_reset_in_progress(&dev_priv->gpu_error)) {
737 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
738 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
739 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
740 POSTING_READ(RING_PP_DIR_BASE(ring));
741 return 0;
742 }
743
744 /* NB: TLBs must be flushed and invalidated before a switch */
745 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
746 if (ret)
747 return ret;
748
749 ret = intel_ring_begin(ring, 6);
750 if (ret)
751 return ret;
752
753 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
754 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
755 intel_ring_emit(ring, PP_DIR_DCLV_2G);
756 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
757 intel_ring_emit(ring, get_pd_offset(ppgtt));
758 intel_ring_emit(ring, MI_NOOP);
759 intel_ring_advance(ring);
760
761 return 0;
762 }
763
764 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
765 struct intel_ring_buffer *ring,
766 bool synchronous)
767 {
768 struct drm_device *dev = ppgtt->base.dev;
769 struct drm_i915_private *dev_priv = dev->dev_private;
770 int ret;
771
772 /* If we're in reset, we can assume the GPU is sufficiently idle to
773 * manually frob these bits. Ideally we could use the ring functions,
774 * except our error handling makes it quite difficult (can't use
775 * intel_ring_begin, ring->flush, or intel_ring_advance)
776 *
777 * FIXME: We should try not to special case reset
778 */
779 if (synchronous ||
780 i915_reset_in_progress(&dev_priv->gpu_error)) {
781 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
782 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
783 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
784 POSTING_READ(RING_PP_DIR_BASE(ring));
785 return 0;
786 }
787
788 /* NB: TLBs must be flushed and invalidated before a switch */
789 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
790 if (ret)
791 return ret;
792
793 ret = intel_ring_begin(ring, 6);
794 if (ret)
795 return ret;
796
797 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
798 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
799 intel_ring_emit(ring, PP_DIR_DCLV_2G);
800 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
801 intel_ring_emit(ring, get_pd_offset(ppgtt));
802 intel_ring_emit(ring, MI_NOOP);
803 intel_ring_advance(ring);
804
805 /* XXX: RCS is the only one to auto invalidate the TLBs? */
806 if (ring->id != RCS) {
807 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
808 if (ret)
809 return ret;
810 }
811
812 return 0;
813 }
814
815 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
816 struct intel_ring_buffer *ring,
817 bool synchronous)
818 {
819 struct drm_device *dev = ppgtt->base.dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
821
822 if (!synchronous)
823 return 0;
824
825 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
826 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
827
828 POSTING_READ(RING_PP_DIR_DCLV(ring));
829
830 return 0;
831 }
832
833 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
834 {
835 struct drm_device *dev = ppgtt->base.dev;
836 struct drm_i915_private *dev_priv = dev->dev_private;
837 struct intel_ring_buffer *ring;
838 int j, ret;
839
840 for_each_ring(ring, dev_priv, j) {
841 I915_WRITE(RING_MODE_GEN7(ring),
842 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
843
844 /* We promise to do a switch later with FULL PPGTT. If this is
845 * aliasing, this is the one and only switch we'll do */
846 if (USES_FULL_PPGTT(dev))
847 continue;
848
849 ret = ppgtt->switch_mm(ppgtt, ring, true);
850 if (ret)
851 goto err_out;
852 }
853
854 return 0;
855
856 err_out:
857 for_each_ring(ring, dev_priv, j)
858 I915_WRITE(RING_MODE_GEN7(ring),
859 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
860 return ret;
861 }
862
863 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
864 {
865 struct drm_device *dev = ppgtt->base.dev;
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 struct intel_ring_buffer *ring;
868 uint32_t ecochk, ecobits;
869 int i;
870
871 ecobits = I915_READ(GAC_ECO_BITS);
872 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
873
874 ecochk = I915_READ(GAM_ECOCHK);
875 if (IS_HASWELL(dev)) {
876 ecochk |= ECOCHK_PPGTT_WB_HSW;
877 } else {
878 ecochk |= ECOCHK_PPGTT_LLC_IVB;
879 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
880 }
881 I915_WRITE(GAM_ECOCHK, ecochk);
882
883 for_each_ring(ring, dev_priv, i) {
884 int ret;
885 /* GFX_MODE is per-ring on gen7+ */
886 I915_WRITE(RING_MODE_GEN7(ring),
887 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
888
889 /* We promise to do a switch later with FULL PPGTT. If this is
890 * aliasing, this is the one and only switch we'll do */
891 if (USES_FULL_PPGTT(dev))
892 continue;
893
894 ret = ppgtt->switch_mm(ppgtt, ring, true);
895 if (ret)
896 return ret;
897 }
898
899 return 0;
900 }
901
902 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
903 {
904 struct drm_device *dev = ppgtt->base.dev;
905 drm_i915_private_t *dev_priv = dev->dev_private;
906 struct intel_ring_buffer *ring;
907 uint32_t ecochk, gab_ctl, ecobits;
908 int i;
909
910 ecobits = I915_READ(GAC_ECO_BITS);
911 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
912 ECOBITS_PPGTT_CACHE64B);
913
914 gab_ctl = I915_READ(GAB_CTL);
915 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
916
917 ecochk = I915_READ(GAM_ECOCHK);
918 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
919
920 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
921
922 for_each_ring(ring, dev_priv, i) {
923 int ret = ppgtt->switch_mm(ppgtt, ring, true);
924 if (ret)
925 return ret;
926 }
927
928 return 0;
929 }
930
931 /* PPGTT support for Sandybdrige/Gen6 and later */
932 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
933 uint64_t start,
934 uint64_t length,
935 bool use_scratch)
936 {
937 struct i915_hw_ppgtt *ppgtt =
938 container_of(vm, struct i915_hw_ppgtt, base);
939 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
940 unsigned first_entry = start >> PAGE_SHIFT;
941 unsigned num_entries = length >> PAGE_SHIFT;
942 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
943 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
944 unsigned last_pte, i;
945
946 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
947
948 while (num_entries) {
949 last_pte = first_pte + num_entries;
950 if (last_pte > I915_PPGTT_PT_ENTRIES)
951 last_pte = I915_PPGTT_PT_ENTRIES;
952
953 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
954
955 for (i = first_pte; i < last_pte; i++)
956 pt_vaddr[i] = scratch_pte;
957
958 kunmap_atomic(pt_vaddr);
959
960 num_entries -= last_pte - first_pte;
961 first_pte = 0;
962 act_pt++;
963 }
964 }
965
966 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
967 struct sg_table *pages,
968 uint64_t start,
969 enum i915_cache_level cache_level)
970 {
971 struct i915_hw_ppgtt *ppgtt =
972 container_of(vm, struct i915_hw_ppgtt, base);
973 gen6_gtt_pte_t *pt_vaddr;
974 unsigned first_entry = start >> PAGE_SHIFT;
975 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
976 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
977 struct sg_page_iter sg_iter;
978
979 pt_vaddr = NULL;
980 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
981 if (pt_vaddr == NULL)
982 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
983
984 pt_vaddr[act_pte] =
985 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
986 cache_level, true);
987 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
988 kunmap_atomic(pt_vaddr);
989 pt_vaddr = NULL;
990 act_pt++;
991 act_pte = 0;
992 }
993 }
994 if (pt_vaddr)
995 kunmap_atomic(pt_vaddr);
996 }
997
998 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
999 {
1000 int i;
1001
1002 if (ppgtt->pt_dma_addr) {
1003 for (i = 0; i < ppgtt->num_pd_entries; i++)
1004 pci_unmap_page(ppgtt->base.dev->pdev,
1005 ppgtt->pt_dma_addr[i],
1006 4096, PCI_DMA_BIDIRECTIONAL);
1007 }
1008 }
1009
1010 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1011 {
1012 int i;
1013
1014 kfree(ppgtt->pt_dma_addr);
1015 for (i = 0; i < ppgtt->num_pd_entries; i++)
1016 __free_page(ppgtt->pt_pages[i]);
1017 kfree(ppgtt->pt_pages);
1018 }
1019
1020 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1021 {
1022 struct i915_hw_ppgtt *ppgtt =
1023 container_of(vm, struct i915_hw_ppgtt, base);
1024
1025 list_del(&vm->global_link);
1026 drm_mm_takedown(&ppgtt->base.mm);
1027 drm_mm_remove_node(&ppgtt->node);
1028
1029 gen6_ppgtt_unmap_pages(ppgtt);
1030 gen6_ppgtt_free(ppgtt);
1031 }
1032
1033 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1034 {
1035 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
1036 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
1037 struct drm_device *dev = ppgtt->base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 bool retried = false;
1040 int ret;
1041
1042 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1043 * allocator works in address space sizes, so it's multiplied by page
1044 * size. We allocate at the top of the GTT to avoid fragmentation.
1045 */
1046 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1047 alloc:
1048 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1049 &ppgtt->node, GEN6_PD_SIZE,
1050 GEN6_PD_ALIGN, 0,
1051 0, dev_priv->gtt.base.total,
1052 DRM_MM_SEARCH_DEFAULT);
1053 if (ret == -ENOSPC && !retried) {
1054 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1055 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1056 I915_CACHE_NONE, 0);
1057 if (ret)
1058 return ret;
1059
1060 retried = true;
1061 goto alloc;
1062 }
1063
1064 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1065 DRM_DEBUG("Forced to use aperture for PDEs\n");
1066
1067 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1068 return ret;
1069 }
1070
1071 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1072 {
1073 int i;
1074
1075 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1076 GFP_KERNEL);
1077
1078 if (!ppgtt->pt_pages)
1079 return -ENOMEM;
1080
1081 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1082 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1083 if (!ppgtt->pt_pages[i]) {
1084 gen6_ppgtt_free(ppgtt);
1085 return -ENOMEM;
1086 }
1087 }
1088
1089 return 0;
1090 }
1091
1092 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1093 {
1094 int ret;
1095
1096 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1097 if (ret)
1098 return ret;
1099
1100 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1101 if (ret) {
1102 drm_mm_remove_node(&ppgtt->node);
1103 return ret;
1104 }
1105
1106 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1107 GFP_KERNEL);
1108 if (!ppgtt->pt_dma_addr) {
1109 drm_mm_remove_node(&ppgtt->node);
1110 gen6_ppgtt_free(ppgtt);
1111 return -ENOMEM;
1112 }
1113
1114 return 0;
1115 }
1116
1117 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1118 {
1119 struct drm_device *dev = ppgtt->base.dev;
1120 int i;
1121
1122 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1123 dma_addr_t pt_addr;
1124
1125 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1126 PCI_DMA_BIDIRECTIONAL);
1127
1128 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1129 gen6_ppgtt_unmap_pages(ppgtt);
1130 return -EIO;
1131 }
1132
1133 ppgtt->pt_dma_addr[i] = pt_addr;
1134 }
1135
1136 return 0;
1137 }
1138
1139 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1140 {
1141 struct drm_device *dev = ppgtt->base.dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 int ret;
1144
1145 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1146 if (IS_GEN6(dev)) {
1147 ppgtt->enable = gen6_ppgtt_enable;
1148 ppgtt->switch_mm = gen6_mm_switch;
1149 } else if (IS_HASWELL(dev)) {
1150 ppgtt->enable = gen7_ppgtt_enable;
1151 ppgtt->switch_mm = hsw_mm_switch;
1152 } else if (IS_GEN7(dev)) {
1153 ppgtt->enable = gen7_ppgtt_enable;
1154 ppgtt->switch_mm = gen7_mm_switch;
1155 } else
1156 BUG();
1157
1158 ret = gen6_ppgtt_alloc(ppgtt);
1159 if (ret)
1160 return ret;
1161
1162 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1163 if (ret) {
1164 gen6_ppgtt_free(ppgtt);
1165 return ret;
1166 }
1167
1168 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1169 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1170 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1171 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1172 ppgtt->base.start = 0;
1173 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1174 ppgtt->debug_dump = gen6_dump_ppgtt;
1175
1176 ppgtt->pd_offset =
1177 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1178
1179 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1180
1181 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1182 ppgtt->node.size >> 20,
1183 ppgtt->node.start / PAGE_SIZE);
1184
1185 return 0;
1186 }
1187
1188 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1189 {
1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 int ret = 0;
1192
1193 ppgtt->base.dev = dev;
1194
1195 if (INTEL_INFO(dev)->gen < 8)
1196 ret = gen6_ppgtt_init(ppgtt);
1197 else if (IS_GEN8(dev))
1198 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1199 else
1200 BUG();
1201
1202 if (!ret) {
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 kref_init(&ppgtt->ref);
1205 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1206 ppgtt->base.total);
1207 i915_init_vm(dev_priv, &ppgtt->base);
1208 if (INTEL_INFO(dev)->gen < 8) {
1209 gen6_write_pdes(ppgtt);
1210 DRM_DEBUG("Adding PPGTT at offset %x\n",
1211 ppgtt->pd_offset << 10);
1212 }
1213 }
1214
1215 return ret;
1216 }
1217
1218 static void
1219 ppgtt_bind_vma(struct i915_vma *vma,
1220 enum i915_cache_level cache_level,
1221 u32 flags)
1222 {
1223 WARN_ON(flags);
1224
1225 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1226 cache_level);
1227 }
1228
1229 static void ppgtt_unbind_vma(struct i915_vma *vma)
1230 {
1231 vma->vm->clear_range(vma->vm,
1232 vma->node.start,
1233 vma->obj->base.size,
1234 true);
1235 }
1236
1237 extern int intel_iommu_gfx_mapped;
1238 /* Certain Gen5 chipsets require require idling the GPU before
1239 * unmapping anything from the GTT when VT-d is enabled.
1240 */
1241 static inline bool needs_idle_maps(struct drm_device *dev)
1242 {
1243 #ifdef CONFIG_INTEL_IOMMU
1244 /* Query intel_iommu to see if we need the workaround. Presumably that
1245 * was loaded first.
1246 */
1247 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1248 return true;
1249 #endif
1250 return false;
1251 }
1252
1253 static bool do_idling(struct drm_i915_private *dev_priv)
1254 {
1255 bool ret = dev_priv->mm.interruptible;
1256
1257 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1258 dev_priv->mm.interruptible = false;
1259 if (i915_gpu_idle(dev_priv->dev)) {
1260 DRM_ERROR("Couldn't idle GPU\n");
1261 /* Wait a bit, in hopes it avoids the hang */
1262 udelay(10);
1263 }
1264 }
1265
1266 return ret;
1267 }
1268
1269 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1270 {
1271 if (unlikely(dev_priv->gtt.do_idle_maps))
1272 dev_priv->mm.interruptible = interruptible;
1273 }
1274
1275 void i915_check_and_clear_faults(struct drm_device *dev)
1276 {
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278 struct intel_ring_buffer *ring;
1279 int i;
1280
1281 if (INTEL_INFO(dev)->gen < 6)
1282 return;
1283
1284 for_each_ring(ring, dev_priv, i) {
1285 u32 fault_reg;
1286 fault_reg = I915_READ(RING_FAULT_REG(ring));
1287 if (fault_reg & RING_FAULT_VALID) {
1288 DRM_DEBUG_DRIVER("Unexpected fault\n"
1289 "\tAddr: 0x%08lx\\n"
1290 "\tAddress space: %s\n"
1291 "\tSource ID: %d\n"
1292 "\tType: %d\n",
1293 fault_reg & PAGE_MASK,
1294 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1295 RING_FAULT_SRCID(fault_reg),
1296 RING_FAULT_FAULT_TYPE(fault_reg));
1297 I915_WRITE(RING_FAULT_REG(ring),
1298 fault_reg & ~RING_FAULT_VALID);
1299 }
1300 }
1301 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1302 }
1303
1304 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1305 {
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307
1308 /* Don't bother messing with faults pre GEN6 as we have little
1309 * documentation supporting that it's a good idea.
1310 */
1311 if (INTEL_INFO(dev)->gen < 6)
1312 return;
1313
1314 i915_check_and_clear_faults(dev);
1315
1316 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1317 dev_priv->gtt.base.start,
1318 dev_priv->gtt.base.total,
1319 false);
1320 }
1321
1322 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1323 {
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct drm_i915_gem_object *obj;
1326 struct i915_address_space *vm;
1327
1328 i915_check_and_clear_faults(dev);
1329
1330 /* First fill our portion of the GTT with scratch pages */
1331 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1332 dev_priv->gtt.base.start,
1333 dev_priv->gtt.base.total,
1334 true);
1335
1336 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1337 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1338 &dev_priv->gtt.base);
1339 if (!vma)
1340 continue;
1341
1342 i915_gem_clflush_object(obj, obj->pin_display);
1343 /* The bind_vma code tries to be smart about tracking mappings.
1344 * Unfortunately above, we've just wiped out the mappings
1345 * without telling our object about it. So we need to fake it.
1346 */
1347 obj->has_global_gtt_mapping = 0;
1348 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1349 }
1350
1351
1352 if (INTEL_INFO(dev)->gen >= 8)
1353 return;
1354
1355 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1356 /* TODO: Perhaps it shouldn't be gen6 specific */
1357 if (i915_is_ggtt(vm)) {
1358 if (dev_priv->mm.aliasing_ppgtt)
1359 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1360 continue;
1361 }
1362
1363 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1364 }
1365
1366 i915_gem_chipset_flush(dev);
1367 }
1368
1369 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1370 {
1371 if (obj->has_dma_mapping)
1372 return 0;
1373
1374 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1375 obj->pages->sgl, obj->pages->nents,
1376 PCI_DMA_BIDIRECTIONAL))
1377 return -ENOSPC;
1378
1379 return 0;
1380 }
1381
1382 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1383 {
1384 #ifdef writeq
1385 writeq(pte, addr);
1386 #else
1387 iowrite32((u32)pte, addr);
1388 iowrite32(pte >> 32, addr + 4);
1389 #endif
1390 }
1391
1392 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1393 struct sg_table *st,
1394 uint64_t start,
1395 enum i915_cache_level level)
1396 {
1397 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1398 unsigned first_entry = start >> PAGE_SHIFT;
1399 gen8_gtt_pte_t __iomem *gtt_entries =
1400 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1401 int i = 0;
1402 struct sg_page_iter sg_iter;
1403 dma_addr_t addr;
1404
1405 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1406 addr = sg_dma_address(sg_iter.sg) +
1407 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1408 gen8_set_pte(&gtt_entries[i],
1409 gen8_pte_encode(addr, level, true));
1410 i++;
1411 }
1412
1413 /*
1414 * XXX: This serves as a posting read to make sure that the PTE has
1415 * actually been updated. There is some concern that even though
1416 * registers and PTEs are within the same BAR that they are potentially
1417 * of NUMA access patterns. Therefore, even with the way we assume
1418 * hardware should work, we must keep this posting read for paranoia.
1419 */
1420 if (i != 0)
1421 WARN_ON(readq(&gtt_entries[i-1])
1422 != gen8_pte_encode(addr, level, true));
1423
1424 /* This next bit makes the above posting read even more important. We
1425 * want to flush the TLBs only after we're certain all the PTE updates
1426 * have finished.
1427 */
1428 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1429 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1430 }
1431
1432 /*
1433 * Binds an object into the global gtt with the specified cache level. The object
1434 * will be accessible to the GPU via commands whose operands reference offsets
1435 * within the global GTT as well as accessible by the GPU through the GMADR
1436 * mapped BAR (dev_priv->mm.gtt->gtt).
1437 */
1438 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1439 struct sg_table *st,
1440 uint64_t start,
1441 enum i915_cache_level level)
1442 {
1443 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1444 unsigned first_entry = start >> PAGE_SHIFT;
1445 gen6_gtt_pte_t __iomem *gtt_entries =
1446 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1447 int i = 0;
1448 struct sg_page_iter sg_iter;
1449 dma_addr_t addr;
1450
1451 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1452 addr = sg_page_iter_dma_address(&sg_iter);
1453 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1454 i++;
1455 }
1456
1457 /* XXX: This serves as a posting read to make sure that the PTE has
1458 * actually been updated. There is some concern that even though
1459 * registers and PTEs are within the same BAR that they are potentially
1460 * of NUMA access patterns. Therefore, even with the way we assume
1461 * hardware should work, we must keep this posting read for paranoia.
1462 */
1463 if (i != 0)
1464 WARN_ON(readl(&gtt_entries[i-1]) !=
1465 vm->pte_encode(addr, level, true));
1466
1467 /* This next bit makes the above posting read even more important. We
1468 * want to flush the TLBs only after we're certain all the PTE updates
1469 * have finished.
1470 */
1471 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1472 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1473 }
1474
1475 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1476 uint64_t start,
1477 uint64_t length,
1478 bool use_scratch)
1479 {
1480 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1481 unsigned first_entry = start >> PAGE_SHIFT;
1482 unsigned num_entries = length >> PAGE_SHIFT;
1483 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1484 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1485 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1486 int i;
1487
1488 if (WARN(num_entries > max_entries,
1489 "First entry = %d; Num entries = %d (max=%d)\n",
1490 first_entry, num_entries, max_entries))
1491 num_entries = max_entries;
1492
1493 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1494 I915_CACHE_LLC,
1495 use_scratch);
1496 for (i = 0; i < num_entries; i++)
1497 gen8_set_pte(&gtt_base[i], scratch_pte);
1498 readl(gtt_base);
1499 }
1500
1501 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1502 uint64_t start,
1503 uint64_t length,
1504 bool use_scratch)
1505 {
1506 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1507 unsigned first_entry = start >> PAGE_SHIFT;
1508 unsigned num_entries = length >> PAGE_SHIFT;
1509 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1510 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1511 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1512 int i;
1513
1514 if (WARN(num_entries > max_entries,
1515 "First entry = %d; Num entries = %d (max=%d)\n",
1516 first_entry, num_entries, max_entries))
1517 num_entries = max_entries;
1518
1519 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1520
1521 for (i = 0; i < num_entries; i++)
1522 iowrite32(scratch_pte, &gtt_base[i]);
1523 readl(gtt_base);
1524 }
1525
1526
1527 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1528 enum i915_cache_level cache_level,
1529 u32 unused)
1530 {
1531 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1532 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1533 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1534
1535 BUG_ON(!i915_is_ggtt(vma->vm));
1536 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1537 vma->obj->has_global_gtt_mapping = 1;
1538 }
1539
1540 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1541 uint64_t start,
1542 uint64_t length,
1543 bool unused)
1544 {
1545 unsigned first_entry = start >> PAGE_SHIFT;
1546 unsigned num_entries = length >> PAGE_SHIFT;
1547 intel_gtt_clear_range(first_entry, num_entries);
1548 }
1549
1550 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1551 {
1552 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1553 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1554
1555 BUG_ON(!i915_is_ggtt(vma->vm));
1556 vma->obj->has_global_gtt_mapping = 0;
1557 intel_gtt_clear_range(first, size);
1558 }
1559
1560 static void ggtt_bind_vma(struct i915_vma *vma,
1561 enum i915_cache_level cache_level,
1562 u32 flags)
1563 {
1564 struct drm_device *dev = vma->vm->dev;
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566 struct drm_i915_gem_object *obj = vma->obj;
1567
1568 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1569 * or we have a global mapping already but the cacheability flags have
1570 * changed, set the global PTEs.
1571 *
1572 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1573 * instead if none of the above hold true.
1574 *
1575 * NB: A global mapping should only be needed for special regions like
1576 * "gtt mappable", SNB errata, or if specified via special execbuf
1577 * flags. At all other times, the GPU will use the aliasing PPGTT.
1578 */
1579 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1580 if (!obj->has_global_gtt_mapping ||
1581 (cache_level != obj->cache_level)) {
1582 vma->vm->insert_entries(vma->vm, obj->pages,
1583 vma->node.start,
1584 cache_level);
1585 obj->has_global_gtt_mapping = 1;
1586 }
1587 }
1588
1589 if (dev_priv->mm.aliasing_ppgtt &&
1590 (!obj->has_aliasing_ppgtt_mapping ||
1591 (cache_level != obj->cache_level))) {
1592 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1593 appgtt->base.insert_entries(&appgtt->base,
1594 vma->obj->pages,
1595 vma->node.start,
1596 cache_level);
1597 vma->obj->has_aliasing_ppgtt_mapping = 1;
1598 }
1599 }
1600
1601 static void ggtt_unbind_vma(struct i915_vma *vma)
1602 {
1603 struct drm_device *dev = vma->vm->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_i915_gem_object *obj = vma->obj;
1606
1607 if (obj->has_global_gtt_mapping) {
1608 vma->vm->clear_range(vma->vm,
1609 vma->node.start,
1610 obj->base.size,
1611 true);
1612 obj->has_global_gtt_mapping = 0;
1613 }
1614
1615 if (obj->has_aliasing_ppgtt_mapping) {
1616 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1617 appgtt->base.clear_range(&appgtt->base,
1618 vma->node.start,
1619 obj->base.size,
1620 true);
1621 obj->has_aliasing_ppgtt_mapping = 0;
1622 }
1623 }
1624
1625 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1626 {
1627 struct drm_device *dev = obj->base.dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 bool interruptible;
1630
1631 interruptible = do_idling(dev_priv);
1632
1633 if (!obj->has_dma_mapping)
1634 dma_unmap_sg(&dev->pdev->dev,
1635 obj->pages->sgl, obj->pages->nents,
1636 PCI_DMA_BIDIRECTIONAL);
1637
1638 undo_idling(dev_priv, interruptible);
1639 }
1640
1641 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1642 unsigned long color,
1643 unsigned long *start,
1644 unsigned long *end)
1645 {
1646 if (node->color != color)
1647 *start += 4096;
1648
1649 if (!list_empty(&node->node_list)) {
1650 node = list_entry(node->node_list.next,
1651 struct drm_mm_node,
1652 node_list);
1653 if (node->allocated && node->color != color)
1654 *end -= 4096;
1655 }
1656 }
1657
1658 void i915_gem_setup_global_gtt(struct drm_device *dev,
1659 unsigned long start,
1660 unsigned long mappable_end,
1661 unsigned long end)
1662 {
1663 /* Let GEM Manage all of the aperture.
1664 *
1665 * However, leave one page at the end still bound to the scratch page.
1666 * There are a number of places where the hardware apparently prefetches
1667 * past the end of the object, and we've seen multiple hangs with the
1668 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1669 * aperture. One page should be enough to keep any prefetching inside
1670 * of the aperture.
1671 */
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1674 struct drm_mm_node *entry;
1675 struct drm_i915_gem_object *obj;
1676 unsigned long hole_start, hole_end;
1677
1678 BUG_ON(mappable_end > end);
1679
1680 /* Subtract the guard page ... */
1681 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1682 if (!HAS_LLC(dev))
1683 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1684
1685 /* Mark any preallocated objects as occupied */
1686 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1687 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1688 int ret;
1689 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1690 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1691
1692 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1693 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1694 if (ret)
1695 DRM_DEBUG_KMS("Reservation failed\n");
1696 obj->has_global_gtt_mapping = 1;
1697 }
1698
1699 dev_priv->gtt.base.start = start;
1700 dev_priv->gtt.base.total = end - start;
1701
1702 /* Clear any non-preallocated blocks */
1703 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1704 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1705 hole_start, hole_end);
1706 ggtt_vm->clear_range(ggtt_vm, hole_start,
1707 hole_end - hole_start, true);
1708 }
1709
1710 /* And finally clear the reserved guard page */
1711 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1712 }
1713
1714 void i915_gem_init_global_gtt(struct drm_device *dev)
1715 {
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 unsigned long gtt_size, mappable_size;
1718
1719 gtt_size = dev_priv->gtt.base.total;
1720 mappable_size = dev_priv->gtt.mappable_end;
1721
1722 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1723 }
1724
1725 static int setup_scratch_page(struct drm_device *dev)
1726 {
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 struct page *page;
1729 dma_addr_t dma_addr;
1730
1731 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1732 if (page == NULL)
1733 return -ENOMEM;
1734 get_page(page);
1735 set_pages_uc(page, 1);
1736
1737 #ifdef CONFIG_INTEL_IOMMU
1738 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1739 PCI_DMA_BIDIRECTIONAL);
1740 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1741 return -EINVAL;
1742 #else
1743 dma_addr = page_to_phys(page);
1744 #endif
1745 dev_priv->gtt.base.scratch.page = page;
1746 dev_priv->gtt.base.scratch.addr = dma_addr;
1747
1748 return 0;
1749 }
1750
1751 static void teardown_scratch_page(struct drm_device *dev)
1752 {
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 struct page *page = dev_priv->gtt.base.scratch.page;
1755
1756 set_pages_wb(page, 1);
1757 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1758 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1759 put_page(page);
1760 __free_page(page);
1761 }
1762
1763 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1764 {
1765 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1766 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1767 return snb_gmch_ctl << 20;
1768 }
1769
1770 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1771 {
1772 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1773 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1774 if (bdw_gmch_ctl)
1775 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1776 return bdw_gmch_ctl << 20;
1777 }
1778
1779 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1780 {
1781 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1782 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1783 return snb_gmch_ctl << 25; /* 32 MB units */
1784 }
1785
1786 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1787 {
1788 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1789 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1790 return bdw_gmch_ctl << 25; /* 32 MB units */
1791 }
1792
1793 static int ggtt_probe_common(struct drm_device *dev,
1794 size_t gtt_size)
1795 {
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 phys_addr_t gtt_bus_addr;
1798 int ret;
1799
1800 /* For Modern GENs the PTEs and register space are split in the BAR */
1801 gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1802 (pci_resource_len(dev->pdev, 0) / 2);
1803
1804 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1805 if (!dev_priv->gtt.gsm) {
1806 DRM_ERROR("Failed to map the gtt page table\n");
1807 return -ENOMEM;
1808 }
1809
1810 ret = setup_scratch_page(dev);
1811 if (ret) {
1812 DRM_ERROR("Scratch setup failed\n");
1813 /* iounmap will also get called at remove, but meh */
1814 iounmap(dev_priv->gtt.gsm);
1815 }
1816
1817 return ret;
1818 }
1819
1820 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1821 * bits. When using advanced contexts each context stores its own PAT, but
1822 * writing this data shouldn't be harmful even in those cases. */
1823 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1824 {
1825 #define GEN8_PPAT_UC (0<<0)
1826 #define GEN8_PPAT_WC (1<<0)
1827 #define GEN8_PPAT_WT (2<<0)
1828 #define GEN8_PPAT_WB (3<<0)
1829 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1830 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1831 #define GEN8_PPAT_LLC (1<<2)
1832 #define GEN8_PPAT_LLCELLC (2<<2)
1833 #define GEN8_PPAT_LLCeLLC (3<<2)
1834 #define GEN8_PPAT_AGE(x) (x<<4)
1835 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1836 uint64_t pat;
1837
1838 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1839 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1840 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1841 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1842 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1843 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1844 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1845 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1846
1847 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1848 * write would work. */
1849 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1850 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1851 }
1852
1853 static int gen8_gmch_probe(struct drm_device *dev,
1854 size_t *gtt_total,
1855 size_t *stolen,
1856 phys_addr_t *mappable_base,
1857 unsigned long *mappable_end)
1858 {
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 unsigned int gtt_size;
1861 u16 snb_gmch_ctl;
1862 int ret;
1863
1864 /* TODO: We're not aware of mappable constraints on gen8 yet */
1865 *mappable_base = pci_resource_start(dev->pdev, 2);
1866 *mappable_end = pci_resource_len(dev->pdev, 2);
1867
1868 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1869 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1870
1871 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1872
1873 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1874
1875 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1876 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1877
1878 gen8_setup_private_ppat(dev_priv);
1879
1880 ret = ggtt_probe_common(dev, gtt_size);
1881
1882 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1883 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1884
1885 return ret;
1886 }
1887
1888 static int gen6_gmch_probe(struct drm_device *dev,
1889 size_t *gtt_total,
1890 size_t *stolen,
1891 phys_addr_t *mappable_base,
1892 unsigned long *mappable_end)
1893 {
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 unsigned int gtt_size;
1896 u16 snb_gmch_ctl;
1897 int ret;
1898
1899 *mappable_base = pci_resource_start(dev->pdev, 2);
1900 *mappable_end = pci_resource_len(dev->pdev, 2);
1901
1902 /* 64/512MB is the current min/max we actually know of, but this is just
1903 * a coarse sanity check.
1904 */
1905 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1906 DRM_ERROR("Unknown GMADR size (%lx)\n",
1907 dev_priv->gtt.mappable_end);
1908 return -ENXIO;
1909 }
1910
1911 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1912 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1913 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1914
1915 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1916
1917 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1918 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1919
1920 ret = ggtt_probe_common(dev, gtt_size);
1921
1922 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1923 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1924
1925 return ret;
1926 }
1927
1928 static void gen6_gmch_remove(struct i915_address_space *vm)
1929 {
1930
1931 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1932
1933 drm_mm_takedown(&vm->mm);
1934 iounmap(gtt->gsm);
1935 teardown_scratch_page(vm->dev);
1936 }
1937
1938 static int i915_gmch_probe(struct drm_device *dev,
1939 size_t *gtt_total,
1940 size_t *stolen,
1941 phys_addr_t *mappable_base,
1942 unsigned long *mappable_end)
1943 {
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 int ret;
1946
1947 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1948 if (!ret) {
1949 DRM_ERROR("failed to set up gmch\n");
1950 return -EIO;
1951 }
1952
1953 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1954
1955 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1956 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1957
1958 if (unlikely(dev_priv->gtt.do_idle_maps))
1959 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1960
1961 return 0;
1962 }
1963
1964 static void i915_gmch_remove(struct i915_address_space *vm)
1965 {
1966 intel_gmch_remove();
1967 }
1968
1969 int i915_gem_gtt_init(struct drm_device *dev)
1970 {
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1972 struct i915_gtt *gtt = &dev_priv->gtt;
1973 int ret;
1974
1975 if (INTEL_INFO(dev)->gen <= 5) {
1976 gtt->gtt_probe = i915_gmch_probe;
1977 gtt->base.cleanup = i915_gmch_remove;
1978 } else if (INTEL_INFO(dev)->gen < 8) {
1979 gtt->gtt_probe = gen6_gmch_probe;
1980 gtt->base.cleanup = gen6_gmch_remove;
1981 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1982 gtt->base.pte_encode = iris_pte_encode;
1983 else if (IS_HASWELL(dev))
1984 gtt->base.pte_encode = hsw_pte_encode;
1985 else if (IS_VALLEYVIEW(dev))
1986 gtt->base.pte_encode = byt_pte_encode;
1987 else if (INTEL_INFO(dev)->gen >= 7)
1988 gtt->base.pte_encode = ivb_pte_encode;
1989 else
1990 gtt->base.pte_encode = snb_pte_encode;
1991 } else {
1992 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1993 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1994 }
1995
1996 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1997 &gtt->mappable_base, &gtt->mappable_end);
1998 if (ret)
1999 return ret;
2000
2001 gtt->base.dev = dev;
2002
2003 /* GMADR is the PCI mmio aperture into the global GTT. */
2004 DRM_INFO("Memory usable by graphics device = %zdM\n",
2005 gtt->base.total >> 20);
2006 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2007 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2008
2009 return 0;
2010 }
2011
2012 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2013 struct i915_address_space *vm)
2014 {
2015 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2016 if (vma == NULL)
2017 return ERR_PTR(-ENOMEM);
2018
2019 INIT_LIST_HEAD(&vma->vma_link);
2020 INIT_LIST_HEAD(&vma->mm_list);
2021 INIT_LIST_HEAD(&vma->exec_list);
2022 vma->vm = vm;
2023 vma->obj = obj;
2024
2025 switch (INTEL_INFO(vm->dev)->gen) {
2026 case 8:
2027 case 7:
2028 case 6:
2029 if (i915_is_ggtt(vm)) {
2030 vma->unbind_vma = ggtt_unbind_vma;
2031 vma->bind_vma = ggtt_bind_vma;
2032 } else {
2033 vma->unbind_vma = ppgtt_unbind_vma;
2034 vma->bind_vma = ppgtt_bind_vma;
2035 }
2036 break;
2037 case 5:
2038 case 4:
2039 case 3:
2040 case 2:
2041 BUG_ON(!i915_is_ggtt(vm));
2042 vma->unbind_vma = i915_ggtt_unbind_vma;
2043 vma->bind_vma = i915_ggtt_bind_vma;
2044 break;
2045 default:
2046 BUG();
2047 }
2048
2049 /* Keep GGTT vmas first to make debug easier */
2050 if (i915_is_ggtt(vm))
2051 list_add(&vma->vma_link, &obj->vma_list);
2052 else
2053 list_add_tail(&vma->vma_link, &obj->vma_list);
2054
2055 return vma;
2056 }
2057
2058 struct i915_vma *
2059 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2060 struct i915_address_space *vm)
2061 {
2062 struct i915_vma *vma;
2063
2064 vma = i915_gem_obj_to_vma(obj, vm);
2065 if (!vma)
2066 vma = __i915_gem_vma_create(obj, vm);
2067
2068 return vma;
2069 }
Linux kernel - Deliverables
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