drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 typedef uint32_t gtt_pte_t;
  32
  33 /* PPGTT stuff */
  34 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  35
  36 #define GEN6_PDE_VALID                  (1 << 0)
  37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  38 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  39
  40 #define GEN6_PTE_VALID                  (1 << 0)
  41 #define GEN6_PTE_UNCACHED               (1 << 1)
  42 #define HSW_PTE_UNCACHED                (0)
  43 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  44 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  45 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  46
  47 static inline gtt_pte_t pte_encode(struct drm_device *dev,
  48                                    dma_addr_t addr,
  49                                    enum i915_cache_level level)
  50 {
  51         gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 /* Haswell doesn't set L3 this way */
  57                 if (IS_HASWELL(dev))
  58                         pte |= GEN6_PTE_CACHE_LLC;
  59                 else
  60                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  61                 break;
  62         case I915_CACHE_LLC:
  63                 pte |= GEN6_PTE_CACHE_LLC;
  64                 break;
  65         case I915_CACHE_NONE:
  66                 if (IS_HASWELL(dev))
  67                         pte |= HSW_PTE_UNCACHED;
  68                 else
  69                         pte |= GEN6_PTE_UNCACHED;
  70                 break;
  71         default:
  72                 BUG();
  73         }
  74
  75
  76         return pte;
  77 }
  78
  79 /* PPGTT support for Sandybdrige/Gen6 and later */
  80 static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
  81                                    unsigned first_entry,
  82                                    unsigned num_entries)
  83 {
  84         gtt_pte_t *pt_vaddr;
  85         gtt_pte_t scratch_pte;
  86         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
  87         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
  88         unsigned last_pte, i;
  89
  90         scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr,
  91                                  I915_CACHE_LLC);
  92
  93         while (num_entries) {
  94                 last_pte = first_pte + num_entries;
  95                 if (last_pte > I915_PPGTT_PT_ENTRIES)
  96                         last_pte = I915_PPGTT_PT_ENTRIES;
  97
  98                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
  99
 100                 for (i = first_pte; i < last_pte; i++)
 101                         pt_vaddr[i] = scratch_pte;
 102
 103                 kunmap_atomic(pt_vaddr);
 104
 105                 num_entries -= last_pte - first_pte;
 106                 first_pte = 0;
 107                 act_pd++;
 108         }
 109 }
 110
 111 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 112 {
 113         struct drm_i915_private *dev_priv = dev->dev_private;
 114         struct i915_hw_ppgtt *ppgtt;
 115         unsigned first_pd_entry_in_global_pt;
 116         int i;
 117         int ret = -ENOMEM;
 118
 119         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 120          * entries. For aliasing ppgtt support we just steal them at the end for
 121          * now. */
 122         first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
 123
 124         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 125         if (!ppgtt)
 126                 return ret;
 127
 128         ppgtt->dev = dev;
 129         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 130         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 131                                   GFP_KERNEL);
 132         if (!ppgtt->pt_pages)
 133                 goto err_ppgtt;
 134
 135         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 136                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 137                 if (!ppgtt->pt_pages[i])
 138                         goto err_pt_alloc;
 139         }
 140
 141         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 142                                      GFP_KERNEL);
 143         if (!ppgtt->pt_dma_addr)
 144                 goto err_pt_alloc;
 145
 146         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 147                 dma_addr_t pt_addr;
 148
 149                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 150                                        PCI_DMA_BIDIRECTIONAL);
 151
 152                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 153                         ret = -EIO;
 154                         goto err_pd_pin;
 155
 156                 }
 157                 ppgtt->pt_dma_addr[i] = pt_addr;
 158         }
 159
 160         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 161
 162         i915_ppgtt_clear_range(ppgtt, 0,
 163                                ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 164
 165         ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
 166
 167         dev_priv->mm.aliasing_ppgtt = ppgtt;
 168
 169         return 0;
 170
 171 err_pd_pin:
 172         if (ppgtt->pt_dma_addr) {
 173                 for (i--; i >= 0; i--)
 174                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 175                                        4096, PCI_DMA_BIDIRECTIONAL);
 176         }
 177 err_pt_alloc:
 178         kfree(ppgtt->pt_dma_addr);
 179         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 180                 if (ppgtt->pt_pages[i])
 181                         __free_page(ppgtt->pt_pages[i]);
 182         }
 183         kfree(ppgtt->pt_pages);
 184 err_ppgtt:
 185         kfree(ppgtt);
 186
 187         return ret;
 188 }
 189
 190 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 194         int i;
 195
 196         if (!ppgtt)
 197                 return;
 198
 199         if (ppgtt->pt_dma_addr) {
 200                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 201                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 202                                        4096, PCI_DMA_BIDIRECTIONAL);
 203         }
 204
 205         kfree(ppgtt->pt_dma_addr);
 206         for (i = 0; i < ppgtt->num_pd_entries; i++)
 207                 __free_page(ppgtt->pt_pages[i]);
 208         kfree(ppgtt->pt_pages);
 209         kfree(ppgtt);
 210 }
 211
 212 static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
 213                                          const struct sg_table *pages,
 214                                          unsigned first_entry,
 215                                          enum i915_cache_level cache_level)
 216 {
 217         gtt_pte_t *pt_vaddr;
 218         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
 219         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 220         unsigned i, j, m, segment_len;
 221         dma_addr_t page_addr;
 222         struct scatterlist *sg;
 223
 224         /* init sg walking */
 225         sg = pages->sgl;
 226         i = 0;
 227         segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
 228         m = 0;
 229
 230         while (i < pages->nents) {
 231                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
 232
 233                 for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
 234                         page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 235                         pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr,
 236                                                  cache_level);
 237
 238                         /* grab the next page */
 239                         if (++m == segment_len) {
 240                                 if (++i == pages->nents)
 241                                         break;
 242
 243                                 sg = sg_next(sg);
 244                                 segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
 245                                 m = 0;
 246                         }
 247                 }
 248
 249                 kunmap_atomic(pt_vaddr);
 250
 251                 first_pte = 0;
 252                 act_pd++;
 253         }
 254 }
 255
 256 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 257                             struct drm_i915_gem_object *obj,
 258                             enum i915_cache_level cache_level)
 259 {
 260         i915_ppgtt_insert_sg_entries(ppgtt,
 261                                      obj->pages,
 262                                      obj->gtt_space->start >> PAGE_SHIFT,
 263                                      cache_level);
 264 }
 265
 266 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 267                               struct drm_i915_gem_object *obj)
 268 {
 269         i915_ppgtt_clear_range(ppgtt,
 270                                obj->gtt_space->start >> PAGE_SHIFT,
 271                                obj->base.size >> PAGE_SHIFT);
 272 }
 273
 274 void i915_gem_init_ppgtt(struct drm_device *dev)
 275 {
 276         drm_i915_private_t *dev_priv = dev->dev_private;
 277         uint32_t pd_offset;
 278         struct intel_ring_buffer *ring;
 279         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 280         gtt_pte_t __iomem *pd_addr;
 281         uint32_t pd_entry;
 282         int i;
 283
 284         if (!dev_priv->mm.aliasing_ppgtt)
 285                 return;
 286
 287
 288         pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
 289         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 290                 dma_addr_t pt_addr;
 291
 292                 pt_addr = ppgtt->pt_dma_addr[i];
 293                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 294                 pd_entry |= GEN6_PDE_VALID;
 295
 296                 writel(pd_entry, pd_addr + i);
 297         }
 298         readl(pd_addr);
 299
 300         pd_offset = ppgtt->pd_offset;
 301         pd_offset /= 64; /* in cachelines, */
 302         pd_offset <<= 16;
 303
 304         if (INTEL_INFO(dev)->gen == 6) {
 305                 uint32_t ecochk, gab_ctl, ecobits;
 306
 307                 ecobits = I915_READ(GAC_ECO_BITS);
 308                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 309
 310                 gab_ctl = I915_READ(GAB_CTL);
 311                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 312
 313                 ecochk = I915_READ(GAM_ECOCHK);
 314                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 315                                        ECOCHK_PPGTT_CACHE64B);
 316                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 317         } else if (INTEL_INFO(dev)->gen >= 7) {
 318                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 319                 /* GFX_MODE is per-ring on gen7+ */
 320         }
 321
 322         for_each_ring(ring, dev_priv, i) {
 323                 if (INTEL_INFO(dev)->gen >= 7)
 324                         I915_WRITE(RING_MODE_GEN7(ring),
 325                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 326
 327                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 328                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 329         }
 330 }
 331
 332 extern int intel_iommu_gfx_mapped;
 333 /* Certain Gen5 chipsets require require idling the GPU before
 334  * unmapping anything from the GTT when VT-d is enabled.
 335  */
 336 static inline bool needs_idle_maps(struct drm_device *dev)
 337 {
 338 #ifdef CONFIG_INTEL_IOMMU
 339         /* Query intel_iommu to see if we need the workaround. Presumably that
 340          * was loaded first.
 341          */
 342         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 343                 return true;
 344 #endif
 345         return false;
 346 }
 347
 348 static bool do_idling(struct drm_i915_private *dev_priv)
 349 {
 350         bool ret = dev_priv->mm.interruptible;
 351
 352         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 353                 dev_priv->mm.interruptible = false;
 354                 if (i915_gpu_idle(dev_priv->dev)) {
 355                         DRM_ERROR("Couldn't idle GPU\n");
 356                         /* Wait a bit, in hopes it avoids the hang */
 357                         udelay(10);
 358                 }
 359         }
 360
 361         return ret;
 362 }
 363
 364 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 365 {
 366         if (unlikely(dev_priv->gtt.do_idle_maps))
 367                 dev_priv->mm.interruptible = interruptible;
 368 }
 369
 370 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 371 {
 372         struct drm_i915_private *dev_priv = dev->dev_private;
 373         struct drm_i915_gem_object *obj;
 374
 375         /* First fill our portion of the GTT with scratch pages */
 376         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 377                                       dev_priv->gtt.total / PAGE_SIZE);
 378
 379         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 380                 i915_gem_clflush_object(obj);
 381                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 382         }
 383
 384         i915_gem_chipset_flush(dev);
 385 }
 386
 387 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 388 {
 389         if (obj->has_dma_mapping)
 390                 return 0;
 391
 392         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 393                         obj->pages->sgl, obj->pages->nents,
 394                         PCI_DMA_BIDIRECTIONAL))
 395                 return -ENOSPC;
 396
 397         return 0;
 398 }
 399
 400 /*
 401  * Binds an object into the global gtt with the specified cache level. The object
 402  * will be accessible to the GPU via commands whose operands reference offsets
 403  * within the global GTT as well as accessible by the GPU through the GMADR
 404  * mapped BAR (dev_priv->mm.gtt->gtt).
 405  */
 406 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 407                                      struct sg_table *st,
 408                                      unsigned int first_entry,
 409                                      enum i915_cache_level level)
 410 {
 411         struct drm_i915_private *dev_priv = dev->dev_private;
 412         struct scatterlist *sg = st->sgl;
 413         gtt_pte_t __iomem *gtt_entries =
 414                 (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 415         int unused, i = 0;
 416         unsigned int len, m = 0;
 417         dma_addr_t addr;
 418
 419         for_each_sg(st->sgl, sg, st->nents, unused) {
 420                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 421                 for (m = 0; m < len; m++) {
 422                         addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 423                         iowrite32(pte_encode(dev, addr, level), &gtt_entries[i]);
 424                         i++;
 425                 }
 426         }
 427
 428         /* XXX: This serves as a posting read to make sure that the PTE has
 429          * actually been updated. There is some concern that even though
 430          * registers and PTEs are within the same BAR that they are potentially
 431          * of NUMA access patterns. Therefore, even with the way we assume
 432          * hardware should work, we must keep this posting read for paranoia.
 433          */
 434         if (i != 0)
 435                 WARN_ON(readl(&gtt_entries[i-1]) != pte_encode(dev, addr, level));
 436
 437         /* This next bit makes the above posting read even more important. We
 438          * want to flush the TLBs only after we're certain all the PTE updates
 439          * have finished.
 440          */
 441         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 442         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 443 }
 444
 445 static void gen6_ggtt_clear_range(struct drm_device *dev,
 446                                   unsigned int first_entry,
 447                                   unsigned int num_entries)
 448 {
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450         gtt_pte_t scratch_pte;
 451         gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 452         const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
 453         int i;
 454
 455         if (WARN(num_entries > max_entries,
 456                  "First entry = %d; Num entries = %d (max=%d)\n",
 457                  first_entry, num_entries, max_entries))
 458                 num_entries = max_entries;
 459
 460         scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC);
 461         for (i = 0; i < num_entries; i++)
 462                 iowrite32(scratch_pte, &gtt_base[i]);
 463         readl(gtt_base);
 464 }
 465
 466
 467 static void i915_ggtt_insert_entries(struct drm_device *dev,
 468                                      struct sg_table *st,
 469                                      unsigned int pg_start,
 470                                      enum i915_cache_level cache_level)
 471 {
 472         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 473                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 474
 475         intel_gtt_insert_sg_entries(st, pg_start, flags);
 476
 477 }
 478
 479 static void i915_ggtt_clear_range(struct drm_device *dev,
 480                                   unsigned int first_entry,
 481                                   unsigned int num_entries)
 482 {
 483         intel_gtt_clear_range(first_entry, num_entries);
 484 }
 485
 486
 487 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 488                               enum i915_cache_level cache_level)
 489 {
 490         struct drm_device *dev = obj->base.dev;
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492
 493         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 494                                          obj->gtt_space->start >> PAGE_SHIFT,
 495                                          cache_level);
 496
 497         obj->has_global_gtt_mapping = 1;
 498 }
 499
 500 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 501 {
 502         struct drm_device *dev = obj->base.dev;
 503         struct drm_i915_private *dev_priv = dev->dev_private;
 504
 505         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 506                                       obj->gtt_space->start >> PAGE_SHIFT,
 507                                       obj->base.size >> PAGE_SHIFT);
 508
 509         obj->has_global_gtt_mapping = 0;
 510 }
 511
 512 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 513 {
 514         struct drm_device *dev = obj->base.dev;
 515         struct drm_i915_private *dev_priv = dev->dev_private;
 516         bool interruptible;
 517
 518         interruptible = do_idling(dev_priv);
 519
 520         if (!obj->has_dma_mapping)
 521                 dma_unmap_sg(&dev->pdev->dev,
 522                              obj->pages->sgl, obj->pages->nents,
 523                              PCI_DMA_BIDIRECTIONAL);
 524
 525         undo_idling(dev_priv, interruptible);
 526 }
 527
 528 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 529                                   unsigned long color,
 530                                   unsigned long *start,
 531                                   unsigned long *end)
 532 {
 533         if (node->color != color)
 534                 *start += 4096;
 535
 536         if (!list_empty(&node->node_list)) {
 537                 node = list_entry(node->node_list.next,
 538                                   struct drm_mm_node,
 539                                   node_list);
 540                 if (node->allocated && node->color != color)
 541                         *end -= 4096;
 542         }
 543 }
 544
 545 void i915_gem_setup_global_gtt(struct drm_device *dev,
 546                                unsigned long start,
 547                                unsigned long mappable_end,
 548                                unsigned long end)
 549 {
 550         drm_i915_private_t *dev_priv = dev->dev_private;
 551         struct drm_mm_node *entry;
 552         struct drm_i915_gem_object *obj;
 553         unsigned long hole_start, hole_end;
 554
 555         BUG_ON(mappable_end > end);
 556
 557         /* Subtract the guard page ... */
 558         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 559         if (!HAS_LLC(dev))
 560                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 561
 562         /* Mark any preallocated objects as occupied */
 563         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 564                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 565                               obj->gtt_offset, obj->base.size);
 566
 567                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 568                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 569                                                      obj->gtt_offset,
 570                                                      obj->base.size,
 571                                                      false);
 572                 obj->has_global_gtt_mapping = 1;
 573         }
 574
 575         dev_priv->gtt.start = start;
 576         dev_priv->gtt.total = end - start;
 577
 578         /* Clear any non-preallocated blocks */
 579         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 580                              hole_start, hole_end) {
 581                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 582                               hole_start, hole_end);
 583                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 584                                               (hole_end-hole_start) / PAGE_SIZE);
 585         }
 586
 587         /* And finally clear the reserved guard page */
 588         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 589 }
 590
 591 static bool
 592 intel_enable_ppgtt(struct drm_device *dev)
 593 {
 594         if (i915_enable_ppgtt >= 0)
 595                 return i915_enable_ppgtt;
 596
 597 #ifdef CONFIG_INTEL_IOMMU
 598         /* Disable ppgtt on SNB if VT-d is on. */
 599         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 600                 return false;
 601 #endif
 602
 603         return true;
 604 }
 605
 606 void i915_gem_init_global_gtt(struct drm_device *dev)
 607 {
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609         unsigned long gtt_size, mappable_size;
 610         int ret;
 611
 612         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
 613         mappable_size = dev_priv->gtt.mappable_end;
 614
 615         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 616                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 617                  * aperture accordingly when using aliasing ppgtt. */
 618                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 619
 620                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 621
 622                 ret = i915_gem_init_aliasing_ppgtt(dev);
 623                 if (ret) {
 624                         mutex_unlock(&dev->struct_mutex);
 625                         return;
 626                 }
 627         } else {
 628                 /* Let GEM Manage all of the aperture.
 629                  *
 630                  * However, leave one page at the end still bound to the scratch
 631                  * page.  There are a number of places where the hardware
 632                  * apparently prefetches past the end of the object, and we've
 633                  * seen multiple hangs with the GPU head pointer stuck in a
 634                  * batchbuffer bound at the last page of the aperture.  One page
 635                  * should be enough to keep any prefetching inside of the
 636                  * aperture.
 637                  */
 638                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 639         }
 640 }
 641
 642 static int setup_scratch_page(struct drm_device *dev)
 643 {
 644         struct drm_i915_private *dev_priv = dev->dev_private;
 645         struct page *page;
 646         dma_addr_t dma_addr;
 647
 648         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 649         if (page == NULL)
 650                 return -ENOMEM;
 651         get_page(page);
 652         set_pages_uc(page, 1);
 653
 654 #ifdef CONFIG_INTEL_IOMMU
 655         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 656                                 PCI_DMA_BIDIRECTIONAL);
 657         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 658                 return -EINVAL;
 659 #else
 660         dma_addr = page_to_phys(page);
 661 #endif
 662         dev_priv->gtt.scratch_page = page;
 663         dev_priv->gtt.scratch_page_dma = dma_addr;
 664
 665         return 0;
 666 }
 667
 668 static void teardown_scratch_page(struct drm_device *dev)
 669 {
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 672         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 673                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 674         put_page(dev_priv->gtt.scratch_page);
 675         __free_page(dev_priv->gtt.scratch_page);
 676 }
 677
 678 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 679 {
 680         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 681         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 682         return snb_gmch_ctl << 20;
 683 }
 684
 685 static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)
 686 {
 687         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 688         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 689         return snb_gmch_ctl << 25; /* 32 MB units */
 690 }
 691
 692 static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
 693 {
 694         static const int stolen_decoder[] = {
 695                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 696         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 697         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 698         return stolen_decoder[snb_gmch_ctl] << 20;
 699 }
 700
 701 int i915_gem_gtt_init(struct drm_device *dev)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         phys_addr_t gtt_bus_addr;
 705         u16 snb_gmch_ctl;
 706         int ret;
 707
 708         dev_priv->gtt.mappable_base = pci_resource_start(dev->pdev, 2);
 709         dev_priv->gtt.mappable_end = pci_resource_len(dev->pdev, 2);
 710
 711         /* On modern platforms we need not worry ourself with the legacy
 712          * hostbridge query stuff. Skip it entirely
 713          */
 714         if (INTEL_INFO(dev)->gen < 6) {
 715                 ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
 716                 if (!ret) {
 717                         DRM_ERROR("failed to set up gmch\n");
 718                         return -EIO;
 719                 }
 720
 721                 dev_priv->mm.gtt = intel_gtt_get();
 722                 if (!dev_priv->mm.gtt) {
 723                         DRM_ERROR("Failed to initialize GTT\n");
 724                         intel_gmch_remove();
 725                         return -ENODEV;
 726                 }
 727
 728                 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev);
 729
 730                 dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 731                 dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 732
 733                 return 0;
 734         }
 735
 736         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 737                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 738
 739         dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL);
 740         if (!dev_priv->mm.gtt)
 741                 return -ENOMEM;
 742
 743         /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
 744         gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
 745
 746         /* i9xx_setup */
 747         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 748         dev_priv->mm.gtt->gtt_total_entries =
 749                 gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
 750         if (INTEL_INFO(dev)->gen < 7)
 751                 dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
 752         else
 753                 dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
 754
 755         /* 64/512MB is the current min/max we actually know of, but this is just a
 756          * coarse sanity check.
 757          */
 758         if ((dev_priv->gtt.mappable_end < (64<<20) ||
 759             (dev_priv->gtt.mappable_end > (512<<20)))) {
 760                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 761                           dev_priv->gtt.mappable_end);
 762                 ret = -ENXIO;
 763                 goto err_out;
 764         }
 765
 766         ret = setup_scratch_page(dev);
 767         if (ret) {
 768                 DRM_ERROR("Scratch setup failed\n");
 769                 goto err_out;
 770         }
 771
 772         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr,
 773                                        dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t));
 774         if (!dev_priv->gtt.gsm) {
 775                 DRM_ERROR("Failed to map the gtt page table\n");
 776                 teardown_scratch_page(dev);
 777                 ret = -ENOMEM;
 778                 goto err_out;
 779         }
 780
 781         /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
 782         DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);
 783         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv->gtt.mappable_end >> 20);
 784         DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);
 785
 786         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 787         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 788
 789         return 0;
 790
 791 err_out:
 792         kfree(dev_priv->mm.gtt);
 793         if (INTEL_INFO(dev)->gen < 6)
 794                 intel_gmch_remove();
 795         return ret;
 796 }
 797
 798 void i915_gem_gtt_fini(struct drm_device *dev)
 799 {
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         iounmap(dev_priv->gtt.gsm);
 802         teardown_scratch_page(dev);
 803         if (INTEL_INFO(dev)->gen < 6)
 804                 intel_gmch_remove();
 805         kfree(dev_priv->mm.gtt);
 806 }