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drm/i915: Rework ppgtt init to no require an aliasing ppgtt
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
35
36 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
37 {
38 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
39 return 0;
40
41 if (enable_ppgtt == 1)
42 return 1;
43
44 if (enable_ppgtt == 2 && HAS_PPGTT(dev))
45 return 2;
46
47 #ifdef CONFIG_INTEL_IOMMU
48 /* Disable ppgtt on SNB if VT-d is on. */
49 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
50 DRM_INFO("Disabling PPGTT because VT-d is on\n");
51 return 0;
52 }
53 #endif
54
55 /* Early VLV doesn't have this */
56 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
57 dev->pdev->revision < 0xb) {
58 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
59 return 0;
60 }
61
62 return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
63 }
64
65
66 static void ppgtt_bind_vma(struct i915_vma *vma,
67 enum i915_cache_level cache_level,
68 u32 flags);
69 static void ppgtt_unbind_vma(struct i915_vma *vma);
70
71 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
72 enum i915_cache_level level,
73 bool valid)
74 {
75 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
76 pte |= addr;
77
78 switch (level) {
79 case I915_CACHE_NONE:
80 pte |= PPAT_UNCACHED_INDEX;
81 break;
82 case I915_CACHE_WT:
83 pte |= PPAT_DISPLAY_ELLC_INDEX;
84 break;
85 default:
86 pte |= PPAT_CACHED_INDEX;
87 break;
88 }
89
90 return pte;
91 }
92
93 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
94 dma_addr_t addr,
95 enum i915_cache_level level)
96 {
97 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
98 pde |= addr;
99 if (level != I915_CACHE_NONE)
100 pde |= PPAT_CACHED_PDE_INDEX;
101 else
102 pde |= PPAT_UNCACHED_INDEX;
103 return pde;
104 }
105
106 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
107 enum i915_cache_level level,
108 bool valid, u32 unused)
109 {
110 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
111 pte |= GEN6_PTE_ADDR_ENCODE(addr);
112
113 switch (level) {
114 case I915_CACHE_L3_LLC:
115 case I915_CACHE_LLC:
116 pte |= GEN6_PTE_CACHE_LLC;
117 break;
118 case I915_CACHE_NONE:
119 pte |= GEN6_PTE_UNCACHED;
120 break;
121 default:
122 WARN_ON(1);
123 }
124
125 return pte;
126 }
127
128 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
129 enum i915_cache_level level,
130 bool valid, u32 unused)
131 {
132 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
133 pte |= GEN6_PTE_ADDR_ENCODE(addr);
134
135 switch (level) {
136 case I915_CACHE_L3_LLC:
137 pte |= GEN7_PTE_CACHE_L3_LLC;
138 break;
139 case I915_CACHE_LLC:
140 pte |= GEN6_PTE_CACHE_LLC;
141 break;
142 case I915_CACHE_NONE:
143 pte |= GEN6_PTE_UNCACHED;
144 break;
145 default:
146 WARN_ON(1);
147 }
148
149 return pte;
150 }
151
152 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
153 enum i915_cache_level level,
154 bool valid, u32 flags)
155 {
156 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
157 pte |= GEN6_PTE_ADDR_ENCODE(addr);
158
159 /* Mark the page as writeable. Other platforms don't have a
160 * setting for read-only/writable, so this matches that behavior.
161 */
162 if (!(flags & PTE_READ_ONLY))
163 pte |= BYT_PTE_WRITEABLE;
164
165 if (level != I915_CACHE_NONE)
166 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
167
168 return pte;
169 }
170
171 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
172 enum i915_cache_level level,
173 bool valid, u32 unused)
174 {
175 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
176 pte |= HSW_PTE_ADDR_ENCODE(addr);
177
178 if (level != I915_CACHE_NONE)
179 pte |= HSW_WB_LLC_AGE3;
180
181 return pte;
182 }
183
184 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
185 enum i915_cache_level level,
186 bool valid, u32 unused)
187 {
188 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
189 pte |= HSW_PTE_ADDR_ENCODE(addr);
190
191 switch (level) {
192 case I915_CACHE_NONE:
193 break;
194 case I915_CACHE_WT:
195 pte |= HSW_WT_ELLC_LLC_AGE3;
196 break;
197 default:
198 pte |= HSW_WB_ELLC_LLC_AGE3;
199 break;
200 }
201
202 return pte;
203 }
204
205 /* Broadwell Page Directory Pointer Descriptors */
206 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
207 uint64_t val, bool synchronous)
208 {
209 struct drm_i915_private *dev_priv = ring->dev->dev_private;
210 int ret;
211
212 BUG_ON(entry >= 4);
213
214 if (synchronous) {
215 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
216 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
217 return 0;
218 }
219
220 ret = intel_ring_begin(ring, 6);
221 if (ret)
222 return ret;
223
224 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
225 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
226 intel_ring_emit(ring, (u32)(val >> 32));
227 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
228 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
229 intel_ring_emit(ring, (u32)(val));
230 intel_ring_advance(ring);
231
232 return 0;
233 }
234
235 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
236 struct intel_engine_cs *ring,
237 bool synchronous)
238 {
239 int i, ret;
240
241 /* bit of a hack to find the actual last used pd */
242 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
243
244 for (i = used_pd - 1; i >= 0; i--) {
245 dma_addr_t addr = ppgtt->pd_dma_addr[i];
246 ret = gen8_write_pdp(ring, i, addr, synchronous);
247 if (ret)
248 return ret;
249 }
250
251 return 0;
252 }
253
254 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
255 uint64_t start,
256 uint64_t length,
257 bool use_scratch)
258 {
259 struct i915_hw_ppgtt *ppgtt =
260 container_of(vm, struct i915_hw_ppgtt, base);
261 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
262 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
263 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
264 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
265 unsigned num_entries = length >> PAGE_SHIFT;
266 unsigned last_pte, i;
267
268 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
269 I915_CACHE_LLC, use_scratch);
270
271 while (num_entries) {
272 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
273
274 last_pte = pte + num_entries;
275 if (last_pte > GEN8_PTES_PER_PAGE)
276 last_pte = GEN8_PTES_PER_PAGE;
277
278 pt_vaddr = kmap_atomic(page_table);
279
280 for (i = pte; i < last_pte; i++) {
281 pt_vaddr[i] = scratch_pte;
282 num_entries--;
283 }
284
285 if (!HAS_LLC(ppgtt->base.dev))
286 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
287 kunmap_atomic(pt_vaddr);
288
289 pte = 0;
290 if (++pde == GEN8_PDES_PER_PAGE) {
291 pdpe++;
292 pde = 0;
293 }
294 }
295 }
296
297 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
298 struct sg_table *pages,
299 uint64_t start,
300 enum i915_cache_level cache_level, u32 unused)
301 {
302 struct i915_hw_ppgtt *ppgtt =
303 container_of(vm, struct i915_hw_ppgtt, base);
304 gen8_gtt_pte_t *pt_vaddr;
305 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
306 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
307 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
308 struct sg_page_iter sg_iter;
309
310 pt_vaddr = NULL;
311
312 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
313 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
314 break;
315
316 if (pt_vaddr == NULL)
317 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
318
319 pt_vaddr[pte] =
320 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
321 cache_level, true);
322 if (++pte == GEN8_PTES_PER_PAGE) {
323 if (!HAS_LLC(ppgtt->base.dev))
324 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
325 kunmap_atomic(pt_vaddr);
326 pt_vaddr = NULL;
327 if (++pde == GEN8_PDES_PER_PAGE) {
328 pdpe++;
329 pde = 0;
330 }
331 pte = 0;
332 }
333 }
334 if (pt_vaddr) {
335 if (!HAS_LLC(ppgtt->base.dev))
336 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
337 kunmap_atomic(pt_vaddr);
338 }
339 }
340
341 static void gen8_free_page_tables(struct page **pt_pages)
342 {
343 int i;
344
345 if (pt_pages == NULL)
346 return;
347
348 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
349 if (pt_pages[i])
350 __free_pages(pt_pages[i], 0);
351 }
352
353 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
354 {
355 int i;
356
357 for (i = 0; i < ppgtt->num_pd_pages; i++) {
358 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
359 kfree(ppgtt->gen8_pt_pages[i]);
360 kfree(ppgtt->gen8_pt_dma_addr[i]);
361 }
362
363 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
364 }
365
366 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
367 {
368 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
369 int i, j;
370
371 for (i = 0; i < ppgtt->num_pd_pages; i++) {
372 /* TODO: In the future we'll support sparse mappings, so this
373 * will have to change. */
374 if (!ppgtt->pd_dma_addr[i])
375 continue;
376
377 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
378 PCI_DMA_BIDIRECTIONAL);
379
380 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
381 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
382 if (addr)
383 pci_unmap_page(hwdev, addr, PAGE_SIZE,
384 PCI_DMA_BIDIRECTIONAL);
385 }
386 }
387 }
388
389 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
390 {
391 struct i915_hw_ppgtt *ppgtt =
392 container_of(vm, struct i915_hw_ppgtt, base);
393
394 list_del(&vm->global_link);
395 drm_mm_takedown(&vm->mm);
396
397 gen8_ppgtt_unmap_pages(ppgtt);
398 gen8_ppgtt_free(ppgtt);
399 }
400
401 static struct page **__gen8_alloc_page_tables(void)
402 {
403 struct page **pt_pages;
404 int i;
405
406 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
407 if (!pt_pages)
408 return ERR_PTR(-ENOMEM);
409
410 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
411 pt_pages[i] = alloc_page(GFP_KERNEL);
412 if (!pt_pages[i])
413 goto bail;
414 }
415
416 return pt_pages;
417
418 bail:
419 gen8_free_page_tables(pt_pages);
420 kfree(pt_pages);
421 return ERR_PTR(-ENOMEM);
422 }
423
424 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
425 const int max_pdp)
426 {
427 struct page **pt_pages[GEN8_LEGACY_PDPS];
428 int i, ret;
429
430 for (i = 0; i < max_pdp; i++) {
431 pt_pages[i] = __gen8_alloc_page_tables();
432 if (IS_ERR(pt_pages[i])) {
433 ret = PTR_ERR(pt_pages[i]);
434 goto unwind_out;
435 }
436 }
437
438 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
439 * "atomic" - for cleanup purposes.
440 */
441 for (i = 0; i < max_pdp; i++)
442 ppgtt->gen8_pt_pages[i] = pt_pages[i];
443
444 return 0;
445
446 unwind_out:
447 while (i--) {
448 gen8_free_page_tables(pt_pages[i]);
449 kfree(pt_pages[i]);
450 }
451
452 return ret;
453 }
454
455 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
456 {
457 int i;
458
459 for (i = 0; i < ppgtt->num_pd_pages; i++) {
460 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
461 sizeof(dma_addr_t),
462 GFP_KERNEL);
463 if (!ppgtt->gen8_pt_dma_addr[i])
464 return -ENOMEM;
465 }
466
467 return 0;
468 }
469
470 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
471 const int max_pdp)
472 {
473 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
474 if (!ppgtt->pd_pages)
475 return -ENOMEM;
476
477 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
478 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
479
480 return 0;
481 }
482
483 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
484 const int max_pdp)
485 {
486 int ret;
487
488 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
489 if (ret)
490 return ret;
491
492 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
493 if (ret) {
494 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
495 return ret;
496 }
497
498 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
499
500 ret = gen8_ppgtt_allocate_dma(ppgtt);
501 if (ret)
502 gen8_ppgtt_free(ppgtt);
503
504 return ret;
505 }
506
507 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
508 const int pd)
509 {
510 dma_addr_t pd_addr;
511 int ret;
512
513 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
514 &ppgtt->pd_pages[pd], 0,
515 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
516
517 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
518 if (ret)
519 return ret;
520
521 ppgtt->pd_dma_addr[pd] = pd_addr;
522
523 return 0;
524 }
525
526 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
527 const int pd,
528 const int pt)
529 {
530 dma_addr_t pt_addr;
531 struct page *p;
532 int ret;
533
534 p = ppgtt->gen8_pt_pages[pd][pt];
535 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
536 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
537 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
538 if (ret)
539 return ret;
540
541 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
542
543 return 0;
544 }
545
546 /**
547 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
548 * with a net effect resembling a 2-level page table in normal x86 terms. Each
549 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
550 * space.
551 *
552 * FIXME: split allocation into smaller pieces. For now we only ever do this
553 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
554 * TODO: Do something with the size parameter
555 */
556 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
557 {
558 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
559 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
560 int i, j, ret;
561
562 if (size % (1<<30))
563 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
564
565 /* 1. Do all our allocations for page directories and page tables. */
566 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
567 if (ret)
568 return ret;
569
570 /*
571 * 2. Create DMA mappings for the page directories and page tables.
572 */
573 for (i = 0; i < max_pdp; i++) {
574 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
575 if (ret)
576 goto bail;
577
578 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
579 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
580 if (ret)
581 goto bail;
582 }
583 }
584
585 /*
586 * 3. Map all the page directory entires to point to the page tables
587 * we've allocated.
588 *
589 * For now, the PPGTT helper functions all require that the PDEs are
590 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
591 * will never need to touch the PDEs again.
592 */
593 for (i = 0; i < max_pdp; i++) {
594 gen8_ppgtt_pde_t *pd_vaddr;
595 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
596 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
597 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
598 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
599 I915_CACHE_LLC);
600 }
601 if (!HAS_LLC(ppgtt->base.dev))
602 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
603 kunmap_atomic(pd_vaddr);
604 }
605
606 ppgtt->switch_mm = gen8_mm_switch;
607 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
608 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
609 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
610 ppgtt->base.start = 0;
611 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
612
613 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
614
615 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
616 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
617 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
618 ppgtt->num_pd_entries,
619 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
620 return 0;
621
622 bail:
623 gen8_ppgtt_unmap_pages(ppgtt);
624 gen8_ppgtt_free(ppgtt);
625 return ret;
626 }
627
628 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
629 {
630 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
631 struct i915_address_space *vm = &ppgtt->base;
632 gen6_gtt_pte_t __iomem *pd_addr;
633 gen6_gtt_pte_t scratch_pte;
634 uint32_t pd_entry;
635 int pte, pde;
636
637 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
638
639 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
640 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
641
642 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
643 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
644 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
645 u32 expected;
646 gen6_gtt_pte_t *pt_vaddr;
647 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
648 pd_entry = readl(pd_addr + pde);
649 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
650
651 if (pd_entry != expected)
652 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
653 pde,
654 pd_entry,
655 expected);
656 seq_printf(m, "\tPDE: %x\n", pd_entry);
657
658 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
659 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
660 unsigned long va =
661 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
662 (pte * PAGE_SIZE);
663 int i;
664 bool found = false;
665 for (i = 0; i < 4; i++)
666 if (pt_vaddr[pte + i] != scratch_pte)
667 found = true;
668 if (!found)
669 continue;
670
671 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
672 for (i = 0; i < 4; i++) {
673 if (pt_vaddr[pte + i] != scratch_pte)
674 seq_printf(m, " %08x", pt_vaddr[pte + i]);
675 else
676 seq_puts(m, " SCRATCH ");
677 }
678 seq_puts(m, "\n");
679 }
680 kunmap_atomic(pt_vaddr);
681 }
682 }
683
684 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
685 {
686 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
687 gen6_gtt_pte_t __iomem *pd_addr;
688 uint32_t pd_entry;
689 int i;
690
691 WARN_ON(ppgtt->pd_offset & 0x3f);
692 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
693 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
694 for (i = 0; i < ppgtt->num_pd_entries; i++) {
695 dma_addr_t pt_addr;
696
697 pt_addr = ppgtt->pt_dma_addr[i];
698 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
699 pd_entry |= GEN6_PDE_VALID;
700
701 writel(pd_entry, pd_addr + i);
702 }
703 readl(pd_addr);
704 }
705
706 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
707 {
708 BUG_ON(ppgtt->pd_offset & 0x3f);
709
710 return (ppgtt->pd_offset / 64) << 16;
711 }
712
713 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
714 struct intel_engine_cs *ring,
715 bool synchronous)
716 {
717 struct drm_device *dev = ppgtt->base.dev;
718 struct drm_i915_private *dev_priv = dev->dev_private;
719 int ret;
720
721 /* If we're in reset, we can assume the GPU is sufficiently idle to
722 * manually frob these bits. Ideally we could use the ring functions,
723 * except our error handling makes it quite difficult (can't use
724 * intel_ring_begin, ring->flush, or intel_ring_advance)
725 *
726 * FIXME: We should try not to special case reset
727 */
728 if (synchronous ||
729 i915_reset_in_progress(&dev_priv->gpu_error)) {
730 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
731 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
732 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
733 POSTING_READ(RING_PP_DIR_BASE(ring));
734 return 0;
735 }
736
737 /* NB: TLBs must be flushed and invalidated before a switch */
738 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
739 if (ret)
740 return ret;
741
742 ret = intel_ring_begin(ring, 6);
743 if (ret)
744 return ret;
745
746 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
747 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
748 intel_ring_emit(ring, PP_DIR_DCLV_2G);
749 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
750 intel_ring_emit(ring, get_pd_offset(ppgtt));
751 intel_ring_emit(ring, MI_NOOP);
752 intel_ring_advance(ring);
753
754 return 0;
755 }
756
757 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
758 struct intel_engine_cs *ring,
759 bool synchronous)
760 {
761 struct drm_device *dev = ppgtt->base.dev;
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 int ret;
764
765 /* If we're in reset, we can assume the GPU is sufficiently idle to
766 * manually frob these bits. Ideally we could use the ring functions,
767 * except our error handling makes it quite difficult (can't use
768 * intel_ring_begin, ring->flush, or intel_ring_advance)
769 *
770 * FIXME: We should try not to special case reset
771 */
772 if (synchronous ||
773 i915_reset_in_progress(&dev_priv->gpu_error)) {
774 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
775 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
776 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
777 POSTING_READ(RING_PP_DIR_BASE(ring));
778 return 0;
779 }
780
781 /* NB: TLBs must be flushed and invalidated before a switch */
782 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
783 if (ret)
784 return ret;
785
786 ret = intel_ring_begin(ring, 6);
787 if (ret)
788 return ret;
789
790 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
791 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
792 intel_ring_emit(ring, PP_DIR_DCLV_2G);
793 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
794 intel_ring_emit(ring, get_pd_offset(ppgtt));
795 intel_ring_emit(ring, MI_NOOP);
796 intel_ring_advance(ring);
797
798 /* XXX: RCS is the only one to auto invalidate the TLBs? */
799 if (ring->id != RCS) {
800 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
801 if (ret)
802 return ret;
803 }
804
805 return 0;
806 }
807
808 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
809 struct intel_engine_cs *ring,
810 bool synchronous)
811 {
812 struct drm_device *dev = ppgtt->base.dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814
815 if (!synchronous)
816 return 0;
817
818 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
819 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
820
821 POSTING_READ(RING_PP_DIR_DCLV(ring));
822
823 return 0;
824 }
825
826 static void gen8_ppgtt_enable(struct drm_device *dev)
827 {
828 struct drm_i915_private *dev_priv = dev->dev_private;
829 struct intel_engine_cs *ring;
830 int j;
831
832 for_each_ring(ring, dev_priv, j) {
833 I915_WRITE(RING_MODE_GEN7(ring),
834 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
835 }
836 }
837
838 static void gen7_ppgtt_enable(struct drm_device *dev)
839 {
840 struct drm_i915_private *dev_priv = dev->dev_private;
841 struct intel_engine_cs *ring;
842 uint32_t ecochk, ecobits;
843 int i;
844
845 ecobits = I915_READ(GAC_ECO_BITS);
846 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
847
848 ecochk = I915_READ(GAM_ECOCHK);
849 if (IS_HASWELL(dev)) {
850 ecochk |= ECOCHK_PPGTT_WB_HSW;
851 } else {
852 ecochk |= ECOCHK_PPGTT_LLC_IVB;
853 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
854 }
855 I915_WRITE(GAM_ECOCHK, ecochk);
856
857 for_each_ring(ring, dev_priv, i) {
858 /* GFX_MODE is per-ring on gen7+ */
859 I915_WRITE(RING_MODE_GEN7(ring),
860 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
861 }
862 }
863
864 static void gen6_ppgtt_enable(struct drm_device *dev)
865 {
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 uint32_t ecochk, gab_ctl, ecobits;
868
869 ecobits = I915_READ(GAC_ECO_BITS);
870 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
871 ECOBITS_PPGTT_CACHE64B);
872
873 gab_ctl = I915_READ(GAB_CTL);
874 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
875
876 ecochk = I915_READ(GAM_ECOCHK);
877 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
878
879 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
880 }
881
882 /* PPGTT support for Sandybdrige/Gen6 and later */
883 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
884 uint64_t start,
885 uint64_t length,
886 bool use_scratch)
887 {
888 struct i915_hw_ppgtt *ppgtt =
889 container_of(vm, struct i915_hw_ppgtt, base);
890 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
891 unsigned first_entry = start >> PAGE_SHIFT;
892 unsigned num_entries = length >> PAGE_SHIFT;
893 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
894 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
895 unsigned last_pte, i;
896
897 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
898
899 while (num_entries) {
900 last_pte = first_pte + num_entries;
901 if (last_pte > I915_PPGTT_PT_ENTRIES)
902 last_pte = I915_PPGTT_PT_ENTRIES;
903
904 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
905
906 for (i = first_pte; i < last_pte; i++)
907 pt_vaddr[i] = scratch_pte;
908
909 kunmap_atomic(pt_vaddr);
910
911 num_entries -= last_pte - first_pte;
912 first_pte = 0;
913 act_pt++;
914 }
915 }
916
917 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
918 struct sg_table *pages,
919 uint64_t start,
920 enum i915_cache_level cache_level, u32 flags)
921 {
922 struct i915_hw_ppgtt *ppgtt =
923 container_of(vm, struct i915_hw_ppgtt, base);
924 gen6_gtt_pte_t *pt_vaddr;
925 unsigned first_entry = start >> PAGE_SHIFT;
926 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
927 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
928 struct sg_page_iter sg_iter;
929
930 pt_vaddr = NULL;
931 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
932 if (pt_vaddr == NULL)
933 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
934
935 pt_vaddr[act_pte] =
936 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
937 cache_level, true, flags);
938
939 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
940 kunmap_atomic(pt_vaddr);
941 pt_vaddr = NULL;
942 act_pt++;
943 act_pte = 0;
944 }
945 }
946 if (pt_vaddr)
947 kunmap_atomic(pt_vaddr);
948 }
949
950 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
951 {
952 int i;
953
954 if (ppgtt->pt_dma_addr) {
955 for (i = 0; i < ppgtt->num_pd_entries; i++)
956 pci_unmap_page(ppgtt->base.dev->pdev,
957 ppgtt->pt_dma_addr[i],
958 4096, PCI_DMA_BIDIRECTIONAL);
959 }
960 }
961
962 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
963 {
964 int i;
965
966 kfree(ppgtt->pt_dma_addr);
967 for (i = 0; i < ppgtt->num_pd_entries; i++)
968 __free_page(ppgtt->pt_pages[i]);
969 kfree(ppgtt->pt_pages);
970 }
971
972 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
973 {
974 struct i915_hw_ppgtt *ppgtt =
975 container_of(vm, struct i915_hw_ppgtt, base);
976
977 list_del(&vm->global_link);
978 drm_mm_takedown(&ppgtt->base.mm);
979 drm_mm_remove_node(&ppgtt->node);
980
981 gen6_ppgtt_unmap_pages(ppgtt);
982 gen6_ppgtt_free(ppgtt);
983 }
984
985 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
986 {
987 struct drm_device *dev = ppgtt->base.dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 bool retried = false;
990 int ret;
991
992 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
993 * allocator works in address space sizes, so it's multiplied by page
994 * size. We allocate at the top of the GTT to avoid fragmentation.
995 */
996 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
997 alloc:
998 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
999 &ppgtt->node, GEN6_PD_SIZE,
1000 GEN6_PD_ALIGN, 0,
1001 0, dev_priv->gtt.base.total,
1002 DRM_MM_TOPDOWN);
1003 if (ret == -ENOSPC && !retried) {
1004 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1005 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1006 I915_CACHE_NONE,
1007 0, dev_priv->gtt.base.total,
1008 0);
1009 if (ret)
1010 return ret;
1011
1012 retried = true;
1013 goto alloc;
1014 }
1015
1016 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1017 DRM_DEBUG("Forced to use aperture for PDEs\n");
1018
1019 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1020 return ret;
1021 }
1022
1023 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1024 {
1025 int i;
1026
1027 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1028 GFP_KERNEL);
1029
1030 if (!ppgtt->pt_pages)
1031 return -ENOMEM;
1032
1033 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1034 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1035 if (!ppgtt->pt_pages[i]) {
1036 gen6_ppgtt_free(ppgtt);
1037 return -ENOMEM;
1038 }
1039 }
1040
1041 return 0;
1042 }
1043
1044 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1045 {
1046 int ret;
1047
1048 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1049 if (ret)
1050 return ret;
1051
1052 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1053 if (ret) {
1054 drm_mm_remove_node(&ppgtt->node);
1055 return ret;
1056 }
1057
1058 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1059 GFP_KERNEL);
1060 if (!ppgtt->pt_dma_addr) {
1061 drm_mm_remove_node(&ppgtt->node);
1062 gen6_ppgtt_free(ppgtt);
1063 return -ENOMEM;
1064 }
1065
1066 return 0;
1067 }
1068
1069 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1070 {
1071 struct drm_device *dev = ppgtt->base.dev;
1072 int i;
1073
1074 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1075 dma_addr_t pt_addr;
1076
1077 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1078 PCI_DMA_BIDIRECTIONAL);
1079
1080 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1081 gen6_ppgtt_unmap_pages(ppgtt);
1082 return -EIO;
1083 }
1084
1085 ppgtt->pt_dma_addr[i] = pt_addr;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1092 {
1093 struct drm_device *dev = ppgtt->base.dev;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1098 if (IS_GEN6(dev)) {
1099 ppgtt->switch_mm = gen6_mm_switch;
1100 } else if (IS_HASWELL(dev)) {
1101 ppgtt->switch_mm = hsw_mm_switch;
1102 } else if (IS_GEN7(dev)) {
1103 ppgtt->switch_mm = gen7_mm_switch;
1104 } else
1105 BUG();
1106
1107 ret = gen6_ppgtt_alloc(ppgtt);
1108 if (ret)
1109 return ret;
1110
1111 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1112 if (ret) {
1113 gen6_ppgtt_free(ppgtt);
1114 return ret;
1115 }
1116
1117 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1118 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1119 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1120 ppgtt->base.start = 0;
1121 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1122 ppgtt->debug_dump = gen6_dump_ppgtt;
1123
1124 ppgtt->pd_offset =
1125 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1126
1127 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1128
1129 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1130 ppgtt->node.size >> 20,
1131 ppgtt->node.start / PAGE_SIZE);
1132
1133 return 0;
1134 }
1135
1136 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1137 {
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139 int ret = 0;
1140
1141 ppgtt->base.dev = dev;
1142 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1143
1144 if (INTEL_INFO(dev)->gen < 8)
1145 ret = gen6_ppgtt_init(ppgtt);
1146 else if (IS_GEN8(dev))
1147 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1148 else
1149 BUG();
1150
1151 if (!ret) {
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 kref_init(&ppgtt->ref);
1154 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1155 ppgtt->base.total);
1156 i915_init_vm(dev_priv, &ppgtt->base);
1157 if (INTEL_INFO(dev)->gen < 8) {
1158 gen6_write_pdes(ppgtt);
1159 DRM_DEBUG("Adding PPGTT at offset %x\n",
1160 ppgtt->pd_offset << 10);
1161 }
1162 }
1163
1164 return ret;
1165 }
1166
1167 int i915_ppgtt_init_hw(struct drm_device *dev)
1168 {
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 struct intel_engine_cs *ring;
1171 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1172 int i, ret = 0;
1173
1174 if (!USES_PPGTT(dev))
1175 return 0;
1176
1177 if (IS_GEN6(dev))
1178 gen6_ppgtt_enable(dev);
1179 else if (IS_GEN7(dev))
1180 gen7_ppgtt_enable(dev);
1181 else if (INTEL_INFO(dev)->gen >= 8)
1182 gen8_ppgtt_enable(dev);
1183 else
1184 WARN_ON(1);
1185
1186 if (ppgtt) {
1187 for_each_ring(ring, dev_priv, i) {
1188 ret = ppgtt->switch_mm(ppgtt, ring, true);
1189 if (ret != 0)
1190 return ret;
1191 }
1192 }
1193
1194 return ret;
1195 }
1196 struct i915_hw_ppgtt *
1197 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1198 {
1199 struct i915_hw_ppgtt *ppgtt;
1200 int ret;
1201
1202 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1203 if (!ppgtt)
1204 return ERR_PTR(-ENOMEM);
1205
1206 ret = i915_ppgtt_init(dev, ppgtt);
1207 if (ret) {
1208 kfree(ppgtt);
1209 return ERR_PTR(ret);
1210 }
1211
1212 ppgtt->file_priv = fpriv;
1213
1214 return ppgtt;
1215 }
1216
1217 void i915_ppgtt_release(struct kref *kref)
1218 {
1219 struct i915_hw_ppgtt *ppgtt =
1220 container_of(kref, struct i915_hw_ppgtt, ref);
1221
1222 /* vmas should already be unbound */
1223 WARN_ON(!list_empty(&ppgtt->base.active_list));
1224 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1225
1226 ppgtt->base.cleanup(&ppgtt->base);
1227 kfree(ppgtt);
1228 }
1229
1230 static void
1231 ppgtt_bind_vma(struct i915_vma *vma,
1232 enum i915_cache_level cache_level,
1233 u32 flags)
1234 {
1235 /* Currently applicable only to VLV */
1236 if (vma->obj->gt_ro)
1237 flags |= PTE_READ_ONLY;
1238
1239 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1240 cache_level, flags);
1241 }
1242
1243 static void ppgtt_unbind_vma(struct i915_vma *vma)
1244 {
1245 vma->vm->clear_range(vma->vm,
1246 vma->node.start,
1247 vma->obj->base.size,
1248 true);
1249 }
1250
1251 extern int intel_iommu_gfx_mapped;
1252 /* Certain Gen5 chipsets require require idling the GPU before
1253 * unmapping anything from the GTT when VT-d is enabled.
1254 */
1255 static inline bool needs_idle_maps(struct drm_device *dev)
1256 {
1257 #ifdef CONFIG_INTEL_IOMMU
1258 /* Query intel_iommu to see if we need the workaround. Presumably that
1259 * was loaded first.
1260 */
1261 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1262 return true;
1263 #endif
1264 return false;
1265 }
1266
1267 static bool do_idling(struct drm_i915_private *dev_priv)
1268 {
1269 bool ret = dev_priv->mm.interruptible;
1270
1271 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1272 dev_priv->mm.interruptible = false;
1273 if (i915_gpu_idle(dev_priv->dev)) {
1274 DRM_ERROR("Couldn't idle GPU\n");
1275 /* Wait a bit, in hopes it avoids the hang */
1276 udelay(10);
1277 }
1278 }
1279
1280 return ret;
1281 }
1282
1283 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1284 {
1285 if (unlikely(dev_priv->gtt.do_idle_maps))
1286 dev_priv->mm.interruptible = interruptible;
1287 }
1288
1289 void i915_check_and_clear_faults(struct drm_device *dev)
1290 {
1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292 struct intel_engine_cs *ring;
1293 int i;
1294
1295 if (INTEL_INFO(dev)->gen < 6)
1296 return;
1297
1298 for_each_ring(ring, dev_priv, i) {
1299 u32 fault_reg;
1300 fault_reg = I915_READ(RING_FAULT_REG(ring));
1301 if (fault_reg & RING_FAULT_VALID) {
1302 DRM_DEBUG_DRIVER("Unexpected fault\n"
1303 "\tAddr: 0x%08lx\\n"
1304 "\tAddress space: %s\n"
1305 "\tSource ID: %d\n"
1306 "\tType: %d\n",
1307 fault_reg & PAGE_MASK,
1308 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1309 RING_FAULT_SRCID(fault_reg),
1310 RING_FAULT_FAULT_TYPE(fault_reg));
1311 I915_WRITE(RING_FAULT_REG(ring),
1312 fault_reg & ~RING_FAULT_VALID);
1313 }
1314 }
1315 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1316 }
1317
1318 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1319 {
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321
1322 /* Don't bother messing with faults pre GEN6 as we have little
1323 * documentation supporting that it's a good idea.
1324 */
1325 if (INTEL_INFO(dev)->gen < 6)
1326 return;
1327
1328 i915_check_and_clear_faults(dev);
1329
1330 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1331 dev_priv->gtt.base.start,
1332 dev_priv->gtt.base.total,
1333 true);
1334 }
1335
1336 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1337 {
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 struct drm_i915_gem_object *obj;
1340 struct i915_address_space *vm;
1341
1342 i915_check_and_clear_faults(dev);
1343
1344 /* First fill our portion of the GTT with scratch pages */
1345 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1346 dev_priv->gtt.base.start,
1347 dev_priv->gtt.base.total,
1348 true);
1349
1350 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1351 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1352 &dev_priv->gtt.base);
1353 if (!vma)
1354 continue;
1355
1356 i915_gem_clflush_object(obj, obj->pin_display);
1357 /* The bind_vma code tries to be smart about tracking mappings.
1358 * Unfortunately above, we've just wiped out the mappings
1359 * without telling our object about it. So we need to fake it.
1360 */
1361 obj->has_global_gtt_mapping = 0;
1362 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1363 }
1364
1365
1366 if (INTEL_INFO(dev)->gen >= 8) {
1367 if (IS_CHERRYVIEW(dev))
1368 chv_setup_private_ppat(dev_priv);
1369 else
1370 bdw_setup_private_ppat(dev_priv);
1371
1372 return;
1373 }
1374
1375 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1376 /* TODO: Perhaps it shouldn't be gen6 specific */
1377 if (i915_is_ggtt(vm)) {
1378 if (dev_priv->mm.aliasing_ppgtt)
1379 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1380 continue;
1381 }
1382
1383 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1384 }
1385
1386 i915_gem_chipset_flush(dev);
1387 }
1388
1389 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1390 {
1391 if (obj->has_dma_mapping)
1392 return 0;
1393
1394 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1395 obj->pages->sgl, obj->pages->nents,
1396 PCI_DMA_BIDIRECTIONAL))
1397 return -ENOSPC;
1398
1399 return 0;
1400 }
1401
1402 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1403 {
1404 #ifdef writeq
1405 writeq(pte, addr);
1406 #else
1407 iowrite32((u32)pte, addr);
1408 iowrite32(pte >> 32, addr + 4);
1409 #endif
1410 }
1411
1412 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1413 struct sg_table *st,
1414 uint64_t start,
1415 enum i915_cache_level level, u32 unused)
1416 {
1417 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1418 unsigned first_entry = start >> PAGE_SHIFT;
1419 gen8_gtt_pte_t __iomem *gtt_entries =
1420 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1421 int i = 0;
1422 struct sg_page_iter sg_iter;
1423 dma_addr_t addr = 0; /* shut up gcc */
1424
1425 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1426 addr = sg_dma_address(sg_iter.sg) +
1427 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1428 gen8_set_pte(&gtt_entries[i],
1429 gen8_pte_encode(addr, level, true));
1430 i++;
1431 }
1432
1433 /*
1434 * XXX: This serves as a posting read to make sure that the PTE has
1435 * actually been updated. There is some concern that even though
1436 * registers and PTEs are within the same BAR that they are potentially
1437 * of NUMA access patterns. Therefore, even with the way we assume
1438 * hardware should work, we must keep this posting read for paranoia.
1439 */
1440 if (i != 0)
1441 WARN_ON(readq(&gtt_entries[i-1])
1442 != gen8_pte_encode(addr, level, true));
1443
1444 /* This next bit makes the above posting read even more important. We
1445 * want to flush the TLBs only after we're certain all the PTE updates
1446 * have finished.
1447 */
1448 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1449 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1450 }
1451
1452 /*
1453 * Binds an object into the global gtt with the specified cache level. The object
1454 * will be accessible to the GPU via commands whose operands reference offsets
1455 * within the global GTT as well as accessible by the GPU through the GMADR
1456 * mapped BAR (dev_priv->mm.gtt->gtt).
1457 */
1458 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1459 struct sg_table *st,
1460 uint64_t start,
1461 enum i915_cache_level level, u32 flags)
1462 {
1463 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1464 unsigned first_entry = start >> PAGE_SHIFT;
1465 gen6_gtt_pte_t __iomem *gtt_entries =
1466 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1467 int i = 0;
1468 struct sg_page_iter sg_iter;
1469 dma_addr_t addr = 0;
1470
1471 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1472 addr = sg_page_iter_dma_address(&sg_iter);
1473 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1474 i++;
1475 }
1476
1477 /* XXX: This serves as a posting read to make sure that the PTE has
1478 * actually been updated. There is some concern that even though
1479 * registers and PTEs are within the same BAR that they are potentially
1480 * of NUMA access patterns. Therefore, even with the way we assume
1481 * hardware should work, we must keep this posting read for paranoia.
1482 */
1483 if (i != 0) {
1484 unsigned long gtt = readl(&gtt_entries[i-1]);
1485 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1486 }
1487
1488 /* This next bit makes the above posting read even more important. We
1489 * want to flush the TLBs only after we're certain all the PTE updates
1490 * have finished.
1491 */
1492 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1493 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1494 }
1495
1496 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1497 uint64_t start,
1498 uint64_t length,
1499 bool use_scratch)
1500 {
1501 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1502 unsigned first_entry = start >> PAGE_SHIFT;
1503 unsigned num_entries = length >> PAGE_SHIFT;
1504 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1505 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1506 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1507 int i;
1508
1509 if (WARN(num_entries > max_entries,
1510 "First entry = %d; Num entries = %d (max=%d)\n",
1511 first_entry, num_entries, max_entries))
1512 num_entries = max_entries;
1513
1514 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1515 I915_CACHE_LLC,
1516 use_scratch);
1517 for (i = 0; i < num_entries; i++)
1518 gen8_set_pte(&gtt_base[i], scratch_pte);
1519 readl(gtt_base);
1520 }
1521
1522 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1523 uint64_t start,
1524 uint64_t length,
1525 bool use_scratch)
1526 {
1527 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1528 unsigned first_entry = start >> PAGE_SHIFT;
1529 unsigned num_entries = length >> PAGE_SHIFT;
1530 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1531 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1532 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1533 int i;
1534
1535 if (WARN(num_entries > max_entries,
1536 "First entry = %d; Num entries = %d (max=%d)\n",
1537 first_entry, num_entries, max_entries))
1538 num_entries = max_entries;
1539
1540 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1541
1542 for (i = 0; i < num_entries; i++)
1543 iowrite32(scratch_pte, &gtt_base[i]);
1544 readl(gtt_base);
1545 }
1546
1547
1548 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1549 enum i915_cache_level cache_level,
1550 u32 unused)
1551 {
1552 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1553 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1554 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1555
1556 BUG_ON(!i915_is_ggtt(vma->vm));
1557 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1558 vma->obj->has_global_gtt_mapping = 1;
1559 }
1560
1561 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1562 uint64_t start,
1563 uint64_t length,
1564 bool unused)
1565 {
1566 unsigned first_entry = start >> PAGE_SHIFT;
1567 unsigned num_entries = length >> PAGE_SHIFT;
1568 intel_gtt_clear_range(first_entry, num_entries);
1569 }
1570
1571 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1572 {
1573 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1574 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1575
1576 BUG_ON(!i915_is_ggtt(vma->vm));
1577 vma->obj->has_global_gtt_mapping = 0;
1578 intel_gtt_clear_range(first, size);
1579 }
1580
1581 static void ggtt_bind_vma(struct i915_vma *vma,
1582 enum i915_cache_level cache_level,
1583 u32 flags)
1584 {
1585 struct drm_device *dev = vma->vm->dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct drm_i915_gem_object *obj = vma->obj;
1588
1589 /* Currently applicable only to VLV */
1590 if (obj->gt_ro)
1591 flags |= PTE_READ_ONLY;
1592
1593 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1594 * or we have a global mapping already but the cacheability flags have
1595 * changed, set the global PTEs.
1596 *
1597 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1598 * instead if none of the above hold true.
1599 *
1600 * NB: A global mapping should only be needed for special regions like
1601 * "gtt mappable", SNB errata, or if specified via special execbuf
1602 * flags. At all other times, the GPU will use the aliasing PPGTT.
1603 */
1604 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1605 if (!obj->has_global_gtt_mapping ||
1606 (cache_level != obj->cache_level)) {
1607 vma->vm->insert_entries(vma->vm, obj->pages,
1608 vma->node.start,
1609 cache_level, flags);
1610 obj->has_global_gtt_mapping = 1;
1611 }
1612 }
1613
1614 if (dev_priv->mm.aliasing_ppgtt &&
1615 (!obj->has_aliasing_ppgtt_mapping ||
1616 (cache_level != obj->cache_level))) {
1617 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1618 appgtt->base.insert_entries(&appgtt->base,
1619 vma->obj->pages,
1620 vma->node.start,
1621 cache_level, flags);
1622 vma->obj->has_aliasing_ppgtt_mapping = 1;
1623 }
1624 }
1625
1626 static void ggtt_unbind_vma(struct i915_vma *vma)
1627 {
1628 struct drm_device *dev = vma->vm->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_i915_gem_object *obj = vma->obj;
1631
1632 if (obj->has_global_gtt_mapping) {
1633 vma->vm->clear_range(vma->vm,
1634 vma->node.start,
1635 obj->base.size,
1636 true);
1637 obj->has_global_gtt_mapping = 0;
1638 }
1639
1640 if (obj->has_aliasing_ppgtt_mapping) {
1641 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1642 appgtt->base.clear_range(&appgtt->base,
1643 vma->node.start,
1644 obj->base.size,
1645 true);
1646 obj->has_aliasing_ppgtt_mapping = 0;
1647 }
1648 }
1649
1650 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1651 {
1652 struct drm_device *dev = obj->base.dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 bool interruptible;
1655
1656 interruptible = do_idling(dev_priv);
1657
1658 if (!obj->has_dma_mapping)
1659 dma_unmap_sg(&dev->pdev->dev,
1660 obj->pages->sgl, obj->pages->nents,
1661 PCI_DMA_BIDIRECTIONAL);
1662
1663 undo_idling(dev_priv, interruptible);
1664 }
1665
1666 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1667 unsigned long color,
1668 unsigned long *start,
1669 unsigned long *end)
1670 {
1671 if (node->color != color)
1672 *start += 4096;
1673
1674 if (!list_empty(&node->node_list)) {
1675 node = list_entry(node->node_list.next,
1676 struct drm_mm_node,
1677 node_list);
1678 if (node->allocated && node->color != color)
1679 *end -= 4096;
1680 }
1681 }
1682
1683 int i915_gem_setup_global_gtt(struct drm_device *dev,
1684 unsigned long start,
1685 unsigned long mappable_end,
1686 unsigned long end)
1687 {
1688 /* Let GEM Manage all of the aperture.
1689 *
1690 * However, leave one page at the end still bound to the scratch page.
1691 * There are a number of places where the hardware apparently prefetches
1692 * past the end of the object, and we've seen multiple hangs with the
1693 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1694 * aperture. One page should be enough to keep any prefetching inside
1695 * of the aperture.
1696 */
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1699 struct drm_mm_node *entry;
1700 struct drm_i915_gem_object *obj;
1701 unsigned long hole_start, hole_end;
1702
1703 BUG_ON(mappable_end > end);
1704
1705 /* Subtract the guard page ... */
1706 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1707 if (!HAS_LLC(dev))
1708 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1709
1710 /* Mark any preallocated objects as occupied */
1711 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1712 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1713 int ret;
1714 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1715 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1716
1717 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1718 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1719 if (ret) {
1720 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1721 return ret;
1722 }
1723 obj->has_global_gtt_mapping = 1;
1724 }
1725
1726 dev_priv->gtt.base.start = start;
1727 dev_priv->gtt.base.total = end - start;
1728
1729 /* Clear any non-preallocated blocks */
1730 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1731 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1732 hole_start, hole_end);
1733 ggtt_vm->clear_range(ggtt_vm, hole_start,
1734 hole_end - hole_start, true);
1735 }
1736
1737 /* And finally clear the reserved guard page */
1738 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1739
1740 return 0;
1741 }
1742
1743 void i915_gem_init_global_gtt(struct drm_device *dev)
1744 {
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 unsigned long gtt_size, mappable_size;
1747
1748 gtt_size = dev_priv->gtt.base.total;
1749 mappable_size = dev_priv->gtt.mappable_end;
1750
1751 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1752 }
1753
1754 static int setup_scratch_page(struct drm_device *dev)
1755 {
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 struct page *page;
1758 dma_addr_t dma_addr;
1759
1760 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1761 if (page == NULL)
1762 return -ENOMEM;
1763 get_page(page);
1764 set_pages_uc(page, 1);
1765
1766 #ifdef CONFIG_INTEL_IOMMU
1767 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1768 PCI_DMA_BIDIRECTIONAL);
1769 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1770 return -EINVAL;
1771 #else
1772 dma_addr = page_to_phys(page);
1773 #endif
1774 dev_priv->gtt.base.scratch.page = page;
1775 dev_priv->gtt.base.scratch.addr = dma_addr;
1776
1777 return 0;
1778 }
1779
1780 static void teardown_scratch_page(struct drm_device *dev)
1781 {
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783 struct page *page = dev_priv->gtt.base.scratch.page;
1784
1785 set_pages_wb(page, 1);
1786 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1787 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1788 put_page(page);
1789 __free_page(page);
1790 }
1791
1792 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1793 {
1794 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1795 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1796 return snb_gmch_ctl << 20;
1797 }
1798
1799 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1800 {
1801 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1802 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1803 if (bdw_gmch_ctl)
1804 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1805
1806 #ifdef CONFIG_X86_32
1807 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1808 if (bdw_gmch_ctl > 4)
1809 bdw_gmch_ctl = 4;
1810 #endif
1811
1812 return bdw_gmch_ctl << 20;
1813 }
1814
1815 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1816 {
1817 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1818 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1819
1820 if (gmch_ctrl)
1821 return 1 << (20 + gmch_ctrl);
1822
1823 return 0;
1824 }
1825
1826 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1827 {
1828 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1829 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1830 return snb_gmch_ctl << 25; /* 32 MB units */
1831 }
1832
1833 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1834 {
1835 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1836 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1837 return bdw_gmch_ctl << 25; /* 32 MB units */
1838 }
1839
1840 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1841 {
1842 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1843 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1844
1845 /*
1846 * 0x0 to 0x10: 32MB increments starting at 0MB
1847 * 0x11 to 0x16: 4MB increments starting at 8MB
1848 * 0x17 to 0x1d: 4MB increments start at 36MB
1849 */
1850 if (gmch_ctrl < 0x11)
1851 return gmch_ctrl << 25;
1852 else if (gmch_ctrl < 0x17)
1853 return (gmch_ctrl - 0x11 + 2) << 22;
1854 else
1855 return (gmch_ctrl - 0x17 + 9) << 22;
1856 }
1857
1858 static int ggtt_probe_common(struct drm_device *dev,
1859 size_t gtt_size)
1860 {
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 phys_addr_t gtt_phys_addr;
1863 int ret;
1864
1865 /* For Modern GENs the PTEs and register space are split in the BAR */
1866 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1867 (pci_resource_len(dev->pdev, 0) / 2);
1868
1869 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1870 if (!dev_priv->gtt.gsm) {
1871 DRM_ERROR("Failed to map the gtt page table\n");
1872 return -ENOMEM;
1873 }
1874
1875 ret = setup_scratch_page(dev);
1876 if (ret) {
1877 DRM_ERROR("Scratch setup failed\n");
1878 /* iounmap will also get called at remove, but meh */
1879 iounmap(dev_priv->gtt.gsm);
1880 }
1881
1882 return ret;
1883 }
1884
1885 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1886 * bits. When using advanced contexts each context stores its own PAT, but
1887 * writing this data shouldn't be harmful even in those cases. */
1888 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1889 {
1890 uint64_t pat;
1891
1892 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1893 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1894 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1895 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1896 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1897 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1898 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1899 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1900
1901 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1902 * write would work. */
1903 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1904 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1905 }
1906
1907 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1908 {
1909 uint64_t pat;
1910
1911 /*
1912 * Map WB on BDW to snooped on CHV.
1913 *
1914 * Only the snoop bit has meaning for CHV, the rest is
1915 * ignored.
1916 *
1917 * Note that the harware enforces snooping for all page
1918 * table accesses. The snoop bit is actually ignored for
1919 * PDEs.
1920 */
1921 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1922 GEN8_PPAT(1, 0) |
1923 GEN8_PPAT(2, 0) |
1924 GEN8_PPAT(3, 0) |
1925 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1926 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1927 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1928 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1929
1930 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1931 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1932 }
1933
1934 static int gen8_gmch_probe(struct drm_device *dev,
1935 size_t *gtt_total,
1936 size_t *stolen,
1937 phys_addr_t *mappable_base,
1938 unsigned long *mappable_end)
1939 {
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941 unsigned int gtt_size;
1942 u16 snb_gmch_ctl;
1943 int ret;
1944
1945 /* TODO: We're not aware of mappable constraints on gen8 yet */
1946 *mappable_base = pci_resource_start(dev->pdev, 2);
1947 *mappable_end = pci_resource_len(dev->pdev, 2);
1948
1949 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1950 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1951
1952 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1953
1954 if (IS_CHERRYVIEW(dev)) {
1955 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1956 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1957 } else {
1958 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1959 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1960 }
1961
1962 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1963
1964 if (IS_CHERRYVIEW(dev))
1965 chv_setup_private_ppat(dev_priv);
1966 else
1967 bdw_setup_private_ppat(dev_priv);
1968
1969 ret = ggtt_probe_common(dev, gtt_size);
1970
1971 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1972 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1973
1974 return ret;
1975 }
1976
1977 static int gen6_gmch_probe(struct drm_device *dev,
1978 size_t *gtt_total,
1979 size_t *stolen,
1980 phys_addr_t *mappable_base,
1981 unsigned long *mappable_end)
1982 {
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984 unsigned int gtt_size;
1985 u16 snb_gmch_ctl;
1986 int ret;
1987
1988 *mappable_base = pci_resource_start(dev->pdev, 2);
1989 *mappable_end = pci_resource_len(dev->pdev, 2);
1990
1991 /* 64/512MB is the current min/max we actually know of, but this is just
1992 * a coarse sanity check.
1993 */
1994 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1995 DRM_ERROR("Unknown GMADR size (%lx)\n",
1996 dev_priv->gtt.mappable_end);
1997 return -ENXIO;
1998 }
1999
2000 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2001 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2002 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2003
2004 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2005
2006 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2007 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2008
2009 ret = ggtt_probe_common(dev, gtt_size);
2010
2011 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2012 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2013
2014 return ret;
2015 }
2016
2017 static void gen6_gmch_remove(struct i915_address_space *vm)
2018 {
2019
2020 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2021
2022 if (drm_mm_initialized(&vm->mm)) {
2023 drm_mm_takedown(&vm->mm);
2024 list_del(&vm->global_link);
2025 }
2026 iounmap(gtt->gsm);
2027 teardown_scratch_page(vm->dev);
2028 }
2029
2030 static int i915_gmch_probe(struct drm_device *dev,
2031 size_t *gtt_total,
2032 size_t *stolen,
2033 phys_addr_t *mappable_base,
2034 unsigned long *mappable_end)
2035 {
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037 int ret;
2038
2039 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2040 if (!ret) {
2041 DRM_ERROR("failed to set up gmch\n");
2042 return -EIO;
2043 }
2044
2045 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2046
2047 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2048 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2049
2050 if (unlikely(dev_priv->gtt.do_idle_maps))
2051 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2052
2053 return 0;
2054 }
2055
2056 static void i915_gmch_remove(struct i915_address_space *vm)
2057 {
2058 if (drm_mm_initialized(&vm->mm)) {
2059 drm_mm_takedown(&vm->mm);
2060 list_del(&vm->global_link);
2061 }
2062 intel_gmch_remove();
2063 }
2064
2065 int i915_gem_gtt_init(struct drm_device *dev)
2066 {
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct i915_gtt *gtt = &dev_priv->gtt;
2069 int ret;
2070
2071 if (INTEL_INFO(dev)->gen <= 5) {
2072 gtt->gtt_probe = i915_gmch_probe;
2073 gtt->base.cleanup = i915_gmch_remove;
2074 } else if (INTEL_INFO(dev)->gen < 8) {
2075 gtt->gtt_probe = gen6_gmch_probe;
2076 gtt->base.cleanup = gen6_gmch_remove;
2077 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2078 gtt->base.pte_encode = iris_pte_encode;
2079 else if (IS_HASWELL(dev))
2080 gtt->base.pte_encode = hsw_pte_encode;
2081 else if (IS_VALLEYVIEW(dev))
2082 gtt->base.pte_encode = byt_pte_encode;
2083 else if (INTEL_INFO(dev)->gen >= 7)
2084 gtt->base.pte_encode = ivb_pte_encode;
2085 else
2086 gtt->base.pte_encode = snb_pte_encode;
2087 } else {
2088 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2089 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2090 }
2091
2092 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2093 &gtt->mappable_base, &gtt->mappable_end);
2094 if (ret)
2095 return ret;
2096
2097 gtt->base.dev = dev;
2098
2099 /* GMADR is the PCI mmio aperture into the global GTT. */
2100 DRM_INFO("Memory usable by graphics device = %zdM\n",
2101 gtt->base.total >> 20);
2102 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2103 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2104 #ifdef CONFIG_INTEL_IOMMU
2105 if (intel_iommu_gfx_mapped)
2106 DRM_INFO("VT-d active for gfx access\n");
2107 #endif
2108 /*
2109 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2110 * user's requested state against the hardware/driver capabilities. We
2111 * do this now so that we can print out any log messages once rather
2112 * than every time we check intel_enable_ppgtt().
2113 */
2114 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2115 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2116
2117 return 0;
2118 }
2119
2120 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2121 struct i915_address_space *vm)
2122 {
2123 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2124 if (vma == NULL)
2125 return ERR_PTR(-ENOMEM);
2126
2127 INIT_LIST_HEAD(&vma->vma_link);
2128 INIT_LIST_HEAD(&vma->mm_list);
2129 INIT_LIST_HEAD(&vma->exec_list);
2130 vma->vm = vm;
2131 vma->obj = obj;
2132
2133 switch (INTEL_INFO(vm->dev)->gen) {
2134 case 8:
2135 case 7:
2136 case 6:
2137 if (i915_is_ggtt(vm)) {
2138 vma->unbind_vma = ggtt_unbind_vma;
2139 vma->bind_vma = ggtt_bind_vma;
2140 } else {
2141 vma->unbind_vma = ppgtt_unbind_vma;
2142 vma->bind_vma = ppgtt_bind_vma;
2143 }
2144 break;
2145 case 5:
2146 case 4:
2147 case 3:
2148 case 2:
2149 BUG_ON(!i915_is_ggtt(vm));
2150 vma->unbind_vma = i915_ggtt_unbind_vma;
2151 vma->bind_vma = i915_ggtt_bind_vma;
2152 break;
2153 default:
2154 BUG();
2155 }
2156
2157 /* Keep GGTT vmas first to make debug easier */
2158 if (i915_is_ggtt(vm))
2159 list_add(&vma->vma_link, &obj->vma_list);
2160 else
2161 list_add_tail(&vma->vma_link, &obj->vma_list);
2162
2163 return vma;
2164 }
2165
2166 struct i915_vma *
2167 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2168 struct i915_address_space *vm)
2169 {
2170 struct i915_vma *vma;
2171
2172 vma = i915_gem_obj_to_vma(obj, vm);
2173 if (!vma)
2174 vma = __i915_gem_vma_create(obj, vm);
2175
2176 if (!i915_is_ggtt(vm))
2177 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2178
2179 return vma;
2180 }
Linux kernel - Deliverables
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