2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
36 * DOC: Global GTT views
38 * Background and previous state
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
65 * Implementation and usage
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
70 * A new flavour of core GEM functions which work with GGTT bound objects were
71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
80 * Code wanting to add or use a new GGTT view needs to:
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
96 static inline struct i915_ggtt
*
97 i915_vm_to_ggtt(struct i915_address_space
*vm
)
99 GEM_BUG_ON(!i915_is_ggtt(vm
));
100 return container_of(vm
, struct i915_ggtt
, base
);
104 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
106 const struct i915_ggtt_view i915_ggtt_view_normal
= {
107 .type
= I915_GGTT_VIEW_NORMAL
,
109 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
110 .type
= I915_GGTT_VIEW_ROTATED
,
113 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
116 bool has_aliasing_ppgtt
;
118 bool has_full_48bit_ppgtt
;
120 has_aliasing_ppgtt
= INTEL_GEN(dev_priv
) >= 6;
121 has_full_ppgtt
= INTEL_GEN(dev_priv
) >= 7;
122 has_full_48bit_ppgtt
=
123 IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9;
125 if (intel_vgpu_active(dev_priv
))
126 has_full_ppgtt
= false; /* emulation is too hard */
128 if (!has_aliasing_ppgtt
)
132 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
133 * execlists, the sole mechanism available to submit work.
135 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
138 if (enable_ppgtt
== 1)
141 if (enable_ppgtt
== 2 && has_full_ppgtt
)
144 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
147 #ifdef CONFIG_INTEL_IOMMU
148 /* Disable ppgtt on SNB if VT-d is on. */
149 if (IS_GEN6(dev_priv
) && intel_iommu_gfx_mapped
) {
150 DRM_INFO("Disabling PPGTT because VT-d is on\n");
155 /* Early VLV doesn't have this */
156 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
157 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
161 if (INTEL_GEN(dev_priv
) >= 8 && i915
.enable_execlists
)
162 return has_full_48bit_ppgtt
? 3 : 2;
164 return has_aliasing_ppgtt
? 1 : 0;
167 static int ppgtt_bind_vma(struct i915_vma
*vma
,
168 enum i915_cache_level cache_level
,
173 /* Currently applicable only to VLV */
175 pte_flags
|= PTE_READ_ONLY
;
177 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
178 cache_level
, pte_flags
);
183 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
185 vma
->vm
->clear_range(vma
->vm
,
191 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
192 enum i915_cache_level level
,
195 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
199 case I915_CACHE_NONE
:
200 pte
|= PPAT_UNCACHED_INDEX
;
203 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
206 pte
|= PPAT_CACHED_INDEX
;
213 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
214 const enum i915_cache_level level
)
216 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
218 if (level
!= I915_CACHE_NONE
)
219 pde
|= PPAT_CACHED_PDE_INDEX
;
221 pde
|= PPAT_UNCACHED_INDEX
;
225 #define gen8_pdpe_encode gen8_pde_encode
226 #define gen8_pml4e_encode gen8_pde_encode
228 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
229 enum i915_cache_level level
,
230 bool valid
, u32 unused
)
232 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
233 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
236 case I915_CACHE_L3_LLC
:
238 pte
|= GEN6_PTE_CACHE_LLC
;
240 case I915_CACHE_NONE
:
241 pte
|= GEN6_PTE_UNCACHED
;
250 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
251 enum i915_cache_level level
,
252 bool valid
, u32 unused
)
254 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
255 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
258 case I915_CACHE_L3_LLC
:
259 pte
|= GEN7_PTE_CACHE_L3_LLC
;
262 pte
|= GEN6_PTE_CACHE_LLC
;
264 case I915_CACHE_NONE
:
265 pte
|= GEN6_PTE_UNCACHED
;
274 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
275 enum i915_cache_level level
,
276 bool valid
, u32 flags
)
278 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
279 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
281 if (!(flags
& PTE_READ_ONLY
))
282 pte
|= BYT_PTE_WRITEABLE
;
284 if (level
!= I915_CACHE_NONE
)
285 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
290 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
291 enum i915_cache_level level
,
292 bool valid
, u32 unused
)
294 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
295 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
297 if (level
!= I915_CACHE_NONE
)
298 pte
|= HSW_WB_LLC_AGE3
;
303 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
304 enum i915_cache_level level
,
305 bool valid
, u32 unused
)
307 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
308 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
311 case I915_CACHE_NONE
:
314 pte
|= HSW_WT_ELLC_LLC_AGE3
;
317 pte
|= HSW_WB_ELLC_LLC_AGE3
;
324 static int __setup_page_dma(struct drm_device
*dev
,
325 struct i915_page_dma
*p
, gfp_t flags
)
327 struct device
*device
= &dev
->pdev
->dev
;
329 p
->page
= alloc_page(flags
);
333 p
->daddr
= dma_map_page(device
,
334 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
336 if (dma_mapping_error(device
, p
->daddr
)) {
337 __free_page(p
->page
);
344 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
346 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
349 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
351 if (WARN_ON(!p
->page
))
354 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
355 __free_page(p
->page
);
356 memset(p
, 0, sizeof(*p
));
359 static void *kmap_page_dma(struct i915_page_dma
*p
)
361 return kmap_atomic(p
->page
);
364 /* We use the flushing unmap only with ppgtt structures:
365 * page directories, page tables and scratch pages.
367 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
369 /* There are only few exceptions for gen >=6. chv and bxt.
370 * And we are not sure about the latter so play safe for now.
372 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
373 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
375 kunmap_atomic(vaddr
);
378 #define kmap_px(px) kmap_page_dma(px_base(px))
379 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
381 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
382 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
383 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
384 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
386 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
390 uint64_t * const vaddr
= kmap_page_dma(p
);
392 for (i
= 0; i
< 512; i
++)
395 kunmap_page_dma(dev
, vaddr
);
398 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
399 const uint32_t val32
)
405 fill_page_dma(dev
, p
, v
);
408 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
410 struct i915_page_scratch
*sp
;
413 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
415 return ERR_PTR(-ENOMEM
);
417 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
423 set_pages_uc(px_page(sp
), 1);
428 static void free_scratch_page(struct drm_device
*dev
,
429 struct i915_page_scratch
*sp
)
431 set_pages_wb(px_page(sp
), 1);
437 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
439 struct i915_page_table
*pt
;
440 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
441 GEN8_PTES
: GEN6_PTES
;
444 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
446 return ERR_PTR(-ENOMEM
);
448 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
454 ret
= setup_px(dev
, pt
);
461 kfree(pt
->used_ptes
);
468 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
471 kfree(pt
->used_ptes
);
475 static void gen8_initialize_pt(struct i915_address_space
*vm
,
476 struct i915_page_table
*pt
)
478 gen8_pte_t scratch_pte
;
480 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
481 I915_CACHE_LLC
, true);
483 fill_px(vm
->dev
, pt
, scratch_pte
);
486 static void gen6_initialize_pt(struct i915_address_space
*vm
,
487 struct i915_page_table
*pt
)
489 gen6_pte_t scratch_pte
;
491 WARN_ON(px_dma(vm
->scratch_page
) == 0);
493 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
494 I915_CACHE_LLC
, true, 0);
496 fill32_px(vm
->dev
, pt
, scratch_pte
);
499 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
501 struct i915_page_directory
*pd
;
504 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
506 return ERR_PTR(-ENOMEM
);
508 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
509 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
513 ret
= setup_px(dev
, pd
);
520 kfree(pd
->used_pdes
);
527 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
531 kfree(pd
->used_pdes
);
536 static void gen8_initialize_pd(struct i915_address_space
*vm
,
537 struct i915_page_directory
*pd
)
539 gen8_pde_t scratch_pde
;
541 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
543 fill_px(vm
->dev
, pd
, scratch_pde
);
546 static int __pdp_init(struct drm_device
*dev
,
547 struct i915_page_directory_pointer
*pdp
)
549 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
551 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
552 sizeof(unsigned long),
554 if (!pdp
->used_pdpes
)
557 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
559 if (!pdp
->page_directory
) {
560 kfree(pdp
->used_pdpes
);
561 /* the PDP might be the statically allocated top level. Keep it
562 * as clean as possible */
563 pdp
->used_pdpes
= NULL
;
570 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
572 kfree(pdp
->used_pdpes
);
573 kfree(pdp
->page_directory
);
574 pdp
->page_directory
= NULL
;
578 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
580 struct i915_page_directory_pointer
*pdp
;
583 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
585 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
587 return ERR_PTR(-ENOMEM
);
589 ret
= __pdp_init(dev
, pdp
);
593 ret
= setup_px(dev
, pdp
);
607 static void free_pdp(struct drm_device
*dev
,
608 struct i915_page_directory_pointer
*pdp
)
611 if (USES_FULL_48BIT_PPGTT(dev
)) {
612 cleanup_px(dev
, pdp
);
617 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
618 struct i915_page_directory_pointer
*pdp
)
620 gen8_ppgtt_pdpe_t scratch_pdpe
;
622 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
624 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
627 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
628 struct i915_pml4
*pml4
)
630 gen8_ppgtt_pml4e_t scratch_pml4e
;
632 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
635 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
639 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
640 struct i915_page_directory_pointer
*pdp
,
641 struct i915_page_directory
*pd
,
644 gen8_ppgtt_pdpe_t
*page_directorypo
;
646 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
649 page_directorypo
= kmap_px(pdp
);
650 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
651 kunmap_px(ppgtt
, page_directorypo
);
655 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
656 struct i915_pml4
*pml4
,
657 struct i915_page_directory_pointer
*pdp
,
660 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
662 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
663 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
664 kunmap_px(ppgtt
, pagemap
);
667 /* Broadwell Page Directory Pointer Descriptors */
668 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
672 struct intel_engine_cs
*engine
= req
->engine
;
677 ret
= intel_ring_begin(req
, 6);
681 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
682 intel_ring_emit_reg(engine
, GEN8_RING_PDP_UDW(engine
, entry
));
683 intel_ring_emit(engine
, upper_32_bits(addr
));
684 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
685 intel_ring_emit_reg(engine
, GEN8_RING_PDP_LDW(engine
, entry
));
686 intel_ring_emit(engine
, lower_32_bits(addr
));
687 intel_ring_advance(engine
);
692 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
693 struct drm_i915_gem_request
*req
)
697 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
698 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
700 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
708 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
709 struct drm_i915_gem_request
*req
)
711 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
714 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
715 struct i915_page_directory_pointer
*pdp
,
718 gen8_pte_t scratch_pte
)
720 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
721 gen8_pte_t
*pt_vaddr
;
722 unsigned pdpe
= gen8_pdpe_index(start
);
723 unsigned pde
= gen8_pde_index(start
);
724 unsigned pte
= gen8_pte_index(start
);
725 unsigned num_entries
= length
>> PAGE_SHIFT
;
726 unsigned last_pte
, i
;
731 while (num_entries
) {
732 struct i915_page_directory
*pd
;
733 struct i915_page_table
*pt
;
735 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
738 pd
= pdp
->page_directory
[pdpe
];
740 if (WARN_ON(!pd
->page_table
[pde
]))
743 pt
= pd
->page_table
[pde
];
745 if (WARN_ON(!px_page(pt
)))
748 last_pte
= pte
+ num_entries
;
749 if (last_pte
> GEN8_PTES
)
750 last_pte
= GEN8_PTES
;
752 pt_vaddr
= kmap_px(pt
);
754 for (i
= pte
; i
< last_pte
; i
++) {
755 pt_vaddr
[i
] = scratch_pte
;
759 kunmap_px(ppgtt
, pt_vaddr
);
762 if (++pde
== I915_PDES
) {
763 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
770 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
775 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
776 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
777 I915_CACHE_LLC
, use_scratch
);
779 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
780 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
784 struct i915_page_directory_pointer
*pdp
;
786 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
787 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
794 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
795 struct i915_page_directory_pointer
*pdp
,
796 struct sg_page_iter
*sg_iter
,
798 enum i915_cache_level cache_level
)
800 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
801 gen8_pte_t
*pt_vaddr
;
802 unsigned pdpe
= gen8_pdpe_index(start
);
803 unsigned pde
= gen8_pde_index(start
);
804 unsigned pte
= gen8_pte_index(start
);
808 while (__sg_page_iter_next(sg_iter
)) {
809 if (pt_vaddr
== NULL
) {
810 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
811 struct i915_page_table
*pt
= pd
->page_table
[pde
];
812 pt_vaddr
= kmap_px(pt
);
816 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
818 if (++pte
== GEN8_PTES
) {
819 kunmap_px(ppgtt
, pt_vaddr
);
821 if (++pde
== I915_PDES
) {
822 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
831 kunmap_px(ppgtt
, pt_vaddr
);
834 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
835 struct sg_table
*pages
,
837 enum i915_cache_level cache_level
,
840 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
841 struct sg_page_iter sg_iter
;
843 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
845 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
846 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
849 struct i915_page_directory_pointer
*pdp
;
851 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
853 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
854 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
860 static void gen8_free_page_tables(struct drm_device
*dev
,
861 struct i915_page_directory
*pd
)
868 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
869 if (WARN_ON(!pd
->page_table
[i
]))
872 free_pt(dev
, pd
->page_table
[i
]);
873 pd
->page_table
[i
] = NULL
;
877 static int gen8_init_scratch(struct i915_address_space
*vm
)
879 struct drm_device
*dev
= vm
->dev
;
882 vm
->scratch_page
= alloc_scratch_page(dev
);
883 if (IS_ERR(vm
->scratch_page
))
884 return PTR_ERR(vm
->scratch_page
);
886 vm
->scratch_pt
= alloc_pt(dev
);
887 if (IS_ERR(vm
->scratch_pt
)) {
888 ret
= PTR_ERR(vm
->scratch_pt
);
889 goto free_scratch_page
;
892 vm
->scratch_pd
= alloc_pd(dev
);
893 if (IS_ERR(vm
->scratch_pd
)) {
894 ret
= PTR_ERR(vm
->scratch_pd
);
898 if (USES_FULL_48BIT_PPGTT(dev
)) {
899 vm
->scratch_pdp
= alloc_pdp(dev
);
900 if (IS_ERR(vm
->scratch_pdp
)) {
901 ret
= PTR_ERR(vm
->scratch_pdp
);
906 gen8_initialize_pt(vm
, vm
->scratch_pt
);
907 gen8_initialize_pd(vm
, vm
->scratch_pd
);
908 if (USES_FULL_48BIT_PPGTT(dev
))
909 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
914 free_pd(dev
, vm
->scratch_pd
);
916 free_pt(dev
, vm
->scratch_pt
);
918 free_scratch_page(dev
, vm
->scratch_page
);
923 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
925 enum vgt_g2v_type msg
;
926 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
929 if (USES_FULL_48BIT_PPGTT(dev_priv
)) {
930 u64 daddr
= px_dma(&ppgtt
->pml4
);
932 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
933 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
935 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
936 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
938 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
939 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
941 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
942 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
945 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
946 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
949 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
954 static void gen8_free_scratch(struct i915_address_space
*vm
)
956 struct drm_device
*dev
= vm
->dev
;
958 if (USES_FULL_48BIT_PPGTT(dev
))
959 free_pdp(dev
, vm
->scratch_pdp
);
960 free_pd(dev
, vm
->scratch_pd
);
961 free_pt(dev
, vm
->scratch_pt
);
962 free_scratch_page(dev
, vm
->scratch_page
);
965 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
966 struct i915_page_directory_pointer
*pdp
)
970 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
971 if (WARN_ON(!pdp
->page_directory
[i
]))
974 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
975 free_pd(dev
, pdp
->page_directory
[i
]);
981 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
985 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
986 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
989 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
992 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
995 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
997 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
999 if (intel_vgpu_active(to_i915(vm
->dev
)))
1000 gen8_ppgtt_notify_vgt(ppgtt
, false);
1002 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
1003 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1005 gen8_ppgtt_cleanup_4lvl(ppgtt
);
1007 gen8_free_scratch(vm
);
1011 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1012 * @vm: Master vm structure.
1013 * @pd: Page directory for this address range.
1014 * @start: Starting virtual address to begin allocations.
1015 * @length: Size of the allocations.
1016 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1017 * caller to free on error.
1019 * Allocate the required number of page tables. Extremely similar to
1020 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1021 * the page directory boundary (instead of the page directory pointer). That
1022 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1023 * possible, and likely that the caller will need to use multiple calls of this
1024 * function to achieve the appropriate allocation.
1026 * Return: 0 if success; negative error code otherwise.
1028 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1029 struct i915_page_directory
*pd
,
1032 unsigned long *new_pts
)
1034 struct drm_device
*dev
= vm
->dev
;
1035 struct i915_page_table
*pt
;
1038 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1039 /* Don't reallocate page tables */
1040 if (test_bit(pde
, pd
->used_pdes
)) {
1041 /* Scratch is never allocated this way */
1042 WARN_ON(pt
== vm
->scratch_pt
);
1050 gen8_initialize_pt(vm
, pt
);
1051 pd
->page_table
[pde
] = pt
;
1052 __set_bit(pde
, new_pts
);
1053 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1059 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1060 free_pt(dev
, pd
->page_table
[pde
]);
1066 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1067 * @vm: Master vm structure.
1068 * @pdp: Page directory pointer for this address range.
1069 * @start: Starting virtual address to begin allocations.
1070 * @length: Size of the allocations.
1071 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1072 * caller to free on error.
1074 * Allocate the required number of page directories starting at the pde index of
1075 * @start, and ending at the pde index @start + @length. This function will skip
1076 * over already allocated page directories within the range, and only allocate
1077 * new ones, setting the appropriate pointer within the pdp as well as the
1078 * correct position in the bitmap @new_pds.
1080 * The function will only allocate the pages within the range for a give page
1081 * directory pointer. In other words, if @start + @length straddles a virtually
1082 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1083 * required by the caller, This is not currently possible, and the BUG in the
1084 * code will prevent it.
1086 * Return: 0 if success; negative error code otherwise.
1089 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1090 struct i915_page_directory_pointer
*pdp
,
1093 unsigned long *new_pds
)
1095 struct drm_device
*dev
= vm
->dev
;
1096 struct i915_page_directory
*pd
;
1098 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1100 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1102 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1103 if (test_bit(pdpe
, pdp
->used_pdpes
))
1110 gen8_initialize_pd(vm
, pd
);
1111 pdp
->page_directory
[pdpe
] = pd
;
1112 __set_bit(pdpe
, new_pds
);
1113 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1119 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1120 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1126 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1127 * @vm: Master vm structure.
1128 * @pml4: Page map level 4 for this address range.
1129 * @start: Starting virtual address to begin allocations.
1130 * @length: Size of the allocations.
1131 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1132 * caller to free on error.
1134 * Allocate the required number of page directory pointers. Extremely similar to
1135 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1136 * The main difference is here we are limited by the pml4 boundary (instead of
1137 * the page directory pointer).
1139 * Return: 0 if success; negative error code otherwise.
1142 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1143 struct i915_pml4
*pml4
,
1146 unsigned long *new_pdps
)
1148 struct drm_device
*dev
= vm
->dev
;
1149 struct i915_page_directory_pointer
*pdp
;
1152 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1154 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1155 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1156 pdp
= alloc_pdp(dev
);
1160 gen8_initialize_pdp(vm
, pdp
);
1161 pml4
->pdps
[pml4e
] = pdp
;
1162 __set_bit(pml4e
, new_pdps
);
1163 trace_i915_page_directory_pointer_entry_alloc(vm
,
1173 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1174 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1180 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1186 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1187 * of these are based on the number of PDPEs in the system.
1190 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1191 unsigned long **new_pts
,
1197 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1201 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1212 free_gen8_temp_bitmaps(pds
, pts
);
1216 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1217 * the page table structures, we mark them dirty so that
1218 * context switching/execlist queuing code takes extra steps
1219 * to ensure that tlbs are flushed.
1221 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1223 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1226 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1227 struct i915_page_directory_pointer
*pdp
,
1231 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1232 unsigned long *new_page_dirs
, *new_page_tables
;
1233 struct drm_device
*dev
= vm
->dev
;
1234 struct i915_page_directory
*pd
;
1235 const uint64_t orig_start
= start
;
1236 const uint64_t orig_length
= length
;
1238 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1241 /* Wrap is never okay since we can only represent 48b, and we don't
1242 * actually use the other side of the canonical address space.
1244 if (WARN_ON(start
+ length
< start
))
1247 if (WARN_ON(start
+ length
> vm
->total
))
1250 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1254 /* Do the allocations first so we can easily bail out */
1255 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1258 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1262 /* For every page directory referenced, allocate page tables */
1263 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1264 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1265 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1271 length
= orig_length
;
1273 /* Allocations have completed successfully, so set the bitmaps, and do
1275 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1276 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1277 struct i915_page_table
*pt
;
1278 uint64_t pd_len
= length
;
1279 uint64_t pd_start
= start
;
1282 /* Every pd should be allocated, we just did that above. */
1285 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1286 /* Same reasoning as pd */
1289 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1291 /* Set our used ptes within the page table */
1292 bitmap_set(pt
->used_ptes
,
1293 gen8_pte_index(pd_start
),
1294 gen8_pte_count(pd_start
, pd_len
));
1296 /* Our pde is now pointing to the pagetable, pt */
1297 __set_bit(pde
, pd
->used_pdes
);
1299 /* Map the PDE to the page table */
1300 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1302 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1303 gen8_pte_index(start
),
1304 gen8_pte_count(start
, length
),
1307 /* NB: We haven't yet mapped ptes to pages. At this
1308 * point we're still relying on insert_entries() */
1311 kunmap_px(ppgtt
, page_directory
);
1312 __set_bit(pdpe
, pdp
->used_pdpes
);
1313 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1316 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1317 mark_tlbs_dirty(ppgtt
);
1324 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1325 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1326 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1329 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1330 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1332 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1333 mark_tlbs_dirty(ppgtt
);
1337 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1338 struct i915_pml4
*pml4
,
1342 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1343 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1344 struct i915_page_directory_pointer
*pdp
;
1348 /* Do the pml4 allocations first, so we don't need to track the newly
1349 * allocated tables below the pdp */
1350 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1352 /* The pagedirectory and pagetable allocations are done in the shared 3
1353 * and 4 level code. Just allocate the pdps.
1355 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1360 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1361 "The allocation has spanned more than 512GB. "
1362 "It is highly likely this is incorrect.");
1364 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1367 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1371 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1374 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1375 GEN8_PML4ES_PER_PML4
);
1380 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1381 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1386 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1387 uint64_t start
, uint64_t length
)
1389 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1391 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1392 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1394 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1397 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1398 uint64_t start
, uint64_t length
,
1399 gen8_pte_t scratch_pte
,
1402 struct i915_page_directory
*pd
;
1405 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1406 struct i915_page_table
*pt
;
1407 uint64_t pd_len
= length
;
1408 uint64_t pd_start
= start
;
1411 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1414 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1415 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1417 gen8_pte_t
*pt_vaddr
;
1419 if (!test_bit(pde
, pd
->used_pdes
))
1422 pt_vaddr
= kmap_px(pt
);
1423 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1425 (pdpe
<< GEN8_PDPE_SHIFT
) |
1426 (pde
<< GEN8_PDE_SHIFT
) |
1427 (pte
<< GEN8_PTE_SHIFT
);
1431 for (i
= 0; i
< 4; i
++)
1432 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1437 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1438 for (i
= 0; i
< 4; i
++) {
1439 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1440 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1442 seq_puts(m
, " SCRATCH ");
1446 /* don't use kunmap_px, it could trigger
1447 * an unnecessary flush.
1449 kunmap_atomic(pt_vaddr
);
1454 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1456 struct i915_address_space
*vm
= &ppgtt
->base
;
1457 uint64_t start
= ppgtt
->base
.start
;
1458 uint64_t length
= ppgtt
->base
.total
;
1459 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1460 I915_CACHE_LLC
, true);
1462 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1463 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1466 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1467 struct i915_page_directory_pointer
*pdp
;
1469 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1470 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1473 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1474 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1479 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1481 unsigned long *new_page_dirs
, *new_page_tables
;
1482 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1485 /* We allocate temp bitmap for page tables for no gain
1486 * but as this is for init only, lets keep the things simple
1488 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1492 /* Allocate for all pdps regardless of how the ppgtt
1495 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1499 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1501 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1507 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1508 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1509 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1513 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1517 ret
= gen8_init_scratch(&ppgtt
->base
);
1521 ppgtt
->base
.start
= 0;
1522 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1523 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1524 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1525 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1526 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1527 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1528 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1530 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1531 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1535 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1537 ppgtt
->base
.total
= 1ULL << 48;
1538 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1540 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1544 ppgtt
->base
.total
= 1ULL << 32;
1545 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1546 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1550 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
))) {
1551 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1557 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
)))
1558 gen8_ppgtt_notify_vgt(ppgtt
, true);
1563 gen8_free_scratch(&ppgtt
->base
);
1567 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1569 struct i915_address_space
*vm
= &ppgtt
->base
;
1570 struct i915_page_table
*unused
;
1571 gen6_pte_t scratch_pte
;
1574 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1576 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1577 I915_CACHE_LLC
, true, 0);
1579 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1581 gen6_pte_t
*pt_vaddr
;
1582 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1583 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1584 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1586 if (pd_entry
!= expected
)
1587 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1591 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1593 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1595 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1597 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1601 for (i
= 0; i
< 4; i
++)
1602 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1607 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1608 for (i
= 0; i
< 4; i
++) {
1609 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1610 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1612 seq_puts(m
, " SCRATCH ");
1616 kunmap_px(ppgtt
, pt_vaddr
);
1620 /* Write pde (index) from the page directory @pd to the page table @pt */
1621 static void gen6_write_pde(struct i915_page_directory
*pd
,
1622 const int pde
, struct i915_page_table
*pt
)
1624 /* Caller needs to make sure the write completes if necessary */
1625 struct i915_hw_ppgtt
*ppgtt
=
1626 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1629 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1630 pd_entry
|= GEN6_PDE_VALID
;
1632 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1635 /* Write all the page tables found in the ppgtt structure to incrementing page
1637 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1638 struct i915_page_directory
*pd
,
1639 uint32_t start
, uint32_t length
)
1641 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1642 struct i915_page_table
*pt
;
1645 gen6_for_each_pde(pt
, pd
, start
, length
, pde
)
1646 gen6_write_pde(pd
, pde
, pt
);
1648 /* Make sure write is complete before other code can use this page
1649 * table. Also require for WC mapped PTEs */
1653 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1655 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1657 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1660 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1661 struct drm_i915_gem_request
*req
)
1663 struct intel_engine_cs
*engine
= req
->engine
;
1666 /* NB: TLBs must be flushed and invalidated before a switch */
1667 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1671 ret
= intel_ring_begin(req
, 6);
1675 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(2));
1676 intel_ring_emit_reg(engine
, RING_PP_DIR_DCLV(engine
));
1677 intel_ring_emit(engine
, PP_DIR_DCLV_2G
);
1678 intel_ring_emit_reg(engine
, RING_PP_DIR_BASE(engine
));
1679 intel_ring_emit(engine
, get_pd_offset(ppgtt
));
1680 intel_ring_emit(engine
, MI_NOOP
);
1681 intel_ring_advance(engine
);
1686 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1687 struct drm_i915_gem_request
*req
)
1689 struct intel_engine_cs
*engine
= req
->engine
;
1692 /* NB: TLBs must be flushed and invalidated before a switch */
1693 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1697 ret
= intel_ring_begin(req
, 6);
1701 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(2));
1702 intel_ring_emit_reg(engine
, RING_PP_DIR_DCLV(engine
));
1703 intel_ring_emit(engine
, PP_DIR_DCLV_2G
);
1704 intel_ring_emit_reg(engine
, RING_PP_DIR_BASE(engine
));
1705 intel_ring_emit(engine
, get_pd_offset(ppgtt
));
1706 intel_ring_emit(engine
, MI_NOOP
);
1707 intel_ring_advance(engine
);
1709 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1710 if (engine
->id
!= RCS
) {
1711 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1719 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1720 struct drm_i915_gem_request
*req
)
1722 struct intel_engine_cs
*engine
= req
->engine
;
1723 struct drm_i915_private
*dev_priv
= req
->i915
;
1725 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1726 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1730 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1732 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1733 struct intel_engine_cs
*engine
;
1735 for_each_engine(engine
, dev_priv
) {
1736 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1737 I915_WRITE(RING_MODE_GEN7(engine
),
1738 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1742 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1744 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1745 struct intel_engine_cs
*engine
;
1746 uint32_t ecochk
, ecobits
;
1748 ecobits
= I915_READ(GAC_ECO_BITS
);
1749 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1751 ecochk
= I915_READ(GAM_ECOCHK
);
1752 if (IS_HASWELL(dev
)) {
1753 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1755 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1756 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1758 I915_WRITE(GAM_ECOCHK
, ecochk
);
1760 for_each_engine(engine
, dev_priv
) {
1761 /* GFX_MODE is per-ring on gen7+ */
1762 I915_WRITE(RING_MODE_GEN7(engine
),
1763 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1767 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1769 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1770 uint32_t ecochk
, gab_ctl
, ecobits
;
1772 ecobits
= I915_READ(GAC_ECO_BITS
);
1773 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1774 ECOBITS_PPGTT_CACHE64B
);
1776 gab_ctl
= I915_READ(GAB_CTL
);
1777 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1779 ecochk
= I915_READ(GAM_ECOCHK
);
1780 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1782 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1785 /* PPGTT support for Sandybdrige/Gen6 and later */
1786 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1791 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1792 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1793 unsigned first_entry
= start
>> PAGE_SHIFT
;
1794 unsigned num_entries
= length
>> PAGE_SHIFT
;
1795 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1796 unsigned first_pte
= first_entry
% GEN6_PTES
;
1797 unsigned last_pte
, i
;
1799 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1800 I915_CACHE_LLC
, true, 0);
1802 while (num_entries
) {
1803 last_pte
= first_pte
+ num_entries
;
1804 if (last_pte
> GEN6_PTES
)
1805 last_pte
= GEN6_PTES
;
1807 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1809 for (i
= first_pte
; i
< last_pte
; i
++)
1810 pt_vaddr
[i
] = scratch_pte
;
1812 kunmap_px(ppgtt
, pt_vaddr
);
1814 num_entries
-= last_pte
- first_pte
;
1820 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1821 struct sg_table
*pages
,
1823 enum i915_cache_level cache_level
, u32 flags
)
1825 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1826 unsigned first_entry
= start
>> PAGE_SHIFT
;
1827 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1828 unsigned act_pte
= first_entry
% GEN6_PTES
;
1829 gen6_pte_t
*pt_vaddr
= NULL
;
1830 struct sgt_iter sgt_iter
;
1833 for_each_sgt_dma(addr
, sgt_iter
, pages
) {
1834 if (pt_vaddr
== NULL
)
1835 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1838 vm
->pte_encode(addr
, cache_level
, true, flags
);
1840 if (++act_pte
== GEN6_PTES
) {
1841 kunmap_px(ppgtt
, pt_vaddr
);
1849 kunmap_px(ppgtt
, pt_vaddr
);
1852 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1853 uint64_t start_in
, uint64_t length_in
)
1855 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1856 struct drm_device
*dev
= vm
->dev
;
1857 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1858 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1859 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1860 struct i915_page_table
*pt
;
1861 uint32_t start
, length
, start_save
, length_save
;
1865 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1868 start
= start_save
= start_in
;
1869 length
= length_save
= length_in
;
1871 bitmap_zero(new_page_tables
, I915_PDES
);
1873 /* The allocation is done in two stages so that we can bail out with
1874 * minimal amount of pain. The first stage finds new page tables that
1875 * need allocation. The second stage marks use ptes within the page
1878 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1879 if (pt
!= vm
->scratch_pt
) {
1880 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1884 /* We've already allocated a page table */
1885 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1893 gen6_initialize_pt(vm
, pt
);
1895 ppgtt
->pd
.page_table
[pde
] = pt
;
1896 __set_bit(pde
, new_page_tables
);
1897 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1901 length
= length_save
;
1903 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1904 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1906 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1907 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1908 gen6_pte_count(start
, length
));
1910 if (__test_and_clear_bit(pde
, new_page_tables
))
1911 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1913 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1914 gen6_pte_index(start
),
1915 gen6_pte_count(start
, length
),
1917 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1921 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1923 /* Make sure write is complete before other code can use this page
1924 * table. Also require for WC mapped PTEs */
1927 mark_tlbs_dirty(ppgtt
);
1931 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1932 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1934 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1935 free_pt(vm
->dev
, pt
);
1938 mark_tlbs_dirty(ppgtt
);
1942 static int gen6_init_scratch(struct i915_address_space
*vm
)
1944 struct drm_device
*dev
= vm
->dev
;
1946 vm
->scratch_page
= alloc_scratch_page(dev
);
1947 if (IS_ERR(vm
->scratch_page
))
1948 return PTR_ERR(vm
->scratch_page
);
1950 vm
->scratch_pt
= alloc_pt(dev
);
1951 if (IS_ERR(vm
->scratch_pt
)) {
1952 free_scratch_page(dev
, vm
->scratch_page
);
1953 return PTR_ERR(vm
->scratch_pt
);
1956 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1961 static void gen6_free_scratch(struct i915_address_space
*vm
)
1963 struct drm_device
*dev
= vm
->dev
;
1965 free_pt(dev
, vm
->scratch_pt
);
1966 free_scratch_page(dev
, vm
->scratch_page
);
1969 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1971 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1972 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1973 struct drm_device
*dev
= vm
->dev
;
1974 struct i915_page_table
*pt
;
1977 drm_mm_remove_node(&ppgtt
->node
);
1979 gen6_for_all_pdes(pt
, pd
, pde
)
1980 if (pt
!= vm
->scratch_pt
)
1983 gen6_free_scratch(vm
);
1986 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1988 struct i915_address_space
*vm
= &ppgtt
->base
;
1989 struct drm_device
*dev
= ppgtt
->base
.dev
;
1990 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1991 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1992 bool retried
= false;
1995 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1996 * allocator works in address space sizes, so it's multiplied by page
1997 * size. We allocate at the top of the GTT to avoid fragmentation.
1999 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
2001 ret
= gen6_init_scratch(vm
);
2006 ret
= drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
,
2007 &ppgtt
->node
, GEN6_PD_SIZE
,
2009 0, ggtt
->base
.total
,
2011 if (ret
== -ENOSPC
&& !retried
) {
2012 ret
= i915_gem_evict_something(dev
, &ggtt
->base
,
2013 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2015 0, ggtt
->base
.total
,
2028 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
2029 DRM_DEBUG("Forced to use aperture for PDEs\n");
2034 gen6_free_scratch(vm
);
2038 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2040 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2043 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2044 uint64_t start
, uint64_t length
)
2046 struct i915_page_table
*unused
;
2049 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
2050 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2053 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2055 struct drm_device
*dev
= ppgtt
->base
.dev
;
2056 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2057 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2060 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
2061 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev
))
2062 ppgtt
->switch_mm
= gen6_mm_switch
;
2063 else if (IS_HASWELL(dev
))
2064 ppgtt
->switch_mm
= hsw_mm_switch
;
2065 else if (IS_GEN7(dev
))
2066 ppgtt
->switch_mm
= gen7_mm_switch
;
2070 ret
= gen6_ppgtt_alloc(ppgtt
);
2074 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2075 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2076 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2077 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2078 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2079 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2080 ppgtt
->base
.start
= 0;
2081 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2082 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2084 ppgtt
->pd
.base
.ggtt_offset
=
2085 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2087 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
2088 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2090 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2092 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2094 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2095 ppgtt
->node
.size
>> 20,
2096 ppgtt
->node
.start
/ PAGE_SIZE
);
2098 DRM_DEBUG("Adding PPGTT at offset %x\n",
2099 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2104 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2106 ppgtt
->base
.dev
= dev
;
2108 if (INTEL_INFO(dev
)->gen
< 8)
2109 return gen6_ppgtt_init(ppgtt
);
2111 return gen8_ppgtt_init(ppgtt
);
2114 static void i915_address_space_init(struct i915_address_space
*vm
,
2115 struct drm_i915_private
*dev_priv
)
2117 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2118 vm
->dev
= &dev_priv
->drm
;
2119 INIT_LIST_HEAD(&vm
->active_list
);
2120 INIT_LIST_HEAD(&vm
->inactive_list
);
2121 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2124 static void gtt_write_workarounds(struct drm_device
*dev
)
2126 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2128 /* This function is for gtt related workarounds. This function is
2129 * called on driver load and after a GPU reset, so you can place
2130 * workarounds here even if they get overwritten by GPU reset.
2132 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2133 if (IS_BROADWELL(dev
))
2134 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
2135 else if (IS_CHERRYVIEW(dev
))
2136 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
2137 else if (IS_SKYLAKE(dev
))
2138 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
2139 else if (IS_BROXTON(dev
))
2140 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
2143 static int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2145 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2148 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2150 kref_init(&ppgtt
->ref
);
2151 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2157 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2159 gtt_write_workarounds(dev
);
2161 /* In the case of execlists, PPGTT is enabled by the context descriptor
2162 * and the PDPs are contained within the context itself. We don't
2163 * need to do anything here. */
2164 if (i915
.enable_execlists
)
2167 if (!USES_PPGTT(dev
))
2171 gen6_ppgtt_enable(dev
);
2172 else if (IS_GEN7(dev
))
2173 gen7_ppgtt_enable(dev
);
2174 else if (INTEL_INFO(dev
)->gen
>= 8)
2175 gen8_ppgtt_enable(dev
);
2177 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2182 struct i915_hw_ppgtt
*
2183 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
2185 struct i915_hw_ppgtt
*ppgtt
;
2188 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2190 return ERR_PTR(-ENOMEM
);
2192 ret
= i915_ppgtt_init(dev
, ppgtt
);
2195 return ERR_PTR(ret
);
2198 ppgtt
->file_priv
= fpriv
;
2200 trace_i915_ppgtt_create(&ppgtt
->base
);
2205 void i915_ppgtt_release(struct kref
*kref
)
2207 struct i915_hw_ppgtt
*ppgtt
=
2208 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2210 trace_i915_ppgtt_release(&ppgtt
->base
);
2212 /* vmas should already be unbound */
2213 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2214 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2216 list_del(&ppgtt
->base
.global_link
);
2217 drm_mm_takedown(&ppgtt
->base
.mm
);
2219 ppgtt
->base
.cleanup(&ppgtt
->base
);
2223 extern int intel_iommu_gfx_mapped
;
2224 /* Certain Gen5 chipsets require require idling the GPU before
2225 * unmapping anything from the GTT when VT-d is enabled.
2227 static bool needs_idle_maps(struct drm_device
*dev
)
2229 #ifdef CONFIG_INTEL_IOMMU
2230 /* Query intel_iommu to see if we need the workaround. Presumably that
2233 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
2239 static bool do_idling(struct drm_i915_private
*dev_priv
)
2241 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2242 bool ret
= dev_priv
->mm
.interruptible
;
2244 if (unlikely(ggtt
->do_idle_maps
)) {
2245 dev_priv
->mm
.interruptible
= false;
2246 if (i915_gem_wait_for_idle(dev_priv
)) {
2247 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2248 /* Wait a bit, in hopes it avoids the hang */
2256 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
2258 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2260 if (unlikely(ggtt
->do_idle_maps
))
2261 dev_priv
->mm
.interruptible
= interruptible
;
2264 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2266 struct intel_engine_cs
*engine
;
2268 if (INTEL_INFO(dev_priv
)->gen
< 6)
2271 for_each_engine(engine
, dev_priv
) {
2273 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2274 if (fault_reg
& RING_FAULT_VALID
) {
2275 DRM_DEBUG_DRIVER("Unexpected fault\n"
2277 "\tAddress space: %s\n"
2280 fault_reg
& PAGE_MASK
,
2281 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2282 RING_FAULT_SRCID(fault_reg
),
2283 RING_FAULT_FAULT_TYPE(fault_reg
));
2284 I915_WRITE(RING_FAULT_REG(engine
),
2285 fault_reg
& ~RING_FAULT_VALID
);
2288 POSTING_READ(RING_FAULT_REG(&dev_priv
->engine
[RCS
]));
2291 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2293 if (INTEL_INFO(dev_priv
)->gen
< 6) {
2294 intel_gtt_chipset_flush();
2296 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2297 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2301 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2303 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2304 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2306 /* Don't bother messing with faults pre GEN6 as we have little
2307 * documentation supporting that it's a good idea.
2309 if (INTEL_INFO(dev
)->gen
< 6)
2312 i915_check_and_clear_faults(dev_priv
);
2314 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
2317 i915_ggtt_flush(dev_priv
);
2320 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2322 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2323 obj
->pages
->sgl
, obj
->pages
->nents
,
2324 PCI_DMA_BIDIRECTIONAL
))
2330 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2335 iowrite32((u32
)pte
, addr
);
2336 iowrite32(pte
>> 32, addr
+ 4);
2340 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2343 enum i915_cache_level level
,
2346 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2347 gen8_pte_t __iomem
*pte
=
2348 (gen8_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2349 (offset
>> PAGE_SHIFT
);
2352 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2354 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
, true));
2356 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2357 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2359 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2362 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2363 struct sg_table
*st
,
2365 enum i915_cache_level level
, u32 unused
)
2367 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2368 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2369 struct sgt_iter sgt_iter
;
2370 gen8_pte_t __iomem
*gtt_entries
;
2371 gen8_pte_t gtt_entry
;
2376 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2378 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2380 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2381 gtt_entry
= gen8_pte_encode(addr
, level
, true);
2382 gen8_set_pte(>t_entries
[i
++], gtt_entry
);
2386 * XXX: This serves as a posting read to make sure that the PTE has
2387 * actually been updated. There is some concern that even though
2388 * registers and PTEs are within the same BAR that they are potentially
2389 * of NUMA access patterns. Therefore, even with the way we assume
2390 * hardware should work, we must keep this posting read for paranoia.
2393 WARN_ON(readq(>t_entries
[i
-1]) != gtt_entry
);
2395 /* This next bit makes the above posting read even more important. We
2396 * want to flush the TLBs only after we're certain all the PTE updates
2399 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2400 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2402 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2405 struct insert_entries
{
2406 struct i915_address_space
*vm
;
2407 struct sg_table
*st
;
2409 enum i915_cache_level level
;
2413 static int gen8_ggtt_insert_entries__cb(void *_arg
)
2415 struct insert_entries
*arg
= _arg
;
2416 gen8_ggtt_insert_entries(arg
->vm
, arg
->st
,
2417 arg
->start
, arg
->level
, arg
->flags
);
2421 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2422 struct sg_table
*st
,
2424 enum i915_cache_level level
,
2427 struct insert_entries arg
= { vm
, st
, start
, level
, flags
};
2428 stop_machine(gen8_ggtt_insert_entries__cb
, &arg
, NULL
);
2431 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2434 enum i915_cache_level level
,
2437 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2438 gen6_pte_t __iomem
*pte
=
2439 (gen6_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2440 (offset
>> PAGE_SHIFT
);
2443 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2445 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), pte
);
2447 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2448 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2450 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2454 * Binds an object into the global gtt with the specified cache level. The object
2455 * will be accessible to the GPU via commands whose operands reference offsets
2456 * within the global GTT as well as accessible by the GPU through the GMADR
2457 * mapped BAR (dev_priv->mm.gtt->gtt).
2459 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2460 struct sg_table
*st
,
2462 enum i915_cache_level level
, u32 flags
)
2464 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2465 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2466 struct sgt_iter sgt_iter
;
2467 gen6_pte_t __iomem
*gtt_entries
;
2468 gen6_pte_t gtt_entry
;
2473 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2475 gtt_entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2477 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2478 gtt_entry
= vm
->pte_encode(addr
, level
, true, flags
);
2479 iowrite32(gtt_entry
, >t_entries
[i
++]);
2482 /* XXX: This serves as a posting read to make sure that the PTE has
2483 * actually been updated. There is some concern that even though
2484 * registers and PTEs are within the same BAR that they are potentially
2485 * of NUMA access patterns. Therefore, even with the way we assume
2486 * hardware should work, we must keep this posting read for paranoia.
2489 WARN_ON(readl(>t_entries
[i
-1]) != gtt_entry
);
2491 /* This next bit makes the above posting read even more important. We
2492 * want to flush the TLBs only after we're certain all the PTE updates
2495 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2496 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2498 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2501 static void nop_clear_range(struct i915_address_space
*vm
,
2508 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2513 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2514 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2515 unsigned first_entry
= start
>> PAGE_SHIFT
;
2516 unsigned num_entries
= length
>> PAGE_SHIFT
;
2517 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2518 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2519 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2523 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2525 if (WARN(num_entries
> max_entries
,
2526 "First entry = %d; Num entries = %d (max=%d)\n",
2527 first_entry
, num_entries
, max_entries
))
2528 num_entries
= max_entries
;
2530 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2533 for (i
= 0; i
< num_entries
; i
++)
2534 gen8_set_pte(>t_base
[i
], scratch_pte
);
2537 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2540 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2545 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2546 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2547 unsigned first_entry
= start
>> PAGE_SHIFT
;
2548 unsigned num_entries
= length
>> PAGE_SHIFT
;
2549 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2550 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2551 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2555 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2557 if (WARN(num_entries
> max_entries
,
2558 "First entry = %d; Num entries = %d (max=%d)\n",
2559 first_entry
, num_entries
, max_entries
))
2560 num_entries
= max_entries
;
2562 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2563 I915_CACHE_LLC
, use_scratch
, 0);
2565 for (i
= 0; i
< num_entries
; i
++)
2566 iowrite32(scratch_pte
, >t_base
[i
]);
2569 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2572 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2575 enum i915_cache_level cache_level
,
2578 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2579 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2580 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2583 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2585 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2587 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2590 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2591 struct sg_table
*pages
,
2593 enum i915_cache_level cache_level
, u32 unused
)
2595 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2596 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2597 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2600 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2602 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2604 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2608 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2613 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2614 unsigned first_entry
= start
>> PAGE_SHIFT
;
2615 unsigned num_entries
= length
>> PAGE_SHIFT
;
2618 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2620 intel_gtt_clear_range(first_entry
, num_entries
);
2622 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2625 static int ggtt_bind_vma(struct i915_vma
*vma
,
2626 enum i915_cache_level cache_level
,
2629 struct drm_i915_gem_object
*obj
= vma
->obj
;
2633 ret
= i915_get_ggtt_vma_pages(vma
);
2637 /* Currently applicable only to VLV */
2639 pte_flags
|= PTE_READ_ONLY
;
2641 vma
->vm
->insert_entries(vma
->vm
, vma
->ggtt_view
.pages
,
2643 cache_level
, pte_flags
);
2646 * Without aliasing PPGTT there's no difference between
2647 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2648 * upgrade to both bound if we bind either to avoid double-binding.
2650 vma
->bound
|= GLOBAL_BIND
| LOCAL_BIND
;
2655 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2656 enum i915_cache_level cache_level
,
2662 ret
= i915_get_ggtt_vma_pages(vma
);
2666 /* Currently applicable only to VLV */
2668 if (vma
->obj
->gt_ro
)
2669 pte_flags
|= PTE_READ_ONLY
;
2672 if (flags
& GLOBAL_BIND
) {
2673 vma
->vm
->insert_entries(vma
->vm
,
2674 vma
->ggtt_view
.pages
,
2676 cache_level
, pte_flags
);
2679 if (flags
& LOCAL_BIND
) {
2680 struct i915_hw_ppgtt
*appgtt
=
2681 to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2682 appgtt
->base
.insert_entries(&appgtt
->base
,
2683 vma
->ggtt_view
.pages
,
2685 cache_level
, pte_flags
);
2691 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2693 struct drm_device
*dev
= vma
->vm
->dev
;
2694 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2695 struct drm_i915_gem_object
*obj
= vma
->obj
;
2696 const uint64_t size
= min_t(uint64_t,
2700 if (vma
->bound
& GLOBAL_BIND
) {
2701 vma
->vm
->clear_range(vma
->vm
,
2707 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2708 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2710 appgtt
->base
.clear_range(&appgtt
->base
,
2717 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2719 struct drm_device
*dev
= obj
->base
.dev
;
2720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2723 interruptible
= do_idling(dev_priv
);
2725 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2726 PCI_DMA_BIDIRECTIONAL
);
2728 undo_idling(dev_priv
, interruptible
);
2731 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2732 unsigned long color
,
2736 if (node
->color
!= color
)
2739 if (!list_empty(&node
->node_list
)) {
2740 node
= list_entry(node
->node_list
.next
,
2743 if (node
->allocated
&& node
->color
!= color
)
2748 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2753 /* Let GEM Manage all of the aperture.
2755 * However, leave one page at the end still bound to the scratch page.
2756 * There are a number of places where the hardware apparently prefetches
2757 * past the end of the object, and we've seen multiple hangs with the
2758 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2759 * aperture. One page should be enough to keep any prefetching inside
2762 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2763 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2764 struct drm_mm_node
*entry
;
2765 struct drm_i915_gem_object
*obj
;
2766 unsigned long hole_start
, hole_end
;
2769 BUG_ON(mappable_end
> end
);
2771 ggtt
->base
.start
= start
;
2773 /* Subtract the guard page before address space initialization to
2774 * shrink the range used by drm_mm */
2775 ggtt
->base
.total
= end
- start
- PAGE_SIZE
;
2776 i915_address_space_init(&ggtt
->base
, dev_priv
);
2777 ggtt
->base
.total
+= PAGE_SIZE
;
2779 ret
= intel_vgt_balloon(dev_priv
);
2784 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2786 /* Mark any preallocated objects as occupied */
2787 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2788 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, &ggtt
->base
);
2790 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2791 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2793 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2794 ret
= drm_mm_reserve_node(&ggtt
->base
.mm
, &vma
->node
);
2796 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2799 vma
->bound
|= GLOBAL_BIND
;
2800 __i915_vma_set_map_and_fenceable(vma
);
2801 list_add_tail(&vma
->vm_link
, &ggtt
->base
.inactive_list
);
2804 /* Clear any non-preallocated blocks */
2805 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2806 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2807 hole_start
, hole_end
);
2808 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2809 hole_end
- hole_start
, true);
2812 /* And finally clear the reserved guard page */
2813 ggtt
->base
.clear_range(&ggtt
->base
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2815 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2816 struct i915_hw_ppgtt
*ppgtt
;
2818 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2822 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2824 ppgtt
->base
.cleanup(&ppgtt
->base
);
2829 if (ppgtt
->base
.allocate_va_range
)
2830 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2833 ppgtt
->base
.cleanup(&ppgtt
->base
);
2838 ppgtt
->base
.clear_range(&ppgtt
->base
,
2843 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2844 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2845 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2852 * i915_gem_init_ggtt - Initialize GEM for Global GTT
2855 void i915_gem_init_ggtt(struct drm_device
*dev
)
2857 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2858 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2860 i915_gem_setup_global_gtt(dev
, 0, ggtt
->mappable_end
, ggtt
->base
.total
);
2864 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2867 void i915_ggtt_cleanup_hw(struct drm_device
*dev
)
2869 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2870 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2872 if (dev_priv
->mm
.aliasing_ppgtt
) {
2873 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2875 ppgtt
->base
.cleanup(&ppgtt
->base
);
2878 i915_gem_cleanup_stolen(dev
);
2880 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2881 intel_vgt_deballoon(dev_priv
);
2883 drm_mm_takedown(&ggtt
->base
.mm
);
2884 list_del(&ggtt
->base
.global_link
);
2887 ggtt
->base
.cleanup(&ggtt
->base
);
2890 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2892 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2893 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2894 return snb_gmch_ctl
<< 20;
2897 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2899 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2900 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2902 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2904 #ifdef CONFIG_X86_32
2905 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2906 if (bdw_gmch_ctl
> 4)
2910 return bdw_gmch_ctl
<< 20;
2913 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2915 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2916 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2919 return 1 << (20 + gmch_ctrl
);
2924 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2926 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2927 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2928 return snb_gmch_ctl
<< 25; /* 32 MB units */
2931 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2933 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2934 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2935 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2938 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2940 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2941 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2944 * 0x0 to 0x10: 32MB increments starting at 0MB
2945 * 0x11 to 0x16: 4MB increments starting at 8MB
2946 * 0x17 to 0x1d: 4MB increments start at 36MB
2948 if (gmch_ctrl
< 0x11)
2949 return gmch_ctrl
<< 25;
2950 else if (gmch_ctrl
< 0x17)
2951 return (gmch_ctrl
- 0x11 + 2) << 22;
2953 return (gmch_ctrl
- 0x17 + 9) << 22;
2956 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2958 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2959 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2961 if (gen9_gmch_ctl
< 0xf0)
2962 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2964 /* 4MB increments starting at 0xf0 for 4MB */
2965 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2968 static int ggtt_probe_common(struct drm_device
*dev
,
2971 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2972 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2973 struct i915_page_scratch
*scratch_page
;
2974 phys_addr_t ggtt_phys_addr
;
2976 /* For Modern GENs the PTEs and register space are split in the BAR */
2977 ggtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2978 (pci_resource_len(dev
->pdev
, 0) / 2);
2981 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2982 * dropped. For WC mappings in general we have 64 byte burst writes
2983 * when the WC buffer is flushed, so we can't use it, but have to
2984 * resort to an uncached mapping. The WC issue is easily caught by the
2985 * readback check when writing GTT PTE entries.
2987 if (IS_BROXTON(dev
))
2988 ggtt
->gsm
= ioremap_nocache(ggtt_phys_addr
, gtt_size
);
2990 ggtt
->gsm
= ioremap_wc(ggtt_phys_addr
, gtt_size
);
2992 DRM_ERROR("Failed to map the gtt page table\n");
2996 scratch_page
= alloc_scratch_page(dev
);
2997 if (IS_ERR(scratch_page
)) {
2998 DRM_ERROR("Scratch setup failed\n");
2999 /* iounmap will also get called at remove, but meh */
3001 return PTR_ERR(scratch_page
);
3004 ggtt
->base
.scratch_page
= scratch_page
;
3009 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3010 * bits. When using advanced contexts each context stores its own PAT, but
3011 * writing this data shouldn't be harmful even in those cases. */
3012 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
3016 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
3017 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
3018 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
3019 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
3020 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
3021 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
3022 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
3023 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
3025 if (!USES_PPGTT(dev_priv
))
3026 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3027 * so RTL will always use the value corresponding to
3029 * So let's disable cache for GGTT to avoid screen corruptions.
3030 * MOCS still can be used though.
3031 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3032 * before this patch, i.e. the same uncached + snooping access
3033 * like on gen6/7 seems to be in effect.
3034 * - So this just fixes blitter/render access. Again it looks
3035 * like it's not just uncached access, but uncached + snooping.
3036 * So we can still hold onto all our assumptions wrt cpu
3037 * clflushing on LLC machines.
3039 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
3041 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
3042 * write would work. */
3043 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
3044 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
3047 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
3052 * Map WB on BDW to snooped on CHV.
3054 * Only the snoop bit has meaning for CHV, the rest is
3057 * The hardware will never snoop for certain types of accesses:
3058 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3059 * - PPGTT page tables
3060 * - some other special cycles
3062 * As with BDW, we also need to consider the following for GT accesses:
3063 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3064 * so RTL will always use the value corresponding to
3066 * Which means we must set the snoop bit in PAT entry 0
3067 * in order to keep the global status page working.
3069 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
3073 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
3074 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
3075 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
3076 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
3078 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
3079 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
3082 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
3084 struct drm_device
*dev
= ggtt
->base
.dev
;
3085 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3089 /* TODO: We're not aware of mappable constraints on gen8 yet */
3090 ggtt
->mappable_base
= pci_resource_start(dev
->pdev
, 2);
3091 ggtt
->mappable_end
= pci_resource_len(dev
->pdev
, 2);
3093 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
3094 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
3096 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3098 if (INTEL_INFO(dev
)->gen
>= 9) {
3099 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
3100 ggtt
->size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3101 } else if (IS_CHERRYVIEW(dev
)) {
3102 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
3103 ggtt
->size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3105 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
3106 ggtt
->size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3109 ggtt
->base
.total
= (ggtt
->size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3111 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3112 chv_setup_private_ppat(dev_priv
);
3114 bdw_setup_private_ppat(dev_priv
);
3116 ret
= ggtt_probe_common(dev
, ggtt
->size
);
3118 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3119 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3120 ggtt
->base
.insert_page
= gen8_ggtt_insert_page
;
3121 ggtt
->base
.clear_range
= nop_clear_range
;
3122 if (!USES_FULL_PPGTT(dev_priv
))
3123 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
3125 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
3126 if (IS_CHERRYVIEW(dev_priv
))
3127 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries__BKL
;
3132 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
3134 struct drm_device
*dev
= ggtt
->base
.dev
;
3138 ggtt
->mappable_base
= pci_resource_start(dev
->pdev
, 2);
3139 ggtt
->mappable_end
= pci_resource_len(dev
->pdev
, 2);
3141 /* 64/512MB is the current min/max we actually know of, but this is just
3142 * a coarse sanity check.
3144 if ((ggtt
->mappable_end
< (64<<20) || (ggtt
->mappable_end
> (512<<20)))) {
3145 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
3149 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
3150 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
3151 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3153 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
3154 ggtt
->size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3155 ggtt
->base
.total
= (ggtt
->size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3157 ret
= ggtt_probe_common(dev
, ggtt
->size
);
3159 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
3160 ggtt
->base
.insert_page
= gen6_ggtt_insert_page
;
3161 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
3162 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3163 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3168 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3170 struct i915_ggtt
*ggtt
= container_of(vm
, struct i915_ggtt
, base
);
3173 free_scratch_page(vm
->dev
, vm
->scratch_page
);
3176 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
3178 struct drm_device
*dev
= ggtt
->base
.dev
;
3179 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3182 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
3184 DRM_ERROR("failed to set up gmch\n");
3188 intel_gtt_get(&ggtt
->base
.total
, &ggtt
->stolen_size
,
3189 &ggtt
->mappable_base
, &ggtt
->mappable_end
);
3191 ggtt
->do_idle_maps
= needs_idle_maps(&dev_priv
->drm
);
3192 ggtt
->base
.insert_page
= i915_ggtt_insert_page
;
3193 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
3194 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
3195 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3196 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3198 if (unlikely(ggtt
->do_idle_maps
))
3199 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3204 static void i915_gmch_remove(struct i915_address_space
*vm
)
3206 intel_gmch_remove();
3210 * i915_ggtt_init_hw - Initialize GGTT hardware
3213 int i915_ggtt_init_hw(struct drm_device
*dev
)
3215 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3216 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3219 if (INTEL_INFO(dev
)->gen
<= 5) {
3220 ggtt
->probe
= i915_gmch_probe
;
3221 ggtt
->base
.cleanup
= i915_gmch_remove
;
3222 } else if (INTEL_INFO(dev
)->gen
< 8) {
3223 ggtt
->probe
= gen6_gmch_probe
;
3224 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3227 ggtt
->base
.pte_encode
= iris_pte_encode
;
3228 else if (IS_HASWELL(dev
))
3229 ggtt
->base
.pte_encode
= hsw_pte_encode
;
3230 else if (IS_VALLEYVIEW(dev
))
3231 ggtt
->base
.pte_encode
= byt_pte_encode
;
3232 else if (INTEL_INFO(dev
)->gen
>= 7)
3233 ggtt
->base
.pte_encode
= ivb_pte_encode
;
3235 ggtt
->base
.pte_encode
= snb_pte_encode
;
3237 ggtt
->probe
= gen8_gmch_probe
;
3238 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3241 ggtt
->base
.dev
= dev
;
3242 ggtt
->base
.is_ggtt
= true;
3244 ret
= ggtt
->probe(ggtt
);
3248 if ((ggtt
->base
.total
- 1) >> 32) {
3249 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3250 "of address space! Found %lldM!\n",
3251 ggtt
->base
.total
>> 20);
3252 ggtt
->base
.total
= 1ULL << 32;
3253 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3257 * Initialise stolen early so that we may reserve preallocated
3258 * objects for the BIOS to KMS transition.
3260 ret
= i915_gem_init_stolen(dev
);
3262 goto out_gtt_cleanup
;
3264 /* GMADR is the PCI mmio aperture into the global GTT. */
3265 DRM_INFO("Memory usable by graphics device = %lluM\n",
3266 ggtt
->base
.total
>> 20);
3267 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
3268 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt
->stolen_size
>> 20);
3269 #ifdef CONFIG_INTEL_IOMMU
3270 if (intel_iommu_gfx_mapped
)
3271 DRM_INFO("VT-d active for gfx access\n");
3277 ggtt
->base
.cleanup(&ggtt
->base
);
3282 int i915_ggtt_enable_hw(struct drm_device
*dev
)
3284 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3290 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3293 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3294 struct drm_i915_gem_object
*obj
;
3295 struct i915_vma
*vma
;
3297 i915_check_and_clear_faults(dev_priv
);
3299 /* First fill our portion of the GTT with scratch pages */
3300 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
3303 /* Cache flush objects bound into GGTT and rebind them. */
3304 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3305 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3306 if (vma
->vm
!= &ggtt
->base
)
3309 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3313 if (obj
->pin_display
)
3314 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3317 if (INTEL_INFO(dev
)->gen
>= 8) {
3318 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3319 chv_setup_private_ppat(dev_priv
);
3321 bdw_setup_private_ppat(dev_priv
);
3326 if (USES_PPGTT(dev
)) {
3327 struct i915_address_space
*vm
;
3329 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3330 /* TODO: Perhaps it shouldn't be gen6 specific */
3332 struct i915_hw_ppgtt
*ppgtt
;
3335 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3337 ppgtt
= i915_vm_to_ppgtt(vm
);
3339 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3340 0, ppgtt
->base
.total
);
3344 i915_ggtt_flush(dev_priv
);
3347 static struct i915_vma
*
3348 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
3349 struct i915_address_space
*vm
,
3350 const struct i915_ggtt_view
*ggtt_view
)
3352 struct i915_vma
*vma
;
3354 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3355 return ERR_PTR(-EINVAL
);
3357 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3359 return ERR_PTR(-ENOMEM
);
3361 INIT_LIST_HEAD(&vma
->vm_link
);
3362 INIT_LIST_HEAD(&vma
->obj_link
);
3363 INIT_LIST_HEAD(&vma
->exec_list
);
3366 vma
->is_ggtt
= i915_is_ggtt(vm
);
3368 if (i915_is_ggtt(vm
))
3369 vma
->ggtt_view
= *ggtt_view
;
3371 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3373 list_add_tail(&vma
->obj_link
, &obj
->vma_list
);
3379 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3380 struct i915_address_space
*vm
)
3382 struct i915_vma
*vma
;
3384 vma
= i915_gem_obj_to_vma(obj
, vm
);
3386 vma
= __i915_gem_vma_create(obj
, vm
,
3387 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3393 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3394 const struct i915_ggtt_view
*view
)
3396 struct drm_device
*dev
= obj
->base
.dev
;
3397 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3398 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3399 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3402 vma
= __i915_gem_vma_create(obj
, &ggtt
->base
, view
);
3408 static struct scatterlist
*
3409 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3410 unsigned int width
, unsigned int height
,
3411 unsigned int stride
,
3412 struct sg_table
*st
, struct scatterlist
*sg
)
3414 unsigned int column
, row
;
3415 unsigned int src_idx
;
3417 for (column
= 0; column
< width
; column
++) {
3418 src_idx
= stride
* (height
- 1) + column
;
3419 for (row
= 0; row
< height
; row
++) {
3421 /* We don't need the pages, but need to initialize
3422 * the entries so the sg list can be happily traversed.
3423 * The only thing we need are DMA addresses.
3425 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3426 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3427 sg_dma_len(sg
) = PAGE_SIZE
;
3436 static struct sg_table
*
3437 intel_rotate_fb_obj_pages(struct intel_rotation_info
*rot_info
,
3438 struct drm_i915_gem_object
*obj
)
3440 const size_t n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3441 unsigned int size_pages
= rot_info
->plane
[0].width
* rot_info
->plane
[0].height
;
3442 unsigned int size_pages_uv
;
3443 struct sgt_iter sgt_iter
;
3444 dma_addr_t dma_addr
;
3446 dma_addr_t
*page_addr_list
;
3447 struct sg_table
*st
;
3448 unsigned int uv_start_page
;
3449 struct scatterlist
*sg
;
3452 /* Allocate a temporary list of source pages for random access. */
3453 page_addr_list
= drm_malloc_gfp(n_pages
,
3456 if (!page_addr_list
)
3457 return ERR_PTR(ret
);
3459 /* Account for UV plane with NV12. */
3460 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
)
3461 size_pages_uv
= rot_info
->plane
[1].width
* rot_info
->plane
[1].height
;
3465 /* Allocate target SG list. */
3466 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3470 ret
= sg_alloc_table(st
, size_pages
+ size_pages_uv
, GFP_KERNEL
);
3474 /* Populate source page list from the object. */
3476 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->pages
)
3477 page_addr_list
[i
++] = dma_addr
;
3479 GEM_BUG_ON(i
!= n_pages
);
3483 /* Rotate the pages. */
3484 sg
= rotate_pages(page_addr_list
, 0,
3485 rot_info
->plane
[0].width
, rot_info
->plane
[0].height
,
3486 rot_info
->plane
[0].width
,
3489 /* Append the UV plane if NV12. */
3490 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
) {
3491 uv_start_page
= size_pages
;
3493 /* Check for tile-row un-alignment. */
3494 if (offset_in_page(rot_info
->uv_offset
))
3497 rot_info
->uv_start_page
= uv_start_page
;
3499 sg
= rotate_pages(page_addr_list
, rot_info
->uv_start_page
,
3500 rot_info
->plane
[1].width
, rot_info
->plane
[1].height
,
3501 rot_info
->plane
[1].width
,
3505 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3506 obj
->base
.size
, rot_info
->plane
[0].width
,
3507 rot_info
->plane
[0].height
, size_pages
+ size_pages_uv
,
3510 drm_free_large(page_addr_list
);
3517 drm_free_large(page_addr_list
);
3519 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3520 obj
->base
.size
, ret
, rot_info
->plane
[0].width
,
3521 rot_info
->plane
[0].height
, size_pages
+ size_pages_uv
,
3523 return ERR_PTR(ret
);
3526 static struct sg_table
*
3527 intel_partial_pages(const struct i915_ggtt_view
*view
,
3528 struct drm_i915_gem_object
*obj
)
3530 struct sg_table
*st
;
3531 struct scatterlist
*sg
;
3532 struct sg_page_iter obj_sg_iter
;
3535 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3539 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3545 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3546 view
->params
.partial
.offset
)
3548 if (st
->nents
>= view
->params
.partial
.size
)
3551 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3552 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3553 sg_dma_len(sg
) = PAGE_SIZE
;
3564 return ERR_PTR(ret
);
3568 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3572 if (vma
->ggtt_view
.pages
)
3575 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3576 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3577 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3578 vma
->ggtt_view
.pages
=
3579 intel_rotate_fb_obj_pages(&vma
->ggtt_view
.params
.rotated
, vma
->obj
);
3580 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3581 vma
->ggtt_view
.pages
=
3582 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3584 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3585 vma
->ggtt_view
.type
);
3587 if (!vma
->ggtt_view
.pages
) {
3588 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3589 vma
->ggtt_view
.type
);
3591 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3592 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3593 vma
->ggtt_view
.pages
= NULL
;
3594 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3595 vma
->ggtt_view
.type
, ret
);
3602 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3604 * @cache_level: mapping cache level
3605 * @flags: flags like global or local mapping
3607 * DMA addresses are taken from the scatter-gather table of this object (or of
3608 * this VMA in case of non-default GGTT views) and PTE entries set up.
3609 * Note that DMA addresses are also the only part of the SG table we care about.
3611 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3617 if (WARN_ON(flags
== 0))
3621 if (flags
& PIN_GLOBAL
)
3622 bind_flags
|= GLOBAL_BIND
;
3623 if (flags
& PIN_USER
)
3624 bind_flags
|= LOCAL_BIND
;
3626 if (flags
& PIN_UPDATE
)
3627 bind_flags
|= vma
->bound
;
3629 bind_flags
&= ~vma
->bound
;
3631 if (bind_flags
== 0)
3634 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3635 /* XXX: i915_vma_pin() will fix this +- hack */
3637 trace_i915_va_alloc(vma
);
3638 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3646 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3650 vma
->bound
|= bind_flags
;
3656 * i915_ggtt_view_size - Get the size of a GGTT view.
3657 * @obj: Object the view is of.
3658 * @view: The view in question.
3660 * @return The size of the GGTT view in bytes.
3663 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3664 const struct i915_ggtt_view
*view
)
3666 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3667 return obj
->base
.size
;
3668 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3669 return intel_rotation_info_size(&view
->params
.rotated
) << PAGE_SHIFT
;
3670 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3671 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3673 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3674 return obj
->base
.size
;
3678 void __iomem
*i915_vma_pin_iomap(struct i915_vma
*vma
)
3682 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3683 if (WARN_ON(!vma
->obj
->map_and_fenceable
))
3684 return ERR_PTR(-ENODEV
);
3686 GEM_BUG_ON(!vma
->is_ggtt
);
3687 GEM_BUG_ON((vma
->bound
& GLOBAL_BIND
) == 0);
3691 ptr
= io_mapping_map_wc(i915_vm_to_ggtt(vma
->vm
)->mappable
,
3695 return ERR_PTR(-ENOMEM
);