2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 typedef uint32_t gtt_pte_t
;
34 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
36 #define GEN6_PDE_VALID (1 << 0)
37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
38 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
40 #define GEN6_PTE_VALID (1 << 0)
41 #define GEN6_PTE_UNCACHED (1 << 1)
42 #define HSW_PTE_UNCACHED (0)
43 #define GEN6_PTE_CACHE_LLC (2 << 1)
44 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
45 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
47 static inline gtt_pte_t
gen6_pte_encode(struct drm_device
*dev
,
49 enum i915_cache_level level
)
51 gtt_pte_t pte
= GEN6_PTE_VALID
;
52 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
55 case I915_CACHE_LLC_MLC
:
56 /* Haswell doesn't set L3 this way */
58 pte
|= GEN6_PTE_CACHE_LLC
;
60 pte
|= GEN6_PTE_CACHE_LLC_MLC
;
63 pte
|= GEN6_PTE_CACHE_LLC
;
67 pte
|= HSW_PTE_UNCACHED
;
69 pte
|= GEN6_PTE_UNCACHED
;
79 /* PPGTT support for Sandybdrige/Gen6 and later */
80 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt
*ppgtt
,
85 gtt_pte_t scratch_pte
;
86 unsigned act_pd
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
87 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
90 scratch_pte
= gen6_pte_encode(ppgtt
->dev
,
91 ppgtt
->scratch_page_dma_addr
,
95 last_pte
= first_pte
+ num_entries
;
96 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
97 last_pte
= I915_PPGTT_PT_ENTRIES
;
99 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pd
]);
101 for (i
= first_pte
; i
< last_pte
; i
++)
102 pt_vaddr
[i
] = scratch_pte
;
104 kunmap_atomic(pt_vaddr
);
106 num_entries
-= last_pte
- first_pte
;
112 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt
*ppgtt
,
113 struct sg_table
*pages
,
114 unsigned first_entry
,
115 enum i915_cache_level cache_level
)
118 unsigned act_pd
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
119 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
120 unsigned i
, j
, m
, segment_len
;
121 dma_addr_t page_addr
;
122 struct scatterlist
*sg
;
124 /* init sg walking */
127 segment_len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
130 while (i
< pages
->nents
) {
131 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pd
]);
133 for (j
= first_pte
; j
< I915_PPGTT_PT_ENTRIES
; j
++) {
134 page_addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
135 pt_vaddr
[j
] = gen6_pte_encode(ppgtt
->dev
, page_addr
,
138 /* grab the next page */
139 if (++m
== segment_len
) {
140 if (++i
== pages
->nents
)
144 segment_len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
149 kunmap_atomic(pt_vaddr
);
156 static int i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
)
158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
159 struct i915_hw_ppgtt
*ppgtt
;
160 unsigned first_pd_entry_in_global_pt
;
164 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
165 * entries. For aliasing ppgtt support we just steal them at the end for
167 first_pd_entry_in_global_pt
= dev_priv
->mm
.gtt
->gtt_total_entries
- I915_PPGTT_PD_ENTRIES
;
169 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
174 ppgtt
->num_pd_entries
= I915_PPGTT_PD_ENTRIES
;
175 ppgtt
->clear_range
= gen6_ppgtt_clear_range
;
176 ppgtt
->insert_entries
= gen6_ppgtt_insert_entries
;
177 ppgtt
->pt_pages
= kzalloc(sizeof(struct page
*)*ppgtt
->num_pd_entries
,
179 if (!ppgtt
->pt_pages
)
182 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
183 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
184 if (!ppgtt
->pt_pages
[i
])
188 ppgtt
->pt_dma_addr
= kzalloc(sizeof(dma_addr_t
) *ppgtt
->num_pd_entries
,
190 if (!ppgtt
->pt_dma_addr
)
193 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
196 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
197 PCI_DMA_BIDIRECTIONAL
);
199 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
204 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
207 ppgtt
->scratch_page_dma_addr
= dev_priv
->gtt
.scratch_page_dma
;
209 ppgtt
->clear_range(ppgtt
, 0,
210 ppgtt
->num_pd_entries
*I915_PPGTT_PT_ENTRIES
);
212 ppgtt
->pd_offset
= (first_pd_entry_in_global_pt
)*sizeof(gtt_pte_t
);
214 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
219 if (ppgtt
->pt_dma_addr
) {
220 for (i
--; i
>= 0; i
--)
221 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
222 4096, PCI_DMA_BIDIRECTIONAL
);
225 kfree(ppgtt
->pt_dma_addr
);
226 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
227 if (ppgtt
->pt_pages
[i
])
228 __free_page(ppgtt
->pt_pages
[i
]);
230 kfree(ppgtt
->pt_pages
);
237 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
)
239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
240 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
246 if (ppgtt
->pt_dma_addr
) {
247 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
248 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
249 4096, PCI_DMA_BIDIRECTIONAL
);
252 kfree(ppgtt
->pt_dma_addr
);
253 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
254 __free_page(ppgtt
->pt_pages
[i
]);
255 kfree(ppgtt
->pt_pages
);
259 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
260 struct drm_i915_gem_object
*obj
,
261 enum i915_cache_level cache_level
)
263 ppgtt
->insert_entries(ppgtt
, obj
->pages
,
264 obj
->gtt_space
->start
>> PAGE_SHIFT
,
268 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
269 struct drm_i915_gem_object
*obj
)
271 ppgtt
->clear_range(ppgtt
,
272 obj
->gtt_space
->start
>> PAGE_SHIFT
,
273 obj
->base
.size
>> PAGE_SHIFT
);
276 void i915_gem_init_ppgtt(struct drm_device
*dev
)
278 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
280 struct intel_ring_buffer
*ring
;
281 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
282 gtt_pte_t __iomem
*pd_addr
;
286 if (!dev_priv
->mm
.aliasing_ppgtt
)
290 pd_addr
= (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ ppgtt
->pd_offset
/sizeof(gtt_pte_t
);
291 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
294 pt_addr
= ppgtt
->pt_dma_addr
[i
];
295 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
296 pd_entry
|= GEN6_PDE_VALID
;
298 writel(pd_entry
, pd_addr
+ i
);
302 pd_offset
= ppgtt
->pd_offset
;
303 pd_offset
/= 64; /* in cachelines, */
306 if (INTEL_INFO(dev
)->gen
== 6) {
307 uint32_t ecochk
, gab_ctl
, ecobits
;
309 ecobits
= I915_READ(GAC_ECO_BITS
);
310 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
312 gab_ctl
= I915_READ(GAB_CTL
);
313 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
315 ecochk
= I915_READ(GAM_ECOCHK
);
316 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
317 ECOCHK_PPGTT_CACHE64B
);
318 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
319 } else if (INTEL_INFO(dev
)->gen
>= 7) {
320 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
321 /* GFX_MODE is per-ring on gen7+ */
324 for_each_ring(ring
, dev_priv
, i
) {
325 if (INTEL_INFO(dev
)->gen
>= 7)
326 I915_WRITE(RING_MODE_GEN7(ring
),
327 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
329 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
330 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
334 extern int intel_iommu_gfx_mapped
;
335 /* Certain Gen5 chipsets require require idling the GPU before
336 * unmapping anything from the GTT when VT-d is enabled.
338 static inline bool needs_idle_maps(struct drm_device
*dev
)
340 #ifdef CONFIG_INTEL_IOMMU
341 /* Query intel_iommu to see if we need the workaround. Presumably that
344 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
350 static bool do_idling(struct drm_i915_private
*dev_priv
)
352 bool ret
= dev_priv
->mm
.interruptible
;
354 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
355 dev_priv
->mm
.interruptible
= false;
356 if (i915_gpu_idle(dev_priv
->dev
)) {
357 DRM_ERROR("Couldn't idle GPU\n");
358 /* Wait a bit, in hopes it avoids the hang */
366 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
368 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
369 dev_priv
->mm
.interruptible
= interruptible
;
372 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
375 struct drm_i915_gem_object
*obj
;
377 /* First fill our portion of the GTT with scratch pages */
378 dev_priv
->gtt
.gtt_clear_range(dev
, dev_priv
->gtt
.start
/ PAGE_SIZE
,
379 dev_priv
->gtt
.total
/ PAGE_SIZE
);
381 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
382 i915_gem_clflush_object(obj
);
383 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
386 i915_gem_chipset_flush(dev
);
389 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
391 if (obj
->has_dma_mapping
)
394 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
395 obj
->pages
->sgl
, obj
->pages
->nents
,
396 PCI_DMA_BIDIRECTIONAL
))
403 * Binds an object into the global gtt with the specified cache level. The object
404 * will be accessible to the GPU via commands whose operands reference offsets
405 * within the global GTT as well as accessible by the GPU through the GMADR
406 * mapped BAR (dev_priv->mm.gtt->gtt).
408 static void gen6_ggtt_insert_entries(struct drm_device
*dev
,
410 unsigned int first_entry
,
411 enum i915_cache_level level
)
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
414 struct scatterlist
*sg
= st
->sgl
;
415 gtt_pte_t __iomem
*gtt_entries
=
416 (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
418 unsigned int len
, m
= 0;
421 for_each_sg(st
->sgl
, sg
, st
->nents
, unused
) {
422 len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
423 for (m
= 0; m
< len
; m
++) {
424 addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
425 iowrite32(gen6_pte_encode(dev
, addr
, level
),
431 /* XXX: This serves as a posting read to make sure that the PTE has
432 * actually been updated. There is some concern that even though
433 * registers and PTEs are within the same BAR that they are potentially
434 * of NUMA access patterns. Therefore, even with the way we assume
435 * hardware should work, we must keep this posting read for paranoia.
438 WARN_ON(readl(>t_entries
[i
-1])
439 != gen6_pte_encode(dev
, addr
, level
));
441 /* This next bit makes the above posting read even more important. We
442 * want to flush the TLBs only after we're certain all the PTE updates
445 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
446 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
449 static void gen6_ggtt_clear_range(struct drm_device
*dev
,
450 unsigned int first_entry
,
451 unsigned int num_entries
)
453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
454 gtt_pte_t scratch_pte
;
455 gtt_pte_t __iomem
*gtt_base
= (gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
456 const int max_entries
= dev_priv
->mm
.gtt
->gtt_total_entries
- first_entry
;
459 if (WARN(num_entries
> max_entries
,
460 "First entry = %d; Num entries = %d (max=%d)\n",
461 first_entry
, num_entries
, max_entries
))
462 num_entries
= max_entries
;
464 scratch_pte
= gen6_pte_encode(dev
, dev_priv
->gtt
.scratch_page_dma
,
466 for (i
= 0; i
< num_entries
; i
++)
467 iowrite32(scratch_pte
, >t_base
[i
]);
472 static void i915_ggtt_insert_entries(struct drm_device
*dev
,
474 unsigned int pg_start
,
475 enum i915_cache_level cache_level
)
477 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
478 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
480 intel_gtt_insert_sg_entries(st
, pg_start
, flags
);
484 static void i915_ggtt_clear_range(struct drm_device
*dev
,
485 unsigned int first_entry
,
486 unsigned int num_entries
)
488 intel_gtt_clear_range(first_entry
, num_entries
);
492 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
493 enum i915_cache_level cache_level
)
495 struct drm_device
*dev
= obj
->base
.dev
;
496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
498 dev_priv
->gtt
.gtt_insert_entries(dev
, obj
->pages
,
499 obj
->gtt_space
->start
>> PAGE_SHIFT
,
502 obj
->has_global_gtt_mapping
= 1;
505 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
)
507 struct drm_device
*dev
= obj
->base
.dev
;
508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
510 dev_priv
->gtt
.gtt_clear_range(obj
->base
.dev
,
511 obj
->gtt_space
->start
>> PAGE_SHIFT
,
512 obj
->base
.size
>> PAGE_SHIFT
);
514 obj
->has_global_gtt_mapping
= 0;
517 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
519 struct drm_device
*dev
= obj
->base
.dev
;
520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
523 interruptible
= do_idling(dev_priv
);
525 if (!obj
->has_dma_mapping
)
526 dma_unmap_sg(&dev
->pdev
->dev
,
527 obj
->pages
->sgl
, obj
->pages
->nents
,
528 PCI_DMA_BIDIRECTIONAL
);
530 undo_idling(dev_priv
, interruptible
);
533 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
535 unsigned long *start
,
538 if (node
->color
!= color
)
541 if (!list_empty(&node
->node_list
)) {
542 node
= list_entry(node
->node_list
.next
,
545 if (node
->allocated
&& node
->color
!= color
)
550 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
552 unsigned long mappable_end
,
555 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
556 struct drm_mm_node
*entry
;
557 struct drm_i915_gem_object
*obj
;
558 unsigned long hole_start
, hole_end
;
560 BUG_ON(mappable_end
> end
);
562 /* Subtract the guard page ... */
563 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
- PAGE_SIZE
);
565 dev_priv
->mm
.gtt_space
.color_adjust
= i915_gtt_color_adjust
;
567 /* Mark any preallocated objects as occupied */
568 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
569 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
570 obj
->gtt_offset
, obj
->base
.size
);
572 BUG_ON(obj
->gtt_space
!= I915_GTT_RESERVED
);
573 obj
->gtt_space
= drm_mm_create_block(&dev_priv
->mm
.gtt_space
,
577 obj
->has_global_gtt_mapping
= 1;
580 dev_priv
->gtt
.start
= start
;
581 dev_priv
->gtt
.total
= end
- start
;
583 /* Clear any non-preallocated blocks */
584 drm_mm_for_each_hole(entry
, &dev_priv
->mm
.gtt_space
,
585 hole_start
, hole_end
) {
586 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
587 hole_start
, hole_end
);
588 dev_priv
->gtt
.gtt_clear_range(dev
, hole_start
/ PAGE_SIZE
,
589 (hole_end
-hole_start
) / PAGE_SIZE
);
592 /* And finally clear the reserved guard page */
593 dev_priv
->gtt
.gtt_clear_range(dev
, end
/ PAGE_SIZE
- 1, 1);
597 intel_enable_ppgtt(struct drm_device
*dev
)
599 if (i915_enable_ppgtt
>= 0)
600 return i915_enable_ppgtt
;
602 #ifdef CONFIG_INTEL_IOMMU
603 /* Disable ppgtt on SNB if VT-d is on. */
604 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
611 void i915_gem_init_global_gtt(struct drm_device
*dev
)
613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 unsigned long gtt_size
, mappable_size
;
617 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
618 mappable_size
= dev_priv
->gtt
.mappable_end
;
620 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
621 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
622 * aperture accordingly when using aliasing ppgtt. */
623 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
625 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
627 ret
= i915_gem_init_aliasing_ppgtt(dev
);
629 mutex_unlock(&dev
->struct_mutex
);
633 /* Let GEM Manage all of the aperture.
635 * However, leave one page at the end still bound to the scratch
636 * page. There are a number of places where the hardware
637 * apparently prefetches past the end of the object, and we've
638 * seen multiple hangs with the GPU head pointer stuck in a
639 * batchbuffer bound at the last page of the aperture. One page
640 * should be enough to keep any prefetching inside of the
643 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
647 static int setup_scratch_page(struct drm_device
*dev
)
649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
653 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
657 set_pages_uc(page
, 1);
659 #ifdef CONFIG_INTEL_IOMMU
660 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
661 PCI_DMA_BIDIRECTIONAL
);
662 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
665 dma_addr
= page_to_phys(page
);
667 dev_priv
->gtt
.scratch_page
= page
;
668 dev_priv
->gtt
.scratch_page_dma
= dma_addr
;
673 static void teardown_scratch_page(struct drm_device
*dev
)
675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
676 set_pages_wb(dev_priv
->gtt
.scratch_page
, 1);
677 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.scratch_page_dma
,
678 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
679 put_page(dev_priv
->gtt
.scratch_page
);
680 __free_page(dev_priv
->gtt
.scratch_page
);
683 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
685 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
686 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
687 return snb_gmch_ctl
<< 20;
690 static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl
)
692 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
693 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
694 return snb_gmch_ctl
<< 25; /* 32 MB units */
697 static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl
)
699 static const int stolen_decoder
[] = {
700 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
701 snb_gmch_ctl
>>= IVB_GMCH_GMS_SHIFT
;
702 snb_gmch_ctl
&= IVB_GMCH_GMS_MASK
;
703 return stolen_decoder
[snb_gmch_ctl
] << 20;
706 int i915_gem_gtt_init(struct drm_device
*dev
)
708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
709 phys_addr_t gtt_bus_addr
;
713 dev_priv
->gtt
.mappable_base
= pci_resource_start(dev
->pdev
, 2);
714 dev_priv
->gtt
.mappable_end
= pci_resource_len(dev
->pdev
, 2);
716 /* On modern platforms we need not worry ourself with the legacy
717 * hostbridge query stuff. Skip it entirely
719 if (INTEL_INFO(dev
)->gen
< 6) {
720 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev
->pdev
, NULL
);
722 DRM_ERROR("failed to set up gmch\n");
726 dev_priv
->mm
.gtt
= intel_gtt_get();
727 if (!dev_priv
->mm
.gtt
) {
728 DRM_ERROR("Failed to initialize GTT\n");
733 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev
);
735 dev_priv
->gtt
.gtt_clear_range
= i915_ggtt_clear_range
;
736 dev_priv
->gtt
.gtt_insert_entries
= i915_ggtt_insert_entries
;
741 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
742 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
744 dev_priv
->mm
.gtt
= kzalloc(sizeof(*dev_priv
->mm
.gtt
), GFP_KERNEL
);
745 if (!dev_priv
->mm
.gtt
)
748 /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
749 gtt_bus_addr
= pci_resource_start(dev
->pdev
, 0) + (2<<20);
752 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
753 dev_priv
->mm
.gtt
->gtt_total_entries
=
754 gen6_get_total_gtt_size(snb_gmch_ctl
) / sizeof(gtt_pte_t
);
755 if (INTEL_INFO(dev
)->gen
< 7)
756 dev_priv
->mm
.gtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
758 dev_priv
->mm
.gtt
->stolen_size
= gen7_get_stolen_size(snb_gmch_ctl
);
760 /* 64/512MB is the current min/max we actually know of, but this is just a
761 * coarse sanity check.
763 if ((dev_priv
->gtt
.mappable_end
< (64<<20) ||
764 (dev_priv
->gtt
.mappable_end
> (512<<20)))) {
765 DRM_ERROR("Unknown GMADR size (%lx)\n",
766 dev_priv
->gtt
.mappable_end
);
771 ret
= setup_scratch_page(dev
);
773 DRM_ERROR("Scratch setup failed\n");
777 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_bus_addr
,
778 dev_priv
->mm
.gtt
->gtt_total_entries
* sizeof(gtt_pte_t
));
779 if (!dev_priv
->gtt
.gsm
) {
780 DRM_ERROR("Failed to map the gtt page table\n");
781 teardown_scratch_page(dev
);
786 /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
787 DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv
->mm
.gtt
->gtt_total_entries
>> 8);
788 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv
->gtt
.mappable_end
>> 20);
789 DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv
->mm
.gtt
->stolen_size
>> 20);
791 dev_priv
->gtt
.gtt_clear_range
= gen6_ggtt_clear_range
;
792 dev_priv
->gtt
.gtt_insert_entries
= gen6_ggtt_insert_entries
;
797 kfree(dev_priv
->mm
.gtt
);
798 if (INTEL_INFO(dev
)->gen
< 6)
803 void i915_gem_gtt_fini(struct drm_device
*dev
)
805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
806 iounmap(dev_priv
->gtt
.gsm
);
807 teardown_scratch_page(dev
);
808 if (INTEL_INFO(dev
)->gen
< 6)
810 kfree(dev_priv
->mm
.gtt
);