2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 typedef uint32_t gtt_pte_t
;
34 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
36 #define GEN6_PDE_VALID (1 << 0)
37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
38 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
40 #define GEN6_PTE_VALID (1 << 0)
41 #define GEN6_PTE_UNCACHED (1 << 1)
42 #define HSW_PTE_UNCACHED (0)
43 #define GEN6_PTE_CACHE_LLC (2 << 1)
44 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
45 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
47 static inline gtt_pte_t
gen6_pte_encode(struct drm_device
*dev
,
49 enum i915_cache_level level
)
51 gtt_pte_t pte
= GEN6_PTE_VALID
;
52 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
55 case I915_CACHE_LLC_MLC
:
56 /* Haswell doesn't set L3 this way */
58 pte
|= GEN6_PTE_CACHE_LLC
;
60 pte
|= GEN6_PTE_CACHE_LLC_MLC
;
63 pte
|= GEN6_PTE_CACHE_LLC
;
67 pte
|= HSW_PTE_UNCACHED
;
69 pte
|= GEN6_PTE_UNCACHED
;
79 /* PPGTT support for Sandybdrige/Gen6 and later */
80 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt
*ppgtt
,
85 gtt_pte_t scratch_pte
;
86 unsigned act_pd
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
87 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
90 scratch_pte
= gen6_pte_encode(ppgtt
->dev
,
91 ppgtt
->scratch_page_dma_addr
,
95 last_pte
= first_pte
+ num_entries
;
96 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
97 last_pte
= I915_PPGTT_PT_ENTRIES
;
99 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pd
]);
101 for (i
= first_pte
; i
< last_pte
; i
++)
102 pt_vaddr
[i
] = scratch_pte
;
104 kunmap_atomic(pt_vaddr
);
106 num_entries
-= last_pte
- first_pte
;
112 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt
*ppgtt
,
113 struct sg_table
*pages
,
114 unsigned first_entry
,
115 enum i915_cache_level cache_level
)
118 unsigned act_pd
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
119 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
120 unsigned i
, j
, m
, segment_len
;
121 dma_addr_t page_addr
;
122 struct scatterlist
*sg
;
124 /* init sg walking */
127 segment_len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
130 while (i
< pages
->nents
) {
131 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pd
]);
133 for (j
= first_pte
; j
< I915_PPGTT_PT_ENTRIES
; j
++) {
134 page_addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
135 pt_vaddr
[j
] = gen6_pte_encode(ppgtt
->dev
, page_addr
,
138 /* grab the next page */
139 if (++m
== segment_len
) {
140 if (++i
== pages
->nents
)
144 segment_len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
149 kunmap_atomic(pt_vaddr
);
156 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt
*ppgtt
)
160 if (ppgtt
->pt_dma_addr
) {
161 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
162 pci_unmap_page(ppgtt
->dev
->pdev
,
163 ppgtt
->pt_dma_addr
[i
],
164 4096, PCI_DMA_BIDIRECTIONAL
);
167 kfree(ppgtt
->pt_dma_addr
);
168 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
169 __free_page(ppgtt
->pt_pages
[i
]);
170 kfree(ppgtt
->pt_pages
);
174 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
176 struct drm_device
*dev
= ppgtt
->dev
;
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 unsigned first_pd_entry_in_global_pt
;
182 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
183 * entries. For aliasing ppgtt support we just steal them at the end for
185 first_pd_entry_in_global_pt
=
186 gtt_total_entries(dev_priv
->gtt
) - I915_PPGTT_PD_ENTRIES
;
188 ppgtt
->num_pd_entries
= I915_PPGTT_PD_ENTRIES
;
189 ppgtt
->clear_range
= gen6_ppgtt_clear_range
;
190 ppgtt
->insert_entries
= gen6_ppgtt_insert_entries
;
191 ppgtt
->cleanup
= gen6_ppgtt_cleanup
;
192 ppgtt
->pt_pages
= kzalloc(sizeof(struct page
*)*ppgtt
->num_pd_entries
,
194 if (!ppgtt
->pt_pages
)
197 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
198 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
199 if (!ppgtt
->pt_pages
[i
])
203 ppgtt
->pt_dma_addr
= kzalloc(sizeof(dma_addr_t
) *ppgtt
->num_pd_entries
,
205 if (!ppgtt
->pt_dma_addr
)
208 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
211 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
212 PCI_DMA_BIDIRECTIONAL
);
214 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
219 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
222 ppgtt
->scratch_page_dma_addr
= dev_priv
->gtt
.scratch_page_dma
;
224 ppgtt
->clear_range(ppgtt
, 0,
225 ppgtt
->num_pd_entries
*I915_PPGTT_PT_ENTRIES
);
227 ppgtt
->pd_offset
= (first_pd_entry_in_global_pt
)*sizeof(gtt_pte_t
);
232 if (ppgtt
->pt_dma_addr
) {
233 for (i
--; i
>= 0; i
--)
234 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
235 4096, PCI_DMA_BIDIRECTIONAL
);
238 kfree(ppgtt
->pt_dma_addr
);
239 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
240 if (ppgtt
->pt_pages
[i
])
241 __free_page(ppgtt
->pt_pages
[i
]);
243 kfree(ppgtt
->pt_pages
);
248 static int i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
251 struct i915_hw_ppgtt
*ppgtt
;
254 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
260 ret
= gen6_ppgtt_init(ppgtt
);
264 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
269 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
)
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
272 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
277 ppgtt
->cleanup(ppgtt
);
280 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
281 struct drm_i915_gem_object
*obj
,
282 enum i915_cache_level cache_level
)
284 ppgtt
->insert_entries(ppgtt
, obj
->pages
,
285 obj
->gtt_space
->start
>> PAGE_SHIFT
,
289 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
290 struct drm_i915_gem_object
*obj
)
292 ppgtt
->clear_range(ppgtt
,
293 obj
->gtt_space
->start
>> PAGE_SHIFT
,
294 obj
->base
.size
>> PAGE_SHIFT
);
297 void i915_gem_init_ppgtt(struct drm_device
*dev
)
299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
301 struct intel_ring_buffer
*ring
;
302 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
303 gtt_pte_t __iomem
*pd_addr
;
307 if (!dev_priv
->mm
.aliasing_ppgtt
)
311 pd_addr
= (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ ppgtt
->pd_offset
/sizeof(gtt_pte_t
);
312 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
315 pt_addr
= ppgtt
->pt_dma_addr
[i
];
316 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
317 pd_entry
|= GEN6_PDE_VALID
;
319 writel(pd_entry
, pd_addr
+ i
);
323 pd_offset
= ppgtt
->pd_offset
;
324 pd_offset
/= 64; /* in cachelines, */
327 if (INTEL_INFO(dev
)->gen
== 6) {
328 uint32_t ecochk
, gab_ctl
, ecobits
;
330 ecobits
= I915_READ(GAC_ECO_BITS
);
331 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
333 gab_ctl
= I915_READ(GAB_CTL
);
334 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
336 ecochk
= I915_READ(GAM_ECOCHK
);
337 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
338 ECOCHK_PPGTT_CACHE64B
);
339 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
340 } else if (INTEL_INFO(dev
)->gen
>= 7) {
341 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
342 /* GFX_MODE is per-ring on gen7+ */
345 for_each_ring(ring
, dev_priv
, i
) {
346 if (INTEL_INFO(dev
)->gen
>= 7)
347 I915_WRITE(RING_MODE_GEN7(ring
),
348 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
350 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
351 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
355 extern int intel_iommu_gfx_mapped
;
356 /* Certain Gen5 chipsets require require idling the GPU before
357 * unmapping anything from the GTT when VT-d is enabled.
359 static inline bool needs_idle_maps(struct drm_device
*dev
)
361 #ifdef CONFIG_INTEL_IOMMU
362 /* Query intel_iommu to see if we need the workaround. Presumably that
365 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
371 static bool do_idling(struct drm_i915_private
*dev_priv
)
373 bool ret
= dev_priv
->mm
.interruptible
;
375 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
376 dev_priv
->mm
.interruptible
= false;
377 if (i915_gpu_idle(dev_priv
->dev
)) {
378 DRM_ERROR("Couldn't idle GPU\n");
379 /* Wait a bit, in hopes it avoids the hang */
387 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
389 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
390 dev_priv
->mm
.interruptible
= interruptible
;
393 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
396 struct drm_i915_gem_object
*obj
;
398 /* First fill our portion of the GTT with scratch pages */
399 dev_priv
->gtt
.gtt_clear_range(dev
, dev_priv
->gtt
.start
/ PAGE_SIZE
,
400 dev_priv
->gtt
.total
/ PAGE_SIZE
);
402 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
403 i915_gem_clflush_object(obj
);
404 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
407 i915_gem_chipset_flush(dev
);
410 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
412 if (obj
->has_dma_mapping
)
415 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
416 obj
->pages
->sgl
, obj
->pages
->nents
,
417 PCI_DMA_BIDIRECTIONAL
))
424 * Binds an object into the global gtt with the specified cache level. The object
425 * will be accessible to the GPU via commands whose operands reference offsets
426 * within the global GTT as well as accessible by the GPU through the GMADR
427 * mapped BAR (dev_priv->mm.gtt->gtt).
429 static void gen6_ggtt_insert_entries(struct drm_device
*dev
,
431 unsigned int first_entry
,
432 enum i915_cache_level level
)
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
435 struct scatterlist
*sg
= st
->sgl
;
436 gtt_pte_t __iomem
*gtt_entries
=
437 (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
439 unsigned int len
, m
= 0;
442 for_each_sg(st
->sgl
, sg
, st
->nents
, unused
) {
443 len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
444 for (m
= 0; m
< len
; m
++) {
445 addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
446 iowrite32(gen6_pte_encode(dev
, addr
, level
),
452 /* XXX: This serves as a posting read to make sure that the PTE has
453 * actually been updated. There is some concern that even though
454 * registers and PTEs are within the same BAR that they are potentially
455 * of NUMA access patterns. Therefore, even with the way we assume
456 * hardware should work, we must keep this posting read for paranoia.
459 WARN_ON(readl(>t_entries
[i
-1])
460 != gen6_pte_encode(dev
, addr
, level
));
462 /* This next bit makes the above posting read even more important. We
463 * want to flush the TLBs only after we're certain all the PTE updates
466 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
467 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
470 static void gen6_ggtt_clear_range(struct drm_device
*dev
,
471 unsigned int first_entry
,
472 unsigned int num_entries
)
474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 gtt_pte_t scratch_pte
;
476 gtt_pte_t __iomem
*gtt_base
= (gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
477 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
480 if (WARN(num_entries
> max_entries
,
481 "First entry = %d; Num entries = %d (max=%d)\n",
482 first_entry
, num_entries
, max_entries
))
483 num_entries
= max_entries
;
485 scratch_pte
= gen6_pte_encode(dev
, dev_priv
->gtt
.scratch_page_dma
,
487 for (i
= 0; i
< num_entries
; i
++)
488 iowrite32(scratch_pte
, >t_base
[i
]);
493 static void i915_ggtt_insert_entries(struct drm_device
*dev
,
495 unsigned int pg_start
,
496 enum i915_cache_level cache_level
)
498 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
499 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
501 intel_gtt_insert_sg_entries(st
, pg_start
, flags
);
505 static void i915_ggtt_clear_range(struct drm_device
*dev
,
506 unsigned int first_entry
,
507 unsigned int num_entries
)
509 intel_gtt_clear_range(first_entry
, num_entries
);
513 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
514 enum i915_cache_level cache_level
)
516 struct drm_device
*dev
= obj
->base
.dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
519 dev_priv
->gtt
.gtt_insert_entries(dev
, obj
->pages
,
520 obj
->gtt_space
->start
>> PAGE_SHIFT
,
523 obj
->has_global_gtt_mapping
= 1;
526 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
)
528 struct drm_device
*dev
= obj
->base
.dev
;
529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
531 dev_priv
->gtt
.gtt_clear_range(obj
->base
.dev
,
532 obj
->gtt_space
->start
>> PAGE_SHIFT
,
533 obj
->base
.size
>> PAGE_SHIFT
);
535 obj
->has_global_gtt_mapping
= 0;
538 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
540 struct drm_device
*dev
= obj
->base
.dev
;
541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
544 interruptible
= do_idling(dev_priv
);
546 if (!obj
->has_dma_mapping
)
547 dma_unmap_sg(&dev
->pdev
->dev
,
548 obj
->pages
->sgl
, obj
->pages
->nents
,
549 PCI_DMA_BIDIRECTIONAL
);
551 undo_idling(dev_priv
, interruptible
);
554 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
556 unsigned long *start
,
559 if (node
->color
!= color
)
562 if (!list_empty(&node
->node_list
)) {
563 node
= list_entry(node
->node_list
.next
,
566 if (node
->allocated
&& node
->color
!= color
)
571 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
573 unsigned long mappable_end
,
576 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
577 struct drm_mm_node
*entry
;
578 struct drm_i915_gem_object
*obj
;
579 unsigned long hole_start
, hole_end
;
581 BUG_ON(mappable_end
> end
);
583 /* Subtract the guard page ... */
584 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
- PAGE_SIZE
);
586 dev_priv
->mm
.gtt_space
.color_adjust
= i915_gtt_color_adjust
;
588 /* Mark any preallocated objects as occupied */
589 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
590 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
591 obj
->gtt_offset
, obj
->base
.size
);
593 BUG_ON(obj
->gtt_space
!= I915_GTT_RESERVED
);
594 obj
->gtt_space
= drm_mm_create_block(&dev_priv
->mm
.gtt_space
,
598 obj
->has_global_gtt_mapping
= 1;
601 dev_priv
->gtt
.start
= start
;
602 dev_priv
->gtt
.total
= end
- start
;
604 /* Clear any non-preallocated blocks */
605 drm_mm_for_each_hole(entry
, &dev_priv
->mm
.gtt_space
,
606 hole_start
, hole_end
) {
607 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
608 hole_start
, hole_end
);
609 dev_priv
->gtt
.gtt_clear_range(dev
, hole_start
/ PAGE_SIZE
,
610 (hole_end
-hole_start
) / PAGE_SIZE
);
613 /* And finally clear the reserved guard page */
614 dev_priv
->gtt
.gtt_clear_range(dev
, end
/ PAGE_SIZE
- 1, 1);
618 intel_enable_ppgtt(struct drm_device
*dev
)
620 if (i915_enable_ppgtt
>= 0)
621 return i915_enable_ppgtt
;
623 #ifdef CONFIG_INTEL_IOMMU
624 /* Disable ppgtt on SNB if VT-d is on. */
625 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
632 void i915_gem_init_global_gtt(struct drm_device
*dev
)
634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 unsigned long gtt_size
, mappable_size
;
638 gtt_size
= dev_priv
->gtt
.total
;
639 mappable_size
= dev_priv
->gtt
.mappable_end
;
641 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
642 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
643 * aperture accordingly when using aliasing ppgtt. */
644 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
646 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
648 ret
= i915_gem_init_aliasing_ppgtt(dev
);
650 mutex_unlock(&dev
->struct_mutex
);
654 /* Let GEM Manage all of the aperture.
656 * However, leave one page at the end still bound to the scratch
657 * page. There are a number of places where the hardware
658 * apparently prefetches past the end of the object, and we've
659 * seen multiple hangs with the GPU head pointer stuck in a
660 * batchbuffer bound at the last page of the aperture. One page
661 * should be enough to keep any prefetching inside of the
664 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
668 static int setup_scratch_page(struct drm_device
*dev
)
670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
674 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
678 set_pages_uc(page
, 1);
680 #ifdef CONFIG_INTEL_IOMMU
681 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
682 PCI_DMA_BIDIRECTIONAL
);
683 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
686 dma_addr
= page_to_phys(page
);
688 dev_priv
->gtt
.scratch_page
= page
;
689 dev_priv
->gtt
.scratch_page_dma
= dma_addr
;
694 static void teardown_scratch_page(struct drm_device
*dev
)
696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
697 set_pages_wb(dev_priv
->gtt
.scratch_page
, 1);
698 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.scratch_page_dma
,
699 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
700 put_page(dev_priv
->gtt
.scratch_page
);
701 __free_page(dev_priv
->gtt
.scratch_page
);
704 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
706 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
707 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
708 return snb_gmch_ctl
<< 20;
711 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
713 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
714 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
715 return snb_gmch_ctl
<< 25; /* 32 MB units */
718 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl
)
720 static const int stolen_decoder
[] = {
721 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
722 snb_gmch_ctl
>>= IVB_GMCH_GMS_SHIFT
;
723 snb_gmch_ctl
&= IVB_GMCH_GMS_MASK
;
724 return stolen_decoder
[snb_gmch_ctl
] << 20;
727 static int gen6_gmch_probe(struct drm_device
*dev
,
731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
732 phys_addr_t gtt_bus_addr
;
733 unsigned int gtt_size
;
737 /* 64/512MB is the current min/max we actually know of, but this is just
738 * a coarse sanity check.
740 if ((dev_priv
->gtt
.mappable_end
< (64<<20) ||
741 (dev_priv
->gtt
.mappable_end
> (512<<20)))) {
742 DRM_ERROR("Unknown GMADR size (%lx)\n",
743 dev_priv
->gtt
.mappable_end
);
747 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
748 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
749 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
750 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
753 *stolen
= gen7_get_stolen_size(snb_gmch_ctl
);
755 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
757 *gtt_total
= (gtt_size
/ sizeof(gtt_pte_t
)) << PAGE_SHIFT
;
759 /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
760 gtt_bus_addr
= pci_resource_start(dev
->pdev
, 0) + (2<<20);
761 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_bus_addr
, gtt_size
);
762 if (!dev_priv
->gtt
.gsm
) {
763 DRM_ERROR("Failed to map the gtt page table\n");
767 ret
= setup_scratch_page(dev
);
769 DRM_ERROR("Scratch setup failed\n");
771 dev_priv
->gtt
.gtt_clear_range
= gen6_ggtt_clear_range
;
772 dev_priv
->gtt
.gtt_insert_entries
= gen6_ggtt_insert_entries
;
777 void gen6_gmch_remove(struct drm_device
*dev
)
779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
780 iounmap(dev_priv
->gtt
.gsm
);
781 teardown_scratch_page(dev_priv
->dev
);
784 static int i915_gmch_probe(struct drm_device
*dev
,
788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
793 DRM_ERROR("failed to set up gmch\n");
797 intel_gtt_get(gtt_total
, stolen
);
799 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
800 dev_priv
->gtt
.gtt_clear_range
= i915_ggtt_clear_range
;
801 dev_priv
->gtt
.gtt_insert_entries
= i915_ggtt_insert_entries
;
806 static void i915_gmch_remove(struct drm_device
*dev
)
811 int i915_gem_gtt_init(struct drm_device
*dev
)
813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
815 unsigned long gtt_size
;
818 gtt
->mappable_base
= pci_resource_start(dev
->pdev
, 2);
819 gtt
->mappable_end
= pci_resource_len(dev
->pdev
, 2);
821 if (INTEL_INFO(dev
)->gen
<= 5) {
822 dev_priv
->gtt
.gtt_probe
= i915_gmch_probe
;
823 dev_priv
->gtt
.gtt_remove
= i915_gmch_remove
;
825 dev_priv
->gtt
.gtt_probe
= gen6_gmch_probe
;
826 dev_priv
->gtt
.gtt_remove
= gen6_gmch_remove
;
829 ret
= dev_priv
->gtt
.gtt_probe(dev
, &dev_priv
->gtt
.total
,
830 &dev_priv
->gtt
.stolen_size
);
834 gtt_size
= (dev_priv
->gtt
.total
>> PAGE_SHIFT
) * sizeof(gtt_pte_t
);
836 /* GMADR is the PCI mmio aperture into the global GTT. */
837 DRM_INFO("Memory usable by graphics device = %zdM\n",
838 dev_priv
->gtt
.total
>> 20);
839 DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
840 dev_priv
->gtt
.mappable_end
>> 20);
841 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
842 dev_priv
->gtt
.stolen_size
>> 20);