drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 typedef uint32_t gtt_pte_t;
  32
  33 /* PPGTT stuff */
  34 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  35
  36 #define GEN6_PDE_VALID                  (1 << 0)
  37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  38 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  39
  40 #define GEN6_PTE_VALID                  (1 << 0)
  41 #define GEN6_PTE_UNCACHED               (1 << 1)
  42 #define HSW_PTE_UNCACHED                (0)
  43 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  44 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  45 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  46
  47 static inline gtt_pte_t pte_encode(struct drm_device *dev,
  48                                    dma_addr_t addr,
  49                                    enum i915_cache_level level)
  50 {
  51         gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 /* Haswell doesn't set L3 this way */
  57                 if (IS_HASWELL(dev))
  58                         pte |= GEN6_PTE_CACHE_LLC;
  59                 else
  60                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  61                 break;
  62         case I915_CACHE_LLC:
  63                 pte |= GEN6_PTE_CACHE_LLC;
  64                 break;
  65         case I915_CACHE_NONE:
  66                 if (IS_HASWELL(dev))
  67                         pte |= HSW_PTE_UNCACHED;
  68                 else
  69                         pte |= GEN6_PTE_UNCACHED;
  70                 break;
  71         default:
  72                 BUG();
  73         }
  74
  75
  76         return pte;
  77 }
  78
  79 /* PPGTT support for Sandybdrige/Gen6 and later */
  80 static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
  81                                    unsigned first_entry,
  82                                    unsigned num_entries)
  83 {
  84         gtt_pte_t *pt_vaddr;
  85         gtt_pte_t scratch_pte;
  86         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
  87         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
  88         unsigned last_pte, i;
  89
  90         scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr,
  91                                  I915_CACHE_LLC);
  92
  93         while (num_entries) {
  94                 last_pte = first_pte + num_entries;
  95                 if (last_pte > I915_PPGTT_PT_ENTRIES)
  96                         last_pte = I915_PPGTT_PT_ENTRIES;
  97
  98                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
  99
 100                 for (i = first_pte; i < last_pte; i++)
 101                         pt_vaddr[i] = scratch_pte;
 102
 103                 kunmap_atomic(pt_vaddr);
 104
 105                 num_entries -= last_pte - first_pte;
 106                 first_pte = 0;
 107                 act_pd++;
 108         }
 109 }
 110
 111 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 112 {
 113         struct drm_i915_private *dev_priv = dev->dev_private;
 114         struct i915_hw_ppgtt *ppgtt;
 115         unsigned first_pd_entry_in_global_pt;
 116         int i;
 117         int ret = -ENOMEM;
 118
 119         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 120          * entries. For aliasing ppgtt support we just steal them at the end for
 121          * now. */
 122         first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
 123
 124         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 125         if (!ppgtt)
 126                 return ret;
 127
 128         ppgtt->dev = dev;
 129         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 130         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 131                                   GFP_KERNEL);
 132         if (!ppgtt->pt_pages)
 133                 goto err_ppgtt;
 134
 135         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 136                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 137                 if (!ppgtt->pt_pages[i])
 138                         goto err_pt_alloc;
 139         }
 140
 141         if (dev_priv->mm.gtt->needs_dmar) {
 142                 ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
 143                                                 *ppgtt->num_pd_entries,
 144                                              GFP_KERNEL);
 145                 if (!ppgtt->pt_dma_addr)
 146                         goto err_pt_alloc;
 147
 148                 for (i = 0; i < ppgtt->num_pd_entries; i++) {
 149                         dma_addr_t pt_addr;
 150
 151                         pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
 152                                                0, 4096,
 153                                                PCI_DMA_BIDIRECTIONAL);
 154
 155                         if (pci_dma_mapping_error(dev->pdev,
 156                                                   pt_addr)) {
 157                                 ret = -EIO;
 158                                 goto err_pd_pin;
 159
 160                         }
 161                         ppgtt->pt_dma_addr[i] = pt_addr;
 162                 }
 163         }
 164
 165         ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
 166
 167         i915_ppgtt_clear_range(ppgtt, 0,
 168                                ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 169
 170         ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
 171
 172         dev_priv->mm.aliasing_ppgtt = ppgtt;
 173
 174         return 0;
 175
 176 err_pd_pin:
 177         if (ppgtt->pt_dma_addr) {
 178                 for (i--; i >= 0; i--)
 179                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 180                                        4096, PCI_DMA_BIDIRECTIONAL);
 181         }
 182 err_pt_alloc:
 183         kfree(ppgtt->pt_dma_addr);
 184         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 185                 if (ppgtt->pt_pages[i])
 186                         __free_page(ppgtt->pt_pages[i]);
 187         }
 188         kfree(ppgtt->pt_pages);
 189 err_ppgtt:
 190         kfree(ppgtt);
 191
 192         return ret;
 193 }
 194
 195 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 199         int i;
 200
 201         if (!ppgtt)
 202                 return;
 203
 204         if (ppgtt->pt_dma_addr) {
 205                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 206                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 207                                        4096, PCI_DMA_BIDIRECTIONAL);
 208         }
 209
 210         kfree(ppgtt->pt_dma_addr);
 211         for (i = 0; i < ppgtt->num_pd_entries; i++)
 212                 __free_page(ppgtt->pt_pages[i]);
 213         kfree(ppgtt->pt_pages);
 214         kfree(ppgtt);
 215 }
 216
 217 static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
 218                                          const struct sg_table *pages,
 219                                          unsigned first_entry,
 220                                          enum i915_cache_level cache_level)
 221 {
 222         gtt_pte_t *pt_vaddr;
 223         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
 224         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 225         unsigned i, j, m, segment_len;
 226         dma_addr_t page_addr;
 227         struct scatterlist *sg;
 228
 229         /* init sg walking */
 230         sg = pages->sgl;
 231         i = 0;
 232         segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
 233         m = 0;
 234
 235         while (i < pages->nents) {
 236                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
 237
 238                 for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
 239                         page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 240                         pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr,
 241                                                  cache_level);
 242
 243                         /* grab the next page */
 244                         if (++m == segment_len) {
 245                                 if (++i == pages->nents)
 246                                         break;
 247
 248                                 sg = sg_next(sg);
 249                                 segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
 250                                 m = 0;
 251                         }
 252                 }
 253
 254                 kunmap_atomic(pt_vaddr);
 255
 256                 first_pte = 0;
 257                 act_pd++;
 258         }
 259 }
 260
 261 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 262                             struct drm_i915_gem_object *obj,
 263                             enum i915_cache_level cache_level)
 264 {
 265         i915_ppgtt_insert_sg_entries(ppgtt,
 266                                      obj->pages,
 267                                      obj->gtt_space->start >> PAGE_SHIFT,
 268                                      cache_level);
 269 }
 270
 271 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 272                               struct drm_i915_gem_object *obj)
 273 {
 274         i915_ppgtt_clear_range(ppgtt,
 275                                obj->gtt_space->start >> PAGE_SHIFT,
 276                                obj->base.size >> PAGE_SHIFT);
 277 }
 278
 279 void i915_gem_init_ppgtt(struct drm_device *dev)
 280 {
 281         drm_i915_private_t *dev_priv = dev->dev_private;
 282         uint32_t pd_offset;
 283         struct intel_ring_buffer *ring;
 284         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 285         gtt_pte_t __iomem *pd_addr;
 286         uint32_t pd_entry;
 287         int i;
 288
 289         if (!dev_priv->mm.aliasing_ppgtt)
 290                 return;
 291
 292
 293         pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
 294         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 295                 dma_addr_t pt_addr;
 296
 297                 if (dev_priv->mm.gtt->needs_dmar)
 298                         pt_addr = ppgtt->pt_dma_addr[i];
 299                 else
 300                         pt_addr = page_to_phys(ppgtt->pt_pages[i]);
 301
 302                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 303                 pd_entry |= GEN6_PDE_VALID;
 304
 305                 writel(pd_entry, pd_addr + i);
 306         }
 307         readl(pd_addr);
 308
 309         pd_offset = ppgtt->pd_offset;
 310         pd_offset /= 64; /* in cachelines, */
 311         pd_offset <<= 16;
 312
 313         if (INTEL_INFO(dev)->gen == 6) {
 314                 uint32_t ecochk, gab_ctl, ecobits;
 315
 316                 ecobits = I915_READ(GAC_ECO_BITS);
 317                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 318
 319                 gab_ctl = I915_READ(GAB_CTL);
 320                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 321
 322                 ecochk = I915_READ(GAM_ECOCHK);
 323                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 324                                        ECOCHK_PPGTT_CACHE64B);
 325                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 326         } else if (INTEL_INFO(dev)->gen >= 7) {
 327                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 328                 /* GFX_MODE is per-ring on gen7+ */
 329         }
 330
 331         for_each_ring(ring, dev_priv, i) {
 332                 if (INTEL_INFO(dev)->gen >= 7)
 333                         I915_WRITE(RING_MODE_GEN7(ring),
 334                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 335
 336                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 337                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 338         }
 339 }
 340
 341 extern int intel_iommu_gfx_mapped;
 342 /* Certain Gen5 chipsets require require idling the GPU before
 343  * unmapping anything from the GTT when VT-d is enabled.
 344  */
 345 static inline bool needs_idle_maps(struct drm_device *dev)
 346 {
 347 #ifdef CONFIG_INTEL_IOMMU
 348         /* Query intel_iommu to see if we need the workaround. Presumably that
 349          * was loaded first.
 350          */
 351         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 352                 return true;
 353 #endif
 354         return false;
 355 }
 356
 357 static bool do_idling(struct drm_i915_private *dev_priv)
 358 {
 359         bool ret = dev_priv->mm.interruptible;
 360
 361         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 362                 dev_priv->mm.interruptible = false;
 363                 if (i915_gpu_idle(dev_priv->dev)) {
 364                         DRM_ERROR("Couldn't idle GPU\n");
 365                         /* Wait a bit, in hopes it avoids the hang */
 366                         udelay(10);
 367                 }
 368         }
 369
 370         return ret;
 371 }
 372
 373 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 374 {
 375         if (unlikely(dev_priv->gtt.do_idle_maps))
 376                 dev_priv->mm.interruptible = interruptible;
 377 }
 378
 379 static void i915_ggtt_clear_range(struct drm_device *dev,
 380                                  unsigned first_entry,
 381                                  unsigned num_entries)
 382 {
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         gtt_pte_t scratch_pte;
 385         gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 386         const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
 387         int i;
 388
 389         if (INTEL_INFO(dev)->gen < 6) {
 390                 intel_gtt_clear_range(first_entry, num_entries);
 391                 return;
 392         }
 393
 394         if (WARN(num_entries > max_entries,
 395                  "First entry = %d; Num entries = %d (max=%d)\n",
 396                  first_entry, num_entries, max_entries))
 397                 num_entries = max_entries;
 398
 399         scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC);
 400         for (i = 0; i < num_entries; i++)
 401                 iowrite32(scratch_pte, &gtt_base[i]);
 402         readl(gtt_base);
 403 }
 404
 405 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 406 {
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408         struct drm_i915_gem_object *obj;
 409
 410         /* First fill our portion of the GTT with scratch pages */
 411         i915_ggtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 412                               dev_priv->gtt.total / PAGE_SIZE);
 413
 414         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 415                 i915_gem_clflush_object(obj);
 416                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 417         }
 418
 419         i915_gem_chipset_flush(dev);
 420 }
 421
 422 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 423 {
 424         if (obj->has_dma_mapping)
 425                 return 0;
 426
 427         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 428                         obj->pages->sgl, obj->pages->nents,
 429                         PCI_DMA_BIDIRECTIONAL))
 430                 return -ENOSPC;
 431
 432         return 0;
 433 }
 434
 435 /*
 436  * Binds an object into the global gtt with the specified cache level. The object
 437  * will be accessible to the GPU via commands whose operands reference offsets
 438  * within the global GTT as well as accessible by the GPU through the GMADR
 439  * mapped BAR (dev_priv->mm.gtt->gtt).
 440  */
 441 static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,
 442                                   enum i915_cache_level level)
 443 {
 444         struct drm_device *dev = obj->base.dev;
 445         struct drm_i915_private *dev_priv = dev->dev_private;
 446         struct sg_table *st = obj->pages;
 447         struct scatterlist *sg = st->sgl;
 448         const int first_entry = obj->gtt_space->start >> PAGE_SHIFT;
 449         const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
 450         gtt_pte_t __iomem *gtt_entries =
 451                 (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 452         int unused, i = 0;
 453         unsigned int len, m = 0;
 454         dma_addr_t addr;
 455
 456         for_each_sg(st->sgl, sg, st->nents, unused) {
 457                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 458                 for (m = 0; m < len; m++) {
 459                         addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 460                         iowrite32(pte_encode(dev, addr, level), &gtt_entries[i]);
 461                         i++;
 462                 }
 463         }
 464
 465         BUG_ON(i > max_entries);
 466         BUG_ON(i != obj->base.size / PAGE_SIZE);
 467
 468         /* XXX: This serves as a posting read to make sure that the PTE has
 469          * actually been updated. There is some concern that even though
 470          * registers and PTEs are within the same BAR that they are potentially
 471          * of NUMA access patterns. Therefore, even with the way we assume
 472          * hardware should work, we must keep this posting read for paranoia.
 473          */
 474         if (i != 0)
 475                 WARN_ON(readl(&gtt_entries[i-1]) != pte_encode(dev, addr, level));
 476
 477         /* This next bit makes the above posting read even more important. We
 478          * want to flush the TLBs only after we're certain all the PTE updates
 479          * have finished.
 480          */
 481         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 482         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 483 }
 484
 485 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 486                               enum i915_cache_level cache_level)
 487 {
 488         struct drm_device *dev = obj->base.dev;
 489         if (INTEL_INFO(dev)->gen < 6) {
 490                 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 491                         AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 492                 intel_gtt_insert_sg_entries(obj->pages,
 493                                             obj->gtt_space->start >> PAGE_SHIFT,
 494                                             flags);
 495         } else {
 496                 gen6_ggtt_bind_object(obj, cache_level);
 497         }
 498
 499         obj->has_global_gtt_mapping = 1;
 500 }
 501
 502 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 503 {
 504         i915_ggtt_clear_range(obj->base.dev,
 505                               obj->gtt_space->start >> PAGE_SHIFT,
 506                               obj->base.size >> PAGE_SHIFT);
 507
 508         obj->has_global_gtt_mapping = 0;
 509 }
 510
 511 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 512 {
 513         struct drm_device *dev = obj->base.dev;
 514         struct drm_i915_private *dev_priv = dev->dev_private;
 515         bool interruptible;
 516
 517         interruptible = do_idling(dev_priv);
 518
 519         if (!obj->has_dma_mapping)
 520                 dma_unmap_sg(&dev->pdev->dev,
 521                              obj->pages->sgl, obj->pages->nents,
 522                              PCI_DMA_BIDIRECTIONAL);
 523
 524         undo_idling(dev_priv, interruptible);
 525 }
 526
 527 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 528                                   unsigned long color,
 529                                   unsigned long *start,
 530                                   unsigned long *end)
 531 {
 532         if (node->color != color)
 533                 *start += 4096;
 534
 535         if (!list_empty(&node->node_list)) {
 536                 node = list_entry(node->node_list.next,
 537                                   struct drm_mm_node,
 538                                   node_list);
 539                 if (node->allocated && node->color != color)
 540                         *end -= 4096;
 541         }
 542 }
 543
 544 void i915_gem_setup_global_gtt(struct drm_device *dev,
 545                                unsigned long start,
 546                                unsigned long mappable_end,
 547                                unsigned long end)
 548 {
 549         drm_i915_private_t *dev_priv = dev->dev_private;
 550         struct drm_mm_node *entry;
 551         struct drm_i915_gem_object *obj;
 552         unsigned long hole_start, hole_end;
 553
 554         BUG_ON(mappable_end > end);
 555
 556         /* Subtract the guard page ... */
 557         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 558         if (!HAS_LLC(dev))
 559                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 560
 561         /* Mark any preallocated objects as occupied */
 562         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 563                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 564                               obj->gtt_offset, obj->base.size);
 565
 566                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 567                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 568                                                      obj->gtt_offset,
 569                                                      obj->base.size,
 570                                                      false);
 571                 obj->has_global_gtt_mapping = 1;
 572         }
 573
 574         dev_priv->gtt.start = start;
 575         dev_priv->gtt.total = end - start;
 576
 577         /* Clear any non-preallocated blocks */
 578         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 579                              hole_start, hole_end) {
 580                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 581                               hole_start, hole_end);
 582                 i915_ggtt_clear_range(dev,
 583                                       hole_start / PAGE_SIZE,
 584                                       (hole_end-hole_start) / PAGE_SIZE);
 585         }
 586
 587         /* And finally clear the reserved guard page */
 588         i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 589 }
 590
 591 static bool
 592 intel_enable_ppgtt(struct drm_device *dev)
 593 {
 594         if (i915_enable_ppgtt >= 0)
 595                 return i915_enable_ppgtt;
 596
 597 #ifdef CONFIG_INTEL_IOMMU
 598         /* Disable ppgtt on SNB if VT-d is on. */
 599         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 600                 return false;
 601 #endif
 602
 603         return true;
 604 }
 605
 606 void i915_gem_init_global_gtt(struct drm_device *dev)
 607 {
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609         unsigned long gtt_size, mappable_size;
 610         int ret;
 611
 612         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
 613         mappable_size = dev_priv->gtt.mappable_end;
 614
 615         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 616                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 617                  * aperture accordingly when using aliasing ppgtt. */
 618                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 619
 620                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 621
 622                 ret = i915_gem_init_aliasing_ppgtt(dev);
 623                 if (ret) {
 624                         mutex_unlock(&dev->struct_mutex);
 625                         return;
 626                 }
 627         } else {
 628                 /* Let GEM Manage all of the aperture.
 629                  *
 630                  * However, leave one page at the end still bound to the scratch
 631                  * page.  There are a number of places where the hardware
 632                  * apparently prefetches past the end of the object, and we've
 633                  * seen multiple hangs with the GPU head pointer stuck in a
 634                  * batchbuffer bound at the last page of the aperture.  One page
 635                  * should be enough to keep any prefetching inside of the
 636                  * aperture.
 637                  */
 638                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 639         }
 640 }
 641
 642 static int setup_scratch_page(struct drm_device *dev)
 643 {
 644         struct drm_i915_private *dev_priv = dev->dev_private;
 645         struct page *page;
 646         dma_addr_t dma_addr;
 647
 648         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 649         if (page == NULL)
 650                 return -ENOMEM;
 651         get_page(page);
 652         set_pages_uc(page, 1);
 653
 654 #ifdef CONFIG_INTEL_IOMMU
 655         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 656                                 PCI_DMA_BIDIRECTIONAL);
 657         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 658                 return -EINVAL;
 659 #else
 660         dma_addr = page_to_phys(page);
 661 #endif
 662         dev_priv->mm.gtt->scratch_page = page;
 663         dev_priv->mm.gtt->scratch_page_dma = dma_addr;
 664
 665         return 0;
 666 }
 667
 668 static void teardown_scratch_page(struct drm_device *dev)
 669 {
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         set_pages_wb(dev_priv->mm.gtt->scratch_page, 1);
 672         pci_unmap_page(dev->pdev, dev_priv->mm.gtt->scratch_page_dma,
 673                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 674         put_page(dev_priv->mm.gtt->scratch_page);
 675         __free_page(dev_priv->mm.gtt->scratch_page);
 676 }
 677
 678 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 679 {
 680         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 681         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 682         return snb_gmch_ctl << 20;
 683 }
 684
 685 static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)
 686 {
 687         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 688         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 689         return snb_gmch_ctl << 25; /* 32 MB units */
 690 }
 691
 692 static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
 693 {
 694         static const int stolen_decoder[] = {
 695                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 696         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 697         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 698         return stolen_decoder[snb_gmch_ctl] << 20;
 699 }
 700
 701 int i915_gem_gtt_init(struct drm_device *dev)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         phys_addr_t gtt_bus_addr;
 705         u16 snb_gmch_ctl;
 706         int ret;
 707
 708         dev_priv->gtt.mappable_base = pci_resource_start(dev->pdev, 2);
 709         dev_priv->gtt.mappable_end = pci_resource_len(dev->pdev, 2);
 710
 711         /* On modern platforms we need not worry ourself with the legacy
 712          * hostbridge query stuff. Skip it entirely
 713          */
 714         if (INTEL_INFO(dev)->gen < 6) {
 715                 ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
 716                 if (!ret) {
 717                         DRM_ERROR("failed to set up gmch\n");
 718                         return -EIO;
 719                 }
 720
 721                 dev_priv->mm.gtt = intel_gtt_get();
 722                 if (!dev_priv->mm.gtt) {
 723                         DRM_ERROR("Failed to initialize GTT\n");
 724                         intel_gmch_remove();
 725                         return -ENODEV;
 726                 }
 727
 728                 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev);
 729
 730                 return 0;
 731         }
 732
 733         dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL);
 734         if (!dev_priv->mm.gtt)
 735                 return -ENOMEM;
 736
 737         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 738                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 739
 740 #ifdef CONFIG_INTEL_IOMMU
 741         dev_priv->mm.gtt->needs_dmar = 1;
 742 #endif
 743
 744         /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
 745         gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
 746
 747         /* i9xx_setup */
 748         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 749         dev_priv->mm.gtt->gtt_total_entries =
 750                 gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
 751         if (INTEL_INFO(dev)->gen < 7)
 752                 dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
 753         else
 754                 dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
 755
 756         /* 64/512MB is the current min/max we actually know of, but this is just a
 757          * coarse sanity check.
 758          */
 759         if ((dev_priv->gtt.mappable_end < (64<<20) ||
 760             (dev_priv->gtt.mappable_end > (512<<20)))) {
 761                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 762                           dev_priv->gtt.mappable_end);
 763                 ret = -ENXIO;
 764                 goto err_out;
 765         }
 766
 767         ret = setup_scratch_page(dev);
 768         if (ret) {
 769                 DRM_ERROR("Scratch setup failed\n");
 770                 goto err_out;
 771         }
 772
 773         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr,
 774                                        dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t));
 775         if (!dev_priv->gtt.gsm) {
 776                 DRM_ERROR("Failed to map the gtt page table\n");
 777                 teardown_scratch_page(dev);
 778                 ret = -ENOMEM;
 779                 goto err_out;
 780         }
 781
 782         /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
 783         DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);
 784         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv->gtt.mappable_end >> 20);
 785         DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);
 786
 787         return 0;
 788
 789 err_out:
 790         kfree(dev_priv->mm.gtt);
 791         if (INTEL_INFO(dev)->gen < 6)
 792                 intel_gmch_remove();
 793         return ret;
 794 }
 795
 796 void i915_gem_gtt_fini(struct drm_device *dev)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         iounmap(dev_priv->gtt.gsm);
 800         teardown_scratch_page(dev);
 801         if (INTEL_INFO(dev)->gen < 6)
 802                 intel_gmch_remove();
 803         kfree(dev_priv->mm.gtt);
 804 }