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drm/i915: Split GEN6 PPGTT initialization up
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_trace.h"
31 #include "intel_drv.h"
32
33 #define GEN6_PPGTT_PD_ENTRIES 512
34 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
35 typedef uint64_t gen8_gtt_pte_t;
36 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
37
38 /* PPGTT stuff */
39 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
40 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
41
42 #define GEN6_PDE_VALID (1 << 0)
43 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
44 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
45
46 #define GEN6_PTE_VALID (1 << 0)
47 #define GEN6_PTE_UNCACHED (1 << 1)
48 #define HSW_PTE_UNCACHED (0)
49 #define GEN6_PTE_CACHE_LLC (2 << 1)
50 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
51 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
52 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
53
54 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
55 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
56 */
57 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
58 (((bits) & 0x8) << (11 - 3)))
59 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
60 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
61 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
62 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
63 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
64 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
65
66 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
67 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
68
69 /* GEN8 legacy style addressis defined as a 3 level page table:
70 * 31:30 | 29:21 | 20:12 | 11:0
71 * PDPE | PDE | PTE | offset
72 * The difference as compared to normal x86 3 level page table is the PDPEs are
73 * programmed via register.
74 */
75 #define GEN8_PDPE_SHIFT 30
76 #define GEN8_PDPE_MASK 0x3
77 #define GEN8_PDE_SHIFT 21
78 #define GEN8_PDE_MASK 0x1ff
79 #define GEN8_PTE_SHIFT 12
80 #define GEN8_PTE_MASK 0x1ff
81
82 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
83 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
84 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
85 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
86
87 static void ppgtt_bind_vma(struct i915_vma *vma,
88 enum i915_cache_level cache_level,
89 u32 flags);
90 static void ppgtt_unbind_vma(struct i915_vma *vma);
91 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
92
93 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
94 enum i915_cache_level level,
95 bool valid)
96 {
97 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
98 pte |= addr;
99 if (level != I915_CACHE_NONE)
100 pte |= PPAT_CACHED_INDEX;
101 else
102 pte |= PPAT_UNCACHED_INDEX;
103 return pte;
104 }
105
106 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
107 dma_addr_t addr,
108 enum i915_cache_level level)
109 {
110 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
111 pde |= addr;
112 if (level != I915_CACHE_NONE)
113 pde |= PPAT_CACHED_PDE_INDEX;
114 else
115 pde |= PPAT_UNCACHED_INDEX;
116 return pde;
117 }
118
119 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
120 enum i915_cache_level level,
121 bool valid)
122 {
123 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
124 pte |= GEN6_PTE_ADDR_ENCODE(addr);
125
126 switch (level) {
127 case I915_CACHE_L3_LLC:
128 case I915_CACHE_LLC:
129 pte |= GEN6_PTE_CACHE_LLC;
130 break;
131 case I915_CACHE_NONE:
132 pte |= GEN6_PTE_UNCACHED;
133 break;
134 default:
135 WARN_ON(1);
136 }
137
138 return pte;
139 }
140
141 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
142 enum i915_cache_level level,
143 bool valid)
144 {
145 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
146 pte |= GEN6_PTE_ADDR_ENCODE(addr);
147
148 switch (level) {
149 case I915_CACHE_L3_LLC:
150 pte |= GEN7_PTE_CACHE_L3_LLC;
151 break;
152 case I915_CACHE_LLC:
153 pte |= GEN6_PTE_CACHE_LLC;
154 break;
155 case I915_CACHE_NONE:
156 pte |= GEN6_PTE_UNCACHED;
157 break;
158 default:
159 WARN_ON(1);
160 }
161
162 return pte;
163 }
164
165 #define BYT_PTE_WRITEABLE (1 << 1)
166 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
167
168 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
169 enum i915_cache_level level,
170 bool valid)
171 {
172 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
173 pte |= GEN6_PTE_ADDR_ENCODE(addr);
174
175 /* Mark the page as writeable. Other platforms don't have a
176 * setting for read-only/writable, so this matches that behavior.
177 */
178 pte |= BYT_PTE_WRITEABLE;
179
180 if (level != I915_CACHE_NONE)
181 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
182
183 return pte;
184 }
185
186 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
187 enum i915_cache_level level,
188 bool valid)
189 {
190 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
191 pte |= HSW_PTE_ADDR_ENCODE(addr);
192
193 if (level != I915_CACHE_NONE)
194 pte |= HSW_WB_LLC_AGE3;
195
196 return pte;
197 }
198
199 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
200 enum i915_cache_level level,
201 bool valid)
202 {
203 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
204 pte |= HSW_PTE_ADDR_ENCODE(addr);
205
206 switch (level) {
207 case I915_CACHE_NONE:
208 break;
209 case I915_CACHE_WT:
210 pte |= HSW_WT_ELLC_LLC_AGE3;
211 break;
212 default:
213 pte |= HSW_WB_ELLC_LLC_AGE3;
214 break;
215 }
216
217 return pte;
218 }
219
220 /* Broadwell Page Directory Pointer Descriptors */
221 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
222 uint64_t val, bool synchronous)
223 {
224 struct drm_i915_private *dev_priv = ring->dev->dev_private;
225 int ret;
226
227 BUG_ON(entry >= 4);
228
229 if (synchronous) {
230 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
231 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
232 return 0;
233 }
234
235 ret = intel_ring_begin(ring, 6);
236 if (ret)
237 return ret;
238
239 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
240 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
241 intel_ring_emit(ring, (u32)(val >> 32));
242 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
243 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
244 intel_ring_emit(ring, (u32)(val));
245 intel_ring_advance(ring);
246
247 return 0;
248 }
249
250 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
251 struct intel_ring_buffer *ring,
252 bool synchronous)
253 {
254 int i, ret;
255
256 /* bit of a hack to find the actual last used pd */
257 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
258
259 for (i = used_pd - 1; i >= 0; i--) {
260 dma_addr_t addr = ppgtt->pd_dma_addr[i];
261 ret = gen8_write_pdp(ring, i, addr, synchronous);
262 if (ret)
263 return ret;
264 }
265
266 return 0;
267 }
268
269 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
270 uint64_t start,
271 uint64_t length,
272 bool use_scratch)
273 {
274 struct i915_hw_ppgtt *ppgtt =
275 container_of(vm, struct i915_hw_ppgtt, base);
276 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
277 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
278 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
279 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
280 unsigned num_entries = length >> PAGE_SHIFT;
281 unsigned last_pte, i;
282
283 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
284 I915_CACHE_LLC, use_scratch);
285
286 while (num_entries) {
287 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
288
289 last_pte = pte + num_entries;
290 if (last_pte > GEN8_PTES_PER_PAGE)
291 last_pte = GEN8_PTES_PER_PAGE;
292
293 pt_vaddr = kmap_atomic(page_table);
294
295 for (i = pte; i < last_pte; i++) {
296 pt_vaddr[i] = scratch_pte;
297 num_entries--;
298 }
299
300 kunmap_atomic(pt_vaddr);
301
302 pte = 0;
303 if (++pde == GEN8_PDES_PER_PAGE) {
304 pdpe++;
305 pde = 0;
306 }
307 }
308 }
309
310 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
311 struct sg_table *pages,
312 uint64_t start,
313 enum i915_cache_level cache_level)
314 {
315 struct i915_hw_ppgtt *ppgtt =
316 container_of(vm, struct i915_hw_ppgtt, base);
317 gen8_gtt_pte_t *pt_vaddr;
318 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
319 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
320 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
321 struct sg_page_iter sg_iter;
322
323 pt_vaddr = NULL;
324
325 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
326 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
327 break;
328
329 if (pt_vaddr == NULL)
330 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
331
332 pt_vaddr[pte] =
333 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
334 cache_level, true);
335 if (++pte == GEN8_PTES_PER_PAGE) {
336 kunmap_atomic(pt_vaddr);
337 pt_vaddr = NULL;
338 if (++pde == GEN8_PDES_PER_PAGE) {
339 pdpe++;
340 pde = 0;
341 }
342 pte = 0;
343 }
344 }
345 if (pt_vaddr)
346 kunmap_atomic(pt_vaddr);
347 }
348
349 static void gen8_free_page_tables(struct page **pt_pages)
350 {
351 int i;
352
353 if (pt_pages == NULL)
354 return;
355
356 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
357 if (pt_pages[i])
358 __free_pages(pt_pages[i], 0);
359 }
360
361 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
362 {
363 int i;
364
365 for (i = 0; i < ppgtt->num_pd_pages; i++) {
366 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
367 kfree(ppgtt->gen8_pt_pages[i]);
368 kfree(ppgtt->gen8_pt_dma_addr[i]);
369 }
370
371 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
372 }
373
374 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
375 {
376 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
377 int i, j;
378
379 for (i = 0; i < ppgtt->num_pd_pages; i++) {
380 /* TODO: In the future we'll support sparse mappings, so this
381 * will have to change. */
382 if (!ppgtt->pd_dma_addr[i])
383 continue;
384
385 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
386 PCI_DMA_BIDIRECTIONAL);
387
388 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
389 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
390 if (addr)
391 pci_unmap_page(hwdev, addr, PAGE_SIZE,
392 PCI_DMA_BIDIRECTIONAL);
393 }
394 }
395 }
396
397 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
398 {
399 struct i915_hw_ppgtt *ppgtt =
400 container_of(vm, struct i915_hw_ppgtt, base);
401
402 list_del(&vm->global_link);
403 drm_mm_takedown(&vm->mm);
404
405 gen8_ppgtt_unmap_pages(ppgtt);
406 gen8_ppgtt_free(ppgtt);
407 }
408
409 static struct page **__gen8_alloc_page_tables(void)
410 {
411 struct page **pt_pages;
412 int i;
413
414 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
415 if (!pt_pages)
416 return ERR_PTR(-ENOMEM);
417
418 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
419 pt_pages[i] = alloc_page(GFP_KERNEL);
420 if (!pt_pages[i])
421 goto bail;
422 }
423
424 return pt_pages;
425
426 bail:
427 gen8_free_page_tables(pt_pages);
428 kfree(pt_pages);
429 return ERR_PTR(-ENOMEM);
430 }
431
432 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
433 const int max_pdp)
434 {
435 struct page **pt_pages[GEN8_LEGACY_PDPS];
436 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
437 int i, ret;
438
439 for (i = 0; i < max_pdp; i++) {
440 pt_pages[i] = __gen8_alloc_page_tables();
441 if (IS_ERR(pt_pages[i])) {
442 ret = PTR_ERR(pt_pages[i]);
443 goto unwind_out;
444 }
445 }
446
447 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
448 * "atomic" - for cleanup purposes.
449 */
450 for (i = 0; i < max_pdp; i++)
451 ppgtt->gen8_pt_pages[i] = pt_pages[i];
452
453 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
454
455 return 0;
456
457 unwind_out:
458 while (i--) {
459 gen8_free_page_tables(pt_pages[i]);
460 kfree(pt_pages[i]);
461 }
462
463 return ret;
464 }
465
466 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
467 {
468 int i;
469
470 for (i = 0; i < ppgtt->num_pd_pages; i++) {
471 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
472 sizeof(dma_addr_t),
473 GFP_KERNEL);
474 if (!ppgtt->gen8_pt_dma_addr[i])
475 return -ENOMEM;
476 }
477
478 return 0;
479 }
480
481 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
482 const int max_pdp)
483 {
484 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
485 if (!ppgtt->pd_pages)
486 return -ENOMEM;
487
488 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
489 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
490
491 return 0;
492 }
493
494 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
495 const int max_pdp)
496 {
497 int ret;
498
499 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
500 if (ret)
501 return ret;
502
503 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
504 if (ret) {
505 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
506 return ret;
507 }
508
509 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
510
511 ret = gen8_ppgtt_allocate_dma(ppgtt);
512 if (ret)
513 gen8_ppgtt_free(ppgtt);
514
515 return ret;
516 }
517
518 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
519 const int pd)
520 {
521 dma_addr_t pd_addr;
522 int ret;
523
524 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
525 &ppgtt->pd_pages[pd], 0,
526 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
527
528 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
529 if (ret)
530 return ret;
531
532 ppgtt->pd_dma_addr[pd] = pd_addr;
533
534 return 0;
535 }
536
537 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
538 const int pd,
539 const int pt)
540 {
541 dma_addr_t pt_addr;
542 struct page *p;
543 int ret;
544
545 p = ppgtt->gen8_pt_pages[pd][pt];
546 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
547 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
548 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
549 if (ret)
550 return ret;
551
552 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
553
554 return 0;
555 }
556
557 /**
558 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
559 * with a net effect resembling a 2-level page table in normal x86 terms. Each
560 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
561 * space.
562 *
563 * FIXME: split allocation into smaller pieces. For now we only ever do this
564 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
565 * TODO: Do something with the size parameter
566 */
567 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
568 {
569 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
570 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
571 int i, j, ret;
572
573 if (size % (1<<30))
574 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
575
576 /* 1. Do all our allocations for page directories and page tables. */
577 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
578 if (ret)
579 return ret;
580
581 /*
582 * 2. Create DMA mappings for the page directories and page tables.
583 */
584 for (i = 0; i < max_pdp; i++) {
585 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
586 if (ret)
587 goto bail;
588
589 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
590 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
591 if (ret)
592 goto bail;
593 }
594 }
595
596 /*
597 * 3. Map all the page directory entires to point to the page tables
598 * we've allocated.
599 *
600 * For now, the PPGTT helper functions all require that the PDEs are
601 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
602 * will never need to touch the PDEs again.
603 */
604 for (i = 0; i < max_pdp; i++) {
605 gen8_ppgtt_pde_t *pd_vaddr;
606 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
607 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
608 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
609 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
610 I915_CACHE_LLC);
611 }
612 kunmap_atomic(pd_vaddr);
613 }
614
615 ppgtt->enable = gen8_ppgtt_enable;
616 ppgtt->switch_mm = gen8_mm_switch;
617 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
618 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
619 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
620 ppgtt->base.start = 0;
621 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
622
623 ppgtt->base.clear_range(&ppgtt->base, 0,
624 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE,
625 true);
626
627 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
628 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
629 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
630 ppgtt->num_pt_pages,
631 (ppgtt->num_pt_pages - min_pt_pages) +
632 size % (1<<30));
633 return 0;
634
635 bail:
636 gen8_ppgtt_unmap_pages(ppgtt);
637 gen8_ppgtt_free(ppgtt);
638 return ret;
639 }
640
641 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
642 {
643 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
644 struct i915_address_space *vm = &ppgtt->base;
645 gen6_gtt_pte_t __iomem *pd_addr;
646 gen6_gtt_pte_t scratch_pte;
647 uint32_t pd_entry;
648 int pte, pde;
649
650 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
651
652 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
653 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
654
655 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
656 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
657 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
658 u32 expected;
659 gen6_gtt_pte_t *pt_vaddr;
660 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
661 pd_entry = readl(pd_addr + pde);
662 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
663
664 if (pd_entry != expected)
665 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
666 pde,
667 pd_entry,
668 expected);
669 seq_printf(m, "\tPDE: %x\n", pd_entry);
670
671 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
672 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
673 unsigned long va =
674 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
675 (pte * PAGE_SIZE);
676 int i;
677 bool found = false;
678 for (i = 0; i < 4; i++)
679 if (pt_vaddr[pte + i] != scratch_pte)
680 found = true;
681 if (!found)
682 continue;
683
684 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
685 for (i = 0; i < 4; i++) {
686 if (pt_vaddr[pte + i] != scratch_pte)
687 seq_printf(m, " %08x", pt_vaddr[pte + i]);
688 else
689 seq_puts(m, " SCRATCH ");
690 }
691 seq_puts(m, "\n");
692 }
693 kunmap_atomic(pt_vaddr);
694 }
695 }
696
697 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
698 {
699 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
700 gen6_gtt_pte_t __iomem *pd_addr;
701 uint32_t pd_entry;
702 int i;
703
704 WARN_ON(ppgtt->pd_offset & 0x3f);
705 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
706 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
707 for (i = 0; i < ppgtt->num_pd_entries; i++) {
708 dma_addr_t pt_addr;
709
710 pt_addr = ppgtt->pt_dma_addr[i];
711 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
712 pd_entry |= GEN6_PDE_VALID;
713
714 writel(pd_entry, pd_addr + i);
715 }
716 readl(pd_addr);
717 }
718
719 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
720 {
721 BUG_ON(ppgtt->pd_offset & 0x3f);
722
723 return (ppgtt->pd_offset / 64) << 16;
724 }
725
726 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
727 struct intel_ring_buffer *ring,
728 bool synchronous)
729 {
730 struct drm_device *dev = ppgtt->base.dev;
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 int ret;
733
734 /* If we're in reset, we can assume the GPU is sufficiently idle to
735 * manually frob these bits. Ideally we could use the ring functions,
736 * except our error handling makes it quite difficult (can't use
737 * intel_ring_begin, ring->flush, or intel_ring_advance)
738 *
739 * FIXME: We should try not to special case reset
740 */
741 if (synchronous ||
742 i915_reset_in_progress(&dev_priv->gpu_error)) {
743 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
744 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
745 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
746 POSTING_READ(RING_PP_DIR_BASE(ring));
747 return 0;
748 }
749
750 /* NB: TLBs must be flushed and invalidated before a switch */
751 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
752 if (ret)
753 return ret;
754
755 ret = intel_ring_begin(ring, 6);
756 if (ret)
757 return ret;
758
759 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
760 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
761 intel_ring_emit(ring, PP_DIR_DCLV_2G);
762 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
763 intel_ring_emit(ring, get_pd_offset(ppgtt));
764 intel_ring_emit(ring, MI_NOOP);
765 intel_ring_advance(ring);
766
767 return 0;
768 }
769
770 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
771 struct intel_ring_buffer *ring,
772 bool synchronous)
773 {
774 struct drm_device *dev = ppgtt->base.dev;
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 int ret;
777
778 /* If we're in reset, we can assume the GPU is sufficiently idle to
779 * manually frob these bits. Ideally we could use the ring functions,
780 * except our error handling makes it quite difficult (can't use
781 * intel_ring_begin, ring->flush, or intel_ring_advance)
782 *
783 * FIXME: We should try not to special case reset
784 */
785 if (synchronous ||
786 i915_reset_in_progress(&dev_priv->gpu_error)) {
787 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
788 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
789 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
790 POSTING_READ(RING_PP_DIR_BASE(ring));
791 return 0;
792 }
793
794 /* NB: TLBs must be flushed and invalidated before a switch */
795 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
796 if (ret)
797 return ret;
798
799 ret = intel_ring_begin(ring, 6);
800 if (ret)
801 return ret;
802
803 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
804 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
805 intel_ring_emit(ring, PP_DIR_DCLV_2G);
806 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
807 intel_ring_emit(ring, get_pd_offset(ppgtt));
808 intel_ring_emit(ring, MI_NOOP);
809 intel_ring_advance(ring);
810
811 /* XXX: RCS is the only one to auto invalidate the TLBs? */
812 if (ring->id != RCS) {
813 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
814 if (ret)
815 return ret;
816 }
817
818 return 0;
819 }
820
821 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
822 struct intel_ring_buffer *ring,
823 bool synchronous)
824 {
825 struct drm_device *dev = ppgtt->base.dev;
826 struct drm_i915_private *dev_priv = dev->dev_private;
827
828 if (!synchronous)
829 return 0;
830
831 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
832 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
833
834 POSTING_READ(RING_PP_DIR_DCLV(ring));
835
836 return 0;
837 }
838
839 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
840 {
841 struct drm_device *dev = ppgtt->base.dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 struct intel_ring_buffer *ring;
844 int j, ret;
845
846 for_each_ring(ring, dev_priv, j) {
847 I915_WRITE(RING_MODE_GEN7(ring),
848 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
849
850 /* We promise to do a switch later with FULL PPGTT. If this is
851 * aliasing, this is the one and only switch we'll do */
852 if (USES_FULL_PPGTT(dev))
853 continue;
854
855 ret = ppgtt->switch_mm(ppgtt, ring, true);
856 if (ret)
857 goto err_out;
858 }
859
860 return 0;
861
862 err_out:
863 for_each_ring(ring, dev_priv, j)
864 I915_WRITE(RING_MODE_GEN7(ring),
865 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
866 return ret;
867 }
868
869 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
870 {
871 struct drm_device *dev = ppgtt->base.dev;
872 drm_i915_private_t *dev_priv = dev->dev_private;
873 struct intel_ring_buffer *ring;
874 uint32_t ecochk, ecobits;
875 int i;
876
877 ecobits = I915_READ(GAC_ECO_BITS);
878 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
879
880 ecochk = I915_READ(GAM_ECOCHK);
881 if (IS_HASWELL(dev)) {
882 ecochk |= ECOCHK_PPGTT_WB_HSW;
883 } else {
884 ecochk |= ECOCHK_PPGTT_LLC_IVB;
885 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
886 }
887 I915_WRITE(GAM_ECOCHK, ecochk);
888
889 for_each_ring(ring, dev_priv, i) {
890 int ret;
891 /* GFX_MODE is per-ring on gen7+ */
892 I915_WRITE(RING_MODE_GEN7(ring),
893 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
894
895 /* We promise to do a switch later with FULL PPGTT. If this is
896 * aliasing, this is the one and only switch we'll do */
897 if (USES_FULL_PPGTT(dev))
898 continue;
899
900 ret = ppgtt->switch_mm(ppgtt, ring, true);
901 if (ret)
902 return ret;
903 }
904
905 return 0;
906 }
907
908 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
909 {
910 struct drm_device *dev = ppgtt->base.dev;
911 drm_i915_private_t *dev_priv = dev->dev_private;
912 struct intel_ring_buffer *ring;
913 uint32_t ecochk, gab_ctl, ecobits;
914 int i;
915
916 ecobits = I915_READ(GAC_ECO_BITS);
917 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
918 ECOBITS_PPGTT_CACHE64B);
919
920 gab_ctl = I915_READ(GAB_CTL);
921 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
922
923 ecochk = I915_READ(GAM_ECOCHK);
924 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
925
926 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
927
928 for_each_ring(ring, dev_priv, i) {
929 int ret = ppgtt->switch_mm(ppgtt, ring, true);
930 if (ret)
931 return ret;
932 }
933
934 return 0;
935 }
936
937 /* PPGTT support for Sandybdrige/Gen6 and later */
938 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
939 uint64_t start,
940 uint64_t length,
941 bool use_scratch)
942 {
943 struct i915_hw_ppgtt *ppgtt =
944 container_of(vm, struct i915_hw_ppgtt, base);
945 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
946 unsigned first_entry = start >> PAGE_SHIFT;
947 unsigned num_entries = length >> PAGE_SHIFT;
948 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
949 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
950 unsigned last_pte, i;
951
952 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
953
954 while (num_entries) {
955 last_pte = first_pte + num_entries;
956 if (last_pte > I915_PPGTT_PT_ENTRIES)
957 last_pte = I915_PPGTT_PT_ENTRIES;
958
959 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
960
961 for (i = first_pte; i < last_pte; i++)
962 pt_vaddr[i] = scratch_pte;
963
964 kunmap_atomic(pt_vaddr);
965
966 num_entries -= last_pte - first_pte;
967 first_pte = 0;
968 act_pt++;
969 }
970 }
971
972 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
973 struct sg_table *pages,
974 uint64_t start,
975 enum i915_cache_level cache_level)
976 {
977 struct i915_hw_ppgtt *ppgtt =
978 container_of(vm, struct i915_hw_ppgtt, base);
979 gen6_gtt_pte_t *pt_vaddr;
980 unsigned first_entry = start >> PAGE_SHIFT;
981 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
982 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
983 struct sg_page_iter sg_iter;
984
985 pt_vaddr = NULL;
986 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
987 if (pt_vaddr == NULL)
988 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
989
990 pt_vaddr[act_pte] =
991 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
992 cache_level, true);
993 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
994 kunmap_atomic(pt_vaddr);
995 pt_vaddr = NULL;
996 act_pt++;
997 act_pte = 0;
998 }
999 }
1000 if (pt_vaddr)
1001 kunmap_atomic(pt_vaddr);
1002 }
1003
1004 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
1005 {
1006 int i;
1007
1008 if (ppgtt->pt_dma_addr) {
1009 for (i = 0; i < ppgtt->num_pd_entries; i++)
1010 pci_unmap_page(ppgtt->base.dev->pdev,
1011 ppgtt->pt_dma_addr[i],
1012 4096, PCI_DMA_BIDIRECTIONAL);
1013 }
1014 }
1015
1016 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1017 {
1018 int i;
1019
1020 kfree(ppgtt->pt_dma_addr);
1021 for (i = 0; i < ppgtt->num_pd_entries; i++)
1022 __free_page(ppgtt->pt_pages[i]);
1023 kfree(ppgtt->pt_pages);
1024 }
1025
1026 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1027 {
1028 struct i915_hw_ppgtt *ppgtt =
1029 container_of(vm, struct i915_hw_ppgtt, base);
1030
1031 list_del(&vm->global_link);
1032 drm_mm_takedown(&ppgtt->base.mm);
1033 drm_mm_remove_node(&ppgtt->node);
1034
1035 gen6_ppgtt_unmap_pages(ppgtt);
1036 gen6_ppgtt_free(ppgtt);
1037 }
1038
1039 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1040 {
1041 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
1042 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
1043 struct drm_device *dev = ppgtt->base.dev;
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 bool retried = false;
1046 int ret;
1047
1048 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1049 * allocator works in address space sizes, so it's multiplied by page
1050 * size. We allocate at the top of the GTT to avoid fragmentation.
1051 */
1052 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1053 alloc:
1054 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1055 &ppgtt->node, GEN6_PD_SIZE,
1056 GEN6_PD_ALIGN, 0,
1057 0, dev_priv->gtt.base.total,
1058 DRM_MM_SEARCH_DEFAULT);
1059 if (ret == -ENOSPC && !retried) {
1060 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1061 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1062 I915_CACHE_NONE, 0);
1063 if (ret)
1064 return ret;
1065
1066 retried = true;
1067 goto alloc;
1068 }
1069
1070 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1071 DRM_DEBUG("Forced to use aperture for PDEs\n");
1072
1073 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1074 return ret;
1075 }
1076
1077 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1078 {
1079 int i;
1080
1081 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1082 GFP_KERNEL);
1083
1084 if (!ppgtt->pt_pages)
1085 return -ENOMEM;
1086
1087 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1088 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1089 if (!ppgtt->pt_pages[i]) {
1090 gen6_ppgtt_free(ppgtt);
1091 return -ENOMEM;
1092 }
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1099 {
1100 int ret;
1101
1102 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1103 if (ret)
1104 return ret;
1105
1106 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1107 if (ret) {
1108 drm_mm_remove_node(&ppgtt->node);
1109 return ret;
1110 }
1111
1112 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1113 GFP_KERNEL);
1114 if (!ppgtt->pt_dma_addr) {
1115 drm_mm_remove_node(&ppgtt->node);
1116 gen6_ppgtt_free(ppgtt);
1117 return -ENOMEM;
1118 }
1119
1120 return 0;
1121 }
1122
1123 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1124 {
1125 struct drm_device *dev = ppgtt->base.dev;
1126 int i;
1127
1128 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1129 dma_addr_t pt_addr;
1130
1131 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1132 PCI_DMA_BIDIRECTIONAL);
1133
1134 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1135 gen6_ppgtt_unmap_pages(ppgtt);
1136 return -EIO;
1137 }
1138
1139 ppgtt->pt_dma_addr[i] = pt_addr;
1140 }
1141
1142 return 0;
1143 }
1144
1145 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1146 {
1147 struct drm_device *dev = ppgtt->base.dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 int ret;
1150
1151 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1152 if (IS_GEN6(dev)) {
1153 ppgtt->enable = gen6_ppgtt_enable;
1154 ppgtt->switch_mm = gen6_mm_switch;
1155 } else if (IS_HASWELL(dev)) {
1156 ppgtt->enable = gen7_ppgtt_enable;
1157 ppgtt->switch_mm = hsw_mm_switch;
1158 } else if (IS_GEN7(dev)) {
1159 ppgtt->enable = gen7_ppgtt_enable;
1160 ppgtt->switch_mm = gen7_mm_switch;
1161 } else
1162 BUG();
1163
1164 ret = gen6_ppgtt_alloc(ppgtt);
1165 if (ret)
1166 return ret;
1167
1168 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1169 if (ret) {
1170 gen6_ppgtt_free(ppgtt);
1171 return ret;
1172 }
1173
1174 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1175 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1176 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1177 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1178 ppgtt->base.start = 0;
1179 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1180 ppgtt->debug_dump = gen6_dump_ppgtt;
1181
1182 ppgtt->pd_offset =
1183 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1184
1185 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1186
1187 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1188 ppgtt->node.size >> 20,
1189 ppgtt->node.start / PAGE_SIZE);
1190
1191 return 0;
1192 }
1193
1194 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1195 {
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 int ret = 0;
1198
1199 ppgtt->base.dev = dev;
1200
1201 if (INTEL_INFO(dev)->gen < 8)
1202 ret = gen6_ppgtt_init(ppgtt);
1203 else if (IS_GEN8(dev))
1204 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1205 else
1206 BUG();
1207
1208 if (!ret) {
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 kref_init(&ppgtt->ref);
1211 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1212 ppgtt->base.total);
1213 i915_init_vm(dev_priv, &ppgtt->base);
1214 if (INTEL_INFO(dev)->gen < 8) {
1215 gen6_write_pdes(ppgtt);
1216 DRM_DEBUG("Adding PPGTT at offset %x\n",
1217 ppgtt->pd_offset << 10);
1218 }
1219 }
1220
1221 return ret;
1222 }
1223
1224 static void
1225 ppgtt_bind_vma(struct i915_vma *vma,
1226 enum i915_cache_level cache_level,
1227 u32 flags)
1228 {
1229 WARN_ON(flags);
1230
1231 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1232 cache_level);
1233 }
1234
1235 static void ppgtt_unbind_vma(struct i915_vma *vma)
1236 {
1237 vma->vm->clear_range(vma->vm,
1238 vma->node.start,
1239 vma->obj->base.size,
1240 true);
1241 }
1242
1243 extern int intel_iommu_gfx_mapped;
1244 /* Certain Gen5 chipsets require require idling the GPU before
1245 * unmapping anything from the GTT when VT-d is enabled.
1246 */
1247 static inline bool needs_idle_maps(struct drm_device *dev)
1248 {
1249 #ifdef CONFIG_INTEL_IOMMU
1250 /* Query intel_iommu to see if we need the workaround. Presumably that
1251 * was loaded first.
1252 */
1253 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1254 return true;
1255 #endif
1256 return false;
1257 }
1258
1259 static bool do_idling(struct drm_i915_private *dev_priv)
1260 {
1261 bool ret = dev_priv->mm.interruptible;
1262
1263 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1264 dev_priv->mm.interruptible = false;
1265 if (i915_gpu_idle(dev_priv->dev)) {
1266 DRM_ERROR("Couldn't idle GPU\n");
1267 /* Wait a bit, in hopes it avoids the hang */
1268 udelay(10);
1269 }
1270 }
1271
1272 return ret;
1273 }
1274
1275 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1276 {
1277 if (unlikely(dev_priv->gtt.do_idle_maps))
1278 dev_priv->mm.interruptible = interruptible;
1279 }
1280
1281 void i915_check_and_clear_faults(struct drm_device *dev)
1282 {
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 struct intel_ring_buffer *ring;
1285 int i;
1286
1287 if (INTEL_INFO(dev)->gen < 6)
1288 return;
1289
1290 for_each_ring(ring, dev_priv, i) {
1291 u32 fault_reg;
1292 fault_reg = I915_READ(RING_FAULT_REG(ring));
1293 if (fault_reg & RING_FAULT_VALID) {
1294 DRM_DEBUG_DRIVER("Unexpected fault\n"
1295 "\tAddr: 0x%08lx\\n"
1296 "\tAddress space: %s\n"
1297 "\tSource ID: %d\n"
1298 "\tType: %d\n",
1299 fault_reg & PAGE_MASK,
1300 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1301 RING_FAULT_SRCID(fault_reg),
1302 RING_FAULT_FAULT_TYPE(fault_reg));
1303 I915_WRITE(RING_FAULT_REG(ring),
1304 fault_reg & ~RING_FAULT_VALID);
1305 }
1306 }
1307 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1308 }
1309
1310 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1311 {
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313
1314 /* Don't bother messing with faults pre GEN6 as we have little
1315 * documentation supporting that it's a good idea.
1316 */
1317 if (INTEL_INFO(dev)->gen < 6)
1318 return;
1319
1320 i915_check_and_clear_faults(dev);
1321
1322 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1323 dev_priv->gtt.base.start,
1324 dev_priv->gtt.base.total,
1325 false);
1326 }
1327
1328 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1329 {
1330 struct drm_i915_private *dev_priv = dev->dev_private;
1331 struct drm_i915_gem_object *obj;
1332 struct i915_address_space *vm;
1333
1334 i915_check_and_clear_faults(dev);
1335
1336 /* First fill our portion of the GTT with scratch pages */
1337 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1338 dev_priv->gtt.base.start,
1339 dev_priv->gtt.base.total,
1340 true);
1341
1342 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1343 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1344 &dev_priv->gtt.base);
1345 if (!vma)
1346 continue;
1347
1348 i915_gem_clflush_object(obj, obj->pin_display);
1349 /* The bind_vma code tries to be smart about tracking mappings.
1350 * Unfortunately above, we've just wiped out the mappings
1351 * without telling our object about it. So we need to fake it.
1352 */
1353 obj->has_global_gtt_mapping = 0;
1354 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1355 }
1356
1357
1358 if (INTEL_INFO(dev)->gen >= 8)
1359 return;
1360
1361 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1362 /* TODO: Perhaps it shouldn't be gen6 specific */
1363 if (i915_is_ggtt(vm)) {
1364 if (dev_priv->mm.aliasing_ppgtt)
1365 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1366 continue;
1367 }
1368
1369 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1370 }
1371
1372 i915_gem_chipset_flush(dev);
1373 }
1374
1375 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1376 {
1377 if (obj->has_dma_mapping)
1378 return 0;
1379
1380 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1381 obj->pages->sgl, obj->pages->nents,
1382 PCI_DMA_BIDIRECTIONAL))
1383 return -ENOSPC;
1384
1385 return 0;
1386 }
1387
1388 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1389 {
1390 #ifdef writeq
1391 writeq(pte, addr);
1392 #else
1393 iowrite32((u32)pte, addr);
1394 iowrite32(pte >> 32, addr + 4);
1395 #endif
1396 }
1397
1398 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1399 struct sg_table *st,
1400 uint64_t start,
1401 enum i915_cache_level level)
1402 {
1403 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1404 unsigned first_entry = start >> PAGE_SHIFT;
1405 gen8_gtt_pte_t __iomem *gtt_entries =
1406 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1407 int i = 0;
1408 struct sg_page_iter sg_iter;
1409 dma_addr_t addr;
1410
1411 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1412 addr = sg_dma_address(sg_iter.sg) +
1413 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1414 gen8_set_pte(&gtt_entries[i],
1415 gen8_pte_encode(addr, level, true));
1416 i++;
1417 }
1418
1419 /*
1420 * XXX: This serves as a posting read to make sure that the PTE has
1421 * actually been updated. There is some concern that even though
1422 * registers and PTEs are within the same BAR that they are potentially
1423 * of NUMA access patterns. Therefore, even with the way we assume
1424 * hardware should work, we must keep this posting read for paranoia.
1425 */
1426 if (i != 0)
1427 WARN_ON(readq(&gtt_entries[i-1])
1428 != gen8_pte_encode(addr, level, true));
1429
1430 /* This next bit makes the above posting read even more important. We
1431 * want to flush the TLBs only after we're certain all the PTE updates
1432 * have finished.
1433 */
1434 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1435 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1436 }
1437
1438 /*
1439 * Binds an object into the global gtt with the specified cache level. The object
1440 * will be accessible to the GPU via commands whose operands reference offsets
1441 * within the global GTT as well as accessible by the GPU through the GMADR
1442 * mapped BAR (dev_priv->mm.gtt->gtt).
1443 */
1444 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1445 struct sg_table *st,
1446 uint64_t start,
1447 enum i915_cache_level level)
1448 {
1449 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1450 unsigned first_entry = start >> PAGE_SHIFT;
1451 gen6_gtt_pte_t __iomem *gtt_entries =
1452 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1453 int i = 0;
1454 struct sg_page_iter sg_iter;
1455 dma_addr_t addr;
1456
1457 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1458 addr = sg_page_iter_dma_address(&sg_iter);
1459 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1460 i++;
1461 }
1462
1463 /* XXX: This serves as a posting read to make sure that the PTE has
1464 * actually been updated. There is some concern that even though
1465 * registers and PTEs are within the same BAR that they are potentially
1466 * of NUMA access patterns. Therefore, even with the way we assume
1467 * hardware should work, we must keep this posting read for paranoia.
1468 */
1469 if (i != 0)
1470 WARN_ON(readl(&gtt_entries[i-1]) !=
1471 vm->pte_encode(addr, level, true));
1472
1473 /* This next bit makes the above posting read even more important. We
1474 * want to flush the TLBs only after we're certain all the PTE updates
1475 * have finished.
1476 */
1477 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1478 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1479 }
1480
1481 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1482 uint64_t start,
1483 uint64_t length,
1484 bool use_scratch)
1485 {
1486 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1487 unsigned first_entry = start >> PAGE_SHIFT;
1488 unsigned num_entries = length >> PAGE_SHIFT;
1489 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1490 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1491 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1492 int i;
1493
1494 if (WARN(num_entries > max_entries,
1495 "First entry = %d; Num entries = %d (max=%d)\n",
1496 first_entry, num_entries, max_entries))
1497 num_entries = max_entries;
1498
1499 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1500 I915_CACHE_LLC,
1501 use_scratch);
1502 for (i = 0; i < num_entries; i++)
1503 gen8_set_pte(&gtt_base[i], scratch_pte);
1504 readl(gtt_base);
1505 }
1506
1507 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1508 uint64_t start,
1509 uint64_t length,
1510 bool use_scratch)
1511 {
1512 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1513 unsigned first_entry = start >> PAGE_SHIFT;
1514 unsigned num_entries = length >> PAGE_SHIFT;
1515 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1516 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1517 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1518 int i;
1519
1520 if (WARN(num_entries > max_entries,
1521 "First entry = %d; Num entries = %d (max=%d)\n",
1522 first_entry, num_entries, max_entries))
1523 num_entries = max_entries;
1524
1525 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1526
1527 for (i = 0; i < num_entries; i++)
1528 iowrite32(scratch_pte, &gtt_base[i]);
1529 readl(gtt_base);
1530 }
1531
1532
1533 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1534 enum i915_cache_level cache_level,
1535 u32 unused)
1536 {
1537 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1538 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1539 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1540
1541 BUG_ON(!i915_is_ggtt(vma->vm));
1542 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1543 vma->obj->has_global_gtt_mapping = 1;
1544 }
1545
1546 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1547 uint64_t start,
1548 uint64_t length,
1549 bool unused)
1550 {
1551 unsigned first_entry = start >> PAGE_SHIFT;
1552 unsigned num_entries = length >> PAGE_SHIFT;
1553 intel_gtt_clear_range(first_entry, num_entries);
1554 }
1555
1556 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1557 {
1558 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1559 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1560
1561 BUG_ON(!i915_is_ggtt(vma->vm));
1562 vma->obj->has_global_gtt_mapping = 0;
1563 intel_gtt_clear_range(first, size);
1564 }
1565
1566 static void ggtt_bind_vma(struct i915_vma *vma,
1567 enum i915_cache_level cache_level,
1568 u32 flags)
1569 {
1570 struct drm_device *dev = vma->vm->dev;
1571 struct drm_i915_private *dev_priv = dev->dev_private;
1572 struct drm_i915_gem_object *obj = vma->obj;
1573
1574 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1575 * or we have a global mapping already but the cacheability flags have
1576 * changed, set the global PTEs.
1577 *
1578 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1579 * instead if none of the above hold true.
1580 *
1581 * NB: A global mapping should only be needed for special regions like
1582 * "gtt mappable", SNB errata, or if specified via special execbuf
1583 * flags. At all other times, the GPU will use the aliasing PPGTT.
1584 */
1585 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1586 if (!obj->has_global_gtt_mapping ||
1587 (cache_level != obj->cache_level)) {
1588 vma->vm->insert_entries(vma->vm, obj->pages,
1589 vma->node.start,
1590 cache_level);
1591 obj->has_global_gtt_mapping = 1;
1592 }
1593 }
1594
1595 if (dev_priv->mm.aliasing_ppgtt &&
1596 (!obj->has_aliasing_ppgtt_mapping ||
1597 (cache_level != obj->cache_level))) {
1598 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1599 appgtt->base.insert_entries(&appgtt->base,
1600 vma->obj->pages,
1601 vma->node.start,
1602 cache_level);
1603 vma->obj->has_aliasing_ppgtt_mapping = 1;
1604 }
1605 }
1606
1607 static void ggtt_unbind_vma(struct i915_vma *vma)
1608 {
1609 struct drm_device *dev = vma->vm->dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 struct drm_i915_gem_object *obj = vma->obj;
1612
1613 if (obj->has_global_gtt_mapping) {
1614 vma->vm->clear_range(vma->vm,
1615 vma->node.start,
1616 obj->base.size,
1617 true);
1618 obj->has_global_gtt_mapping = 0;
1619 }
1620
1621 if (obj->has_aliasing_ppgtt_mapping) {
1622 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1623 appgtt->base.clear_range(&appgtt->base,
1624 vma->node.start,
1625 obj->base.size,
1626 true);
1627 obj->has_aliasing_ppgtt_mapping = 0;
1628 }
1629 }
1630
1631 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1632 {
1633 struct drm_device *dev = obj->base.dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 bool interruptible;
1636
1637 interruptible = do_idling(dev_priv);
1638
1639 if (!obj->has_dma_mapping)
1640 dma_unmap_sg(&dev->pdev->dev,
1641 obj->pages->sgl, obj->pages->nents,
1642 PCI_DMA_BIDIRECTIONAL);
1643
1644 undo_idling(dev_priv, interruptible);
1645 }
1646
1647 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1648 unsigned long color,
1649 unsigned long *start,
1650 unsigned long *end)
1651 {
1652 if (node->color != color)
1653 *start += 4096;
1654
1655 if (!list_empty(&node->node_list)) {
1656 node = list_entry(node->node_list.next,
1657 struct drm_mm_node,
1658 node_list);
1659 if (node->allocated && node->color != color)
1660 *end -= 4096;
1661 }
1662 }
1663
1664 void i915_gem_setup_global_gtt(struct drm_device *dev,
1665 unsigned long start,
1666 unsigned long mappable_end,
1667 unsigned long end)
1668 {
1669 /* Let GEM Manage all of the aperture.
1670 *
1671 * However, leave one page at the end still bound to the scratch page.
1672 * There are a number of places where the hardware apparently prefetches
1673 * past the end of the object, and we've seen multiple hangs with the
1674 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1675 * aperture. One page should be enough to keep any prefetching inside
1676 * of the aperture.
1677 */
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1680 struct drm_mm_node *entry;
1681 struct drm_i915_gem_object *obj;
1682 unsigned long hole_start, hole_end;
1683
1684 BUG_ON(mappable_end > end);
1685
1686 /* Subtract the guard page ... */
1687 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1688 if (!HAS_LLC(dev))
1689 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1690
1691 /* Mark any preallocated objects as occupied */
1692 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1693 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1694 int ret;
1695 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1696 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1697
1698 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1699 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1700 if (ret)
1701 DRM_DEBUG_KMS("Reservation failed\n");
1702 obj->has_global_gtt_mapping = 1;
1703 }
1704
1705 dev_priv->gtt.base.start = start;
1706 dev_priv->gtt.base.total = end - start;
1707
1708 /* Clear any non-preallocated blocks */
1709 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1710 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1711 hole_start, hole_end);
1712 ggtt_vm->clear_range(ggtt_vm, hole_start,
1713 hole_end - hole_start, true);
1714 }
1715
1716 /* And finally clear the reserved guard page */
1717 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1718 }
1719
1720 void i915_gem_init_global_gtt(struct drm_device *dev)
1721 {
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 unsigned long gtt_size, mappable_size;
1724
1725 gtt_size = dev_priv->gtt.base.total;
1726 mappable_size = dev_priv->gtt.mappable_end;
1727
1728 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1729 }
1730
1731 static int setup_scratch_page(struct drm_device *dev)
1732 {
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734 struct page *page;
1735 dma_addr_t dma_addr;
1736
1737 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1738 if (page == NULL)
1739 return -ENOMEM;
1740 get_page(page);
1741 set_pages_uc(page, 1);
1742
1743 #ifdef CONFIG_INTEL_IOMMU
1744 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1745 PCI_DMA_BIDIRECTIONAL);
1746 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1747 return -EINVAL;
1748 #else
1749 dma_addr = page_to_phys(page);
1750 #endif
1751 dev_priv->gtt.base.scratch.page = page;
1752 dev_priv->gtt.base.scratch.addr = dma_addr;
1753
1754 return 0;
1755 }
1756
1757 static void teardown_scratch_page(struct drm_device *dev)
1758 {
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 struct page *page = dev_priv->gtt.base.scratch.page;
1761
1762 set_pages_wb(page, 1);
1763 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1764 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1765 put_page(page);
1766 __free_page(page);
1767 }
1768
1769 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1770 {
1771 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1772 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1773 return snb_gmch_ctl << 20;
1774 }
1775
1776 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1777 {
1778 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1779 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1780 if (bdw_gmch_ctl)
1781 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1782 return bdw_gmch_ctl << 20;
1783 }
1784
1785 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1786 {
1787 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1788 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1789 return snb_gmch_ctl << 25; /* 32 MB units */
1790 }
1791
1792 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1793 {
1794 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1795 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1796 return bdw_gmch_ctl << 25; /* 32 MB units */
1797 }
1798
1799 static int ggtt_probe_common(struct drm_device *dev,
1800 size_t gtt_size)
1801 {
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 phys_addr_t gtt_bus_addr;
1804 int ret;
1805
1806 /* For Modern GENs the PTEs and register space are split in the BAR */
1807 gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1808 (pci_resource_len(dev->pdev, 0) / 2);
1809
1810 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1811 if (!dev_priv->gtt.gsm) {
1812 DRM_ERROR("Failed to map the gtt page table\n");
1813 return -ENOMEM;
1814 }
1815
1816 ret = setup_scratch_page(dev);
1817 if (ret) {
1818 DRM_ERROR("Scratch setup failed\n");
1819 /* iounmap will also get called at remove, but meh */
1820 iounmap(dev_priv->gtt.gsm);
1821 }
1822
1823 return ret;
1824 }
1825
1826 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1827 * bits. When using advanced contexts each context stores its own PAT, but
1828 * writing this data shouldn't be harmful even in those cases. */
1829 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1830 {
1831 #define GEN8_PPAT_UC (0<<0)
1832 #define GEN8_PPAT_WC (1<<0)
1833 #define GEN8_PPAT_WT (2<<0)
1834 #define GEN8_PPAT_WB (3<<0)
1835 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1836 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1837 #define GEN8_PPAT_LLC (1<<2)
1838 #define GEN8_PPAT_LLCELLC (2<<2)
1839 #define GEN8_PPAT_LLCeLLC (3<<2)
1840 #define GEN8_PPAT_AGE(x) (x<<4)
1841 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1842 uint64_t pat;
1843
1844 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1845 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1846 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1847 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1848 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1849 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1850 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1851 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1852
1853 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1854 * write would work. */
1855 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1856 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1857 }
1858
1859 static int gen8_gmch_probe(struct drm_device *dev,
1860 size_t *gtt_total,
1861 size_t *stolen,
1862 phys_addr_t *mappable_base,
1863 unsigned long *mappable_end)
1864 {
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 unsigned int gtt_size;
1867 u16 snb_gmch_ctl;
1868 int ret;
1869
1870 /* TODO: We're not aware of mappable constraints on gen8 yet */
1871 *mappable_base = pci_resource_start(dev->pdev, 2);
1872 *mappable_end = pci_resource_len(dev->pdev, 2);
1873
1874 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1875 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1876
1877 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1878
1879 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1880
1881 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1882 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1883
1884 gen8_setup_private_ppat(dev_priv);
1885
1886 ret = ggtt_probe_common(dev, gtt_size);
1887
1888 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1889 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1890
1891 return ret;
1892 }
1893
1894 static int gen6_gmch_probe(struct drm_device *dev,
1895 size_t *gtt_total,
1896 size_t *stolen,
1897 phys_addr_t *mappable_base,
1898 unsigned long *mappable_end)
1899 {
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 unsigned int gtt_size;
1902 u16 snb_gmch_ctl;
1903 int ret;
1904
1905 *mappable_base = pci_resource_start(dev->pdev, 2);
1906 *mappable_end = pci_resource_len(dev->pdev, 2);
1907
1908 /* 64/512MB is the current min/max we actually know of, but this is just
1909 * a coarse sanity check.
1910 */
1911 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1912 DRM_ERROR("Unknown GMADR size (%lx)\n",
1913 dev_priv->gtt.mappable_end);
1914 return -ENXIO;
1915 }
1916
1917 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1918 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1919 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1920
1921 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1922
1923 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1924 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1925
1926 ret = ggtt_probe_common(dev, gtt_size);
1927
1928 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1929 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1930
1931 return ret;
1932 }
1933
1934 static void gen6_gmch_remove(struct i915_address_space *vm)
1935 {
1936
1937 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1938
1939 drm_mm_takedown(&vm->mm);
1940 iounmap(gtt->gsm);
1941 teardown_scratch_page(vm->dev);
1942 }
1943
1944 static int i915_gmch_probe(struct drm_device *dev,
1945 size_t *gtt_total,
1946 size_t *stolen,
1947 phys_addr_t *mappable_base,
1948 unsigned long *mappable_end)
1949 {
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 int ret;
1952
1953 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1954 if (!ret) {
1955 DRM_ERROR("failed to set up gmch\n");
1956 return -EIO;
1957 }
1958
1959 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1960
1961 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1962 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1963
1964 if (unlikely(dev_priv->gtt.do_idle_maps))
1965 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1966
1967 return 0;
1968 }
1969
1970 static void i915_gmch_remove(struct i915_address_space *vm)
1971 {
1972 intel_gmch_remove();
1973 }
1974
1975 int i915_gem_gtt_init(struct drm_device *dev)
1976 {
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1978 struct i915_gtt *gtt = &dev_priv->gtt;
1979 int ret;
1980
1981 if (INTEL_INFO(dev)->gen <= 5) {
1982 gtt->gtt_probe = i915_gmch_probe;
1983 gtt->base.cleanup = i915_gmch_remove;
1984 } else if (INTEL_INFO(dev)->gen < 8) {
1985 gtt->gtt_probe = gen6_gmch_probe;
1986 gtt->base.cleanup = gen6_gmch_remove;
1987 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1988 gtt->base.pte_encode = iris_pte_encode;
1989 else if (IS_HASWELL(dev))
1990 gtt->base.pte_encode = hsw_pte_encode;
1991 else if (IS_VALLEYVIEW(dev))
1992 gtt->base.pte_encode = byt_pte_encode;
1993 else if (INTEL_INFO(dev)->gen >= 7)
1994 gtt->base.pte_encode = ivb_pte_encode;
1995 else
1996 gtt->base.pte_encode = snb_pte_encode;
1997 } else {
1998 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1999 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2000 }
2001
2002 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2003 &gtt->mappable_base, &gtt->mappable_end);
2004 if (ret)
2005 return ret;
2006
2007 gtt->base.dev = dev;
2008
2009 /* GMADR is the PCI mmio aperture into the global GTT. */
2010 DRM_INFO("Memory usable by graphics device = %zdM\n",
2011 gtt->base.total >> 20);
2012 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2013 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2014
2015 return 0;
2016 }
2017
2018 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2019 struct i915_address_space *vm)
2020 {
2021 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2022 if (vma == NULL)
2023 return ERR_PTR(-ENOMEM);
2024
2025 INIT_LIST_HEAD(&vma->vma_link);
2026 INIT_LIST_HEAD(&vma->mm_list);
2027 INIT_LIST_HEAD(&vma->exec_list);
2028 vma->vm = vm;
2029 vma->obj = obj;
2030
2031 switch (INTEL_INFO(vm->dev)->gen) {
2032 case 8:
2033 case 7:
2034 case 6:
2035 if (i915_is_ggtt(vm)) {
2036 vma->unbind_vma = ggtt_unbind_vma;
2037 vma->bind_vma = ggtt_bind_vma;
2038 } else {
2039 vma->unbind_vma = ppgtt_unbind_vma;
2040 vma->bind_vma = ppgtt_bind_vma;
2041 }
2042 break;
2043 case 5:
2044 case 4:
2045 case 3:
2046 case 2:
2047 BUG_ON(!i915_is_ggtt(vm));
2048 vma->unbind_vma = i915_ggtt_unbind_vma;
2049 vma->bind_vma = i915_ggtt_bind_vma;
2050 break;
2051 default:
2052 BUG();
2053 }
2054
2055 /* Keep GGTT vmas first to make debug easier */
2056 if (i915_is_ggtt(vm))
2057 list_add(&vma->vma_link, &obj->vma_list);
2058 else
2059 list_add_tail(&vma->vma_link, &obj->vma_list);
2060
2061 return vma;
2062 }
2063
2064 struct i915_vma *
2065 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2066 struct i915_address_space *vm)
2067 {
2068 struct i915_vma *vma;
2069
2070 vma = i915_gem_obj_to_vma(obj, vm);
2071 if (!vma)
2072 vma = __i915_gem_vma_create(obj, vm);
2073
2074 return vma;
2075 }
Linux kernel - Deliverables
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